24C04A-I/SM [ETC]

I2C Serial EEPROM ; I2C串行EEPROM\n


型号：	24C04A-I/SM
厂家：	ETC
描述：	I2C Serial EEPROM I2C串行EEPROM\n 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总12页 (文件大小：136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24C04A

2 ™

4K 5.0V I C Serial EEPROM

FEATURES

PACKAGE TYPES

• Low power CMOS technology

• Hardware write protect

• Two wire serial interface bus, I²C™ compatible

• 5.0V only operation

DIP

VCC

• Self-timed write cycle (including auto-erase)

• Page-write buffer

• 1 ms write cycle time for single byte

• 1,000,000 Erase/Write cycles guaranteed

• Data retention >200 years

SCL

SDA

VSS

• 8-pin DIP/SOIC packages

• Available for extended temperature ranges

8-lead

SOIC

VCC

- Commercial (C):

- Industrial (I):

- Automotive (E):

0˚C to +70˚C

-40˚C to +85˚C

-40˚C to +125˚C

SCL

SDA

DESCRIPTION

The Microchip Technology Inc. 24C04A is a 4K bit

Electrically Erasable PROM. The device is organized

as with a standard two wire serial interface. Advanced

CMOS technology allows a signiﬁcant reduction in

power over NMOS serial devices. A special feature

provides hardware write protection for the upper half of

the block. The 24C04A has a page write capability of

up to eight bytes, and up to four 24C04A devices may

be connected to the same two wire bus.

VSS

14-lead

SOIC

Vcc

This device offers fast (1ms) byte write and

extended (-40°C to 125°C) temperature operation.

It is recommended that all other applications use

Microchip’s 24LC04B.

SCL

SDA

Vss

BLOCK DIAGRAM

Data

Buffer

(FIFO)

Vcc

VPP

R/W Amp

Vss

Data Reg.

A P

d o

Memory

Array

SDA

Slave Addr.

A0 to

s e

Control

Logic

Increment

SCL

A0 A1 A2 WP

I²C is a trademark of Philips Corporation.

1998 Microchip Technology Inc.

DS11183E-page 1

24C04A

TABLE 1-1:

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL CHARACTERISTICS

Name

1.1

Maximum Ratings*

No Function - Must be connected to

VCC or VSS

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V

Storage temperature ..................................... -65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds) ............. +300˚C

ESD protection on all pins................................................4 kV

A1, A2

VSS

Chip Address Inputs

Ground

SDA

SCL

Serial Address/Data I/O

Serial Clock

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

Write Protect Input

+5V Power Supply

VCC

TABLE 1-2:

DC CHARACTERISTICS

VCC = +5V (±10%)

Commercial (C): Tamb = 0°C to +70°C

Industrial (I): Tamb = -40°C to +85°C

Automotive (E): Tamb = -40°C to +125°C

Parameter

Symbol

Min.

Max.

Units

Conditions

VCC detector threshold

VTH

2.8

4.5

SCL and SDA pins:

High level input voltage

Low level input voltage

Low level output voltage

VIH

VIL

VOL

VCC x 0.7 VCC + 1

-0.3

VCC x 0.3

0.4

IOL = 3.2 mA (SDA only)

A1 & A2 pins:

High level input voltage

Low level input voltage

VIH

VIL

VCC - 0.5 VCC + 0.5

-0.3

0.5

Input leakage current

Output leakage current

ILI

—

µA

VIN = 0V to VCC

ILO

—

VOUT = 0V to VCC

Pin capacitance

CIN,

—

7.0

VIN/VOUT = 0V (Note)

(all inputs/outputs)

COUT

Tamb = +25˚C, f = 1 MHz

Operating current

ICC

Write

—

3.5

4.25

750

100

µA

FCLK = 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = 0˚C to +70˚C

ICC

Write

FCLK = 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = (I) and (E)

ICC

Read

VCC = 5V, Tamb= (C), (I) and (E)

Standby current

ICCS

µA

SDA=SCL=VCC=5V (no PROGRAM active)

WP/TEST = VSS, A0, A1, A2 = VSS

Note: This parameter is periodically sampled and not 100% tested

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL

SDA

THD:STA

TSU:STA

TSU:STO

START

STOP

DS11183E-page 2

1998 Microchip Technology Inc.

24C04A

TABLE 1-3:

AC CHARACTERISTICS

Parameter

Symbol

Min.

Typ

Max.

Units

Remarks

Clock frequency

FCLK

THIGH

TLOW

—

4000

4700

—

100

—

kHz

Clock high time

Clock low time

—

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

1000

300

—

THD:STA

4000

After this period the ﬁrst

clock pulse is generated

START condition setup time

TSU:STA

4700

—

Only relevant for repeated

START condition

Data input hold time

Data input setup time

Data output delay time

STOP condition setup time

Bus free time

THD:DAT

TSU:DAT

TAA

—

250

300

4700

3500

—

(Note 1)

TSU:STO

TBUF

—

Time the bus must be free

before a new transmission

can start

Input ﬁlter time constant

(SDA and SCL pins)

—

100

Program cycle time

TWC

.4N

—

Byte mode

Page mode, N=# of bytes

Endurance

—

cycles

25°C, Vcc = 5.0V, Block

Mode (Note 2)

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undeﬁned region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

FIGURE 1-2: BUS TIMING DATA

THIGH

TLOW

SCL

TSU:STA

THD:DAT

TSU:DAT

TSU:STO

THD:STA

SDA

TSP

TBUF

TAA

THD:STA

SDA

OUT

1998 Microchip Technology Inc.

DS11183E-page 3

24C04A

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The 24C04A supports a bidirectional two wire bus and

data transmission protocol. A device that sends data

onto the bus is deﬁned as transmitter, and a device

receiving data as receiver. The bus has to be con-

trolled by a master device which generates the serial

clock (SCL), controls the bus access, and generates

the START and STOP conditions, while the 24C04A

works as slave. Both master and slave can operate as

transmitter or receiver but the master device deter-

mines which mode is activated.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited.

Up to four 24C04As can be connected to the bus,

selected by A1 and A2 chip address inputs. A0 must

be tied to VCC or VSS.

3.5

Acknowledge

3.0

BUS CHARACTERISTICS

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Note: The 24C04A does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

DS11183E-page 4

1998 Microchip Technology Inc.

24C04A

4.0

SLAVE ADDRESS

5.0

BYTE PROGRAM MODE

The chip address inputs A1 and A2 must be externally

connected to either VCC or ground (VSS), thereby

assigning a unique address to each device. A0 is not

used on the 24C04A and must be connected to either

VCC or VSS. Up to four 24C04A devices may be con-

nected to the bus. Chip selection is then accomplished

through software by setting the bits A1 and A2 of the

slave address to the corresponding hard-wired logic lev-

els of the selected 24C04A. After generating a START

condition, the bus master transmits the slave address

consisting of a 4-bit device code (1010), followed by the

chip address bits A0, A1 and A2. The seventh bit of that

byte (A0) is used to select the upper block (addresses

100—1FF) or the lower block (addresses 000—0FF) of

the array.

In this mode, the master sends addresses and one

data byte to the 24C04A.

Following the START signal from the master, the device

code (4-bits), the slave address (3-bits), and the R/W

bit, which is logic LOW, are placed onto the bus by the

master. This indicates to the addressed 24C04A that a

byte with a word address will follow after it has gener-

ated an acknowledge bit.Therefore the next byte trans-

mitted by the master is the word address and will be

written into the address pointer of the 24C04A. After

receiving the acknowledge, the master device trans-

mits the data word to be written into the addressed

memory location. The 24C04A acknowledges again

and the master generates a STOP condition. This ini-

tiates the internal programming cycle (Figure 6-1).

The eighth bit of the slave address determines if the

master device wants to read or write to the 24C04A

(Figure 4-1).

The 24C04A monitors the bus for its corresponding

slave address all the time. It generates an acknowl-

edge bit if the slave address was true and it is not in a

programming mode.

FIGURE 4-1: SLAVE ADDRESS

ALLOCATION

START

READ/WRITE

SLAVE ADDRESS

R/W

1998 Microchip Technology Inc.

DS11183E-page 5

24C04A

as a result of only allowing the address registers bot-

tom 3 bits to increment while the upper 5 bits remain

unchanged.

6.0

PAGE PROGRAM MODE

To program the master sends addresses and data to

the 24C04A which is the slave (Figure 6-1 and

Figure 6-2). This is done by supplying a START condi-

tion followed by the 4-bit device code, the 3-bit slave

address, and the R/W bit which is deﬁned as a logic

LOW for a write. This indicates to the addressed slave

that a word address will follow so the slave outputs the

acknowledge pulse to the master during the ninth clock

pulse. When the word address is received by the

24C04A, it places it in the lower 8 bits of the address

pointer deﬁning which memory location is to be written.

(The A0 bit transmitted with the slave address is the

ninth bit of the address pointer). The 24C04A will gen-

erate an acknowledge after every 8-bits received and

store them consecutively in a RAM (8 bytes maximum)

buffer until a STOP condition is detected. This STOP

condition initiates the internal programming cycle.. If

more than 8 bytes are transmitted by the master, the

24C04A will roll over and overwrite the data beginning

with the ﬁrst received byte. This does not affect erase/

write cycles of the EEPROM array and is accomplished

If the master generates a STOP condition after trans-

mitting the ﬁrst data word (Point ‘P’ on Figure 6-1), byte

programming mode is entered.

The internal, completely self-timed PROGRAM cycle

starts after the STOP condition has been generated by

the master and all received data bytes in the page

buffer will be written in a serial manner.

The PROGRAM cycle takes N milliseconds, whereby N

is the number of received data bytes.

FIGURE 6-1: BYTE WRITE

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS

DATA

SDA LINE

BUS ACTIVITY

FIGURE 6-2: PAGE WRITE

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 1

DATA n + 7

SDA LINE

BUS ACTIVITY

DS11183E-page 6

1998 Microchip Technology Inc.

24C04A

7.0

ACKNOWLEDGE POLLING

8.0

WRITE PROTECTION

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately.This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 7-1 for ﬂow diagram.

Programming of the upper half of the memory will not

take place if the WP pin is connected to VCC (+5.0V).

The device will accept slave and word addresses but if

the memory accessed is write protected by the WP pin,

the 24C04A will not generate an acknowledge after the

ﬁrst byte of data has been received, and thus the pro-

gram cycle will not be started when the STOP condition

is asserted.

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

Operation

1998 Microchip Technology Inc.

DS11183E-page 7

24C04A

9.0

READ MODE

Note 1: If the master knows where the address

pointer is, it can begin the read sequence

at the current address (Figure 9-1) and

save time transmitting the slave and word

addresses.

In this mode the 24C04A transmits data to the master

devide.

As can be seen from Figure 9-2 and Figure 9-3, the

master ﬁrst sets up the slave and word addresses by

doing a write. (Note: Although this is a read mode, the

address pointer must be written to). During this period

the 24C04A generates the necessary acknowledge

bits as deﬁned in the appropriate section.

Note 2: In all modes, the address pointer will not

increment through a block (256 byte)

boundary, but will rotate back to the ﬁrst

location in that block.

The master now generates another START condition

and transmits the slave address again, except this time

the read/write bit is set into the read mode. After the

slave generates the acknowledge bit, it then outputs

the data from the addressed location on to the SDA pin,

increments the address pointer and, if it receives an

acknowledge from the master, will transmit the next

consecutive byte. This auto-increment sequence is

only aborted when the master sends a STOP condition

instead of an acknowledge.

FIGURE 9-1: CURRENT ADDRESS READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

SDA LINE

BUS ACTIVITY

FIGURE 9-2: RANDOM READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

DATA (n)

SDA LINE

BUS ACTIVITY

FIGURE 9-3: SEQUENTIAL READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

SDA LINE

BUS ACTIVITY

DS11183E-page 8

1998 Microchip Technology Inc.

24C04A

10.4

WP Write Protection

10.0 PIN DESCRIPTION

This pin must be connected to either VCC or VSS. If tied

to VCC, write operations to the upper memory block will

not be executed. Read operations are possible.

10.1

A0, A1, A2 Chip Address Inputs

A0 is not used as a chip select bit and must be tied to

either Vss or Vcc. The levels on the remaining two

address inputs(A1, A2) are compared with the corre-

sponding bits in the slave address. The chip is selected

if the compare is true. These inputs must be connected

to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory).

This feature allows the user to assign the upper half of

the memory as ROM which can be protected against

accidental programming. When write is disabled, slave

address and word address will be acknowledged but

data will not be acknowledged.

These two address inputs allow up to four 24C04A's

can be connected to the bus

10.2

SDASerialAddress/DataInput/Output

Note 1: A “page” is deﬁned as the maximum num-

ber of bytes that can be programmed in a

single write cycle. The 24C04A page is 8

bytes long.

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typical 10KΩ).

Note 2: A “block” is deﬁned as a continuous area

of memory with distinct boundaries. The

address pointer can not cross the bound-

ary from one block to another. It will how-

ever, wrap around from the end of a block

to the ﬁrst location in the same block. The

24C04A has two blocks, 256 bytes each.

For normal data transfer, SDA is allowed to change only

during SCL LOW. Changes during SCL HIGH are

reserved for indicating the START and STOP condi-

tions.

10.3

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

1998 Microchip Technology Inc.

DS11183E-page 9

24C04A

NOTES:

DS11183E-page 10

1998 Microchip Technology Inc.

24C04A

24C04A Product Identiﬁcation System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

24C04A

P = Plastic DIP

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

Package:

Blank = 0°C to +70°C

= -40°C to +85°C

Temperature

Range:

E = -40°C to +125°C

24C04A

24C04AT

4K I C Serial EEPROM

Device:

4K I C Serial EEPROM (Tape and Reel)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip Worldwide Web Site (www.microchip.com)

DS11183E-page 11

1998 Microchip Technology Inc.

WORLDWIDE SALES AND SERVICE

AMERICAS

AMERICAS (continued)

ASIA/PACIFIC (continued)

Corporate Office

Toronto

Singapore

Microchip Technology Inc.

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Technical Support: 480-786-7627

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11/15/99

San Jose

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Microchip Technology Inc.

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Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed

by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products

as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip

logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

 1999 Microchip Technology Inc.

24C04A-I/SM [ETC]

相关型号：

24C04A-I/SN

24C04A-I/SO

24C04A-IP

24C04A-ISL

24C04A-ISM

24C04A-ISN

24C04A-P

24C04A-SL

24C04A-SM

24C04A-SN

24C04A/J

24C04A/P