24LCS52ST [ETC]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | 24LCS52ST |
| 厂家： | 
ETC |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总12页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24LCS52
2K 2.2V I2C™ Serial EEPROM with Software Write Protect
FEATURES
PACKAGE TYPES
PDIP/SOIC
• Single supply with operation down to 2.2V
• Low power CMOS technology
- 1 mA active current typical
A0
1
8
Vcc
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as a single block of 256 bytes (256 x 8)
• Software write protection for lower 128 bytes
• Hardware write protection for entire array
• 2-wire serial interface bus, I2C™ compatible
• 100kHz (2.2V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 3.5 ms typical write cycle time for page-write
• 1,000,000 erase/write cycles guaranteed
• ESD protection >4,000V
A1
A2
2
3
7
6
WP
SCL
Vss
4
5
SDA
TSSOP
• Data retention > 200 years
• 8-pin DIP, SOIC or TSSOP packages
• Available for extended temperature ranges
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
A0
A1
A2
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
Vss
DESCRIPTION
The Microchip Technology Inc. 24LCS52 is a 2K bit
Electrically Erasable PROM capable of operation
across a broad voltage range (2.2V to 5.5V). This
device has a software write protect feature for the lower
half of the array, as well as an external pin that can be
used to write protect the entire array. The software write
protect feature is enabled by sending the device a spe-
cial command, and once this feature has been enabled,
it cannot be reversed. In addition to the software pro-
tect feature, there is a WP pin that can be used to write
protect the entire array, regardless of whether the soft-
ware write protect register has been written or not. This
allows the system designer to protect none, half or all
of the array, depending on the application. The device
is organized as a single block of 256 x 8-bit memory
with a 2-wire serial interface. Low voltage design per-
mits operation down to 2.2 volts with typical standby
and active currents of only 5 µA and 1 mA respectively.
The device has a page-write capability for up to 16
bytes of data. The device is available in the standard 8-
pin DIP, 8-pin SOIC and TSSOP packages.
BLOCK DIAGRAM
WP
A0 A1 A2
HV Generator
Software write
protected area
(00h-7Fh)
I/O
Control
Logic
Memory
Control
Logic
XDEC
Standard
Array
SDA
SCL
Vcc
Vss
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
1999 Microchip Technology Inc.
DS21166E-page 1
This Material Copyrighted by Its Respective Manufacturer
24LCS52
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
VSS
SDA
Ground
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins............................................ Š 4 kV
Serial Address/Data I/O
Serial Clock
SCL
VCC
+2.2V to 5.5V Power Supply
Chip Selects
A0, A1, A2
WP
Hardware Write Protect
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +2.2V to +5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial
(I): Tamb = -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
VIH
.7 VCC
V
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
Input leakage current
All I/O pins
VIL
VHYS
VOL
.3 VCC
—
V
V
V
.05 VCC
(Note)
.40
IOL = 3.0 mA, VCC = 2.5V
ILI
ILI
-10
-10
-10
—
10
50
10
10
µA
µA
µA
pF
VIN = 0.1V to 5.5V, WP = Vss
WP = VCC
WP pin
Output leakage current
Pin capacitance (all inputs/outputs)
ILO
VOUT = 0.1V to 5.5V
CIN,
VCC = 5.0V (Note)
COUT
Tamb = 25°C, FCLK = 1 MHz
Operating current
Standby current
ICC Write
ICC Read
ICCS
—
—
—
3
1
mA
mA
µA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V, SCL = 400 kHz
VCC = 3.0V, SDA = SCL = VCC
30
100
µA
VCC = 5.5V, SDA = SCL = VCC
WP = VSS, A0, A1, A2 = VSS
Note:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
START
STOP
DS21166E-page 2
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LCS52
TABLE 1-3:
AC CHARACTERISTICS
Vcc = 2.2-5.5V Vcc = 4.5 - 5.5V
STD MODE FAST MODE
Parameter
Symbol
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
FCLK
THIGH
TLOW
TR
TF
THD:STA
—
4000
4700
—
—
4000
100
—
—
1000
300
—
—
600
1300
—
—
600
400
—
—
300
300
—
kHz
ns
ns
ns
ns
(Note 1)
(Note 1)
ns
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
START condition setup time
TSU:STA
4700
—
600
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
—
3500
—
0
—
—
—
900
—
ns
ns
ns
ns
ns
250
4000
—
100
600
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
TOF
TSP
TWR
—
—
250
50
20 +0.1
CB
250
50
ns
ns
(Note 1), CB ð 100 pF
—
(Note 3)
—
1M
10
—
—
1M
10
—
ms
Byte or Page mode
Endurance
cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
THD:STA
TAA
TBUF
TAA
SDA
OUT
1999 Microchip Technology Inc.
DS21166E-page 3
This Material Copyrighted by Its Respective Manufacturer
24LCS52
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
2.0
FUNCTIONAL DESCRIPTION
The 24LCS52 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LCS52
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
Note: The 24LCS52 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus Not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
3.6
Device Addressing
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
A control byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit control code which
is set to 1010 for normal read and write operations and
0110 for writing to the write protect register. The control
byte is followed by three chip select bits (A2, A1, A0).
The chip select bits allow the use of up to eight
24LCS52 devices on the same bus and are used to
determine which device is accessed. The chip select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond. The device will not acknowledge if
you attempt a read command with the control code set
to 0110.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
DS21166E-page 4
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LCS52
The eighth bit of slave address determines if the master
device wants to read or write to the 24LCS52 (Figure 3-
2). When set to a one a read operation is selected and
when set to a zero a write operation is selected.
another acknowledge signal from the 24LCS52 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS52
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and
during this time the 24LCS52 will not generate
acknowledge signals (Figure 4-1). If an attempt is
made to write to the array when the software or hard-
ware write protection has been enabled, the device will
acknowledge the command but no data will be written.
The write cycle time must be observed even if the write
protection is enabled.
Control
Code
Chip
Select
Operation
R/W
Read
Write
Set Write Protect
Register
1010
1010
0110
A2 A1 A0
A2 A1 A0
A2 A1 A0
1
0
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
4.2
Page Write
START
READ/WRITE
The write control byte, word address and the first data
byte are transmitted to the 24LCS52 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 15 additional data
bytes to the 24LCS52 which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi-
tion. After the receipt of each word, the four lower order
address pointer bits are internally incremented by one.
The higher order four bits of the word address remains
constant. If the master should transmit more than 16
bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2). If an attempt is
made to write to the array when the hardware write pro-
tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.
SLAVE ADDRESS
R/W
A
1
0
1
1
1
0
A2
A2
A1
A1
A0
A0
OR
0
0
4.0
WRITE OPERATIONS
4.1
Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24LCS52. After receiving
Note: Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
1999 Microchip Technology Inc.
DS21166E-page 5
This Material Copyrighted by Its Respective Manufacturer
24LCS52
FIGURE 4-1: BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 4-2: PAGE WRITE
S
T
S
T
O
P
BUS ACTIVITY
MASTER
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
DS21166E-page 6
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LCS52
5.0
ACKNOWLEDGE POLLING
6.0
WRITE PROTECTION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
The 24LCS52 has a software write protect feature that
allows the lower half of the array (addresses 00h - 7Fh)
to be permanently write protected, as well as a WP pin
that can be used to protect the entire array.
6.1
Software Write Protect
The software write protect feature is invoked by writing
to the write protect register. This is done by sending a
command similar to a normal write command. As
shown in Figure 6-1, the write protect register is written
by sending a write command with the slave address set
to 0110 instead of 1010 and the address bits and data
bits are don’t cares. Once the software write protect
register has been written, the device will not acknowl-
edge the 0110 control byte. Once the software write
protect register has been written, the write protec-
tion is enabled and cannot be reversed, even if the
device is powered down.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
6.2
Hardware Write Protect
The WP pin can be tied to Vcc, VSS, or left floating. If
tied to VCC, the entire array will be write protected,
regardless of whether the software write protect regis-
ter has been written or not. If the WP pin is set to VCC,
it will prevent the software write protect register from
being written. If the WP is tied to VSS or left floating,
then write protection is determined by the status of the
software write protect register.
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
FIGURE 6-1: SETTING WRITE PROTECT REGISTER
S
T
A
R
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
T
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
DS21166E-page 7
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LCS52
7.3
Sequential Read
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LCS52 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LCS52 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
7.1
Current Address Read
To provide sequential reads the 24LCS52 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
The 24LCS52 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the 24LCS52 issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LCS52 discontinues transmission (Figure 7-1).
7.4
Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 16K bits by add-
ing up to eight 24LCS52 devices on the same bus. In
this case, software can use A0 of the control byte as
address bit A8, A1 as address bit A9, and A2 as
address bit A10. It is not possible to sequentially read
across device boundaries.
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS52 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LCS52 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LCS52 dis-
continues transmission (Figure 7-2). After this com-
mand, the internal address counter will point to the
address location following the one that was just read.
FIGURE 7-1: CURRENT ADDRESS READ
S
T
S
BUS ACTIVITY
A
CONTROL
BYTE
T
MASTER
R
DATA
O
P
T
SDA LINE
P
S
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS21166E-page 8
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LCS52
FIGURE 7-2: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 7-3: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
is left floating, an internal pull down resistor will pull the
WP pin to Vss and the hardware write protection will be
disabled.
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/Output
8.5
Noise Protection
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10k¾ for 100 kHz, 2 k¾ for
400 kHz).
The 24LCS52 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
A0, A1, A2
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24LCS52 devices may be connected to the
same bus by using different chip select bit combina-
tions. These inputs must be connected to either Vcc or
Vss.
8.4
WP
This is the hardware write protect pin. It can be tied to
VCC, VSS, or left floating. If tied to Vcc, the hardware
write protection is enabled. If the WP pin is tied to Vss
the hardware write protection is disabled. If the WP pin
1999 Microchip Technology Inc.
DS21166E-page 9
This Material Copyrighted by Its Respective Manufacturer
24LCS52
NOTES:
DS21166E-page 10
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
24LCS52
24LCS52 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24LCS52
—
/P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = TSSOP, 8-lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = –40°C to +85°C
24LCS52
24LCS52T
2K I2C Serial EEPROM
Device:
2K I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
DS21166E-page 11
This Material Copyrighted by Its Respective Manufacturer
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
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200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
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