25C040T-SN [ETC]
SPI Serial EEPROM ; SPI串行EEPROM\n
| 型号： | 25C040T-SN |
| 厂家： | 
ETC |
| 描述： | SPI Serial EEPROM
|
| 文件： | 总12页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
25AA040/25LC040/25C040
4K SPI Bus Serial EEPROM
M
™
PACKAGE TYPES
DEVICE SELECTION TABLE
Part
Number
VCC
Range
Max Clock
Frequency
Temp
Ranges
PDIP/SOIC
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
25AA040
25LC040
25C040
1.8-5.5V
2.5-5.5V
4.5-5.5V
1 MHz
2 MHz
3 MHz
C,I
C,I
C,I,E
WP
VSS
FEATURES
• Low power CMOS technology
- Write current: 3 mA typical
- Read current: 500 µA typical
- Standby current: 500 nA typical
• 512 x 8 bit organization
TSSOP
1
2
3
4
8
7
6
5
SCK
SI
VSS
WP
HOLD
VCC
CS
• 16 byte page
• Write cycle time: 5ms max.
• Self-timed ERASE and WRITE cycles
• Block write protection
SO
- Protect none, 1/4, 1/2, or all of array
• Built-in write protection
- Power on/off data protection circuitry
- Write enable latch
BLOCK DIAGRAM
Status
Register
- Write protect pin
• Sequential read
HV Generator
• High reliability
- Endurance: 1M cycles (guaranteed)
- Data retention: > 200 years
- ESD protection: > 4000 V
• 8-pin PDIP, SOIC, and TSSOP packages
• Temperature ranges supported:
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Dec
- Automotive (E) (25C040):
Page Latches
DESCRIPTION
SI
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25xx040 ) is a 4K bit serial Electrically Eras-
*
Y Decoder
SO
able PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a chip select (CS)
input.
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write protect pin (WP).
*25xx040 is used in this document as a generic part number for the 25AA040/25LC040/25C040 devices.
SPI is a trademark of Motorola.
1998 Microchip Technology Inc.
DS21204B-page 1
Powered by ICminer.com Electronic-Library Service CopyRight 2003
25AA040/25LC040/25C040
FIGURE 1-2: AC TEST CIRCUIT
1.0
ELECTRICAL
CHARACTERISTICS
VCC
1.1
Maximum Ratings*
2.25 K
Vcc ...................................................................................7.0V
All inputs and outputs w.r.t. Vss.................. -0.6V to Vcc+1.0V
Storage temperature ....................................... -65˚C to 150˚C
Ambient temperature under bias..................... -65˚C to 125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins.................................................4kV
SO
1.8 K
100 pF
*Notice: Stresses above those listed under ‘Maximum ratings’ may
cause permanent damage to the device.This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability
1.2
AC Test Conditions
AC Waveform:
VLO = 0.2V
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
VHI = VCC - 0.2V
VHI = 4.0V
(Note 1)
(Note 2)
CS
SO
Chip Select Input
Serial Data Output
Serial Data Input
Serial Clock Input
Write Protect Pin
Ground
Timing Measurement Reference Level
Input
0.5 VCC
0.5 VCC
SI
Output
SCK
WP
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
VSS
VCC
HOLD
Supply Voltage
Hold Input
TABLE 1-3:
DC CHARACTERISTICS
All parameters apply over the Commercial (C): TAMB = 0°C to +70°C
VCC = 1.8V to 5.5V
specified operating ranges
unless otherwise noted.
Industrial (I):
TAMB = -40°C to +85°C
VCC = 1.8V to 5.5V
Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)
Parameter
Symbol
Min
Max
Units
Test Conditions
VCC ≥ 2.7V (Note)
VIH1
VIH2
VIL1
VIL2
VOL
VOL
VOH
ILI
2.0
0.7 VCC
-0.3
VCC+1
VCC+1
0.8
V
V
High level input voltage
VCC< 2.7V (Note)
V
VCC ≥ 2.7V (Note)
Low level input voltage
Low level output voltage
-0.3
0.3 VCC
0.4
V
VCC < 2.7V (Note)
—
V
IOL = 2.1 mA
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
IOH =-400 µA
High level output voltage
Input leakage current
Output leakage current
VCC -0.5
-10
—
V
10
µA
µA
pF
CS = VCC, VIN = VSS TO VCC
CS = VCC, VOUT = VSS TO VCC
ILO
-10
10
Internal Capacitance
(all inputs and outputs)
CINT
—
7
TAMB = 25˚C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
ICC Read
ICC Write
ICCS
—
—
1
500
mA
µA
VCC = 5.5V; FCLK=3.0 MHz; SO = Open
VCC = 2.5V; FCLK=2.0 MHz; SO = Open
Operating Current
Standby Current
—
—
5
3
mA
mA
VCC= 5.5V
VCC = 2.5V
—
—
5
2
µA
µA
CS = Vcc = 5.5V, Inputs tied to VCC or VSS
CS = Vcc = 2.5V, Inputs tied to VCC or VSS
Note: This parameter is periodically sampled and not 100% tested.
DS21204B-page 2
1998 Microchip Technology Inc.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
25AA040/25LC040/25C040
TABLE 1-4:
AC CHARACTERISTICS
All parameters apply over the
specified operating ranges
unless otherwise noted.
Commercial (C): Tamb = 0°C to +70°C
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
Industrial (I):
Tamb = -40°C to +85°C
Automotive (E):
Tamb = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)
Parameter
Symbol
Min
Max
Units
Test Conditions
Clock Frequency
FCLK
—
—
—
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
CS Setup Time
CS Hold Time
TCSS
TCSH
100
250
500
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
CS Disable Time
Data Setup Time
TCSD
TSU
500
—
ns
30
50
50
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Data Hold Time
THD
50
100
100
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
CLK Rise Time
CLK Fall Time
Clock High Time
TR
TF
—
—
2
2
µs
µs
(Note 1)
(Note 1)
THI
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Clock Low Time
TLO
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Clock Delay Time
Clock Enable Time
TCLD
TCLE
TV
50
50
—
—
ns
ns
Output Valid from
Clock Low
—
—
—
150
250
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Output Hold Time
THO
TDIS
0
—
ns
(Note 1)
Output Disable Time
—
—
—
200
250
500
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
HOLD Setup Time
THS
THH
THZ
THV
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
HOLD Hold Time
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
HOLD Low to Output High-Z
HOLD High to Output Valid
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Internal Write Cycle Time
Endurance
TWC
—
—
5
ms
1M
—
E/W Cycles (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our website.
1998 Microchip Technology Inc.
DS21204B-page 3
Powered by ICminer.com Electronic-Library Service CopyRight 2003
25AA040/25LC040/25C040
FIGURE 1-5: HOLD TIMING
CS
THH
THS
THS
THH
SCK
SO
THZ
THV
high impedance
don’t care
n
TSU
n
n+2
n+2
n+1
n
n-1
n+1
n
n-1
SI
HOLD
FIGURE 1-6: SERIAL INPUT TIMING
TCSD
CS
TCLE
TCLD
TR
TCSS
TF
TCSH
Mode 1,1
Mode 0,0
Tsu
SCK
SI
THD
MSB in
LSB in
high impedance
SO
FIGURE 1-7: SERIAL OUTPUT TIMING
CS
TCSH
THI
TLO
Mode 1,1
Mode 0,0
SCK
TV
TDIS
THC
MSB out
ISB out
SO
SI
don’t care
DS21204B-page 4
1998 Microchip Technology Inc.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
25AA040/25LC040/25C040
2.5
Write Protect (WP)
2.0
PIN DESCRIPTIONS
This pin is a hardware write protect input pin. When
WP is low, all writes to the array or status register are
disabled, but any other operation functions normally.
When WP is high, all functions, including non-volatile
writes operate normally. WP going low at any time will
reset the write enable latch and inhibit programming,
except when an internal write has already begun. If an
internal write cycle has already begun, WP going low
will have no effect on the write. See Table 3-7 for Write
Protect Functionality Matrix.
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already initi-
ated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a pro-
gram cycle, the device will go in standby mode as
soon as the programming cycle is complete. As soon
as the device is deselected, SO goes to the high
impedance state, allowing multiple parts to share the
same SPI bus. A low to high transition on CS after a
valid write sequence initiates an internal write cycle.
After power-up, a low level on CS is required prior to
any sequence being initiated.
2.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25xx040 while in the middle of a serial sequence with-
out having to re-transmit the entire sequence over at a
later time. It must be held high any time this function is
not being used. Once the device is selected and a
serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication with-
out resetting the serial sequence. The HOLD pin must
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low transition. The 25xx040 must remain selected dur-
ing this sequence. The SI, SCK, and SO pins are in a
high impedance state during the time the part is
paused and transitions on these pins will be ignored.
To resume serial communication, HOLD must be
brought high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
2.2
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.3
Serial Output (SO)
The SO pin is used to transfer data out of the 25xx040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.4
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25xx040. Instructions,
addresses, or data present on the SI pin are latched
on the rising edge of the clock input, while data on the
SO pin is updated after the falling edge of the clock
input.
1998 Microchip Technology Inc.
DS21204B-page 5
Powered by ICminer.com Electronic-Library Service CopyRight 2003
25AA040/25LC040/25C040
3.3
Write Sequence
3.0
FUNCTIONAL DESCRIPTION
Prior to any attempt to write data to the 25xx040, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-5). This is done by setting CS low
and then clocking out the proper instruction into the
25xx040. After all eight bits of the instruction are trans-
mitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.
3.1
PRINCIPLES OF OPERATION
The 25xx040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25xx040 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. The CS pin must be low
and the HOLD pin must be high for the entire opera-
tion. The WP pin must be held high to allow writing to
the memory array.
Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issuing a write instruction,
followed by the address, and then the data to be writ-
ten. Keep in mind that the most significant address bit
(A8) is included in the instruction byte. Up to 16 bytes
of data can be sent to the 25xx040 before a write cycle
is necessary. The only restriction is that all of the bytes
must reside in the same page. A page address begins
with XXXX 0000 and ends with XXXX 1111. If the
internal address counter reaches XXXX 1111 and the
clock continues, the counter will roll back to the first
address of the page and overwrite any data in the
page that may have been written.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The most signif-
icant address bit (A8) is located in the instruction byte.
All instructions, addresses, and data are transferred
MSB first, LSB last.
Data is sampled on the first rising edge of SCK after
CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25xx040 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
th
of the n data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-3 and Figure 3-4
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the status register may
be read to check the status of the WIP, WEL, BP1, and
BP0 bits (Figure 3-8). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
3.2
Read Sequence
The part is selected by pulling CS low. The 8-bit read
instruction with the A8 address bit is transmitted to the
25xx040 followed by the lower 8-bit address (A7
through A0). After the correct read instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin.The data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses. The
internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by raising the
CS pin (Figure 3-2).
TABLE 3-1:
INSTRUCTION SET
Instruction Name
Instruction Format
0000 A 011
Description
READ
WRITE
WRDI
WREN
RDSR
WRSR
th
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read status register
8
0000 A 010
8
0000 0100
0000 0110
0000 0101
0000 0001
Write status register
Note: A is the 9 address bit necessary to fully address 512 bytes.
8
DS21204B-page 6
1998 Microchip Technology Inc.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
25AA040/25LC040/25C040
FIGURE 3-2: READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
instruction
A8
lower address byte
0
0
0
0
0
1
1
A7
6
5
4
3
2
1
A0
don’t care
data out
high impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-3: BYTE WRITE SEQUENCE
CS
twc
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
data byte
instruction
A8
lower address byte
7
A0
6
5
4
3
2
1
0
0
0
0
0
0
1
0
A7
6
5
4
3
2
1
high impedance
SO
FIGURE 3-4: PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 13 14 15 16 17 18 19 20 21 22 23 24
SCK
SI
instruction
A8
lower address byte
data byte 1
3
0
0
0
0
0
1
0
A7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
CS
25 26 27 28 29 30 31 32
data byte 2
34 35 36 37 38 39 40
data byte 3
33
SCK
SI
data byte n (16 max)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1998 Microchip Technology Inc.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DS21204B-page 7
25AA040/25LC040/25C040
The following is a list of conditions under which the
write enable latch will be reset:
3.4
Write Enable (WREN) and Write
Disable (WRDI)
• Power-up
The 25xx040 contains a write enable latch.
See
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
• WP line is low
Table 3-10 for the Write Protect Functionality Matrix.
This latch must be set before any write operation will
be completed internally. The WREN instruction will set
the latch, and the WRDI will reset the latch.
FIGURE 3-5: WRITE ENABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
high impedance
SO
FIGURE 3-6: WRITE DISABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
high impedance
SO
DS21204B-page 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
1998 Microchip Technology Inc.
25AA040/25LC040/25C040
3.5
Read Status Register (RDSR)
3.6
Write Status Register(WRSR)
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Table 3-7.
7
6
5
4
3
2
1
0
X
X
X
X
BP1
BP0
WEL
WIP
The Write-In-Process (WIP) bit indicates whether the
25xx040 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.
See Figure 3-9 for WRSR timing sequence
TABLE 3-7:
BP1
ARRAY PROTECTION
Array Addresses
BP0
The Write Enable Latch (WEL) bit indicates the sta-
tus of the write enable latch. When set to a ‘1’ the latch
allows writes to the array, when set to a ‘0’ the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the status
register. This bit is read only.
Write Protected
0
0
0
1
none
upper 1/4
(0180h - 01FFh)
upper 1/2
(0100h - 01FFh)
1
1
0
1
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
all
(0000h - 01FFh)
See Figure 3-8 for RDSR timing sequence
FIGURE 3-8: READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
SI
instruction
0
0
0
0
0
1
0
1
data from status register
high impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-9: WRITE STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
data to status register
SCK
SI
instruction
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
high impedance
SO
1998 Microchip Technology Inc.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DS21204B-page 9
25AA040/25LC040/25C040
3.7
Data Protection
3.8
Power On State
The following protection has been implemented to pre-
vent inadvertent writes to the array:
The 25xx040 powers on in the following state:
• The device is in low power standby mode
(CS= 1).
• The write enable latch is reset.
• SO is in high impedance state.
• A low level on CS is required to enter active state.
• The write enable latch is reset on power-up.
• A write enable instruction must be issued to set
the write enable latch.
• After a byte write, page write, or status register
write, the write enable latch is reset.
• CS must be set high after the proper number of
clock cycles to start an internal write cycle.
• Access to the array during an internal write cycle
is ignored and programming is continued.
• The write enable latch is reset when the WP pin is
low.
.
TABLE 3-10: WRITE PROTECT FUNCTIONALITY MATRIX
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
Low
High
High
X
0
1
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Protected
Writable
DS21204B-page 10
1998 Microchip Technology Inc.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
25AA040/25LC040/25C040
25AA040/25LC040/25C040 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
25xx040 /P
—
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = TSSOP, 8-lead
Package:
Blank = 0°C to +70°C
I = –40°C to +85°C
E = –40°C to +125°C
Temperature
Range:
25AA040
25AA040T
25AA040X
4096 bit 1.8V SPI Serial EEPROM
4096 bit 1.8V SPI Serial EEPROM Tape and Reel
4096 bit 1.8V SPI Serial EEPROM
in alternate pinout (ST only)
25AA040XT
4096 bit 1.8V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
4096 bit 2.5V SPI Serial EEPROM
4096 bit 2.5V SPI Serial EEPROM Tape and Reel
4096 bit 2.5V SPI Serial EEPROM
in alternate pinout (ST only)
25LC040
25LC040T
25LC040X
Devices:
25LC040XT
4096 bit 2.5V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
4096 bit 5.0V SPI Serial EEPROM
4096 bit 5.0V SPI Serial EEPROM Tape and Reel
4096 bit 5.0V SPI Serial EEPROM
in alternate pinout (ST only)
25C040
25C040T
25C040X
25C040XT
4096 bit 5.0V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Web Site (www.microchip.com)
1998 Microchip Technology Inc.
DS21204B-page 11
Powered by ICminer.com Electronic-Library Service CopyRight 2003
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
Microchip Technology Inc.
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Powered by ICminer.com Electronic-Library Service CopyRight 2003
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明