28F004BL-B
更新时间:2024-09-18 02:44:41
品牌:ETC
描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
28F004BL-B 概述
4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
4 MBLT ( 256K x 16位512K ×8 )低功耗BOOT BLOCK闪存系列\n
28F004BL-B 数据手册
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PDF下载4-MBlT (256K x 16, 512K x 8)
LOW-POWER BOOT BLOCK
FLASH MEMORY FAMILY
28F400BL-T/B, 28F004BL-T/B
Y
Y
Low Voltage Operation for Very
Low-Power Portable Applications
SRAM-Compatible Write Interface
Automatic Power Savings Feature
Y
Y
e
e
Ð V
Ð V
3.0V–3.6V Read
3.15V–3.6V Program/Erase
CC
CC
Ð 0.8 mA typical I
Static Operation
Active Current in
CC
Y
Y
Expanded Temperature Range
b
Very High-Performance Read
Ð 150 ns Maximum Access Time
Ð 65 ns Maximum Output Enable Time
a
20 C to 70 C
Ð
§
§
x8/x16 Input/Output Architecture
Ð 28F400BL-T, 28F400BL-B
Ð For High Performance and High
Integration 16-bit and 32-bit CPUs
Y
Y
Low Power Consumption
Ð 15 mA Typical Active Read Current
Reset/Deep Power-Down Input:
Y
x8-only Input/Output Architecture
Ð 28F004BL-T, 28F004BL-B
Ð For Space Constrained 8-bit
Applications
Ð 0.2 mA I
Typical
Ð Acts as Reset for Boot Operations
CC
Y
Y
Write Protection for Boot Block
Hardware Data Protection Feature
Ð Erase/Write Lockout During Power
Transitions
Y
Y
Upgradeable to Intel’s SmartVoltage
Products
Optimized High Density Blocked
Architecture
Ð One 16-KB Protected Boot Block
Ð Two 8-KB Parameter Blocks
Ð One 96-KB Main Block
Y
Industry Standard Surface Mount
Packaging
Ð 28F400BL: JEDEC ROM
Compatible
44-Lead PSOP
Ð Three 128-KB Main Blocks
Ð Top or Bottom Boot Locations
56-Lead TSOP
Ð 28F004BL: 40-Lead TSOP
Y
Y
Extended Cycling Capability
Ð 10,000 Block Erase Cycles
Y
Y
12V Word/Byte Write and Block Erase
e
g
12V 5% Standard
Ð V
PP
Automated Word/Byte Write and Block
Erase
Ð Command User Interface
Ð Status Registers
Ð Erase Suspend Capability
ETOXTM III Flash Technology
Ð 3.3V Read
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1995
Order Number: 290450-005
28F400BL-T/B, 28F004BL-T/B
Intel’s 4-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes
block-selective erasure, automated write and erase operations and standard microprocessor interface. The
4-Mbit Low Power Flash Memory Family enhances the Boot Block Architecture by adding more density and
blocks, x8/x16 input/output control, very low power, very high speed, an industry standard ROM compatible
pinout and surface mount packaging. The 4-Mbit low power flash family opens a new capability for 3V battery-
operated portable systems and is an easy upgrade to Intel’s 2-Mbit Low Power Boot Block Flash Memory
Family.
The Intel 28F400BL-T/B are 16-bit wide low power flash memory offerings. These high density flash memories
provide user selectable bus operation for either 8-bit or 16-bit applications. The 28F400BL-T and 28F400BL-B
are 4,194,304-bit non-volatile memories organized as either 524,288 bytes or 262,144 words of information.
They are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the
industry standard ROM/EPROM pinout. The Intel 28F004BL-T/B are 8-bit wide low power flash memories
with 4,194,304 bits organized as 524,288 bytes of information. They are offered in a 40-Lead TSOP package,
which is ideal for space-constrained portable systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F400BL-T/28F004BL-T provide block locations compatible with
Intel’s Low Voltage MCS-186 family, i386TM, i486TM microprocessors. The 28F400BL-B/28F004BL-B provide
compatibility with Intel’s 80960KX and 80960SX families as well as other low voltage embedded microproces-
sors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 150 ns, these 4-Mbit low power flash devices are very high performance memories at
3.3V which interface to a wide range of low voltage microprocessors and microcontrollers. A deep power-
down mode lowers the total V power consumption to 0.66 mW which is critical in handheld battery powered
CC
systems such as Handy Cellular Phones. For very high speed applications using a 5V supply, refer to the Intel
28F400BX-T/B, 28F004BX-T/B 4-Mbit Boot Block Flash Memory family datasheet.
Manufactured on Intel’s 0.8 micron ETOX III process, the 4-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 4 Mbit density level.
2
28F400BL-T/B, 28F004BL-T/B
1.0 PRODUCT FAMILY OVERVIEW
1.2 Main Features
Throughout this datasheet 28F400BL refers to both
the 28F400BL-T and 28F400BL-B devices and
28F004BL refers to both the 28F004BL-T and
28F004BL-B devices. The 4-Mbit flash family refers
to both the 28F400BL and 28F004BL products. This
datasheet comprises the specifications for four sep-
arate products in the 4-Mbit flash family, Section 1
provides an overview of the 4-Mbit flash family in-
cluding applications, pinouts and pin descriptions.
Sections 2 and 3 describe in detail the specific mem-
ory organizations for the 28F400BL and 28F004BL
products respectively, Section 4 combines a de-
scription of the family’s principles of operations. Fi-
nally section 5 describes the family’s operating
specifications.
The 28F400BL/28F004BL boot block flash memory
family is a very high performance 4-Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.
Seven Separately Erasable Blocks including a
Hardware-Lockable boot block (16,384 Bytes),
two parameter blocks (8,192 Bytes each) and four
main blocks (1 block of 98,304 Bytes and 3 blocks
of 131,072 Bytes) are included on the 4-Mbit family.
An erase operation erases one of the main blocks in
typically 3.4 seconds and the boot or parameter
blocks in typically 2.0 seconds, independent of the
remaining blocks. Each block can be independently
erased and programmed 10,000 times.
Product Family
The Boot Block is located at either the top (-T) or
the bottom (-B) of the address map in order to ac-
commodate different microprocessor protocols for
boot code location. The hardware Iockable boot
block provides the most secure code storage. The
boot block is intended to store the kernel code re-
x8/x16 Products
28F400BL-T
x8-Only Products
28F004BL-T
28F400BL-B
28F004BL-B
Ý
quired for booting-up a system. When the RP pin is
1.1 Designing for Upgrade to
SmartVoltage Products
between 11.4V and 12.6V the boot block is unlocked
and program and erase operations can be per-
Ý
formed. When the RP pin is at or below 4.1V the
Today’s high volume boot block products are up-
gradeable to Intel’s SmartVoltage boot block prod-
ucts that provide program and erase operation at 5V
boot block is locked and program and erase opera-
tions to the boot block are ignored.
or 12V V
and read operation at 3V or 5V V
.
The 28F400BL products are available in the
ROM/EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2mm thick)
PP
CC
Intel’s SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this datasheet:
package as shown in Figures
28F004BL products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.
3 and 4, The
Ý
1. DU pin is replaced by WP to provide a means to
lock and unlock the boot block with logic signals.
2. 5V Program/Erase operation uses proven pro-
g
gram and erase techniques with 5V 10% ap-
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon-
troller and the internal operation of the 28F400BL
and 28F004BL flash memory products.
plied to V
.
PP
3. Enhanced circuits optimize performance at 3.3V
.
V
CC
Refer to the 2, 4 or 8Mbit SmartVoltage Boot Block
Flash Memory datasheets for complete specifica-
tions.
Program and Erase Automation allow program
and erase operations to be executed using a two-
write command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there-
by unburdening the microprocessor or microcontrol-
ler. Writing of memory data is performed in word or
byte increments for the 28F400BL family and in byte
increments for the 28F004BL family typically within
11 ms.
When you design with 12V V boot block products
PP
you should provide the capability in your board de-
sign to upgrade to SmartVoltage products.
Follow these guidelines to ensure compatibility:
Ý
1. Connect DU (WP on SmartVoltage products) to
a control signal or to V or GND.
CC
2. If adding a switch on V for write protection,
PP
switch to GND for complete write protection.
3. Allow for connecting 5V to V and disconnect
PP
12V from the V line, if desired.
PP
3
28F400BL-T/B, 28F004BL-T/B
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
For the 2SF400BL, Byte-wide or Word-wide In-
put/Output Control is possible by controlling the
Ý
Ý
BYTE pin. When the BYTE pin is at a logic low
the device is in the byte-wide mode (x8) and data is
[ ]
read and written through DQ 0:7 . During the byte-
Maximum Access Time of 150 ns (t
over the commercial temperature range (0 C to
) is achieved
§
ACC
b
1
becomes the lowest order address pin. When the
[
]
wide mode, DQ 8:14 are tri-stated and DQ15/A
a
4.5V to 5.5V) and 50 pF output load.
70 C), V
supply voltage range (3.0V to 3.6V,
§
CC
Ý
BYTE pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
[
]
through DQ 0:15 .
I
Program current is 40 mA for x16 operation
and 30 mA for x8 operation. I Erase current is
pp
PP
erase and programming
30 mA maximum. V
PP
voltage is 11.4V to 12.6V (V
der all operating conditions.
e
g
12V 5%) un-
1.3 Applications
PP
The 4-Mbit low power boot block flash memory fami-
ly combines high density, very low power, high per-
formance, cost-effective flash memories with block-
ing and hardware protection capabilities. Its flexibility
and versatility will reduce costs throughout the prod-
uct life cycle. Flash memory is ideal for Just-In-Time
production flow, reducing system inventory and
costs, and eliminating component handling during
the production phase. During the product life cycle,
when code updates or feature enhancements be-
come necessary, flash memory will reduce the up-
date costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link. The 4-Mbit flash family provides full
function, blocked flash memories suitable for a wide
range of applications. These applications include
Extended PC BIOS and ROM-able applications
storage, Handy Digital Cellular Phone program
and data storage and various other low power em-
bedded applications where both program and data
storage are required.
Typical I Active Current of 15 mA is achieved
CC
for the x16 products and the x8 products.
The 4-Mbit flash family is also designed with an Au-
tomatic Power Savings (APS) feature to minimize
system battery current drain and allow for very low
power designs. Once the device is accessed to read
the array data, APS mode will immediately put the
memory in static mode of operation where I active
CC
current is typically 0.8 mA until the next read is initia-
ted.
Ý
Ý
When the CE and RP pins are at V
BYTE pin (28F400BX-L-only) is at either V
and the
CC
Ý
or
CC
GND the CMOS Standby mode is enabled where
is typically 45 mA.
I
CC
A Deep Power-Down Mode is enabled when the
PWD pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions. I
current during deep power-down mode
CC
Portable systems such as Notebook/Palmtop com-
puters, are ideal applications for the 4-Mbit low pow-
er flash products. Portable and handheld personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest microprocessor tech-
nology, the availability of ROM-based application
software, pen tablet code for electronic hand writing,
and diagnostic code. Figure 1 shows an example of
a 28F400BL-T application.
is 0.20 mA typical. An initial maximum access time
Ý
or Reset Time of 600 ns is required from RP
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 1 ms until
writes to the Command User Interface are recog-
Ý
nized. When RP is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre-
vents data corruption and protects the code stored
in the device during system reset. The system Reset
Ý
pin can be tied to RP to reset the memory to nor-
This increase in software sophistication augments
the probability that a code update will be required
after the Notebook is shipped. The 4-Mbit flash
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 4-Mbit flash products’ deep power-down mode
provides added flexibility for these battery-operated
portable designs which require operation at very low
power levels.
mal read mode upon activation of the Reset pin.
When the CPU enters reset mode, it expects to read
the contents of a memory location. Furthermore,
with on-chip program/erase automation in the
Ý
4-Mbit family and the RP functionality for data pro-
tection, when the CPU is reset and even if a program
or erase command is issued, the device will not rec-
Ý
ognize any operation until RP returns to its normal
state.
4
28F400BL-T/B, 28F004BL-T/B
The 4-Mbit low power flash products also provide
excellent design solutions for Handy Digital Cellular
Phone applications requiring low voltage supply,
high performance, high density storage capability
coupled with modular software designs, and a small
form factor package (x8-only bus). The 4-Mbit’s
blocking scheme allows for an easy segmentation of
the embedded code with; 16-Kbytes of Hardware-
Protected Boot code, 4 Main Blocks of program
code and 2 Parameter Blocks of 8-Kbytes each for
frequently updatable data storage and diagnostic
messages (e.g., phone numbers, authorization
codes). Figure 2 is an example of such an applica-
tion with the 28F004BL-T.
These are a few actual examples of the wide range
of applications for the 4-Mbit low power Boot Block
flash memory family which enable system designers
achieve the best possible product design. Only your
imagination limits the applicability of such a versatile
low power product family.
290450–7
Figure 1. 28F400BL Interface to Intel386TM EX Embedded Processor
290450–23
Figure 2. 28F004BL Interface to INTEL 80L188EB Low Voltage 8-bit Embedded Processor
5
28F400BL-T/B, 28F004BL-T/B
1.4 Pinouts
pinout shown in Figure 4 provides density upgrades
to future higher density boot block memories.
The 28F400BL 44-Lead PSOP pinout follows the
industry standard ROM/EPROM pinout as shown
The 28F004BL 40-Lead TSOP pinout shown in Fig-
ure 5 is 100% compatible and provides a density
upgrade for the 28F002BL 2-Mbit Low Power Boot
Block flash memory family.
in Figure
3 and provides an upgrade for the
28F200BL Low Power Boot Block flash memory
family. Furthermore, the 28F400BL 56-Lead TSOP
290450–24
Figure 3. PSOP Lead Configuration for x8/x16 28F400BL
6
28F400BL-T/B, 28F004BL-T/B
290450–6
Figure 4. TSOP Lead Configuration for x8 28F400BL
290450–5
Figure 5. TSOP Lead Configuration for x8 28F004BL
7
28F400BL-T/B, 28F004BL-T/B
1.5 Pin Descriptions for x8/x16 28F400BL
Symbol
A –A
Type
Name and Function
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.
0
17
A
I
ADDRESS INPUT: When A is at 12V the signature mode is accessed. During this
9
9
Ý
mode A decodes between the manufacturer and device ID’s. When BYTE is at
b
0
a logic low only the lower byte of the signatures are read. DQ /A
Ý
care in the signature mode when BYTE is low.
is a don’t
1
15
Ý
Ý
DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
during a program command. Inputs commands to the command user interface
DQ –DQ
0
I/O
7
Ý
Ý
when CE and WE are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
Ý
Ý
DQ –DQ
8
I/O
DATA INPUT/OUTPUTS: Inputs array data on the second CE and WE cycle
during a program command. Data is internally latched during the write and program
cycles. The data pins float to tri-state when the chip is deselected or the outputs
15
e
DQ /A becomes the lowest order address for data output on DQ –DQ .
Ý
are disabled as in the byte-wide mode (BYTE
b
‘‘0’’). In the byte-wide mode
15
1
0
7
Ý
Ý
CE
RP
I
I
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
Ý
Ý
sense amplifiers. CE is active low; CE high deselects the memory device and
Ý
Ý
reduces power consumption to standby levels. If CE and RP are high, but not
at a CMOS high level, the standby current will increase due to current flow through
Ý
Ý
the CE and RP input stages.
RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the boot block from program/erase.
Ý
When RP is at logic high level and equals 4.1V maximum the boot block is
locked and cannot be programmed or erased.
e
Ý
When RP
or erased.
11.4V minimum the boot block is unlocked and can be programmed
Ý
When RP is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
Ý
transitions. When RP transitions from logic low to logic high, the flash memory
enters the read-array mode.
Ý
OE
I
I
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
Ý
read cycle. OE is active low.
Ý
WE
WRITE ENABLE: Controls writes to the Command Register and array blocks.
Ý
WE is active low. Addresses and data are latched on the rising edge of the WE
pulse.
Ý
8
28F400BL-T/B, 28F004BL-T/B
1.5 Pin Descriptions for x8/x16 28F400BL (Continued)
Symbol
Type
Name and Function
Ý
Ý
BYTE
I
BYTE ENABLE: Controls whether the device operates in the byte-wide mode (x8) or
e
Ý
the word-wide mode (x16). BYTE
read and programmed on DQ –DQ and DQ /A
b
1
‘‘0’’ enables the byte-wide mode, where data is
becomes the lowest order
0
7
15
address that decodes between the upper and lower byte. DQ –DQ are tri-stated
8
14
‘‘1’’ enables the word-wide mode where data is
e
Ý
during the byte-wide mode. BYTE
read and programmed on DQ –DQ
.
15
0
V
V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
PP
CC
k
Note: V
V
memory contents cannot be altered.
PP
PPLMAX
g
g
DEVICE POWER SUPPLY (3.3V 0.3, 5V 10%)
GROUND: For all internal circuitry.
GND
NC
NO CONNECT: Pin may be driven or left floating.
DON’T USE PIN: Pin should not be connected to anything.
DU
9
28F400BL-T/B, 28F004BL-T/B
1.6 Pin Descriptions for x8 28F004BL
Symbol
A –A
Type
Name and Function
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
0
18
A
I
ADDRESS INPUT: When A is at 12V the signature mode is accessed. During this
9
mode A decodes between the manufacturer and device ID’s.
9
0
Ý
Ý
DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
during a program command. Inputs commands to the command user interface
DQ –DQ
0
I/O
7
Ý
Ý
when CE and WE are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
Ý
Ý
CE
RP
I
I
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
Ý
Ý
sense amplifiers. CE is active low; CE high deselects the memory device and
reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
Ý
When RP is at logic high level and equals 4.1V maximum the Boot Block is locked
and cannot be programmed or erased.
e
Ý
When RP
or erased.
11.4V minimum the Boot Block is unlocked and can be programmed
Ý
When RP is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
Ý
transitions. When RP transitions from logic low to logic high, the flash memory
enters the read-array mode.
Ý
OE
I
I
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
Ý
read cycle. OE is active low.
Ý
Ý
WE
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE
Ý
is active low. Addresses and data are latched on the rising edge of the WE pulse.
V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
PP
k
Note: V
V
memory contents cannot be altered.
PPLMAX
PP
g
g
V
DEVICE POWER SUPPLY (3.3V 0.3V, 5V 10%)
GROUND: For all internal circuitry.
CC
GND
NC
NO CONNECT: Pin may be driven or left floating.
DON’T USE PIN: Pin should not be connected to anything.
DU
10
28F400BL-T/B, 28F004BL-T/B
2.0 28F400BL PRODUCTS DESCRIPTION
Figure 6. 28F400BL Word/Byte-Wide Block Diagram
11
28F400BL-T/B, 28F004BL-T/B
2.1.2 BLOCK MEMORY MAP
2.1 28F400BL Memory Organization
Two versions of the 28F400BL product exist to sup-
port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F400BL-T
memory map is inverted from the 28F400BL-B mem-
ory map.
2.1.1 BLOCKING
The 28F400BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F400BL is
a random read/write memory, only erasure is per-
formed by block.
2.1.2.1 28F400BL-B Memory Map
The 28F400BL-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H. In the
28F400BL-B the first 8-Kbyte parameter block re-
sides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to 0FFFFH. The three 128-Kbyte main
block resides in memory space from 10000H to
1FFFFH, 20000H to 2FFFFH and 30000H to
3FFFFH (word locations). See Figure 7.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
Ý
erased when RP is not at 12V. The boot block can
be erased and written when RP is held at 12V for
Ý
(Word Addresses)
3FFFFH
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address lo-
cations of the boot block for the 28F400BL-T and
28F400BL-B.
128-Kbyte MAIN BLOCK
30000H
2FFFFH
2.1.1.2 Parameter Block Operation
128-Kbyte MAIN BLOCK
The 28F400BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa-
rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. The parameter blocks pro-
vide for more efficient memory utilization when deal-
ing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for ad-
dress locations of the parameter blocks for the
28F400BL-T and 28F400BL-B.
20000H
1FFFFH
128-Kbyte MAIN BLOCK
10000H
0FFFFH
96-Kbyte MAIN BLOCK
04000H
03FFFH
8-Kbyte PARAMETER BLOCK
03000H
02FFFH
8-Kbyte PARAMETER BLOCK
02000H
2.1.1.3 Main Block Operation
01FFFH
16-Kbyte BOOT BLOCK
Four main blocks of memory exist on the 28F400BL
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F400BL-T
and 28F400BL-B products.
00000H
Figure 7. 28F400BL-B Memory Map
12
28F400BL-T/B, 28F004BL-T/B
2.1.2.2 28F400BL-T Memory Map
The 28F400BL-T device has the 16-Kbyte boot
block located from 3E000H to 3FFFFH to accommo-
date those microprocessors that boot from the top
of the address map. In the 28F400BX-T the first
8-Kbyte parameter block resides in memory space
from 3D000H to 3DFFFH. The second 8-Kbyte pa-
rameter block resides in memory space from
3C000H to 3CFFFH. The 96-Kbyte main block re-
sides in memory space from 30000H to 3BFFFH.
The three 128-Kbyte main blocks reside in memory
space from 20000H to 2FFFFH, 10000H to 1FFFFH
and 00000H to 0FFFFH as shown in Figure 8.
(Word Addresses)
3FFFFH
16-Kbyte BOOT BLOCK
3E000H
3DFFFH
8-Kbyte PARAMETER BLOCK
3D000H
3CFFFH
8-Kbyte PARAMETER BLOCK
3C000H
3BFFFH
96-Kbyte MAIN BLOCK
30000H
2FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
10000H
0FFFFH
128-Kbyte MAIN BLOCK
00000H
Figure 8. 28F400BL-T Memory Map
13
28F400BL-T/B, 28F004BL-T/B
3.0 28F004BL PRODUCTS DESCRIPTION
Figure 9. 28F004BL and Byte-Wide Block Diagram
14
28F400BL-T/B, 28F004BL-T/B
3.1.2 BLOCK MEMORY MAP
3.1 28F004BL Memory Organization
Two versions of the 28F004BL product exist to sup-
port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F004BL-T
memory map is inverted from the 28F004BL-B mem-
ory map.
3.1.1 BLOCKING
The 28F004BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUl. The 28F004BL is
a random read/write memory, only erasure is per-
formed by block.
3.1.2.1 28F004BL-B Memory Map
The 28F004BL-B device has the 16-Kbyte boot
block located from 00000H to 03FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H. In the
28F004BL-B the first 8-Kbyte parameter block re-
sides in memory from 04000H to 05FFFH. The sec-
ond 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The three 128-Kbyte main blocks reside in
memory space from 20000H to 3FFFFH, 40000H to
5FFFFH and 60000H to 7FFFH. See Figure 10.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
Ý
or erased when RP is not at 12V. The boot block
can be erased and programmed when RP is held
Ý
7FFFFH
at 12V for the duration of the erase or program oper-
ation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F004BL-T and 28F004BL-B.
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
3.1.1.2 Parameter Block Operation
40000H
3FFFFH
The 28F004BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa-
rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map sec-
tion for address locations of the parameter blocks
for the 28F004BL-T and 28F004BL-B.
128-Kbyte MAIN BLOCK
20000H
1FFFFH
96-Kbyte MAIN BLOCK
08000H
07FFFH
8-Kbyte PARAMETER BLOCK
06000H
05FFFH
8-Kbyte PARAMETER BLOCK
04000H
03FFFH
16-Kbyte BOOT BLOCK
3.1.1.3 Main Block Operation
00000H
Two main blocks of memory exist on the 28F004BL
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F004BL-T
and 28F004BL-B.
Figure 10. 28F004BL-B Memory Map
15
28F400BL-T/B, 28F004BL-T/B
3.1.2.2 28F004BL-T Memory Map
4.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
The 28F004BL-T device has the 16-Kbyte boot
block located from 7C000H to 7FFFFH to accom-
modate those microprocessors that boot from the
top of the address map. In the 28F004BL-T the first
8-Kbyte parameter block resides in memory space
from 7A000H to 7BFFFH. The second 8-Kbyte pa-
rameter block resides in memory space from
78000H to 79FFFH. The 96-Kbyte main block re-
sides in memory space from 60000H to 77FFFH.
The three 128-Kbyte main blocks reside in memory
space from 40000H to 5FFFFH, 20000H to 3FFFFH
and 00000H to 1FFFFH.
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 4-Mbit flash
memory family utilizes a Command User Interface
(CUI) and internally generated and timed algorithms
to simplify write and erase operations.
The CUI allows for fixed power supplies during era-
sure and programming, and maximum EPROM com-
patibility.
In the absence of high voltage on the V pin, the
PP
4-Mbit flash family will only successfully execute the
following commands: Read Array, Read Status Reg-
ister, Clear Status Register and Intelligent Identifier
mode. The device provides standard EPROM read,
standby and output disable operations. Manufactur-
er Identification and Device Identification data can
be accessed through the CUI or through the stan-
7FFFFH
16-Kbyte BOOT BLOCK
7C000H
7BFFFH
8-Kbyte PARAMETER BLOCK
7A000H
dard EPROM A9 high voltage access (V ) (for
ID
PROM programmer equipment).
79FFFH
8-Kbyte PARAMETER BLOCK
78000H
77FFFH
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the V pin. In addition, high voltage on V al-
lows write and erase of the device. All functions as-
sociated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
96-Kbyte MAIN BLOCK
PP
PP
60000H
5FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
128-Kbyte MAIN BLOCK
20000H
1FFFFH
Ý
WE interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
128-Kbyte MAIN BLOCK
00000H
4.1 28F400BL Bus Operations
Figure 11. 28F004BL-T Memory Map
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
16
28F400BL-T/B, 28F004BL-T/B
e
Ý
Table 1. Bus Operations for WORD-WIDE Mode (BYTE
V )
IH
Ý
Ý
Ý
Ý
WE
Mode
Notes
RP
CE
OE
A
A
V
DQ
0-15
9
0
PP
Read
1, 2
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
D
OUT
IH
IL
IL
IH
Output Disable
V
IH
X
X
X
X
X
X
High Z
High Z
High Z
0089H
IH
IH
IL
IH
Standby
V
X
X
IH
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
9
V
X
X
X
IL
IH
IH
3, 4
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IH
IH
ID
ID
IL
3, 4, 5, 10
V
V
V
V
4470H
4471H
IH
Write
6, 7, 8
V
V
V
IH
V
IL
X
X
X
D
IN
IH
IL
e
Ý
Table 2. Bus Operations for BYTE-WIDE Mode (BYTE
V )
IL
Ý
Ý
Ý
Ý
WE
Mode
Notes
RP
CE
OE
A
9
A
0
A
V
DQ
DQ
8–14
-1
PP
0-7
Read
1, 2
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
D
High Z
IH
IL
IL
IH
OUT
Output Disable
Standby
V
IH
X
X
X
X
X
X
X
X
X
X
High Z High Z
High Z High Z
High Z High Z
IH
IH
IL
IH
V
IH
X
X
Deep Power-Down
V
X
X
X
IL
Intelligent Identifier
(Mfr)
3, 4
V
V
V
V
IL
V
IL
V
IL
V
V
IH
V
V
89H
High Z
High Z
High Z
IH
IL
IL
IH
ID
IL
Intelligent Identifier 3, 4, 5, 10
(Device)
V
V
IH
V
V
X
X
X
X
70H
71H
IH
IH
ID
IH
Write
6, 7, 8
V
V
X
X
D
IN
IL
NOTES:
1. Refer to DC Characteristics.
2. X can be V or V for control pins and addresses, V
IL IH
or V
for V
.
PP
PPL
PPH
3. See DC Characteristics for V
, V
, V , V voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A –A
PPL PPH HH ID
e
V .
IL
1
17
e
6. Refer to Table 4 for valid D during a write operation.
5. Device ID
4470H for 28F400BL-T and 4471H for 28F400BL-B.
IN
7. Command writes for Block Erase or Word/Byte Write are only executed when V
e
V
.
PP
PPH
Ý
8. To write or erase the boot block, hold RP at V
.
HH
9. RP must be at GND 0.2V to meet the 1.2 mA maximum deep power-down current.
10. The device ID codes are identical to those of the 28F400BX 5V version and SmartVoltage equivalent.
Ý
g
17
28F400BL-T/B, 28F004BL-T/B
4.2 28F004BL Bus Operations
Table 3. Bus Operations
Ý
Ý
Ý
Ý
WE
Mode
Notes
RP
CE
OE
A
9
A
0
V
DQ
0-7
PP
Read
1, 2
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
D
OUT
IH
IL
IL
IH
Output Disable
Standby
V
IH
X
X
X
X
X
X
High Z
High Z
High Z
89H
IH
IH
IL
IH
V
X
X
IH
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
9
V
X
X
X
IL
IH
IH
3, 4
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IH
IH
ID
ID
IL
3, 4, 5, 10
V
V
V
V
78H
79H
IH
Write
6, 7, 8
V
IH
V
V
IH
V
IL
X
X
X
D
IN
IL
NOTES:
1. Refer to DC Characteristics.
2. X can be V or V for control pins and addresses, V
or V
for V
.
PP
IL IH
PPL
, V , V voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A –A , A –A
PPH
3. See DC Characteristics for V
, V
PPL PPH HH ID
e
V .
IL
1
8
10
18
e
6. Refer to Table 4 for valid D during a write operation.
5. Device ID
78H for 28F004BL-T and 79H for 28F004BL-B.
IN
7. Command writes for Block erase or byte program are only executed when V
e
V
PPH
.
PP
Ý
8. Program or erase the Boot block by holding RP at V
.
HH
9. RP must be at GND 0.2V to meet the 1.2 mA maximum deep power-down current.
10. The device ID codes are identical to those of the 28F004BX 5V version and SmartVoltage equivalent.
Ý
g
4.3.1.2 Input Control
4.3 Read Operations
Ý
With WE at logic-high level (V ), input to the de-
vice is disabled. Data Input/Output pins (DQ 0:15
The 4-Mbit flash family has three user read modes;
Array, Intelligent Identifier, and Status Register.
Status Register read mode will be discussed in detail
in the ‘‘Write Operations’’ section.
IH
[
]
[
]
Ý
or DQ 0:7 ) are controlled by OE .
4.3.2 INTELLIGENT IDENTlFlERS
28F400BL PRODUCTS
During power-up conditions (V supply ramping), it
at 3.0V mini-
CC
takes a maximum of 600 ns from V
CC
mum to obtain valid data on the outputs.
The manufacturer and device codes are read via the
CUI or by taking the A9 pin to 12V. Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location 00000H outputs the
manufacturer’s identification code, 0089H, and loca-
tion 00001H outputs the device code; 4470H for
28F400BL-T, 4471H for 28F4001BL-B. When
4.3.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode com-
mand to the CUI. The 4-Mbit flash family has three
control functions, all of which must be logically ac-
Ý
tive, to obtain data at the outputs. Chip-Enable CE
Ý
is the device selection control. Power-Down RP is
the device power control. Output-Enable OE is the
DATA INPUT/OUTPUT (DQ 0:15 or DQ 0:7 ) direc-
tion control and when active is used to drive data
from the selected memory onto the I/O bus.
Ý
BYTE is at a logic low only the lower byte of the
above signatures is read and DQ /A is a ‘‘don’t
b
15
1
Ý
]
care’’ during Intelligent Identifier mode. A read array
command must be written to the CUI to return to the
read array mode.
[
]
[
4.3.1.1 Output Control
Ý
With OE at logic-high level (V ), the output from
the device is disabled and data input/output pins
IH
[
]
[
(DQ 0:15 or DQ 0:7 are tri-stated. Data input is
then controlled by WE
]
Ý
.
18
28F400BL-T/B, 28F004BL-T/B
28F004BL PRODUCTS
4.4.1 BOOT BLOCK WRITE OPERATIONS
The manufacturer and device codes are also read
via the CUI or by taking the A9 pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location 00000H out-
puts the manufacturer’s identification code, 89H,
and location 00001H outputs the device code; 78H
for 28F004BL-T, 79H for 28F004BL-B.
In the case of Boot Block modifications (write and
e
Ý
erase), RP is set to V
tion to V at high voltage.
12V typically, in addi-
HH
PP
Ý
However, if RP is not at V
when a program or
HH
erase operation of the boot block is attempted, the
corresponding status register bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for Status Regis-
ter Definitions) is set to indicate the failure to com-
plete the operation.
4.4 Write Operations
Commands are written to the CUI using standard mi-
croprocessor write timings. The CUI serves as the
interface between the microprocessor and the inter-
nal chip operation. The CUI can decipher Read Ar-
ray, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program com-
mands. In the event of a read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state ma-
chine that a write or erase has been requested. Dur-
ing a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full com-
mand set. The CUI will stay in the current command
state until the microprocessor issues another com-
mand.
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a ‘‘1’’, which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Device Mode
Codes
00
10
20
40
50
70
90
B0
D0
FF
Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
The CUI will successfully initiate an erase or write
operation only when V is within its voltage range.
PP
Depending upon the application, the system design-
er may choose to make the V
power supply
PP
switchable, available only when memory updates
are desired. The system designer can also choose
to ‘‘hard-wire’’ V to 12V. The 4-Mbit flash memory
Erase Resume/Erase Confirm
Read Array
PP
family is designed to accommodate either design
Ý
cal Reset for data protection during unstable CPU
reset function as described in the ‘‘Product Family
Overview’’ section.
practice. It is recommended that RP be tied to logi-
4.4.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 4 below defines the
4-Mbit flash memory family commands.
19
28F400BL-T/B, 28F004BL-T/B
Table 4. Command Definitions
Bus
Notes
First Bus Cycle
Second Bus Cycle
Command
Cycles
Req’d
8
1
Operation Address Data Operation Address Data
Read Array
1
3
2
1
2
2
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
20H
40H
Intelligent Identifier
2, 4
3
Read
Read
IA
X
IID
Read Status Register
Clear Status Register
Erase Setup/Erase Confirm
X
SRD
X
5
BA
WA
Write
Write
BA
D0H
WD
Word/Byte Write
Setup/Write
6, 7
WA
Erase Suspend/Erase Resume
2
2
Write
X
B0H
WA
Write
10H
X
D0H
WA
Alternate Word/Byte Write
Setup/Write
WD
2, 3, 7
Write
Write
NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
e
2. IA
Identifier Address: 00H for manufacturer code, 01H for device code.
e
3. SRD
Data read from Status Register.
Intelligent Identifier Data.
Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
e
4. IID
e
5. BA
6. WA
WD
Address within the block being erased.
Address to be written.
Data to be written at location WA.
e
e
7. Either 40H or 10H commands is valid.
8. When writing commands to the device the upper data bus DQ –DQ
to avoid burning additional current.
e
]
[
X (28F400BL-only) which is either V or V
CC SS
8
15
Invalid/Reserved
Read Status Register (70H)
These are unassigned commands. It is not recom-
mended that the customer use any command other
than the valid commands specified above. Intel re-
serves the right to redefine these codes for future
functions.
This is one of the two commands that is executable
while the state machine is operating. After this com-
mand is written, a read of the device will output the
contents of the status register, regardless of the ad-
dress presented to the device.
The device automatically enters this mode after pro-
gram or erase has completed.
Read Array (FFH)
This single write command points the read path at
Ý
Ý
the array. If the host CPU performs a CE /OE
Clear Status Register (50H)
controlled read immediately following a two-write se-
quence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchro-
nization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after pro-
gramming the string. Thus, if any errors exist while
programming the string, the status register wiII re-
turn the accumulated error status.
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A0 is used in this mode, alI
other address inputs are ignored).
20
28F400BL-T/B, 28F004BL-T/B
tinue to run, idling in the SUSPEND state, regardless
of the state of alI input control pins, with the exclu-
Program Setup (40H or 10H)
Ý
Ý
sion of RP . RP low will immediately shut down
the WSM and the remainder of the chip.
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Pro-
gram Setup. Both commands are included to ac-
commodate efforts to achieve an industry standard
command code set.
Erase Resume (D0H)
This command will cause the CUI to clear the Sus-
pend state and set the WSM Status bit to a ‘‘0’’, but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algo-
rithm. While the WSM finishes the algorithm, the de-
vice will output Status Register contents. Note that
the WSM cannot be suspended during program-
ming.
4.4.3 STATUS REGISTER
The 4 Mbit flash family contains a status register
which may be read to determine when a program or
erase operation is complete, and whether that oper-
ation completed successfully. The status register
may be read at any time by writing the Read Status
command to the CUI. After writing this command, all
subsequent Read operations output data from the
status register until another command is written to
the CUI. A Read Array command must be written to
the CUl to return to the Read Array mode.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a ‘‘1’’, place the device into the
Read Status Register state, and wait for another
command.
[
]
The status register bits are output on DQ 0:7
whether the device is in the byte-wide (x8) or word-
wide (x16) mode for the 28F400BL. In the word-wide
[
]
mode the upper byte, DQ 8:15 is set to 00H during
a Read Status command. In the byte-wide mode,
Erase Confirm (D0H)
[
]
DO 8:14 is tri-stated and DQ /A
order address function.
retains the low
b
15
1
If the previous command was an Erase Setup com-
mand, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is exe-
cuting, the device will output Status Register data
It should be noted that the contents of the status
Ý
register are latched on the falling edge of OE or
CE whichever occurs last in the read cycle. This
Ý
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE or OE must be toggled
with each subsequent status read, or the completion
of a program or erase operation will not be evident.
Ý
when OE is toggled low. Status Register data can
only be updated by toggling either OE or CE low.
Ý
Ý
Ý
Ý
Erase Suspend (B0H)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will initi-
ate the WSM to suspend Erase operations, and then
return to responding to only Read Status Register or
to the Erase Resume commands. Once the WSM
has reached the Suspend state, it will set an output
into the CUI which allows the CUI to respond to the
Read Array, Read Status Register, and Erase Re-
sume commands. In this mode, the CUI will not re-
spond to any other commands. The WSM will also
set the WSM Status bit to a ‘‘1’’. The WSM will con-
The Status Register is the interface between the mi-
croprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets
status bits ‘‘Three’’ through ‘‘Seven’’ and clears bits
‘‘Six’’ and ‘‘Seven’’, but cannot clear status bits
‘‘Three’’ through ‘‘Five’’. These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.
21
28F400BL-T/B, 28F004BL-T/B
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
WSMS
7
ESS
6
ES
5
PS
4
VPPS
R
2
R
1
R
0
3
NOTES:
e
e
e
SR.7
WRITE STATE MACHINE STATUS
Ready
Busy
Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.
1
0
e
e
e
SR.6
ERASE SUSPEND STATUS
Erase Suspended
Erase in Progress/Completed
1
0
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to ‘‘1’’. ESS bit re-
mains set to ‘‘1’’ until an Erase Resume command is is-
sued.
e
e
e
SR.5
ERASE STATUS
Error in Block Erasure
Successful Block Erase
1
0
When this bit is set to ‘‘1’’. WSM has applied the maxi-
mum number of erase pulses to the block and is still un-
able to successfully perform an erase verify.
e
e
e
e
e
e
SR.4
1
0
SR.3
1
PROGRAM STATUS
Error in Byte/Word Program
Successful Byte/Word Program
When this bit is set to ‘‘1’’, WSM has attempted but failed
to Program a byte or word.
V
PP
V
PP
V
PP
STATUS
Low Detect; Operation Abort
OK
The V
PP
Status bit unlike an A/D converter, does not
provide continuous indication of V level. The WSM in-
0
PP
terrogates the V level only after the byte write or block
PP
erase command sequences have been entered and in-
forms the system if V has not been switched on. The
V
PP
Status bit is not guaranteed to report accurate feed-
PP
back between V
and V
.
PPH
PPL
e
These bits are reserved for future use and should be masked out when polling the Status Register.
SR.2–SR.0
RESERVED FOR FUTURE ENHANCEMENTS
4.4.3.2 Clearing the Status Register
4.4.4 PROGRAM MODE
Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure con-
ditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in se-
quence). The status register may then be read to
determine if an error occurred during that program-
ming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read com-
mand must be written to the CUI to specify whether
the read data is to come from the array, status regis-
ter, or Intelligent Identifier.
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI fol-
lowed by a second write which specifies the address
and data to be programmed. The write state ma-
chine will execute a sequence of internally timed
events to:
1. program the desired bits of the addressed memo-
ry word (byte), and
2. verify that the desired bits are sufficiently pro-
grammed.
Programming of the memory results in specific bits
within a byte or word being changed to a ‘‘0’’.
If the user attempts to program ‘‘1’’s, there will be no
change of the memory cell content and no error oc-
curs.
22
28F400BL-T/B, 28F004BL-T/B
Similar to erasure, the status register indicates
whether programming is complete. While the pro-
gram sequence is executing, bit 7 of the status regis-
ter is a ‘‘0’’. The status register can be polled by
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a ‘‘1’’ to indicate an
Ý
Ý
toggling either CE or OE to determine when the
program sequence is complete. Only the Read
Status Register command is valid while program-
ming is active.
Erase Failure. If V was not within acceptable limits
PP
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit 5 of the status register is set to a ‘‘1’’ to indicate
an Erase Failure, and Bit 3 is set to a ‘‘1’’ to identify
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status regis-
ter is set to a ‘‘1’’ to indicate a Program Failure. If
Bit 3 is set then V was not within acceptable limits,
PP
and the WSM will not execute the programming se-
quence.
that V
limits.
supply voltage was not within acceptable
PP
The status register should be cleared before at-
tempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be ac-
complished until the CUI is given the appropriate
command. A Read Array command must first be giv-
en before memory contents can be read.
The status register should be cleared before at-
tempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be ac-
complished until the CUI is given the appropriate
command. A Read Array command must first be giv-
en before memory contents can be read.
Figure 13 shows a system software flowchart for
Block Erase operation.
4.4.5.1 Suspending and Resuming Erase
Figure 12 shows a system software flowchart for de-
vice byte programming operation. Figure 13 shows a
similar flowchart for device word programming oper-
ation (28F400BL-only).
Since an erase operation typically requires 2 sec-
onds to 5 seconds to complete, an Erase Suspend
command is provided. This allows erase-sequence
interruption in order to read data from another block
of the memory. Once the erase sequence is started,
writing the Erase Suspend command to the CUI re-
quests that the Write State Machine (WSM) pause
the erase sequence at a predetermined point in the
erase algorithm. The status register must be read to
determine when the erase operation has been sus-
pended.
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
[
]
CUI, along with the addresses, A 12:17 for the
[
]
28F400BL or A 12:18 for the 28F004BL, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is is-
sued. Block erasure results in all bits within the block
being set to ‘‘1’’.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
The WSM will execute a sequence of internally
timed events to:
Figure 14 shows a system software flowchart detail-
ing the operation.
1. program all bits within the block
2. verify that all bits within the block are sufficiently
programmed
During Erase Suspend mode, the chip can go into a
Ý
pseudo-standby mode by taking CE to V and the
active current is now a maximum of 6 mA. If the chip
3. erase all bits within the block and
IH
4. verify that all bits within the block are sufficiently
erased
Ý
is enabled while in this mode by taking CE to V
,
IL
the Erase Resume command can be issued to re-
sume the erase operation.
While the erase sequence is executing, Bit 7 of the
status register is a ‘‘0’’.
23
28F400BL-T/B, 28F004BL-T/B
Upon completion of reads from any block other than
the block being erased, the Erase Resume com-
mand must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in or-
der to continue.
4.4.6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 4-Mbit
low voltage flash memory family is designed for
10,000 program/erase cycles on each of the seven
blocks. The combination of low electric fields, clean
oxide processing and minimized oxide area per
memory cell subjected to the tunneling electric field,
results in very high cycling capability.
24
28F400BL-T/B, 28F004BL-T/B
Bus
Command
Comments
Operation
e
40H
Write
Write
Setup
Data
e
programmed
Program
Address
Byte to be
Program
Data to be programmed
e
programmed
Address
Byte to be
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to update
Status Register
Standby
Check SR.7
e
e
Busy
1
Ready, 0
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290450–9
Full Status Check Procedure
Bus
Operation
Command
Comments
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Check SR.4
e
1
Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
290450–10
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 12. Automated Byte Programming Flowchart
25
28F400BL-T/B, 28F004BL-T/B
Bus
Command
Comments
Operation
e
40H
Write
Write
Setup
Data
e
programmed
Program
Address
Word to be
Program
Data to be programmed
e
programmed
Address
Word to be
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to update
Status Register
Standby
Check SR.7
e
e
Busy
1
Ready, 0
Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.
Write FFH after the last word programming operation to
reset the device to Read Array Mode.
290450–11
Full Status Check Procedure
Bus
Command
Comments
Operation
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Check SR.4
e
1
Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
290450–12
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated Word Programming Flowchart
26
28F400BL-T/B, 28F004BL-T/B
Bus
Command
Comments
Operation
e
20H
Write
Write
Setup
Erase
Data
e
Address
erased
Within block to be
e
D0H
Erase
Data
e
Address
erased
Within block to be
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to update
Status Register
Standby
Check SR.7
e
e
Busy
1
Ready, 0
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
290450–13
Full Status Check Procedure
Bus
Command
Comments
Operation
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Standby
Check SR.4,5
e
Both 1
Error
Command Sequence
Check SR.5
e
1
Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290450–14
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
27
28F400BL-T/B, 28F004BL-T/B
Bus
Command
Comments
Operation
e
Write
Read
Erase
Data
B0H
Suspend
Status Register Data.
Ý
Ý
Toggle OE or CE to
update Status Register
Standby
Standby
Check SR.7
e
1
Ready
Check SR.6
e
1
Suspended
e
FFH
Write
Read
Read Array
Data
Read array data from block
other than that being
erased.
e
D0H
Write
Erase Resume Data
290450–15
Figure 15. Erase Suspend/Resume Flowchart
typical I current is 0.8 mA and maximum I
cur-
CC
CC
4.5 Power Consumption
rent is 2 mA. The device stays in this static state with
outputs valid until a new memory location is read.
4.5.1 ACTIVE POWER
Ý
Ý
With CE at a logic-low level and RP at a logic-
high level, the device is placed in the active mode.
4.5.3 STANDBY POWER
Ý
With CE at a logic-high level (V ), and the CUI
read mode, the memory is placed in standby mode
The device I
5 MHz.
current is a maximum of 22 mA at
IH
CC
where the maximum I
standby current is 120 mA
CC
with CMOS input signals. The standby operation dis-
ables much of the device’s circuitry and substantially
reduces device power consumption. The outputs
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power fea-
ture during active mode of operation. The 4-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the de-
vice to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device’s pow-
er consumption by entering the APS mode where
[
]
[
(DQ 0:15 or DQ 0:7 are placed in a high-imped-
ance state independent of the status of the OE
]
Ý
signal. When the 4-Mbit flash family is deselected
during erase or program functions, the devices will
continue to perform the erase or program function
and consume program or erase active power until
program or erase is completed.
28
28F400BL-T/B, 28F004BL-T/B
Ý
Ý
active. Since both WE and CE must be low for a
command write, driving either signal to V will inhibit
4.5.4 RESET/DEEP POWER-DOWN
IH
The 4-Mbit flash family supports a typical I
of
writes to the device. The CUl architecture provides
an added level of protection since alteration of mem-
ory contents can only occur after successful com-
pletion of the two-step command sequences. Finally
CC
0.2 mA in deep power-down mode. One of the target
markets for these devices is in portable equipment
where the power consumption of the machine is of
prime importance. The 4-Mbit flash family has a
Ý
the device is disabled until RP is brought to V
,
IH
Ý
RP pin which places the device in the deep power-
down mode. When RP is at a logic-low (GND
regardless of the state of its control inputs. This fea-
ture provides yet another level of memory protec-
tion.
Ý
g
0.2V), all circuits are turned off and the device typ-
ically draws 0.2 mA of V current.
CC
Ý
During read modes, the RP pin going low dese-
lects the memory and places the output drivers in a
high impedance state. Recovery from the deep pow-
er-down state, requires a maximum of 600 ns to ac-
4.7 Power Supply Decoupling
Flash memory’s power switching characteristics re-
quire careful device decoupling methods. System
designers are interested in 3 supply current issues:
cess valid data (t
).
PHQV
Standby current levels (I
Active current levels (I
)
#
#
#
CCS
Ý
During erase or program modes, RP low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
)
CCR
Transient peaks produced by falling and rising
Ý
edges of CE
.
Ý
corrupted by the RP function. As in the read mode
above, all internal circuitry is turned off to achieve
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 mF ceramic capacitor
the 0.2 mA current level.
Ý
RP transitions to V or turning power off to the
device will clear the status register.
IL
connected between each V
and GND, and be-
tween its V and GND. These high frequency, low-
Ý
This use of RP during system reset is important
CC
with automated write/erase devices. When the sys-
tem comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization fol-
PP
inherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1
V TRACE ON PRINTED CIRCUIT
PP
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
Ý
lowing a system reset through the use of the RP
Ý
input. In this application RP is controlled by the
same RESET signal that resets the system CPU.
V
PP
designer. The V
power supply trace by the printed circuit board
pin supplies the flash memory
PP
Ý
cell’s current for programming and erasing. One
should use similar trace widths and layout consider-
ations given to the V
quate V
power supply trace. Ade-
supply traces and decoupling will de-
CC
4.6 Power-up Operation
PP
crease spikes and overshoots.
The 4-Mbit flash memory family is designed to offer
protection against accidental block erasure or pro-
gramming during power transitions. Upon power-up
the 4-Mbit flash memory family is indifferent as to
Ý
V , V AND RP TRANSITIONS
CC PP
4.7.2
The CUI latches commands as issued by system
which power supply, V
Power supply sequencing is not required.
or V , powers-up first.
PP
CC
Ý
or CE tran-
sitions or WSM actions. Its state upon power-up, af-
software and is not altered by V
PP
ter exit from deep power-down mode or after V
transitions below V
Array mode.
The 4-Mbit flash memory family ensures the CUI is
reset to the read mode on power-up.
CC
(Lockout voltage), is Read
LKO
In addition, on power-up the user must either drop
After any word/byte write or block erase operation is
complete and even after V transitions down to
Ý
CE low or present a new address to ensure valid
data at the outputs.
PP
, the CUI must be reset to Read Array mode via
V
PPL
the Read Array command when accesses to the
flash memory are desired.
A system designer must guard against spurious
when V
writes for V
voltages above V
is
PP
CC
LKO
29
28F400BL-T/B, 28F004BL-T/B
5.0 OPERATING SPECIFICATIONS
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 C to 70 C
(1)
b
a
During Block Erase/Byte Write ÀÀÀÀ0 C to 70 C
§
§
a
§
§
§
§
b
a
Temperature Under BiasÀÀÀÀÀÀÀÀÀ 20 C to 80 C
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 125 C
b
a
§
Voltage on any Pin
(except V , V , A and RP
with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V
Ý
b
)
CC PP
9
(2)
a
Ý
Voltage on Pin RP or Pin A
with Respect to GND ÀÀÀÀÀ 2.0V to 13.5V
9
b
(2, 3)
a
V Program Voltage with
CC
Respect to GND
during Block Erase and
Word/Byte Write ÀÀÀÀÀÀÀÀÀ 2.0V to 14.0V
(2, 3)
(2)
b
a
V
Supply Voltage
CC
b
a
with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V
(4)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
70
Unit
b
T
A
Operating Temperature
20
C
§
V
V
Supply Voltage
Program/Erase
3.15
3.00
4.50
3.60
3.60
5.50
V
V
V
CC
CC
Read
5
V
CC
V
Supply Voltage
CC
NOTES:
1. Operating temperature is for commercial product defined by this specification.
b
b
2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods
a
k
20 ns. Maximum DC voltage on input/output pins is V
2.0V for periods
a
0.5V which during transitions may overshoot to V
CC
CC
k
3. Maximum DC voltage on V may overshoot to 14.0V for periods 20 ns. Maximum DC voltage on RP or A may
20 ns.
k
a
Ý
PP
overshoot to 13.5V for periods
9
k
4. Output shorted for no more than one second. No more than one output shorted at a time.
20 ns.
5. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifica-
tions.
DC CHARACTERISTICS
e
g
3.3V 0.3V Read, 3.15V–3.6V Program/Erase
V
CC
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Conditions
e
g
I
Input Load Current
1
1.0
mA
V
V
V
Max
CC
or GND
LI
CC
e
V
IN
CC
e
g
I
Output Leakage Current
1
10
mA
V
V
V
Max
CC
or GND
CC
LO
CC
e
V
OUT
30
28F400BL-T/B, 28F004BL-T/B
DC CHARACTERISTICS (Continued)
e
g
3.3V 0.3V Read, 3.15V–3.6V Program/Erase
V
CC
Symbol
Parameter
Notes Min Typ
Max
Unit
Test Conditions
e
I
V
Standby Current
1, 3
45
120
mA
V
CE
V
Max
CC
CCS
CC
CC
e
e
Ý
Ý
RP
V
V
IH
e
45
120
mA
V
V
Max
CC
e
Ý
CC
e
Ý
g
0.2V
CE
28F400BX:
RP
CC
e
Ý
BYTE
or GND
g
0.2V
V
CC
e
g
GND 0.2V
Ý
I
I
V
V
Deep Power-Down Current
Read Current for
1
0.20
15
1.2
25
mA RP
CCD
CCR
CC
CC
e
5 MHz, I
e
Ý
1
5, 6
mA V
f
V
Max, CE
CC
GND
CC
e
CMOS Inputs
e
0 mA
28F400BX-L Word-Wide and
Byte-Wide Mode and
28F004BX-L Byte-Wide Mode
OUT
e
5 MHz, I
e
V
Ý
15
25
mA V
f
V
Max, CE
CC
CC
IL
e
TTL Inputs
e
0 mA
OUT
I
I
I
I
V
V
V
V
Word Write Current
Byte Write Current
1
1
30
30
20
6
mA Word Write in Progress
mA Byte Write in Progress
mA Block Erase in Progress
CCW
CCW
CCE
CC
CC
CC
CC
Block Erase Current
Erase Suspend Current
1
e
V
IH
Ý
1, 2
3
mA CE
CCES
Block Erase Suspended
s
g
I
I
I
I
V
V
V
V
Standby Current
1
15
mA
V
V
CC
PPS
PPD
PPR
PPW
PP
PP
PP
PP
PP
e
Ý
g
Deep Power-Down Current
Read Current
1
5.0
mA RP
GND 0.2V
l
V
CC
1, 4
1, 4
200
40
mA
V
PP
PP
e
Word Write Current
mA V
V
PPH
Word Write in Progress
e
V
PPH
I
I
I
V
V
V
Byte Write Current
1, 4
1, 4
1
30
30
mA V
PPW
PPE
PP
PP
PP
PP
Byte Write in Progress
e
V
PPH
Block Erase Current
Erase Suspend Current
mA V
PP
Block Erase in Progress
e
V
PPH
200
mA
V
PPES
PP
Block Erase Suspended
e
V
HH
Ý
RP Boot Block Unlock Current 1, 4
Ý
I
I
500
500
13.0
0.6
mA RP
Ý
RP
ID
e
A
A
Intelligent Identifier Current
Intelligent Identifier Voltage
1, 4
mA
V
A
V
ID
9
9
9
V
V
V
V
11.4 12.0
ID
b
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
V
IL
a
2.0
V
0.5
V
IH
OL
CC
e
e
0.4
V
V
V
2 mA
Min
CC
CC
I
OL
31
28F400BL-T/B, 28F004BL-T/B
DC CHARACTERISTICS (Continued)
e
g
3.3V 0.3V Read, 3.15V–3.6V Program/Erase
V
CC
Symbol
Parameter
Notes
Min
Typ Max Unit
Test Conditions
e
V
Output High Voltage (TTL)
2.4
V
V
V
Min
OH1
CC
CC
e b
I
2 mA
OH
e
e b
V
Output High Voltage
(CMOS)
0.85 V
V
V
V
Min
CC
2.5 mA
OH2
CC
CC
I
OH
b
e
V
V
CC
0.4
V
Min
100 mA
CC
CC
e b
I
OH
V
V
V
V
V
V
V
during Normal Operations
during Erase/Write Operations
Erase/Write Lock Voltage
3
0.0
4.1
V
V
V
V
PPL
PPH
LKO
HH
PP
PP
CC
11.4
2.0
12.0 12.6
Ý
RP Unlock Voltage
11.4
12.0 13.0
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
12.0V, T 25 C. These currents
3.3V, V
PP
§
CC
2.
I
is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
.
CCR
CCES
of I
and I
CCES
3. Block Erase and Word/Byte Writes are inhibited when V
e
V
PPL
and not guaranteed in the range between V
and
PPH
PP
V
4. Sampled, not 100% tested.
.
PPL
5. Automatic Power Savings (APS) reduces I
g
to less than 1 mA in static operation.
CCR
g
6. CMOS Inputs are either V
0.2V or GND 0.2V. TTL Inputs are either V or V .
IL IH
CC
(1)
e
e
1 MHz
CAPACITANCE
T
A
25 C, f
§
Symbol
Parameter
Input Capacitance
Output Capacitance
Typ
6
Max
8
Unit
pF
Condition
e
C
C
V
V
0V
IN
IN
e
0V
10
12
pF
OUT
OUT
NOTE:
1. Sampled, not 100% tested.
32
28F400BL-T/B, 28F004BL-T/B
(4)
DC CHARACTERISTICS
e
g
5.0V 10%
V
CC
Symbol
Parameter
Notes Min Typ Max Unit
Test Conditions
e
g
I
I
I
Input Load Current
1
1
1
1.0 mA
10 mA
1.5 mA
V
V
V
Max
or GND
LI
CC
CC
e
V
IN
CC
e
g
Output Leakage Current
V
V
V
CC
Max
LO
CCS
CC
e
V
or GND
OUT
CC
e
V
CC
Standby Current
V
CE
V
CC
Max
e
CC
e
Ý
Ý
RP
V
V
IH
e
100 mA
V
CE
V
Max
CC
e
Ý
CC
e
Ý
g
0.2V
RP
CC
e
e
Ý
g
GND 0.2V
0 mA
I
I
V
V
Deep Power-Down Current
Read Current for
RP
I
CCD
CCR
CC
1
1
1.2
40
mA
OUT
e
5 MHz, I
e
Ý
mA
V
V
Max, CE
GND
CC
CC
CC
e
CMOS Inputs
e
0 mA
28F400BX-L Word-Wide Mode
and Byte Wide Mode
and 28F004BX-L
f
OUT
e
5 MHz, I
e
V
Ý
40
mA
V
V
Max, CE
CC
CC
IL
e
TTL Inputs
e
0 mA
f
OUT
I
I
I
V
CC
V
CC
V
CC
Word Byte Write Current
Block Erase Current
1, 4
1, 4
1, 2
70
30
10
mA Word Write in Progress
mA Block Erase in Progress
mA Block Erase Suspended,
CCW
CCE
Erase Suspend Current
CCES
e
Ý
CE
V
IH
s
V
CC
g
I
I
I
I
V
V
V
V
Standby Current
1
1
10 mA
V
PPS
PPD
PPR
PPW
PP
PP
PP
PP
PP
e
Ý
g
Deep Power-Down Current
Read Current
5.0
mA RP
GND 0.2V
l
V
CC
1
200 mA
V
PP
e
V
PPH
Word Write Current
1, 4
40
30
30
mA
mA
mA
V
PP
Word Write in Progress
e
V
PPH
I
I
I
I
I
V
PP
V
PP
V
PP
Byte Write Current
1, 4
1, 4
1
V
PPW
PPE
PP
Byte Write in Progress
e
V
PPH
Block Erase Current
Erase Suspend Current
V
PP
Block Erase in Progress
e
V
PPH
200 mA
V
PPES
PP
Block Erase Suspended
e
V
HH
Ý
RP Boot Block
Unlock Current
Ý
1, 4
1, 4
500 mA RP
Ý
RP
ID
e
A Intelligent
Identifier Current
500 mA
11.4 12.0 13.0
A
V
ID
9
9
V
A Intelligent
Identifier Voltage
V
ID
9
33
28F400BL-T/B, 28F004BL-T/B
(4)
DC CHARACTERISTICS (Continued)
e
g
5.0V 10%
V
CC
Symbol
Parameter
Input Low Voltage
Notes
Min
Typ
Max
0.8
a
Unit
V
Test Condition
b
V
V
V
0.5
IL
Input High Voltage
Output Low Voltage
2.0
V
0.5
V
IH
OL
CC
e
0.45
V
V
V
Min
CC
CC
5.8 mA
e
I
OL
e
V
V
Output High Voltage (TTL)
2.4
V
V
V
V
Min
OH1
OH2
CC
CC
e b
I
2.5 mA
e
V Min
CC
OH
Output High Voltage
(CMOS)
0.85 V
V
CC
CC
e b
I
2.5 mA
OL
b
e
V
V
0.4
V
Min
CC
CC
CC
e b
I
100 mA
OL
V
V
V
V
V
V
V
during Normal Operations
during Erase/Write Operations
Erase/Write Lock Voltage
3
0.0
6.5
V
V
V
V
PPL
PPH
LKO
HH
PP
PP
CC
11.4
2.2
12.0
12.6
Ý
RP Unlock Voltage
11.4
12.0
13.0
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
12.0V, T 25 C. These currents
5.0V, V
PP
§
CC
2. I
of I
is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
.
CCES
and I
CCES
CCR
e
3. Block Erases and Word/Byte Writes are inhibited when V
V
PPL
and not guaranteed in the range between V and
PPH
PP
V .
PPL
4. All parameters are sampled, not 100% tested.
AC INPUT/OUTPUT REFERENCE WAVEFORM
AC TESTING LOAD CIRCUIT
290450–16
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0 for a Logic ‘‘0’’.
Input timing begins, and output timing ends at 1.5V. Input rise and fall times
k
(10% to 90%)
10 ns.
290450–17
e
C
L
C
L
50 pF
Includes Jig Capacitance
e
R
L
3.3 KX
34
28F400BL-T/B, 28F004BL-T/B
(1)
AC CHARACTERISTICS-Read-Only Operations
e
g g
3.3V 0.3V, 5.0V 10%
V
CC
28F400BL-150
28F004BL-150
Versions
Parameter
Unit
Symbol
Notes
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
Address to Output Delay
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
ELQV
PHQV
GLQV
ELQX
EHOZ
GLQX
GHQZ
RC
150
150
600
65
ACC
CE
Ý
CE to Output Delay
2
Ý
RP High to Output Delay
PWH
OE
Ý
OE to Output Delay
2
3
3
3
3
3
Ý
CE to Output Low Z
0
0
0
LZ
Ý
CE High to Output High Z
55
45
HZ
Ý
OE to Output Low Z
OLZ
DF
Ý
OE High to Output High Z
Ý
Output Hold from Addresses, CE or OE
Change, Whichever is First
Ý
OH
t
t
Input Rise Time
Input Fall Time
10
10
5
ns
ns
ns
IR
IF
Ý
Ý
CE to BYTE Switching Low or High
t
t
3
ELFL
ELFH
Ý
BYTE Switching High to Valid Output Delay
t
t
3, 4
3
150
45
ns
ns
FHQV
FLQZ
Ý
BYTE Switching Low to Output High Z
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
Ý
2. OE may be delayed up to t -t
3. Sampled, not 100% tested.
Ý
after the falling edge of CE without impact on t
.
CE
CE OE
Ý
t , BYTE switching low to valid output delay will be equal to t
FLQV AVQV
valid.
4.
, measured from the time DQ /A becomes
15 -1
35
28F400BL-T/B, 28F004BL-T/B
Figure 16. AC Waveforms for Read Operations
36
28F400BL-T/B, 28F004BL-T/B
290450–25
Ý
Figure 17. BYTE Timing Diagram for Both Read and Write Operations
37
28F400BL-T/B, 28F004BL-T/B
(1)
Ý
AC CHARACTERISTICS FOR WE -CONTROLLED WRITE OPERATIONS
e
g
3.15V–3.6V, 5.0V 10%
V
CC
28F400BL-150
28F004BL-150
(4)
Versions
Unit
Symbol
Parameter
Notes
Min
Max
t
t
t
t
Write Cycle Time
150
1.0
ns
AVAV
PHWL
WC
Ý
RP High Recovery
to WE Going Low
ms
PS
Ý
Ý
CE Setup to WE
Going Low
Ý
t
t
t
0
ns
ns
ELWL
CS
Ý
Going High
Ý
t
RP
V Setup to WE
HH
6, 8
200
PHHWH
PHS
Ý
Setup to WE Going High
t
t
t
t
V
PP
5, 8
3
200
95
ns
ns
VPWH
AVWH
VPS
Ý
Address Setup to WE
Going High
AS
Ý
Data Setup to WE Going High
t
t
t
t
t
t
4
100
100
0
ns
ns
ns
DVWH
WLWH
WHDX
DS
WP
DH
Ý
WE Pulse Width
Ý
Data Hold from WE High
Ý
WE High
4
3
Ý
Address Hold from WE High
t
t
t
t
t
t
t
10
10
50
6
ns
ns
ns
ms
WHAX
WHEH
WHWL
WHQV1
AH
Ý
Ý
CE Hold from WE High
CH
Ý
WE Pulse Width High
WPH
Duration of Word/Byte
Programming Operation
2, 5, 6
2, 5, 6
2, 5, 6
2, 5, 6
t
t
t
Duration of Erase
Operation (Boot)
0.3
0.3
0.6
s
s
s
WHQV2
WHQV3
WHQV4
Duration of Erase
Operation (Parameter)
Duration of Erase
Operation (Main)
t
t
t
t
t
V Hold from Valid SRD
PP
5, 8
6, 8
7, 8
0
0
ns
ns
ns
ns
ns
QVVL
QVPH
PHBR
VPH
Ý
RP
V
Hold from Valid SRD
HH
PHH
Boot-Block Relock Delay
Input Rise Time
200
10
t
t
IR
Input Fall Time
10
IF
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter-
nally which includes verify and margining operations.
3. Refer to command definition table for valid A
4. Refer to command definition table for valid D
.
.
IN
IN
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 1).
e
until operation completes successfully.
Ý
6. For Boot Block Program/Erase, PWD should be held at V
HH
is required for successful relocking of the Boot Block.
7. Time t
PHBR
8. Sampled but not 100% tested.
38
28F400BL-T/B, 28F004BL-T/B
BLOCK ERASE AND BYTE/WORD WRITE PERFORMANCE
e
g
3.15V–3.6V, 5.0V 10%
V
CC
28F400BL-150
28F004BL-150
Parameter
Notes
Unit
(1)
Min
Typ
Max
8.6
Boot/Parameter Block Erase Time
Main Block Erase Time
2
2
2
2
2.0
3.4
1.4
0.7
s
s
s
s
17.0
5.3
Main Block Byte Program Time
Main Block Word Program Time
2.7
NOTES:
1. 25 C, 12.0V V
.
§
PP
2. Excludes System-Level Overhead.
39
28F400BL-T/B, 28F004BL-T/B
Ý
Figure 18. AC Waveforms for Write and Erase Operations (WE -Controlled Writes)
40
28F400BL-T/B, 28F004BL-T/B
Ý
AC CHARACTERISTICS FOR CE -CONTROLLED WRITE OPERATIONS
e
g
3.15V–3.6V, 5.0V 10%
V
CC
28F400BL-150
28F004BL-150
Versions
Parameter
Unit
Symbol
Notes
Min
150
1.0
Max
t
t
t
t
Write Cycle Time
ns
AVAV
PHEL
WC
PS
Ý
RP High Recovery to
ms
Ý
CE Going Low
Ý
Ý
WE Setup to CE Going Low
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0
200
200
95
100
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
WLEL
PHHEH
VPEH
AVEH
DVEH
ELEH
EHDX
EHAX
EHWH
EHEL
EHQV1
WS
PHS
VPS
AS
Ý
Ý
Setup to CE Going High
RP
V
6, 8
5, 8
3
HH
Ý
Setup to CE Going High
V
PP
Ý
Address Setup to CE Going High
Ý
Data Setup to CE Going High
4
DS
Ý
CE Pulse Width
CP
Ý
Data Hold from CE High
4
3
DH
Ý
Address Hold from CE High
10
10
50
6
AH
Ý
Ý
WE Hold from CE High
WH
CPH
Ý
CE Pulse Width High
Duration of Programming
Operation Word/Byte
2, 5, 6
t
t
Duration of Erase Operation (Boot)
2, 5, 6
2, 5, 6
0.3
0.3
s
s
EHQV2
EHQV3
Duration of Erase
Operation (Parameter)
t
t
t
t
Duration of Erase Operation (Main)
2, 5, 6
5, 8
0.6
0
s
EHQV4
QVVL
QVPH
PHBR
t
t
V
Hold from Valid SRD
PP
ns
ns
ns
ns
ns
VPH
PPH
Ý
RP
V
Hold from Valid SRD
6, 8
0
HH
Boot-Block Relock Delay
Input Rise Time
7, 8
200
10
t
t
IR
IF
Input Fall Time
10
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE in systems where
Ý
Ý
CE defines the write pulse-width (within a longer WE timing waveform), all set-up, hold and inactive WE times
Ý
should be measured relative to the CE waveform.
Ý
Ý
Ý
2, 3, 4, 5, 6, 7, 8. Refer to AC Characteristics for WE -Controlled Write operations.
Ý
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
41
28F400BL-T/B, 28F004BL-T/B
Ý
Figure 19. Alternate AC Waveforms for Write and Erase Operations (CE -Controlled Writes)
42
28F400BL-T/B, 28F004BL-T/B
ORDERING INFORMATION
290450–21
VALID COMBINATIONS:
E28F400BL-T150
E28F400BL-B150
PA28F400BL-T150
PA28F400BL-B150
290450–22
VALID COMBINATIONS:
E28F004BL-T150
E28F004BL-B150
ADDITIONAL INFORMATION
References
Order
Document
Number
290448
290449
290451
290531
290530
290539
292098
292148
292178
292130
292154
28F002/200-T/B Mbit Boot Block Flash Memory Datasheet
28F002/200BL-T/B 2 Mbit Low Power Boot Block Flash Memory Datasheet
28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
AP-363 ‘‘Extended Flash BIOS Concepts for Portable Computers’’
AP-604 ‘‘Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM’’
AP-623 ‘‘Multisite Layout Planning Using Intel’s Boot Block Flash Memory’’
AB-57 ‘‘Boot Block Architecture for Safe Firmware Updates’’
AB-60 ‘‘2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family’’
43
28F400BL-T/B, 28F004BL-T/B
Revision History
Number
Description
-001
-002
Original Version
Ý
Modified BYTE Timing Waveforms
Modified t parameter for AC Characteristics for Write Operations
DVWH
Ý
PWD renamed to RP for JEDEC standarization compatibility.
-003
Combined V Read Current for 28F400BX-L Word-Wide and Byte-Wide Mode
CC
and 28F004BX-L Byte Wide Mode in DC Characteristics tables.
g g
current spec from 10 mA to 15 mA in DC Characteristics table.
Changed I
PPS
Added Boot Block Unlock current spec in DC Characteristics tables.
Improved t
spec to 600 ns (was 700 ns).
PWH
Changed I
maximum spec from 20 mA to 25 mA, and added 15 mA typical spec
CCR
in DC Characteristics Table.
-004
Added I CMOS specification.
OH
Expanded temperature operating range
b
from 0 C–70 C to 20 C–70 C
§
§
§
Product naming changed:
§
28F400BX-TL/BL changed to 28F400BL-T/B
28F004BX-TL/BL changed to 28F004BL-T/B
Typographical errors corrected.
Added 28F400BX interface to Intel386TM EX
Embedded Processor block diagram.
Added upgrade considerations for
SmartVoltage Boot Block products.
Previously specified V tolerance of 3.0V to 3.6V for Read,
CC
Program and Erase has been changed to 3.15V to 3.6V for
Program and Erase while Read remains 3.0V to 3.6V
-005
Added references to input rise/fall times.
44
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