2N174A_技术文档

CY7C1339

128K x 32 Synchronous-Pipelined Cache RAM

The CY7C1339 I/O pins can operate at either the 2.5V or the

Features

3.3V level; the I/O pins are 3.3V tolerant when V

=2.5V.

DDQ

• Supports 100-MHz bus for Pentium and PowerPC™

operations with zero wait states

• Fully registered inputs and outputs for pipelined oper-

ation

• 128K by 32 common I/O architecture

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 3.5 ns (166-MHz

device).

The CY7C1339 supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The burst

sequence is selected through the MODE pin. Accesses can

be initiated by asserting either the Processor Address Strobe

(ADSP) or the Controller Address Strobe (ADSC) at clock rise.

Address advancement through the burst sequence is con-

trolled by the ADV input. A 2-bit on-chip wraparound burst

counter captures the first address in a burst sequence and

automatically increments the address for the rest of the burst

access.

• User-selectable burst counter supporting Intel Pen-

tium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Byte write operations are qualified with the four Byte Write

Select (BW

) inputs. A Global Write Enable (GW) overrides

• JEDEC-standard 100 TQFP pinout

[3:0]

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

Three synchronous Chip Selects (CE , CE , CE ) and an

1

2

3

The CY7C1339 is a 3.3V, 128K by 32 synchronous-pipelined

cache SRAM designed to support zero wait state secondary

cache with minimal glue logic.

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to provide prop-

er data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

MODE

Logic Block Diagram

2

(A

)

[1;0]

Q

0

CLK

ADV

ADSC

BURST

COUNTER

CE

CLR

Q

1

ADSP

Q

15

17

ADDRESS

REGISTER

CE

D

128KX32

MEMORY

ARRAY

A

[16:0]

17

15

GW

Q

DQ[31:24]

D

BYTEWRITE

REGISTERS

BWE

BW

3

D

DQ[23:16]

BYTEWRITE

REGISTERS

BW

2

DQ[15:8]

BYTEWRITE

REGISTERS

BW

1

DQ[7:0]

BYTEWRITE

REGISTERS

BW

0

32

CE

1

2

CE

D

CE

ENABLE

REGISTER

CLK

Q

CE

3

D

Q

OUTPUT

REGISTERS

CLK

INPUT

REGISTERS

CLK

ENABLE DELAY

REGISTER

CLK

OE

ZZ

SLEEP

CONTROL

DQ

[31:0]

Intel and Pentium are trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

May 8, 2000

CY7C1339

Pin Configuration

NC

DQ₁₆

DQ₁₇

V_DDQ

V_SSQ

DQ₁₈

DQ₁₉

DQ₂₀

DQ₂₁

V_SSQ

V_DDQ

DQ₂₂

DQ₂₃

NC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQ₁₅

DQ₁₄

V_DDQ

V_SSQ

DQ₁₃

DQ₁₂

DQ₁₁

DQ₁₀

V_SSQ

V_DDQ

DQ₉

DQ₈

V_SS

BYTE2

BYTE1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100

r

100-Pin TQFP

V_DD

NC

V_SS

NC

V_DD

ZZ

CY7C1339

DQ₂₄

DQ₂₅

V_DDQ

V_SSQ

DQ₂₆

DQ₂₇

DQ₂₈

DQ₂₉

V_SSQ

V_DDQ

DQ₃₀

DQ₃₁

NC

DQ₇

DQ₆

V_DDQ

V_SSQ

DQ₅

DQ₄

DQ₃

DQ₂

V_SSQ

V_DDQ

DQ₁

DQ₀

NC

BYTE3

BYTE0

10

Selection Guide

7C1339-166

7C1339-133

7C1339-100

Maximum Access Time (ns)

3.5

420

10

4.0

375

10

5.5

325

10

Maximum Operating Current (mA)

Commercial

Maximum CMOS Standby Current (mA)

2

CY7C1339

Pin Definitions

Pin Number

Name

I/O

Description

Address Inputs used to select one of the 64K address locations. Sampled at the

50–44, 81,

82, 99, 100,

32–37

A

Input-

[16:0]

Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE

1

2

3

are sampled active. A

feed the 2-bit counter.

[1:0]

96–93

BW

Input-

Synchronous to the SRAM. Sampled on the rising edge of CLK.

Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of

Synchronous CLK, a global write is conducted (ALL bytes are written, regardless of the values

on BW and BWE).

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes

[3:0]

88

GW

[3:0]

87

89

98

BWE

CLK

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

Synchronous signal must be asserted LOW to conduct a byte write.

Input-Clock

Input-

Clock input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

CE

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

1

Synchronous conjunction with CE and CE to select/deselect the device. ADSP is ignored if

2

3

CE is HIGH.

1

97

92

86

CE

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

2

3

Synchronous conjunction with CE and CE to select/deselect the device.

1

3

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE and CE to select/deselect the device.

1

2

OE

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O

Asynchronous pins. When LOW, the I/O pins behave as outputs. When deserted HIGH, I/O pins

are three-stated, and act as input data pins. OE is masked during the first clock of

a read cycle when emerging from a deselected state.

83

84

ADV

Input-

Synchronous matically increments the address in a burst cycle.

Input- Address Strobe from Processor, sampled on the rising edge of CLK. When assert-

Synchronous ed LOW, A is captured in the address registers. A are also loaded into the

Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-

ADSP

[16:0]

[1:0]

burst counter. When ADSP and ADSC are both asserted, onlyADSP is recognized.

ASDP is ignored when CE is deserted HIGH.

1

85

64

ADSC

ZZ

Input-

Address Strobe from Controller, sampled on the rising edge of CLK. When assert-

Synchronous ed LOW, A

is captured in the address registers. A

are also loaded into the

[16:0]

[1:0]

burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical

Asynchronous “sleep” condition with data integrity preserved. Leaving ZZ floating or NC will de-

fault the device into an active state. ZZ has an internal pull down.

29, 28, 25-22, DQ

19, 18,13,12,

9–6, 3, 2, 79,

78, 75–72,

69, 68, 63, 62

59–56, 53, 52

I/O-

Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by A during the previous clock rise of the

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

[31:0]

[16:0]

read cycle. The direction of the pins is controlled by OE. When OE is asserted

LOW, the pins behave as outputs. When HIGH, DQ

condition.

are placed in a three-state

[31:0]

15, 41, 65, 91

V

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power

supply.

DD

17, 40, 67, 90

V

Ground

Ground for the core of the device. Should be connected to ground of the system.

SS

4, 11, 20, 27,

54, 61, 70, 77

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power

supply.

DDQ

5, 10, 21, 26,

55, 60, 71, 76

V

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

SSQ

31

MODE

Input-

Static

Selects burst order. When tied to GND selects linear burst sequence. When tied

to V

or left floating selects interleaved burst sequence. This is a strap pin and

DDQ

should remain static during device operation. When left floating or NC, defaults to

interleaved burst order. Mode pin has an internal pull up.

1, 14, 16, 30, NC

38, 39, 42, 43,

51, 66, 80

-

No Connects.

3

CY7C1339

sponding address location in the RAM core. If GW is HIGH,

then the write operation is controlled by BWE and BW

sig-

Introduction

[3:0]

nals. The CY7C1339 provides byte write capability that is de-

scribed in the Write Cycle Descriptions table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise (t ) is 3.5 ns (166-MHz

device).

(BW

) input will selectively write to only the desired bytes.

[3:0]

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.

CO

Because the CY7C1339 is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

The CY7C1339 supports secondary cache in systems utilizing

either a linear or interleaved burst sequence. The interleaved

burst order supports Pentium and i486 processors. The linear

burst sequence is suited for processors that utilize a linear

burst sequence. The burst order is user selectable, and is de-

termined by sampling the MODE input. Accesses can be initi-

ated with either the Processor Address Strobe (ADSP) or the

Controller Address Strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input. A

two-bit on-chip wraparound burst counter captures the first ad-

dress in a burst sequence and automatically increments the

address for the rest of the burst access.

to the DQ

inputs. Doing so will three-state the output driv-

[31:0]

ers. As a safety precaution, DQ

are automatically

[31:0]

three-stated whenever a write cycle is detected, regardless of

the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE , CE , CE are all asserted active, and

1

2

3

(4) the appropriate combination of the write inputs (GW, BWE,

and BW ) are asserted active to conduct a write to the de-

[3:0]

Byte write operations are qualified with the Byte Write Enable

sired byte(s). ADSC- triggered write accesses require a single

(BWE) and Byte Write Select (BW

) inputs. A Global Write

[3:0]

clock cycle to complete. The address presented to A is

[16:0]

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchro-

nous self-timed write circuitry.

loaded into the address register and the address advancement

logic while being delivered to the RAM core. The ADV input is

ignored during this cycle. If a global write is conducted, the

Three synchronous Chip Selects (CE , CE , CE ) and an

data presented to the DQ

is written into the corresponding

1

2

3

[31:0]

asynchronous Output Enable (OE) provide for easy bank se-

address location in the RAM core. If a byte write is conducted,

only the selected bytes are written. Bytes not selected during

a byte write operation will remain unaltered. A synchronous

self-timed write mechanism has been provided to simplify the

write operations.

lection and output three-state control. ADSP is ignored if CE

is HIGH.

1

Single Read Accesses

This access is initiated when the following conditions are sat-

isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

Because the CY7C1339 is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

CE , CE , CE are all asserted active, and (3) the write signals

1

2

3

to the DQ

inputs. Doing so will three-state the output driv-

[31:0]

(GW, BWE) are all deserted HIGH. ADSP is ignored if CE is

1

ers. As a safety precaution, DQ

are automatically

[31:0]

HIGH. The address presented to the address inputs (A

) is

[16:0]

three-stated whenever a write cycle is detected, regardless of

the state of OE.

stored into the address advancement logic and the Address

Register while being presented to the memory core. The cor-

responding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 3.5 ns (166-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

OE signal. Consecutive single read cycles are supported.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will three-state

immediately.

Burst Sequences

The CY7C1339 provides a two-bit wraparound counter, fed by

A

, that implements either an interleaved or linear burst se-

[1:0]

quence. The interleaved burst sequence is designed specifi-

cally to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a lin-

ear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Single Write Accesses Initiated by ADSP

Interleaved Burst Sequence

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)

First

Address

Second

Address

Third

Address

Fourth

Address

CE , CE , CE are all asserted active. The address presented

1

2

3

A

[1:0]

to A

is loaded into the address register and the address

[1:0]

[16:0]

advancement logic while being delivered to the RAM core. The

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

write signals (GW, BWE, and BW

nored during this first cycle.

) and ADV inputs are ig-

[3:0]

ADSP-triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ

inputs is written into the corre-

[31:0]

4

CY7C1339

Sleep Mode

Linear Burst Sequence

The ZZ input pin is an asynchronous input. Asserting ZZ plac-

es the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered

valid nor is the completion of the operation guaranteed. The

device must be deselected prior to entering the “sleep” mode.

First

Second

Third

Fourth

Address

A

[1:0]

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

CE , CE , CE , ADSP, and ADSC must remain inactive for the

1

2

3

duration of t

after the ZZ input returns LOW.

ZZREC

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

I

t

Snooze mode

standby current

ZZ > V − 0.2V

3

mA

DDZZ

DD

Deviceoperationto

ZZ

ZZ > V − 0.2V

2t

CYC

ns

ZZS

DD

ZZ recovery time

ZZ < 0.2V

2t

ns

ZZREC

CYC

5

CY7C1339

Cycle Descriptions^{[1, 2, 3]}

Next Cycle

Unselected

Add. Used

None

ZZ

L

H

CE

X

1

CE

X

0

CE

1

ADSP

X

0

ADSC

ADV

X

0

OE

X

1

DQ

Hi-Z

DQ

Write

X

3

2

1

0

X

0

X

0

1

0

1

X

Unselected

None

0

X

Unselected

None

X

1

0

X

Unselected

None

X

0

1

X

Unselected

None

X

0

1

X

Begin Read

External

0

X

Begin Read

0

1

0

1

Read

Write

X

Continue Read

Suspend Read

Begin Write

X

0

X

1

X

1

0

X

1

0

1

Hi-Z

DQ

0

Current

External

X

1

Hi-Z

DQ

1

0

X

1

Hi-Z

DQ

1

0

X

1

X

Hi-Z

Begin Write

X

1

Begin Write

0

X

0

Continue Write

Suspend Write

X

1

0

Current

None

X

1

X

1

ZZ “Sleep”

X

Note:

1. X=”Don't Care,” 1=HIGH, 0=LOW.

2. Write is defined by BWE, BW_[3:0], and GW. See Write Cycle Descriptions table.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6

CY7C1339

Write Cycle Descriptions^{[4, 5, 6]}

Function

GW

1

BWE

1

BW

X

1

BW

X

1

BW

X

1

BW

X

1

3

2

1

0

Read

1

0

Write Byte 0 - DQ

1

0

1

0

[7:0]

Write Byte 1 - DQ

Write Bytes 1, 0

Write Byte 2 - DQ

Write Bytes 2, 0

Write Bytes 2, 1

1

0

1

0

1

[15:8]

1

0

1

0

1

0

1

0

1

[23:16]

1

0

1

0

1

0

1

0

1

0

1

Write Bytes 2, 1, 0

1

0

1

0

Write Byte 3 - DQ

Write Bytes 3, 0

Write Bytes 3, 1

1

0

1

[31:24]

1

0

1

0

1

0

1

0

1

Write Bytes 3, 1, 0

Write Bytes 3, 2

Write Bytes 3, 2, 0

Write Bytes 3, 2, 1

Write All Bytes

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write All Bytes

0

X

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current.................................................... >200 mA

Storage Temperature ..................................... −65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Ambient

Range Temperature

[8]

V

DDQ

DD

Supply Voltage on V Relative to GND.........−0.5V to +4.6V

DD

Com’l

0°C to +70°C

3.3V

−5%/+10%

2.5V −5%

3.3V /+10%

DC Voltage Applied to Outputs

[7]

in High Z State ....................................... −0.5V to V + 0.5V

DD

[7]

Ind’l

–40°C to +85°C

3.3V

−5%/+10%

2.5V −5%

3.3V /+10%

DC Input Voltage .................................... −0.5V to V + 0.5V

DD

Current into Outputs (LOW).........................................20 mA

Note:

4. X=”Don't Care,” 1=Logic HIGH, 0=Logic LOW.

5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW_[3:0].Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is

a don't care for the remainder of the write cycle.

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ=High-Z when OE is inactive or

when the device is deselected, and DQ=data when OE is active.

7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.

8. T_Ais the case temperature.

7

CY7C1339

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

3.135

2.375

2.4

Max.

3.6

Unit

V

Power Supply Voltage 3.3V −5%/+10%

DD

I/O Supply Voltage

2.5V −5% to 3.3V +10%

3.6

V

DDQ

V

Output HIGH Voltage

V

= 3.3V, V = Min., I = –4.0 mA

V

OH

DDQ

DD

OH

= 2.5V, V = Min., I = –2.0 mA

2.0

V

DD

OH

V

Output LOW Voltage

= 3.3V, V = Min., I = 8.0 mA

0.4

0.7

V

OL

DD

OL

= 2.5V, V = Min., I = 2.0 mA

V

DD

OL

V

Input HIGH Voltage

V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

2.0

1.7

V

+ 0.3V

V

IH

IL

DDQ

DD

V

+ 0.3V

V

[7]

Input LOW Voltage

–0.3

−5

0.8

V

[7]

Input LOW Voltage

0.7

5

V

IL

I

Input Load Current

GND ≤ V ≤ V

µA

X

I

DDQ

except ZZ and MODE

Input Current of MODE Input = V

Input = V

−30

−5

µA

SS

5

DDQ

SS

Input Current of ZZ

Input = V

30

5

DDQ

I

Output Leakage

Current

GND ≤ V ≤ V

Output Disabled

−5

OZ

I

DDQ,

V

Operating Supply

V

f = f

= Max., I

= 0 mA,

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

All speeds

420

375

325

150

125

115

10

mA

DD

OUT

= 1/t

MAX CYC

Current

I

Automatic CS

Power-Down

Current—TTL Inputs

Max. V , Device Deselected,

DD

V

f = f

SB1

≥ V or V ≤ V

IN

IH

IN

IL

= 1/t

MAX CYC

I

Automatic CS

Power-Down

Current—CMOS Inputs

Max.V , DeviceDeselected, V

DD IN

≤ 0.3V or V > V

SB2

– 0.3V, f = 0

IN

DDQ

Automatic CS

Power-Down

Current—CMOS Inputs f = f

Max. V , Device Deselected, or 6-ns cycle, 166 MHz

V

125

95

mA

SB3

DD

≤ 0.3V or V > V

– 0.3V

IN

CYC

DDQ

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

= 1/t

MAX

85

I

Automatic CS

Max. V , Device Deselected,

18

SB4

DD

Power-Down

V

≥ V or V ≤ V , f = 0

IN IH IN IL

Current—TTL Inputs

Capacitance^[9]

Parameter

Description

Input Capacitance

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

pF

C

4

IN

A

V

= 3.3V.

DD

Clock Input Capacitance

pF

CLK

= 3.3V

DDQ

Input/Output Capacitance

pF

I/O

Note:

9. Tested initially and after any design or process changes that may affect these parameters.

8

CY7C1339

AC Test Loads and Waveforms

R=317

Ω

3.3V

[10]

OUTPUT

ALL INPUT PULSES

90%

OUTPUT

2.5V

GND

90%

10%

=50

Z

0

Ω

10%

2.5 ns

R =50

Ω

L

5 pF

R=351

Ω

2.5ns

≤

V = 1.5V

L

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

[11,12,13]

Switching Characteristics Over the Operating Range

-166

-133

-100

Parameter

Description

Clock Cycle Time

Min.

6.0

1.7

2.0

0.5

Max.

Min.

7.5

1.9

2.5

0.5

Max.

Min.

Max.

Unit

ns

t

10

3.5

2.5

0.5

CYC

CH

t

Clock HIGH

Clock LOW

CL

Address Set-Up Before CLK Rise

Address Hold After CLK Rise

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

ADSP, ADSC Set-Up Before CLK Rise

ADSP, ADSC Hold After CLK Rise

BWE, GW, BW[3:0] Set-Up Before CLK Rise

BWE, GW, BW[3:0] Hold After CLK Rise

ADV Set-Up Before CLK Rise

ADV Hold After CLK Rise

AS

AH

3.5

4.0

5.5

CO

1.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.0

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

DOH

ADS

ADH

WES

WEH

ADVS

ADVH

DS

Data Input Set-Up Before CLK Rise

Data Input Hold After CLK Rise

Chip Select Set-Up

DH

CES

CEH

CHZ

CLZ

EOHZ

EOLZ

EOV

Chip Select Hold After CLK Rise

[12]

Clock to High-Z

3.5

4.0

3.5

5.5

[12]

Clock to Low-Z

0

[12, 13]

OE HIGH to Output High-Z

[12, 13]

OE LOW to Output Low-Z

[12]

OE LOW to Output Valid

Notes:

10. Input waveform should have a slew rate of 1 V/ns.

11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a) and (b) of AC test loads.

12. t_CHZ, t_CLZ, t_EOV, t_EOLZ, and t_EOHZare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mf from steady-state

voltage.

13. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZ

.

9

CY7C1339

Switching Waveforms

[14, 15]

Write Cycle Timing

Single Write

Burst Write

Pipelined Write

t

Unselected

CH

t

CYC

CLK

t

ADH

t

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

ADSC

ADV

t

ADH

t

ADSC initiated write

ADS

t

ADVH

ADVS

t

ADV Must Be Inactive for ADSP Write

WD2

AS

WD3

WD1

ADD

GW

WE

t

AH

t

WH

t

WH

t

WS

t

WS

t

CES

CE masks ADSP

CEH

1

CE

1

t

CEH

CES

Unselected with CE

2

CE

2

3

t

CES

t

CEH

OE

t

DH

t

DS

High-Z

Data In

3a

2a

= UNDEFINED

2c

2d

1a

2b

= DON’T CARE

Notes:

14. WE is the combination of BWE, BW_[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).

15. WDx stands for Write Data to Address X.

10

CY7C1339

Switching Waveforms (continued)

[14, 16]

Read Cycle Timing

Burst Read

Single Read

Unselected

t

CYC

CH

Pipelined Read

CLK

t

ADH

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

t

ADS

ADSC initiated read

ADSC

ADV

t

ADVS

t

Suspend Burst

ADH

t

ADVH

AS

ADD

GW

WE

RD3

RD1

RD2

t

AH

t

WS

t

WS

t

WH

t

CES

CEH

t

WH

CE masks ADSP

1

CE

1

2

Unselected with CE

2

t

CES

t

CEH

CE

OE

3

CES

t

DOE

t

CEH

t

OEHZ

t

DOH

t

CO

Data Out

2c

1a

3a

2d

2a

2b

t

CLZ

t

CHZ

= DON’T CARE

= UNDEFINED

Note:

16. RDx stands for Read Data from Address X.

11

CY7C1339

Switching Waveforms (continued)

[14, 15, 16, 17]

Read/Write Cycle Timing

Single Read

Single Write

Unselected

Burst Read

t

CYC

t

CH

Pipelined Read

CLK

t

ADH

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

ADSC

ADV

t

ADS

t

ADVS

ADH

t

AS

t

ADVH

ADD

RD1

WD2

RD3

t

AH

GW

WE

t

WS

t

WS

WH

t

CES

t

CEH

WH

CE masks ADSP

1

CE

1

2

t

CES

t

CEH

CE

3

t

DOE

CES

t

CEH

OE

t

OEHZ

t

DS

t

DH

DOH

See Note 17

t

OELZ

2a

3b

Out

3c

Out

3a

Out

3d

Out

Data In/Out

1a

2a

In

Out

t

CO

t

CHZ

= UNDEFINED

= DON’T CARE

Note:

17. Data bus is driven by SRAM, but data is not guaranteed.

12

CY7C1339

Switching Waveforms (continued)

[18, 19]

Pipeline Timing

t

CYC

CL

CH

CLK

t

AS

WD1

WD2

WD3

WD4

RD1

RD2

RD3

RD4

ADD

t

ADS

ADH

ADSC initiated Reads

ADSC

ADSP

ADV

ADSP initiated Reads

t

CEH

CES

CE

1

t

WEH

WES

WE

OE

ADSP ignored

with CE HIGH

1

t

CLZ

Data In/Out

1a

In

1a

2a

3a

4a

2a

In

3a

In

4a

I^Dn^(C)

Out Out Out Out

CO

t

DOH

Back to Back Reads

= DON’T CARE

t

CHZ

= UNDEFINED

Notes:

18. Device originally deselected.

19. CE is the combination of CE₂and CE₃. All chip selects need to be active in order to select the device.

13

CY7C1339

Switching Waveforms (continued)

[20, 21]

ZZ Mode Timing

CLK

ADSP

HIGH

ADSC

CE

1

2

LOW

CE

HIGH

CE

ZZ

3

t

ZZS

I

DD

I

(active)

DD

t

ZZREC

I

DDZZ

I/O’s

Three-state

NotefjdfdhfdjfdfjdjdjdjNo

Note:

20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21. I/Os are in three-state when exiting ZZ sleep mode.

14

CY7C1339

Ordering Information

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

Package Type

166

CY7C1339-166AC

CY7C1339-133AC

CY7C1339-100AC

CY7C1339-133AI

A101

100-Lead Thin Quad Flat Pack

Commercial

133

100

133

Industrial

Document #: 38-00723-C

Package Diagram

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	2N174A
厂家：	ETC
描述：	TRANSISTOR \| BJT \| PNP \| 70V V(BR)CEO \| 15A I(C) \| TO-36 晶体管\| BJT \| PNP \| 70V V（ BR ） CEO \| 15A I（C ） \| TO- 36\n 晶体晶体管
文件：	总20页 (文件大小：1041K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2N174A [ETC]

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