3D3215Z-40 [ETC]
Delay Line ; 延迟线\n
| 型号： | 3D3215Z-40 |
| 厂家： | 
ETC |
| 描述： | Delay Line
|
| 文件： | 总4页 (文件大小：35K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D3215
Ò
MONOLITHIC 5-TAP 3.3V
FIXED DELAY LINE
(SERIES 3D3215)
data
3
delay
inc.
devices,
PACKAGES
FEATURES
·
·
·
·
·
·
·
·
·
·
·
All-silicon, low-power 3.3V CMOS technology
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
IN
O2
O4
1
2
3
4
8
7
6
5
VDD
O1
O3
IN
O2
VDD
1
2
3
4
8
7
6
5
O1
O3
O5
GND
O5
O4
Low ground bounce noise
3D3215Z-xx
SOIC (150 Mil)
GND
Leading- and trailing-edge accuracy
Delay range: 1.5ns through 300ns
Total delay tolerance: 2% or 0.5ns (3.3V, 25C)
Temperature stability: ±1% typical (0C-70C)
Vdd stability: ±1% typical (3.0V-3.6V)
Static Idd: 1.3ma typical
3D3215M-xx
DIP (300 Mil)
For mechanical dimensions, click here.
For package marking details, click here.
Minimum input pulse width: 25% of total delay
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3215 5-Tap Delay Line product family consists of fixed-delay
3.3V CMOS integrated circuits. Each package contains a single delay
line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-
tap (incremental) delay values can range from 1.5ns through 60ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D3215 is 3.3V CMOS-
compatible and features both rising- and falling-edge accuracy.
IN
Delay Line Input
O1
O2
O3
O4
O5
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
VDD +3.3 Volts
GND Ground
The all-CMOS 3D3215 integrated circuit has been designed as a
N/C No Connection
reliable, economic alternative to hybrid fixed delay lines. It is offered in a
standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DASH #
3D3215Z-xx
3D3215M-xx
DELAY SPECIFICATIONS
INPUT RESTRICTIONS
RECOMMENDED ABSOLUTE
Max Freq Min P.W.
TOTAL
TAP-TAP
DELAY (ns)
DELAY (ns)
Max Freq
Min P.W.
6.00 ns
-1.5
-2
-2.5
-3
-4
-5
23.8 MHz
20.8 MHz
18.5 MHz
16.7 MHz
13.9 MHz
11.9 MHz
10.4 MHz
8.33 MHz
6.67 MHz
5.56 MHz
4.42 MHz
3.33 MHz
2.66 MHz
2.22 MHz
1.67 MHz
1.33 MHz
1.11 MHz
21.0 ns
24.0 ns
27.0 ns
30.0 ns
36.0 ns
42.0 ns
48.0 ns
60.0 ns
75.0 ns
90.0 ns
113 ns
150 ns
188 ns
225 ns
300 ns
375 ns
450 ns
83.3 MHz
83.3 MHz
66.7 MHz
55.6 MHz
50.0 MHz
40.0 MHz
55.6 MHz
41.7 MHz
40.0 MHz
33.3 MHz
26.7 MHz
20.0 MHz
16.0 MHz
13.3 MHz
10.0 MHz
8.0 MHz
6.0 ± 0.5*
8.0 ± 0.5*
10.0 ± 0.5*
12.0 ± 0.5*
16.0 ± 0.5*
20.0 ± 0.5*
24.0 ± 0.5*
40.0 ± 0.8
50.0 ± 1.0
60.0 ± 1.2
75.0 ± 1.5
100 ± 2.0
125 ± 2.5
150 ± 3.0
200 ± 4.0
250 ± 5.0
300 ± 6.0
1.5 ± 0.7
2.0 ± 0.8
2.5 ± 1.0
3.0 ± 1.3
4.0 ± 1.3
5.0 ± 1.4
6.0 ± 1.4
8.0 ± 1.4
10.0 ± 1.5
12.0 ± 1.5
15.0 ± 1.5
20.0 ± 2.0
25.0 ± 2.5
30.0 ± 3.0
40.0 ± 4.0
50.0 ± 5.0
60.0 ± 6.0
6.00 ns
7.50 ns
9.00 ns
10.00 ns
12.50 ns
9.00 ns
-6
-8
12.00 ns
12.50 ns
15.00 ns
18.75 ns
25.00 ns
31.25 ns
37.50 ns
50.00 ns
62.50 ns
75.00 ns
-10
-12
-15
-20
-25
-30
-40
-50
-60
6.7 MHz
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns ± 1.5ns
NOTE: Any dash number between 1.5 and 60 not shown is also available as standard
Ó2001 Data Delay Devices
Doc #01014
12/3/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D3215
APPLICATION NOTES
delay accuracy is guaranteed. To guarantee the
Table 1 delay accuracy for input frequencies
higher than the Recommended Maximum
Frequency, the 3D3215 must be tested at the
user operating frequency. Therefore, to facilitate
production and device identification, the part
number will include a custom reference
designator identifying the intended frequency of
operation. The programmed delay accuracy of
the device is guaranteed, therefore, only at the
user specified input frequency. Small input
frequency variation about the selected frequency
will only marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
OPERATIONAL DESCRIPTION
The 3D3215 five-tap delay line architecture is
shown in Figure 1. The delay line is composed of
a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time. The
delay cells are matched and share the same
compensation signals, which minimizes tap-to-tap
delay deviations over temperature and supply
voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Recommended
Maximum and an Absolute Maximum operating
input frequency and a Recommended Minimum
and an Absolute Minimum operating pulse width
have been specified.
OPERATING PULSE WIDTH
The Absolute Minimum Pulse Width (high or
low) specification, tabulated in Table 1,
determines the smallest Pulse Width of the delay
line input signal that can be reproduced, shifted in
time at the device output, with acceptable pulse
width distortion.
OPERATING FREQUENCY
The Recommended Minimum Pulse Width
(high or low) specification determines the
smallest Pulse Width of the delay line input signal
for which the output delay accuracy tabulated in
Table 1 is guaranteed.
The Absolute Maximum Frequency
specification, tabulated in Table 1, determines the
highest frequency of the delay line input signal
that can be reproduced, shifted in time at the
device output, with acceptable duty cycle
distortion.
To guarantee the Table 1 delay accuracy for input
pulse width smaller than the Recommended
Minimum Pulse Width, the 3D3215 must be
tested at the user operating pulse width.
The Recommended Maximum Frequency
specification determines the highest frequency of
the delay line input signal for which the output
Therefore, to facilitate production and device
IN O1
O2
O3
O4
O5
IN
O1
O2
O3
O4
O5
25%
25%
25%
25%
20%
20%
20%
20%
20%
Temp & VDD
Compensation
Temp & VDD
Compensation
Dash numbers < 8
Dash numbers >= 8
VDD
GND
VDD
GND
Figure 1: 3D3215 Functional Diagram
Doc #01014
12/3/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D3215
APPLICATION NOTES (CONT’D)
identification, the part number will include a
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
The thermal coefficient is reduced to 200 PPM/C,
which is equivalent to a variation, over the 0C-
70C operating range, of ±1% or 0.25ns
(whichever is greater) from the 25C delay
settings. The power supply coefficient is reduced,
over the 3.0V-3.6V operating range, to ±1% or
1ns (whichever is greater) of the delay settings at
the nominal 3.3VDC power supply.
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
The temperature and power supply sensitivities
are based on the measured delay of Tap 5 with
respect to Tap 1. The sensitivity of the Input-to-
Tap 1 delay will be somewhat higher, particularly
with the smaller dash numbers.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
It is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D3215 delay line utilizes novel
and innovative compensation circuitry to minimize
the delay variations induced by fluctuations in
power supply and/or temperature.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
VIN
IIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
VDD+0.3
1.0
150
300
UNITS NOTES
V
V
mA
C
25C
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 3.0V to 3.6V)
PARAMETER
SYMBOL
MIN
TYP
1.3
MAX
2.0
UNITS
mA
V
V
mA
NOTES
VDD = 3.6V
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
IDD
VIH
VIL
IIH
IIL
IOH
2.0
0.8
0.1
0.1
-6.0
-0.1
-0.1
0.0
0.0
-8.0
VIH = VDD
VIL = 0V
VDD = 3.0V
VOH = 2.4V
VDD = 3.0V
VOL = 0.4V
CLD = 5 pf
mA
mA
Low Level Output Current
IOL
6.0
7.5
2
mA
ns
Output Rise & Fall Time
TR & TF
*IDD(Dynamic) = 5 * CLD * VDD * F
where: CLD = Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
Doc #01014
12/3/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D3215
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 3.3V ± 0.1V
Rload
:
:
10KW ± 10%
5pf ± 10%
Cload
Input Pulse:
High = 3.3V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance:
Rise/Fall Time:
50W Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.5 x Total Delay
PERIN = 3.0 x Total Delay
Device
Under
Test
Digital
Scope
10KW
Pulse Width:
Period:
5pf
470W
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
OUT1
PULSE
GENERATOR
OUT
OUT2
OUT3
OUT4
OUT5
IN
DIGITAL SCOPE/
TIME INTERVAL COUNTER
DEVICE UNDER
TEST (DUT)
TRIG
IN
TRIG
Figure 2: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
SIGNAL
VIH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
VIL
tPLH
tPHL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Figure 3: Timing Diagram
DATA DELAY DEVICES, INC.
Doc #01014
12/3/01
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
相关型号：
©2020 ICPDF网 联系我们和版权申明