4420-DKDB1 [ETC]
Si4420 Universal ISM Band FSK Transceiver;
| 型号： | 4420-DKDB1 |
| 厂家： | 
ETC |
| 描述： | Si4420 Universal ISM Band FSK Transceiver ISM频段 |
| 文件： | 总33页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4420 Universal ISM
Si4420
Band FSK Transceiver
PIN ASSIGNMENT
DESCRIPTION
Silicon Labs’ Si4420 is a single chip, low power, multi-channel FSK
transceiver designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 315, 433, 868 and 915 MHz
bands. The Si4420 transceiver is a part of Silicon Labs’ EZRadioTM product
line, which produces a flexible, low cost, and highly integrated solution that
does not require production alignments. The chip is a complete analog RF
and baseband transceiver including a multi-band PLL synthesizer with PA,
LNA, I/Q down converter mixers, baseband filters and amplifiers, and an
I/Q demodulator. All required RF functions are integrated. Only an external
crystal and bypass filtering are needed for operation.
Rev C and later
This document refers to Si4420-IC Rev D1.
See www.silabs.com/integration for any applicable
errata. See back page for ordering information.
The Si4420 features a completely integrated PLL for easy RF design, and
its rapid settling time allows for fast frequency-hopping, bypassing
multipath fading and interference to achieve robust wireless links. The
PLL’s high resolution allows the usage of multiple channels in any of the
bands. The receiver baseband bandwidth (BW) is programmable to
accommodate various deviation, data rate and crystal tolerance
requirements. The transceiver employs the Zero-IF approach with I/Q
demodulation. Consequently, no external components (except crystal and
decoupling) are needed in most applications.
FEATURES
Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast-settling, programmable, high-resolution PLL synthesizer
Fast frequency-hopping capability
High bit rate (up to 115.2 kbps in digital mode and 256 kbps
in analog mode)
The Si4420 dramatically reduces the load on the microcontroller with the
integrated digital data processing features: data filtering, clock recovery,
data pattern recognition, integrated FIFO and TX data register. The
automatic frequency control (AFC) feature allows the use of a low accuracy
(low cost) crystal. To minimize the system cost, the Si4420 can provide a
clock signal for the microcontroller, avoiding the need for two crystals.
Direct differential antenna input/output
Integrated power amplifier
Programmable TX frequency deviation (15 to 240 KHz)
Programmable RX baseband bandwidth (67 to 400 kHz)
Analog and digital RSSI outputs
Automatic frequency control (AFC)
Data quality detection (DQD)
Internal data filtering and clock recovery
RX synchron pattern recognition
SPI compatible serial control interface
Clock and reset signals for microcontroller
16 bit RX Data FIFO
For low power applications, the Si4420 supports low duty cycle operation
based on the internal wake-up timer.
FUNCTIONAL BLOCK DIAGRAM
Two 8 bit TX data registers
Low power duty cycle mode
Standard 10 MHz crystal reference
Wake-up timer
MIX
I
DCLK /
CFIL /
AMP
OC
7
6
FFIT
/
clk
13
12
RF1
RF2
Data Filt
CLK Rec
I/Q
DEMOD
Self cal.
OC
FSK /
DATA /
nFFS
LNA
data
MIX
Q
AMP
PA
2.2 to 5.4 V supply voltage
FIFO
Low power consumption
Low standby current (0.3 A)
RSSI
PLL & I/Q VCO
with cal.
COMP
DQD
AFC
RF Parts
BB Amp/Filt./Limiter
Data processing units
Compact 16 pin TSSOP package
WTM
with cal.
CLK div
Xosc
LBD
Low Power parts
Controller
TYPICAL APPLICATIONS
Remote control
Bias
Home security and alarm
Wireless keyboard/mouse and other PC peripherals
Toy controls
8
9
15
1
2
5
10
16
3
4
11
14
CLK
VDD
XTL /
REF
ARSSI SDI
SCK nSEL SDO
nIRQ nRES nINT /
VDI
VSS
Remote keyless entry
Tire pressure monitoring
Telemetry
Remote automatic meter reading
1
Si4420-DS Rev 1.7r 0308
www.silabs.com
Si4420
DETAILED FEATURE-LEVEL DESCRIPTION
The Si4420 FSK transceiver is designed to cover the unlicensed
frequency bands at 315, 433, 868 and 915 MHz. The devices
facilitate compliance with FCC and ETSI requirements.
The receiver block employs the Zero-IF approach with I/Q
demodulation, allowing the use of a minimal number of external
components in a typical application. The Si4420 incorporates a
fully integrated multi-band PLL synthesizer, PA with antenna
tuning, an LNA with switchable gain, I/Q down converter mixers,
baseband filters and amplifiers, and an I/Q demodulator
followed by a data filter.
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip
crystal-controlled reference oscillator. The PLL’s high resolution
allows the usage of multiple channels in any of the bands.
Data Filtering and Clock Recovery
Output data filtering can be completed by an external capacitor
or by using digital filtering according to the final application.
The RF VCO in the PLL performs automatic calibration, which
requires only a few microseconds. Calibration always occurs
when the synthesizer starts. If temperature or supply voltage
changes significantly or operational band has changed, VCO
recalibration is recommended.. Recalibration can be initiated at
any time by switching the synthesizer off and back on again.
Analog operation: The filter is an RC type low-pass filter followed
by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are
integrated on the chip. An (external) capacitor can be chosen
according to the actual bit rate. In this mode, the receiver can
handle up to 256 kbps data rate. The FIFO can not be used in
this mode and clock is not provided for the demodulated data.
RF Power Amplifier (PA)
Digital operation: A digital filter is used with a clock frequency at
29 times the bit rate. In this mode there is a clock recovery
circuit (CR), which can provide synchronized clock to the data.
Using this clock the received data can fill a FIFO. The CR has
three operation modes: fast, slow, and automatic. In slow mode,
its noise immunity is very high, but it has slower settling time and
requires more accurate data timing than in fast mode. In
automatic mode the CR automatically changes between fast and
slow mode. The CR starts in fast mode, then after locking it
automatically switches to slow mode.
The power amplifier has an open-collector differential output and
can directly drive a loop antenna with a programmable output
power level. An automatic antenna tuning circuit is built in to
avoid costly trimming procedures and the so-called “hand effect.”
LNA
The LNA has 250 Ohm input impedance, which functions well
with the proposed antennas (see: Application Notes available
from www.silabs.com/integration)
If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct
matching and to minimize the noise figure of the receiver.
(Only the digital data filter and the clock recovery use the bit rate
clock. For analog operation, there is no need for setting the
correct bit rate.)
The LNA gain can be selected (0, –6, –14, –20 dB relative to the
highest gain) according to RF signal strength. It can be useful in
an environment with strong interferers.
Baseband Filters
The receiver bandwidth is selectable by programming the
bandwidth (BW) of the baseband filters. This allows setting up
the receiver according to the characteristics of the signal to be
received.
An appropriate bandwidth can be chosen to accommodate
various FSK deviation, data rate and crystal tolerance
requirements. The filter structure is 7th order Butterworth low-
pass with 40 dB suppression at 2*BW frequency. Offset
cancellation is done by using a high-pass filter with a cut-off
frequency below 7 kHz.
2
Si4420
When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the Configuration Setting
Command, the chip provides a fixed number (196) of further
clock pulses (“clock tail”) for the microcontroller to let it go to idle
or sleep mode.
Data Validity Blocks
RSSI
A digital RSSI output is provided to monitor the input signal level.
It goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available.
The RSSI settling time depends on the external filter capacitor.
Pin 15 is used as analog RSSI output. The digital RSSI can be
can be monitored by reading the status register.
Low Battery Voltage Detector
The low battery detector circuit monitors the supply voltage and
generates an interrupt if it falls below a programmable threshold
level. The detector circuit has 50 mV hysteresis.
Analog RSSI Voltage vs. RF Input Power
Wake-Up Timer
The wake-up timer has very low current consumption (1.5 μA
typical) and can be programmed from 1 ms to several days with
an accuracy of ±5%.
It calibrates itself to the crystal oscillator at every startup. When
the crystal oscillator is switched off, the calibration circuit
switches it on only long enough for a quick calibration (a few
milliseconds) to facilitate accurate wake-up timing.
Event Handling
In order to minimize current consumption, the transceiver
supports different power saving modes. Active mode can be
initiated by several wake-up events (negative logical pulse on
nINT input, wake-up timer timeout, low supply voltage detection,
on-chip FIFO filled up or receiving a request through the serial
interface).
P1
P2
P3
P4
-65 dBm
-65 dBm
1300 mV
1000 mV
600 mV
300 mV
-100 dBm
-100 dBm
If any wake-up event occurs, the wake-up logic generates an
interrupt signal, which can be used to wake up the
DQD
microcontroller,
effectively
reducing
the
period
the
The Data Quality Detector is based on counting the spikes on the
unfiltered received data. For correct operation, the “DQD
threshold” parameter must be filled in by using the Data Filter
Command.
microcontroller has to be active. The source of the interrupt can
be read out from the transceiver by the microcontroller through
the SDO pin.
Interface and Controller
AFC
An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
bandwidth of the baseband signal path. Division ratio for the
microcontroller clock, wake-up timer period, and low supply
voltage detector threshold are also programmable. Any of these
auxiliary functions can be disabled when not needed. All
parameters are set to default after power-on; the programmed
values are retained during sleep mode. The interface supports
the read-out of a status register, providing detailed information
about the status of the transceiver and the received data.
By using an integrated Automatic Frequency Control (AFC)
feature, the receiver can minimize the TX/RX offset in discrete
steps, allowing the use of:
Inexpensive, low accuracy crystals
Narrower receiver bandwidth (i.e. increased sensitivity)
Higher data rate
Crystal Oscillator
The Si4420 has a single-pin crystal oscillator circuit, which
provides a 10 MHz reference signal for the PLL. To reduce
external parts and simplify design, the crystal load capacitor is
internal and programmable. Guidelines for selecting the
appropriate crystal can be found later in this datasheet.
The transmitter block is equipped with an 8 bit wide TX data
register. It is possible to write 8 bits into the register in burst
mode and the internal bit rate generator transmits the bits out
with the predefined rate.
It is also possible to store the received data bits into a FIFO
register and read them out in a buffered mode.
The transceiver can supply the clock signal for the
microcontroller; so accurate timing is possible without the need
for a second crystal.
3
Si4420
PACKAGE PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
Pin
1
Name
SDI
Type Function
DI
Data input of the serial control interface
2
SCK
DI
Clock input of the serial control interface
3
nSEL
SDO
nIRQ
FSK
DI
Chip select input of the serial control interface (active low)
Serial data output with bus hold (tri-state)
4
DO
DO
DI
5
Interrupt request output (active low)
Transmit FSK data input
6
7
DATA
nFFS
DLCK
CFIL
DO
DI
Received data output (FIFO not used)
FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration Setting Command
Received data clock output (Digital filter used, FIFO not used)
External data filter capacitor connection (Analog filter used)
DO
AIO
FIFO interrupt (active high) Number of the bits in the RX FIFO that reach the preprogrammed limit
In FIFO mode, when bit ef is set in Configuration Setting Command
FFIT
DO
8
9
CLK
XTL
DO
AIO
AIO
DIO
S
Microcontroller clock output
Crystal connection (the other terminal of crystal to VSS) or external reference input
External reference input. Use 33 pF series coupling capacitor
Open drain reset output with internal pull-up and input buffer (active low)
Ground reference voltage
REF
nRES
VSS
RF2
RF1
VDD
10
11
12
13
14
15
AIO
AIO
S
RF differential signal input/output
RF differential signal input/output
Positive supply voltage
ARSSI AO
Analog RSSI output
nINT
VDI
DI
Interrupt input (active low)
16
DO
Valid data indicator output
Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver.
4
Si4420
Typical Application
Typical application with FIFO usage
VCC
C1
1u
C2
100p
C3
10p
(optional)
(optional)
VDI
P7
P6
TP
C4
2.2n
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDI
SCK
nSEL
SDO
nIRQ
nFFS
FFIT
CLK
P5
P4
P3
Si4420
P2
(optional)
(optional)
(optional)
P1
P0
CLKin
PCB
Antenna
nRES (optional)
nRES
X1
10MHz
Pin 6
Pin 7
Transmit mode
TX Data input
-
-
el=0 in Configuration Setting Command
Transmit mode
Connect to logic
high
el=1 in Configuration Setting Command
Receive mode
RX Data clock
output
RX Data output
nFFS input
ef=0 in Configuration Setting Command
Receive mode
FFIT output
ef=1 in Configuration Setting Command
5
Si4420
GENERAL DEVICE SPECIFICATIONS
All voltages are referenced to Vss, the potential on the ground reference pin VSS.
Absolute Maximum Ratings (non-operating)
Symbol
Vdd
Parameter
Min
Max
Units
Positive supply voltage
-0.5
-0.5
-0.5
-25
6
V
Vin
Voltage on any pin (except RF1 and RF2)
Voltage on open collector outputs (RF1, RF2)
Input current into any pin except VDD and VSS
Electrostatic discharge with human body model
Storage temperature
Vdd+0.5
V
V
Voc
Vdd+1.5 (Note 1)
Iin
25
1000
125
260
mA
ESD
Tst
V
-55
oC
oC
Tld
Lead temperature (soldering, max 10 s)
Recommended Operating Range
Symbol
Vdd
Parameter
Min
Max
Units
V
Positive supply voltage
2.2
5.4
Vdd+1.5 (Note 2)
Vdd+1.5
VocDC
VocAC
Top
DC voltage on open collector outputs (RF1, RF2)
AC peak voltage on open collector outputs (RF1, RF2)
Ambient operating temperature
V
V
dd-1.5 (Note 1)
-40
V
85
oC
Note 1: At maximum, Vdd+1.5 V cannot be higher than 7 V. At minimum, Vdd - 1.5 V cannot be lower than 1.2 V.
Note 2: At maximum, Vdd+1.5 V cannot be higher than 5.5 V.
6
Si4420
ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range, typ conditions: Top = 27 oC; Vdd = Voc = 2.7 V)
DC Characteristics
Symbol
Parameter
Conditions/Notes
315/433 MHz bands
868 MHz band
Min
Typ
13
16
17
21
23
24
11
12
13
0.3
Max
14
Units
Supply current
(TX mode, Pout = 0 dBm)
Idd_TX_0
mA
18
19
22
25
26
13
14
15
915 MHz band
315/433 MHz bands
868 MHz band
Supply current
(TX mode, Pout = Pmax
Idd_TX_PMAX
mA
mA
)
915 MHz band
315/433 MHz bands
868 MHz band
Supply current
(RX mode)
Idd_RX
915 MHz band
Ipd
Ilb
Iwt
Ix
Standby current (Sleep mode)
All blocks disabled
µA
µA
µA
mA
Low battery voltage detector current
consumption
0.5
1.5
3
Wake-up timer current consumption
Crystal oscillator and baseband
parts are on
Idle current
3.5
Vlb
Vlba
Vil
Low battery detect threshold
Low battery detection accuracy
Digital input low level voltage
Digital input high level voltage
Digital input current
Programmable in 0.1 V steps
2.25
5.35
V
%
V
+/-3
0.3*Vdd
Vih
Iil
0.7*Vdd
V
Vil = 0 V
-1
-1
1
1
µA
µA
V
Iih
Digital input current
Vih = Vdd, Vdd = 5.4 V
Iol = 2 mA
Vol
Voh
Digital output low level
0.4
Digital output high level
Ioh = -2 mA
Vdd-0.4
V
7
Si4420
AC Characteristics (PLL parameters)
Symbol
Parameter
Conditions/Notes
Min
Typ
10
Max
Units
fref
PLL reference frequency
(Note 1)
8
12
MHz
315 MHz band, 2.5 kHz resolution
433 MHz band, 2.5 kHz resolution
868 MHz band, 5.0 kHz resolution
915 MHz band, 7.5 kHz resolution
Frequency error < 1kHz
310.24
430.24
860.48
900.72
319.75
439.75
879.51
929.27
Receiver LO/Transmitter
carrier frequency
fo
MHz
tlock
tst, P
PLL lock time
20
µs
µs
after 10 MHz step
PLL startup time
With a running crystal oscillator
250
AC Characteristics (Receiver)
Symbol
Parameter
Conditions/Notes
mode 0
Min
60
Typ
Max
75
Units
67
mode 1
120
180
240
300
360
0.6
134
200
270
350
400
150
225
300
375
450
115.2
mode 2
BW
Receiver bandwidth
kHz
mode 3
mode 4
mode 5
BR
FSK bit rate
With internal digital filters
kbps
kbps
dBm
BRA
FSK bit rate
With analog filter
256
Pmin
Receiver Sensitivity
AFC locking range
Input IP3
BER 10-3, BW=67 kHz, BR=1.2 kbps (Note 2)
dfFSK: FSK deviation in the received signal
In band interferers in high bands (868, 915 MHz)
-109
0.8*dfFSK
-21
-100
AFCrange
IIP3inh
dBm
dBm
dBm
dBm
Out of band interferers
l f-fo l > 4 MHz
IIP3outh
IIP3inl
Input IP3
-18
-15
-12
IIP3 (LNA –6 dB gain)
IIP3 (LNA –6 dB gain)
In band interferers in low bands (315, 433 MHz)
Out of band interferers
l f-fo l > 4 MHz
IIP3outl
Pmax
Cin
Maximum input power
RF input capacitance
RSSI accuracy
LNA: high gain
0
1
dBm
pF
1
RSa
RSr
+/-5
46
dB
RSSI range
dB
CARSSI
Filter capacitor for ARSSI
nF
RSSI programmable level
steps
RSstep
RSresp
6
dB
µs
Until the RSSI signal goes high after the input signal
exceeds the preprogrammed limit CARRSI = 5 nF
DRSSI response time
500
All notes for tables above are on page 10.
8
Si4420
AC Characteristics (Transmitter)
Symbol
Parameter
Conditions/Notes
Min
0.5
Typ
Max
Units
IOUT
Open collector output DC current
Programmable
6
mA
Available output power with optimal
antenna impedance
(Note 3, 4)
In low bands
8
4
Pmax
dBm
In high bands
Pout
Psp
Typical output power
Selectable in 2.5 dB steps (Note 5)
Pmax-21
Pmax
-50
dBm
dBc
At max power with loop antenna
(Note 6)
Spurious emission
Output capacitance
(set by the automatic antenna tuning
circuit)
In low bands
In high bands
2
2.6
2.7
3.2
3.3
Co
pF
2.1
In low bands
13
8
15
10
17
12
Quality factor of the output
capacitance
Qo
In high bands
100 kHz from carrier
1 MHz from carrier
-75
-85
Lout
Output phase noise
dBc/Hz
BR
FSK bit rate
256
240
kbps
kHz
dffsk
FSK frequency deviation
Programmable in 15 kHz steps
15
AC Characteristics (Turn-on/Turnaround timings)
Symbol
Parameter
Conditions/Notes
Min
Typ
Max
Units
tsx
Crystal oscillator startup time
Crystal ESR < 100 (Note 8)
1
5
ms
Synthesizer off, crystal oscillator on during
TX/RX change with 10 MHz step
Ttx_rx_XTAL_ON
Trx_tx_XTAL_ON
Ttx_rx_SYNT_ON
Trx_tx_SYNT_ON
Transmitter - Receiver turnover time
Receiver - Transmitter turnover time
Transmitter - Receiver turnover time
Receiver - Transmitter turnover time
450
µs
µs
µs
µs
Synthesizer off, crystal oscillator on during
RX/TX change with 10 MHz step
350
425
300
Synthesizer and crystal oscillator on
during TX/RX change with 10 MHz step
Synthesizer and crystal oscillator on
during RX/TX change with 10 MHz step
AC Characteristics (Others)
Symbol
Parameter
Conditions/Notes
Min
Typ
Max
Units
Crystal load capacitance,
see crystal selection guide
Programmable in 0.5 pF steps, tolerance
+/- 10%
Cxl
8.5
16
pF
After Vdd has reached 90% of final value
(Note 7)
tPOR
Internal POR timeout
150
ms
%
Crystal oscillator must be enabled to
ensure proper calibration at startup
(Note 8)
tPBt
Wake-up timer clock accuracy
+/-10
Cin, D
tr, f
Digital input capacitance
Digital output rise/fall time
2
pF
ns
15 pF pure capacitive load
10
All notes for tables above are on page 10.
9
Si4420
AC Characteristics (continued)
Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will
change accordingly.
Note 2: See the BER diagrams in the measurement results section for detailed information (Not available at this time).
Note 3: See matching circuit parameters and antenna design guide for information.
Note 4: Optimal antenna admittance/impedance:
Si4420
315 MHz
Yantenna [S]
1.5E-3 - j5.14E-3
Zantenna [Ohm]
52 + j179
Lantenna [nH]
98.00
433 MHz
868 MHz
915 MHz
1.4E-3 - j7.1E-3
2E-3 - j1.5E-2
27 + j136
52.00
8.7 + j66
12.50
2.2E-3 - j1.55E-2
9 + j63
11.20
Note 5: Adjustable in 8 steps.
Note 6: With selective resonant antennas (see: Application Notes available from www.silabs.com/integration).
Note 7: During this period, commands are not accepted by the chip. For detailed information see the Reset modes section.
Note 8: The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR
crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray
capacitance.
10
Si4420
CONTROL INTERFACE
Commands (or TX data) to the transceiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock
on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of
a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits
having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command
registers.
The status information or received data can be read serially over the SDO pin. Bits are shifted out upon the falling edge of CLK signal. When
the nSEL is high, the SDO output is in a high impedance state.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
The TX register is ready to receive the next byte (RGIT)
The FIFO has received the preprogrammed amount of bits (FFIT)
Power-on reset (POR)
FIFO overflow (FFOV) / TX register underrun (RGUR)
Wake-up timer timeout (WKUP)
Negative pulse on the interrupt input pin nINT (EXT)
Supply voltage below the preprogrammed value is detected (LBD)
FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the
source of the IT, the status bits should be read out.
Timing Specification
Symbol
tCH
Parameter
Minimum value [ns]
Clock high time
25
25
10
10
25
5
tCL
Clock low time
tSS
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
tSH
tSHI
tDS
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
tDH
5
tOD
10
Timing Diagram
11
Si4420
Control Commands
Control Command
Related Parameters/Functions
Related control bits
Frequency band, crystal oscillator load capacitance,
TX register, RX FIFO
1
2
Configuration Setting Command
el, ef, b1 to b0, x3 to x0
Receiver/Transmitter mode change, synthesizer, xtal
osc, PA, wake-up timer, clock output can be enabled
here
Power Management Command
er, ebb, et, es, ex, eb, ew, dc
3
4
Frequency Setting Command
Data Rate Command
Frequency of the local oscillator/carrier signal
Bit rate
f11 to f0
cs, r6 to r0
Function of pin 16, Valid Data Indicator, baseband
bw, LNA gain, digital RSSI threshold
p16, d1 to d0, i2 to i0, g1 to g0, r2
to r0
5
6
7
Receiver Control Command
Data Filter Command
Data filter type, clock recovery parameters
al, ml, s, f2 to f0
Data FIFO IT level, FIFO start control, FIFO enable
and FIFO fill enable
FIFO and Reset Mode Command
f3 to f0, al, ff, dr
8
9
Receiver FIFO Read Command
AFC Command
RX FIFO can be read with this command
AFC parameters
a1 to a0, rl1 to rl0, st, fi, oe, en
mp, m3 to m0, p2 to p0
t7 to t0
10 TX Configuration Control Command
11 Transmitter Register Write Command
12 Wake-Up Timer Command
Modulation parameters, output power, ea
TX data register can be written with this command
Wake-up time period
r4 to r0, m7 to m0
d6 to d0, en
13 Low Duty-Cycle Command
Enable low duty-cycle mode. Set duty-cycle.
Low Battery Detector and
14 Microcontroller Clock Divider
Command
LBD voltage and microcontroller clock division ratio
Status bits can be read out
d2 to d0, v4 to v0
15 Status Read Command
In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of
the command registers after power-on.
Description of the Control Commands
1. Configuration Setting Command
Bit
15
1
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
POR
el
ef
b1
b0
x3
x2
x1
x0
8008h
Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level.
Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.
b1 b0
Frequency Band {MHz]
x3 x2 x1 x0
Crystal Load Capacitance [pF]
0
0
1
1
0
1
0
1
315
433
868
915
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
8.5
9.0
9.5
10.0
…
1
1
1
1
1
1
0
1
15.5
16.0
12
Si4420
2. Power Management Command
Bit
15
1
14
0
13
0
12
0
11
0
10
0
9
1
8
0
7
6
5
4
3
2
1
0
POR
er
ebb
et
es
ex
eb
ew
dc
8208h
Bit
er
Function of the control bit
Enables the whole receiver chain
Related blocks
RF front end, baseband, synthesizer, oscillator
Baseband
ebb
The receiver baseband circuit can be separately switched on
Switches on the PLL, the power amplifier, and starts the
transmission (If TX register is enabled)
et
Power amplifier, synthesizer, oscillator
es
ex
eb
ew
dc
Turns on the synthesizer
Synthesizer
Turns on the crystal oscillator
Enables the low battery detector
Enables the wake-up timer
Disables the clock output (pin 8)
Crystal oscillator
Low battery detector
Wake-up timer
Clock output buffer
The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time.
Logic connections between power control bits:
enable
power amplifier
et
start TX
Edge
detector
clear TX latch
(If TX latch is used)
enable
RF synthesizer
es
er
(osc.must be on)
enable
RF front end
enable baseband
circuits
ebb
(synt. must be on)
enable
oscillator
ex
13
Si4420
3. Frequency Setting Command
Bit
15
1
14
0
13
1
12
0
11
10
9
8
7
6
5
4
3
2
1
0
POR
f11
f10
f9
f8
f7
f6
f5
f4
f3
f2
f1
f0
A680h
The 12-bit parameter F (bits f11 to f0) should be in the range of
96 and 3903. When F value sent is out of range, the previous
value is kept. The synthesizer center frequency f0 can be
calculated as:
The constants C1 and C2 are determined by
the selected band as:
Band [MHz] C1 C2
315
433
868
915
1
1
2
3
31
43
43
30
f0 = 10 * C1 * (C2 + F/4000) [MHz]
4. Data Rate Command
15
1
14
1
13
0
12
0
11
0
10
1
9
1
8
0
7
cs
6
r6
5
r5
4
r4
3
r3
2
r2
1
r1
0
r0
POR
C623h
Bit
The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit
parameter R (bits r6 to r0) and bit cs.
BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]
In the receiver set R according to the next function:
R= (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps.
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
Clock recovery in slow mode: BR / BR < 1 / (29*Nbit)
Clock recovery in fast mode: BR / BR < 3 / (29*Nbit)
BR is the bit rate set in the receiver and BR is the bit rate difference between the transmitter and the receiver. Nbit is the maximal number of
consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be
careful to use the same division ratio in the receiver and in the transmitter.
5. Power Setting Command
Bit
15
1
14
0
13
0
12
1
11
0
10
9
8
7
6
5
4
3
2
1
0
POR
p16 d1
d0
i2
i1
i0
g1
g0
r2
r1
r0
9080h
Bit 10 (p16): pin16 function select
p16
0
Function of pin 16
Interrupt input
VDI output
1
14
Si4420
Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:
d1 d0 Response
0
0
1
1
0
1
0
1
Fast
Medium
Slow
Always on
CR_LOCK
DQD
d0
d1
SEL0
SEL1
CR_LOCK
FAST
IN0
DRSSI
DQD
MEDIUM
IN1
IN2
IN3
VDI
Y
SLOW
LOGIC HIGH
MUX
DRSSI
DQD
SET
Q
CR_LOCK
R/S FF
CLR
Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:
i2
0
0
0
0
1
1
1
1
i1
0
0
1
1
0
0
1
1
i0
0
1
0
1
0
1
0
1
BW [kHz]
reserved
400
340
270
200
134
67
reserved
15
Si4420
Bits 4-3 (g1 to g0): LNA gain select:
g1 g0
relative to maximum [dB]
0
0
1
1
0
1
0
1
0
-6
-14
-20
Bits 2-0 (r2 to r0): RSSI detector threshold:
r2
r1
0
0
1
1
0
0
1
1
r0
0
1
0
1
0
1
0
1
RSSIsetth [dBm]
0
0
0
0
1
1
1
1
-103
-97
-91
-85
-79
-73
Reserved
Reserved
The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
RSSIth=RSSIsetth+GLNA
6. Data Filter Command
Bit
15
1
14
1
13
0
12
0
11
0
10
0
9
1
8
0
7
al
6
ml
5
1
4
s
3
1
2
f2
1
f1
0
f0
POR
C22Ch
Bit 7 (al): Clock recovery (CR) auto lock control, if set.
CR will start in fast mode, then after locking it will automatically switch to slow mode.
Bit 6 (ml): Clock recovery lock control
1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010...) is recommended)
0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended)
Using the slow mode requires more accurate bit timing (see Data Rate Command).
Bits 4 (s): Select the type of the data filter:
s
0
1
Filter Type
Digital filter
Analog RC filter
Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is
automatically adjusted to the bit rate defined by the Data Rate Command.
Note: Bit rate can not exceed 115 kpbs in this mode.
Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external
capacitor connected to this pin and VSS.
C = 1 / (3 * R * Bit Rate), therefore the suggested value for 9600 bps is 3.3 nF
Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used.
16
Si4420
Bits 2-0 (f2 to f0): DQD threshold parameter.
Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is
close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as
well.
7. FIFO and Reset Mode Command
Bit
15
1
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
f3
6
f2
5
f1
4
f0
3
0
2
al
1
ff
0
dr
POR
CA80h
Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Bit 2 (al): Set the input of the FIFO fill start condition:
al
0
1
Synchron pattern
Always fill
Note: Synchron pattern in microcontroller mode is 2DD4h.
FIFO_LOGIC
al
FIFO_WRITE _EN
FFOV
SYNCHRON
PATTERN
ff
ef*
FFIT
er**
nFIFO_RESET
Note:
* For details see the Configuration Setting Command
** For deatils see the Power Management Command
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
Note: To restart the synchron pattern recognition, bit 1 should be cleared and set.
17
Si4420
8. Receiver FIFO Read Command
Bit
15
1
14
0
13
1
12
1
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
B000h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
nSEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SDI
received bits out
FFIT in RX mode / RGIT otherwise
SDO
MSB
LSB
Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command
9. AFC Command
Bit
15
1
14
1
13
0
12
0
11
0
10
1
9
0
8
0
7
6
5
4
3
2
fi
1
0
POR
a1
a0
rl1
rl0
st
oe
en
C4F7h
Bit 7-6 (a1 to a0): Automatic operation mode selector:
a1
a0
0
0
0
1
Auto mode off (Strobe is controlled by microcontroller)
Runs only once after each power-up
Keep the foffset only during receiving
Keep the foffset value
1
1
0
1
Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
fres:
rl1 rl0
Max deviation
No restriction
+15 fres to -16 fres
+7 fres to -8 fres
+3 fres to -4 fres
0
0
1
1
0
1
0
1
315, 433 MHz bands: 2.5 kHz
868 MHz band: 5 kHz
915 MHz band: 7.5 kHz
Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block.
Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement
uncertainty is about the half.
Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.
18
Si4420
ATGL**
BASEBAND SIGNAL IN
ASAME***
FINE
fi
OFFS
<6:0>
SE L
DIGITAL LIMITER
12 BIT
7 BIT
CLK
Y
10MHz CLK
I0
DIGITAL AFC
CORE LOGIC
ADDER
I1
MUX
FREQ.
OFFSET
REGISTER
/4
IF IN>MaxDEV THEN
OUT=MaxDEV
7
7
ENABLE CALCULATION
AUTO OPERATION
Fcorr<11:0>
en
Corrected frequency
parameter to
VDI*
IF IN<MinDEV THEN
OUT=MinDEV
a1 to a0
synthesizer
singals for auto
operation modes
ELSE
OUT=IN
Power-on reset
(POR)
CLK CLR
RANGE LIMIT
STROBE
rl1 to rl0
st
strobe
output enable
OUTPUT ENABLE
oe
F<11:0>
NOTE:
Parameter from
* VDI (valid data indicator) is an internal signal of the
controller. See the Receiver Setting Command for details.
** ATGL: toggling in each measurement cycle
Frequency control word
*** ASAME: logic high when the result is stable
Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring results are the same, toggle bit
changes state in every measurement cycle.
In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is
automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the
same result in two subsequent cycles.
There are three operation modes, example from the possible application:
1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. In this way extended TX-RX maximum distance can be
achieved.
Possible application:
In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the
crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an
interferer.
2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern –easier to receive-
(i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the
corrected frequency settings.
2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility to
reduce it.
In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use
these settings when receiving signals from different transmitters transmitting in the same nominal frequencies.
3, (a1=1, a0=1) It’s the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a
complete measuring cycle, the measured value is kept independently of the state of the VDI signal.
10. TX Configuration Control Command
Bit
15
1
14
0
13
0
12
1
11
1
10
0
9
0
8
7
6
5
4
3
0
2
1
0
POR
mp
m3
m2
m1
m0
p2
p1
p0
9800h
19
Si4420
Bits 8-4 (mp, m3 to m0): FSK modulation parameters:
The resulting output frequency can be calculated as:
fout = f0 + (-1)SIGN * (M + 1) * (15 kHz)
Pout
where:
f0 is the channel center frequency (see the
Frequency Setting Command)
M is the four bit binary number <m3 : m0>
SIGN = (mp) XOR (FSK input)
dffsk
dffsk
fout
Bits 2-0 (p2 to p0): Output power:
f 0
p2 p1 p0
Relative Output Power [dB]
mp=0 and FSK=0
or
mp=1 and FSK=1
mp=0 and FSK=1
or
mp=1 and FSK=0
0
0
0
0
0
1
0
-3
0
0
1
1
0
1
-6
-9
1
1
1
1
0
0
1
1
0
1
0
1
-12
-15
-18
-21
The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance.
(See: Antenna Application Note: IA ISM-AN1)
11. Transmitter Register Write Command
Bit
15
1
14
0
13
1
12
1
11
1
10
0
9
0
8
0
7
t7
6
t6
5
t5
4
t4
3
t3
2
t2
1
t1
0
t0
POR
B8AAh
With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting
Command.
12. Wake-Up Timer Command
Bit
15
1
14
1
13
1
12
r4
11
r3
10
r2
9
r1
8
r0
7
6
5
4
3
2
1
0
POR
E196h
m7 m6 m5 m4 m3 m2 m1 m0
The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
wake-up = M * 2R [ms]
Note:
T
For continual operation the et bit should be cleared and set at the end of every cycle.
For future compatibility, use R in a range of 0 and 29.
Software reset: Sending FE00h command to the chip triggers software reset. For more details see the Reset modes section.
20
Si4420
13. Low Duty-Cycle Command
Bit
15
1
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
d6
6
d5
5
d4
4
d3
3
d2
2
d1
1
d0
0
en
POR
C80Eh
With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode.
The time cycle is determined by the Wake-Up Timer Command.
The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.)
Duty-Cycle= (D * 2 +1) / M *100%
Xtal osc.
enable
Receiver
On
2.25ms
Ton
2.25ms
Ton
Ton
Twake-up
Twake-up
Twake-up
DQD
Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode.
Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command.
14. Low Battery Detector and Microcontroller Clock Divider Command
Bit
15
1
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
d2
6
d1
5
d0
4
v4
3
v3
2
v2
1
v1
0
v0
POR
C000h
The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage Vlb of the detector:
Vlb= 2.25 + V * 0.1 [V]
Clock divider configuration:
Clock Output
d2 d1 d0
Frequency [MHz]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1.25
1.66
2
2.5
3.33
5
10
The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management
Command.
21
Si4420
15. Status Read Command
The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits
will be clocked out on the SDO pin as follows:
Status Register Read Sequence with FIFO Read Example:
RGIT
FFIT
TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command)
The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the
FIFO read methods)
POR
Power-on reset (Cleared after Status Read Command)
TX register under run, register over write (Cleared after Status Read Command)
RX FIFO overflow (Cleared after Status Read Command)
Wake-up timer overflow (Cleared after Status Read Command)
Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command)
Low battery detect, the power supply voltage is below the pre-programmed limit
FIFO is empty
RGUR
FFOV
WKUP
EXT
LBD
FFEM
ATS
Antenna tuning circuit detected strong enough RF signal
The strength of the incoming signal is above the pre-programmed limit
Data quality detector output
RSSI
DQD
CRL
Clock recovery locked
ATGL
Toggling in each AFC cycle
OFFS(6)
OFFS(3) -OFFS(0)
MSB of the measured frequency offset (sign of the offset value)
Offset value to be added to the value of the frequency control parameter (Four LSB bits)
22
Si4420
TX REGISTER BUFFERED DATA TRANSMISSION
In this operating mode (enabled by bit el, the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers.
The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management
Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored
to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller.
TX Register Simplified Block Diagram (Before Transmit)
TX Register Simplified Block Diagram (During Transmit)
Typical TX Register Usage
Note: The content of the data registers are initialized by clearing bit et.
23
Si4420
RX FIFO BUFFERED DATA READ
In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data
Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being
filled with noise and overloading the external microcontroller.
Polling Mode:
The nFFS signal selects the buffer directly and its content can be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In this case,
as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need
to be taken. An SPI read command is also available.
Interrupt Controlled Mode:
The user can define the FIFO level (the number of received bits), which will generate the nFFIT when exceeded. The status bits report the
changed FIFO status in this case.
FIFO Read Example with FFIT Polling
nSEL
0
1
2
3
4
SCK
nFFS
SDO
FFIT
FIFO read out
FIFO OUT
FO+1
FO+2
FO+3
FO+4
During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency.
24
Si4420
CRYSTAL SELECTION GUIDELINES
The crystal oscillator of the Si4420 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to
minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With
appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.
When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the
oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR
values guarantee faster oscillator startup.
The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO). Therefore fLO is directly
proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be
determined from the maximum allowable local oscillator frequency error.
Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the
load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the “midrange”,
for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C0.
Maximum XTAL Tolerances Including Temperature and Aging [ppm]
Bit Rate: 2.4kbps
Deviation [+/- kHz]
30
45
60
75
90
105
120
315 MHz
25
20
10
10
50
30
20
15
75
50
25
25
100
70
100
90
100
100
50
100
100
60
433 MHz
868 MHz
915 MHz
30
40
30
40
50
50
Bit Rate: 9.6kbps
Deviation [+/- kHz]
30
45
60
75
90
105
120
315 MHz
433 MHz
868 MHz
915 MHz
20
15
8
50
30
15
15
70
50
25
25
75
70
30
30
100
80
100
100
50
100
100
60
40
8
40
50
50
Bit Rate: 38.3kbps
Deviation [+/- kHz]
30
45
60
75
90
105
120
315 MHz
433 MHz
868 MHz
915 MHz
don't use
don't use
don't use
don't use
7
5
3
3
30
20
10
10
50
30
20
15
75
50
25
25
100
75
100
75
30
40
30
40
25
Si4420
RESET MODES
The chip will enter into reset mode if any of the following conditions are met:
Power-on reset: During a power up sequence until the Vdd has reached the correct level and stabilized
Power glitch reset: Transients present on the Vdd line
Software reset: Special control command received by the chip
Hardware reset: nRES input activated
Power-on reset
After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp signal), which
is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual Vdd and the internal
reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the Vdd voltage is less than 1.6V (typical)
the chip stays in reset mode regardless the voltage difference between the Vdd and the internal ramp signal.
The reset event can last up to 150ms supposing that the Vdd reaches 90% its final value within 1ms. During this period the chip does not
accept control commands via the serial control interface.
Power-on reset example:
Power glitch reset
The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be changed
by the appropriate control command (see Related control commands at the end of this section). In normal mode the power glitch detection
circuit is disabled.
There can be spikes or glitches on the Vdd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too
high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the Vdd has a rising
rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the Vdd reaches the reset threshold voltage
(600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current consumption
(for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset cannot be
disabled step-by-step decrease of the current consumption (by turning off the different stages one by one) can help to avoid this problem.
Any negative change in the supply voltage will not cause reset event unless the Vdd level reaches the reset threshold voltage (250mV in
normal mode, 1.6V in sensitive reset mode).
If the sensitive mode is disabled and the power supply turned off the Vdd must drop below 250mV in order to trigger a power-on reset event
when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that no reset will
be generated upon power-up because the power glitch detector circuit is disabled.
Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.
26
Si4420
Sensitive Reset Enabled, Ripple on Vdd
:
Vdd
Reset threshold voltage
(600mV)
Reset ramp line
(100mV/ms)
1.6V
time
H
L
nRes
output
Sensitive reset disabled:
Vdd
Reset threshold voltage
(600mV)
Reset ramp line
(100mV/ms)
250mV
time
H
nRes
output
L
Hardware reset
The hardware reset puts the controller and the corresponding analog circuits into their default state and loads the power-on values of the
registers. This mode can be activated by pulling the nRES input (pin 10) to logic low for at least 1us. The chip is ready for operation 1ms after
releasing (setting to logic H) the nRES pin.
Software reset
Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The result of the
command is the same as if power-on reset was occurred. When the nRES pin connected to the reset pin of the microcontroller, using the
software reset command may cause unexpected problems.
Vdd line filtering
During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to keep
the Vdd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out
from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below
10mVp-p in the DC – 50kHz range for 200ms from Vdd ramp start.. Typical example when a switch-mode regulator is used to supply the radio,
switching noise may be present on the Vdd line. Follow the manufacturer’s recommendations how to decrease the ripple of the regulator IC
and/or how to shift the switching frequency.
Related control commands
“FIFO and Reset Mode Command”
Setting bit<0> to high will change the reset mode to normal from the default sensitive.
“SW Reset Command”
Issuing FE00h command will trigger software reset. See the Wake-up Timer Command.
27
Si4420
RX-TX ALIGNMENT PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to
use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the
output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived
from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be
no offset if the CLK signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the
status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be
disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).
TYPICAL APPLICATIONS
Repeater Demo (915 MHz)
Schematics
IC1
SEL
IC2
SW1
5
2
1
14
13
12
11
10
9
1
4
3
6
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
SJ1
1
2
28
27
26
25
24
23
1
16
15
14
13
12
11
10
9
CLK
IRQ
MOSI
SCK
SEL
MISO
IRQ
INT/VDI
ARSSI
VCC
SDI
NINT/VDI
ARSSI
VDD
GND
R3
2
TX
RX
SCK
NSEL
SDO
NIRQ
820
R4
8
7
3
4
5
6
7
8
820
R5
GND
RF1
22
21
20
19
18
17
16
15
6
5
4
SCK
MISO
MOSI
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/C2D
/RST/C2CK
VDD
820
R6
RF2
820
R7
1k
X1
FFS
FFE
CLK
FSK/DATA/NFFS
DCLK/CFIL
VSS
FFS
FFE
INT/VDI
ARSSI
VCC
NRES
C1
3
GND
CLK
XTL/REF
100nF
GND
Q1
C2
4,7nF
C8051F311
10MHz
IA4420-REVC
GND
GND
3
2
1
3
2
1
TX
RX
GND
GND
J1
DEBUG
GND
GND
3,3V
IC3
1
BATTERY
1
5
4
IN OUT
2
6V
2
3
GND
C3
C4
2,2uF
C5
1uF
C6
C7
ON POK
2,2uF
100pF 10pF
IA2112-3.3V
GND
GND
28
Si4420
PCB Layout
Top View
Bottom View
29
Si4420
PACKAGE INFORMATION
16-pin TSSOP
See Detail “A”
Section B-B
Gauge Plane
0.25
Detail “A”
Dimensions in mm
Nom.
Dimensions in Inches
Nom.
Symbol
Min.
Max.
Min.
Max.
0,047
0,006
0,041
0,012
0,010
0,008
0,006
0,201
A
1,20
0,15
1,05
0,30
0,25
0,20
0,16
5,10
A1
A2
b
0,05
0,80
0,19
0,19
0,09
0,09
4,90
0,002
0,031
0,007
0,007
0,004
0,004
0,90
0,22
0,035
0,009
b1
c
c1
D
5,00
0.65 BSC.
6.40 BSC.
4,40
0,193
0,197
0.026 BSC.
0.252 BSC.
0,173
e
E
E1
L
4,30
0,50
4,50
0,75
0,169
0,020
0,177
0,030
0,60
0,024
L1
R
1.00 REF.
0.39 REF.
0,09
0,09
0
0,004
0,004
0
R1
1
8
8
2
3
12 REF.
12 REF.
12 REF.
12 REF.
30
Si4420
This page has been intentionally left blank.
31
Si4420
RELATED PRODUCTS AND DOCUMENTS
Si4420 Universal ISM Band FSK Transceiver
DESCRIPTION
ORDERING NUMBER
Si4420 16-pin TSSOP
Si4420-IC CC16
Rev D1
Demo Boards and Development Kits
DESCRIPTION
ORDERING NUMBER
IA ISM – DK
Development Kit
ISM Repeater Demo
IA ISM – DARP
Related Resources
DESCRIPTION
ORDERING NUMBER
IA ISM – AN1
IA ISM – AN2
Antenna Selection Guide
Antenna Development Guide
Si4220/21 Universal ISM Band FSK Transmitters
Si4320 Universal ISM Band FSK Receiver
See www.silabs.com for details
See www.silabs.com for details
Note: Volume orders must include chip revision to be accepted.
The specifications and descriptions in this document are based on
information available at the time of publication and are subject to change
without notice. Silicon Laboratories assumes no responsibility for errors or
omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories
assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes to the
product and its documentation at any time. Silicon Laboratories makes no
representations, warranties, or guarantees regarding the suitability of its
products for any particular purpose and does not assume any liability arising
out of the application or use of any product or circuit, and specifically
disclaims any and all liability for consequential or incidental damages arising
out of use or failure of the product. Nothing in this document shall operate
as an express or implied license or indemnity under the intellectual property
rights of Silicon Laboratories or third parties. The products described in this
document are not intended for use in implantation or other direct life support
applications where malfunction may result in the direct physical harm or
injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS
DOCUMENT.
Silicon Labs, Inc.
400 West Cesar Chavez
Austin, Texas 78701
Tel: 512.416.8500
Fax: 512.416.9669
Toll Free: 877.444.3032
www.silabs.com
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Laboratories, Inc. All other trademarks belong to their respective owners.
wireless@silabs.com
32
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