5962-9459902MXX [ETC]
CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM; CMOS NV SRAM 8K ×8自动存储非易失性静态RAM
| 型号： | 5962-9459902MXX |
| 厂家： | 
ETC |
| 描述： | CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM |
| 文件： | 总10页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK12C68-M
CMOS nvSRAM
8K x 8 AutoStore™
Nonvolatile Static RAM
MIL-STD-883 / SMD # 5962-94599
DESCRIPTION
FEATURES
The Simtek STK12C68-M is a fast static RAM (40, 45
and 55ns), with a nonvolatile EEPROM element incor-
porated in each static memory cell. The SRAM can be
• 40, 45 and 55ns Access Times
• 15 mA I at 200ns Access Speed
CC
• Automatic STORE to EEPROM on Power Down
• Hardware or Software initiated STORE to
EEPROM
read and written an unlimited number of times, while
independent nonvolatile data resides in EEPROM.
Data transfers from the SRAM to the EEPROM (the
STOREoperation)takeplaceautomaticallyuponpower
down using charge stored in an external 100 µF
capacitor. Transfers from the EEPROM to the SRAM
(the RECALL operation) take place automatically on
power up. Software sequences may also be used to
• Automatic STORE Timing
• 100,000 STORE cycles to EEPROM
• 10 year data retention in EEPROM
• Automatic RECALL on Power Up
• Software initiated RECALL from EEPROM
• Unlimited RECALL cycles from EEPROM
• Single 5V±10% Operation
initiate both STORE and RECALL operations.
STORE can also be initiated via a single pin.
A
The STK12C68-M is available in the following pack-
ages: a 28-pin 300 mil ceramic DIP and 28-pad LCC.
• Available in multiple standard packages
LOGIC BLOCK DIAGRAM
PIN CONFIGURATIONS
1
V
28
V
CCX
CAP
EEPROM ARRAY
256 x 256
2
3
27
26
W
A
A
A
A
A
A
12
HSB
7
3
2
28 27
26
A3
25
24
1
4
5
A
A
A
G
8
9
6
4
5
A
A
HSB
6
5
4
STORE
5
25
24
23
22
21
A
A
A
8
9
A4
23
22
6
7
6
4
11
A
A
A
A
A5
7
RECALL
STATIC RAM
3
3
2
1
0
11
8
9
21
20
8
A
A
A
E
G
A
E
10
TOP VIEW
2
1
0
0
A6
ARRAY
9
10
A7
10
11
19
18
10
A
DQ
DQ
DQ
DQ
DQ
7
6
20
19
18
A
DQ
DQ
A 0
A12
256 x 256
11
12
DQ
DQ
DQ
0
1
7
6
A8
A9
17
16
15
12
13
14
DQ
DQ
V
5
4
1
2
13 14 15 16 17
HSB
STORE/
RECALL
CONTROL
3
SS
A
12
28 - 300 C-DIP
28 - LCC
DQ0
COLUMN I/O
DQ1
DQ2
DQ3
PIN NAMES
A
- A
12
Address Inputs
0
COLUMN DECODER
W
Write Enable
Data In/Out
DQ - DQ
0
7
DQ4
DQ5
E
Chip Enable
Output Enable
Power (+5V)
Ground
A0
A1
A2
A
A11
10
G
E
G
DQ6
DQ7
V
CCX
V
SS
V
Capacitor
CAP
W
Hardware Store/Busy
HSB
4-53
STK12C68-M
a
ABSOLUTE MAXIMUM RATINGS
Voltage on typical input relative to V . . . . . . . . . . . . . –0.6V to 7.0V Note a: Stresses greater than those listed under "Absolute Maximum
SS
Voltage on DQ and G. . . . . . . . . . . . . . . . . . .–0.5V to (V +0.5V)
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposuretoabsolutemaximumratingconditionsforextended
0-7
CC
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA periods may affect reliability.
(One output at a time, one second duration)
d
DC CHARACTERISTICS
(V = 5.0V ± 10%)
CC
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
b
I
Average V Current
CC
85
80
75
8
mA
mA
mA
mA
t
t
t
= 40ns
CC
1
AVAV
AVAV
AVAV
= 45ns
= 55ns
I
Average V Current During STORE
CC
All inputs ≤ 0.2V or ≥ (V – 0.2V)
CC
2
CC
b
I
Average V Current
CC
15
4
mA
mA
E ≤ 0.2V, W ≥ (V – 0.2V)
CC
CC
3
at t
= 200ns
others ≤ 0.2V or ≥ (V – 0.2V)
AVAV
CC
I
Average VCC current during AutoStore™ cycle
All inputs ≤ 0.2V or ≥ (V - 0.2V)
CC
4
CC
c
I
Average V Current
CC
35
32
28
mA
mA
mA
t
t
t
= 40ns
= 45ns
= 55ns
SB
1
AVAV
AVAV
AVAV
(Standby, Cycling TTL Input Levels)
E ≥ V ; all others cycling
IH
b
I
Average V Current
CC
4
mA
µA
µA
E ≥ (V – 0.2V)
CC
2
CC
(Standby, Stable CMOS Input Levels)
Input Leakage Current (Any Input)
I
±1
±5
V
V
V
V
= max
CC
ILK
= V to V
SS
IN
CC
I
Off State Output Leakage Current
= max
OLK
CC
= V to V
CC
OUT
SS
V
Input Logic "1" Voltage
Input Logic "0" Voltage
Output Logic "1" Voltage
Output Logic "0" Voltage
Operating Temperature
2.2
V
+.5
V
V
All Inputs
All Inputs
IH
CC
V
IL
V
–.5
0.8
SS
V
2.4
V
I
I
= –4mA except HSB
= 8mA except HSB
OH
OUT
OUT
V
0.4
V
OL
T
A
–55
125
°C
Note b: I
and I
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
3
CC
CC
1
Note c: Bringing E ≥ V will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
IH
Note d: V reference levels throughout this datasheet refer to V
CC
if that is where the power supply connection is made, or V
if V
is connected to ground.
CCX
CAP
CCX
AC TEST CONDITIONS
5.0V
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
480 Ohms
Output
30pF
CAPACITANCE (T =25°C, f=1.0MHz)
A
INCLUDING
SCOPE
255 Ohms
AND FIXTURE
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
MAX
UNITS
pF
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
8
7
IN
C
pF
OUT
Figure 1: AC Output Loading
4-54
STK12C68-M
SRAM MEMORY OPERATION
d
(V = 5.0V ± 10%)
CC
READ CYCLES #1 & #2
SYMBOLS
NO.
STK12C68-40M
STK12C68-45M
STK12C68-55M
UNITS
PARAMETER
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
Chip Enable Access Time
40
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
ACS
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
40
45
55
RC
g
3
t
Address Access Time
40
20
45
25
55
35
AA
4
t
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
OE
5
t
5
5
5
5
5
5
OH
6
t
LZ
h
7
t
17
17
35
20
20
45
25
25
55
HZ
8
t
0
0
0
0
0
0
OLZ
h
9
t
GHQZ
OHZ
e
10
11
t
ELICCH
EHICCL
PA
c,e
t
PS
Note c: Bringing E ≥V will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
IH
Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured ± 200mV from steady state output voltage.
f,g
READ CYCLE #1
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (Data Out)
DATA VALID
f
READ CYCLE #2
2
AVAV
t
ADDRESS
E
1
ELQV
t
11
EHICCL
t
6
ELQX
t
7
t
4
EHQZ
t
GLQV
G
8
9
t
t
GLQX
GHQZ
DQ (Data Out)
DATA VALID
10
ELICCH
t
ACTIVE
I
STANDBY
CC
4-55
STK12C68-M
d
WRITE CYCLES #1 & #2
(V = 5.0V ± 10%)
CC
SYMBOLS
NO.
STK12C68-40M
STK12C68-45M
STK12C68-55M
UNITS
PARAMETER
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
35
30
30
18
0
45
35
35
20
0
55
45
45
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
WLEH
ELEH
DVEH
EHDX
AVEH
AVEL
EHAX
WC
WP
CW
DW
DH
t
t
t
t
t
t
t
t
t
t
Write Pulse Width
WLWH
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
ELWH
t
DVWH
t
WHDX
t
30
0
35
0
45
0
AVWH
AW
AS
t
AVWL
t
0
0
0
WHAX
WR
WZ
OW
h,j
t
17
20
25
WLQZ
t
5
5
5
WHQX
Note h: Measured ±200mV from steady state output voltage.
Note i: E or W must be ≥ V during address transitions.
IH
Note j: If W is low when E goes low, the outputs remain in the high impedance state.
i
WRITE CYCLE #1: W CONTROLLED
12
AVAV
t
ADDRESS
14
ELWH
19
t
t
WHAX
E
17
t
AVWH
18
AVWL
13
WLWH
t
t
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
21
t
t
WHQX
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
i
WRITE CYCLE #2: E CONTROLLED
12
AVAV
t
ADDRESS
18
AVEL
14
ELEH
19
EHAX
t
t
t
E
17
AVEH
t
13
WLEH
t
W
DATA IN
15
DVEH
16
t
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA OUT
4-56
STK12C68-M
NONVOLATILE MEMORY OPERATION
MODE SELECTION
E
W
HSB
A
- A (hex)
0
MODE
I/O
POWER
NOTES
12
H
L
L
L
X
H
L
H
H
H
H
X
Not Selected
Read SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
X
l
X
Write SRAM
H
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
X
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output High Z
k,l
k,l
k,l
k,l
k,l
k
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Read SRAM
L
H
H
Active
k,l
k,l
k,l
k,l
k,l
k
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
STORE/Inhibit
X
X
L
I
/Standby
m
CC
2
Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0,
0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details.
Note l: I/O state assumes that G ≤ V . Activation of nonvolatile cycles does not depend on the state of G.
IL
Note m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the
part will go into standby mode inhibiting all operation until HSB rises.
HARDWARE STORE /RECALL
SYMBOLS
NO.
PARAMETER
MIN
MAX
UNITS
NOTES
22
23
24
25
26
t
t
t
t
t
RECALL Cycle Duration
STORE Cycle Duration
HSB Low to Inhibit On
20
10
µs
ms
µs
ns
ns
V
Note o
RECALL
STORE
t
V
≥ 4.5V
CC
HLHH
t
1
DELAY
HLQZ
t
HSB High to Inhibit Off
External STORE Pulse Width
Low Voltage Trigger Level
HSB Output Low Current
HSB Output High Current
300
4.5
60
Note e
Note e
RECOVER
ASSERT
HHQX
t
250
4.0
3
HLHX
V
I
SWITCH
mA
µA
HSB = V , Note e, n
OL
HSB_OL
HSB_OH
I
5
HSB = V , Note e, n
IL
Note e: These parameters guaranteed but not tested.
Note n: HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-Ms to be ganged together for
simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68-M HSB pins.
Note o: A RECALL cycle is initiated automatically at power up when V exceeds V
CC
. t
is measured from the point at which V exceeds 4.5V.
CC
SWITCH RECALL
HARDWARE STORE /RECALL
V
SWITCH
V
26
ASSERT
CAP
24
DELAY
t
t
HSB
W
22
RECALL
24
DELAY
25
t
t
t
RECOVER
RECALL
STORE
23
STORE
23
STORE
23
t
t
t
STORE
SRAM
Inhibit
Power Up RECALL Brown Out RECALL
Power Down STORE
HSB Initiated STORE
Software STORE
4-57
STK12C68-M
d
SOFTWARE STORE/RECALL CYCLE
(V = 5.0V ± 10%)
CC
SYMBOLS
STK12C68-40M
STK12C68-45M
STK12C68-55M
UNITS
NO.
PARAMETER
Std.
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
28
29
30
31
32
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Chip Enable to Output Inactive
Address Set-up to Chip Enable
Chip Enable Pulse Width
35
45
55
ns
ns
ns
ns
ns
AVAV
RC
p
85
85
85
ELQZ
t
t
t
0
25
0
0
35
0
0
45
0
AVELN
ELEHN
AE
EP
EA
q,r
Chip Disable to Address Change
EHAXN
Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note q: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence.
Note r: If the Chip Enable Pulse Width is less than t (see READ CYCLE #2) but greater than or equal to t , then the data may not be valid at the end
ELQV
ELEHN
of the low pulse, however the STORE or RECALL will still be initiated.
Note s: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout.
Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-M performs a STORE or RECALL.
Note t: E must be used to clock in the address sequence for the Software STORE and RECALL cycles.
q,r,t
SOFTWARE STORE/RECALL CYCLE
28
AVAV
28
AVAV
t
t
ADDRESS
E
ADDRESS #1
ADDRESS #2
ADDRESS #6
30
AVELN
32
31
ELEHN
t
t
EHAXN
t
23
STORE
22
t
t
RECALL
29
t
ELQZ
HIGH IMPEDANCE
DQ(Data Out)
VALID
VALID
4-58
STK12C68-M
DEVICE OPERATION
The STK12C68-M has two separate modes of opera- address locations. By relying on READ cycles only, the
tion: SRAM mode and nonvolatile mode. In SRAM STK12C68-M implements nonvolatile operation while
mode, the memory operates as a standard fast static remaining compatible with standard 8Kx8 SRAMs.
RAM. In nonvolatile mode, data is transferred from During the STORE cycle, an erase of the previous
SRAM to EEPROM (the STORE operation) or from nonvolatile data is first performed, followed by a pro-
EEPROMtoSRAM(theRECALL operation). Inthismode gram of the nonvolatile elements. The program opera-
SRAM functions are disabled.
tion copies the SRAM data into the nonvolatile ele-
ments. Once a STORE cycle is initiated, further input
STORE cycles may be initiated under user control via a and output are disabled until the cycle is completed.
software sequence or HSB assertion and are also
automatically initiated when the power supply voltage Because a sequence of addresses is used for STORE
level of the chip falls below V
. RECALL opera- initiation, it is critical that no other read or write ac-
SWITCH
tions are automatically initiated upon power-up and cesses intervene in the sequence or the sequence will
whenever the power supply voltage level rises above be aborted.
V
. RECALL cycles may also be initiated by a
SWITCH
software sequence.
To initiate the STORE cycle the following READ se-
quence must be performed:
SRAM READ
The STK12C68-M performs a READ cycle whenever E
andGareLOW andHSBandWareHIGH. Theaddress
specified on pins A
databyteswillbeaccessed. WhentheREADisinitiated
by an address transition, the outputs will be valid after
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE Cycle
determines which of the 8192
0-12
a delay of t
outputs will be valid at t
. If the READ is initiated by E or G, the
AVQV
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
or at t
, whichever is
ELQV
GLQV
later. The data outputs will repeatedly respond to
address changes within the t access time without
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought HIGH or W or HSB is brought LOW.
AVQV
valid. Afterthet
cycletimehasbeenfulfilled, the
STORE
SRAM will again be activated for READ and WRITE
operation.
SRAM WRITE
A write cycle is performed whenever E and W are LOW
andHSBishigh. Theaddressinputsmustbestableprior
to entering the WRITE cycle and must remain stable
untileitherEorWgoHIGH at the endof the cycle. The
SOFTWARE RECALL
A RECALL cycle of the EEPROM data into the SRAM is
initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
data on pins DQ will be written into the memory if it
0-7
is valid t
before the end of a W controlled WRITE
DVWH
or t
before the end of an E controlled WRITE.
DVEH
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000(hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL Cycle
ItisrecommendedthatGbekeptHIGHduringtheentire
WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
after W goes LOW.
WLQZ
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
SOFTWARE STORE
The STK12C68-M software STORE cycle is initiated by
executing sequential READ cycles from six specific
4-59
STK12C68-M
EEPROMcells. Thenonvolatiledatacanberecalledan connected together. Each chip contains a small inter-
unlimited number of times.
nalcurrentsourcetopullHSBHIGH whenitisnotbeing
driven low. To decrease the sensitivity of this signal to
noise generated on the PC board, it may optionally be
AUTOMATIC RECALL
During power up, or after any low power condition
pulled to V
via an external resistor with a value
CCX
such that the combined load of the resistor and all
parallel chip connections does not exceed I at
(V
< V
), when V
exceeds the sense
CAP
SWITCH
CAP
voltage of V
, a RECALL cycle will automatically
HSB_OL
SWITCH
V
V
. Do not connect this or any other pull-up to the
be initiated. After the initiation of this automatic RE-
CALL, if V falls below V , then another RE-
CALL operation will be performed whenever V
OL
node.
CAP
CAP
SWITCH
CAP
If HSB is to be connected to external circuits other than
otherSTK12C68-Ms,anexternalpull-upresistorshould
be used.
again rises above V
.
SWITCH
If the STK12C68-M is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor should
During any STORE operation, regardless of how it was
initiated, the STK12C68-M will continue to drive the
HSB pin low, releasing it only when the STORE is
complete. Upon completion of a STORE operation, the
part will be disabled until HSB actually goes HIGH.
be connected between W and system V
.
CC
HARDWARE PROTECT
The STK12C68-M offers hardware protection against
inadvertent STORE operation during low voltage
AUTOMATIC STORE OPERATION
During normal operation, the STK12C68-M will draw
conditions. When V
< V
all externally
SWITCH,
CAP
initiated STORE operations will be inhibited.
current from V
to charge up a capacitor connected
CCX
to the V
pin. This stored charge will be used by the
HSB OPERATION
CAP
chip to perform a single STORE operation. After power
up, when the voltage on the V pin drops below
The Hardware Store Busy pin (HSB) is an open drain
circuit acting as both input and output to perform two
different functions. When driven low by the internal
chip circuitry it indicates that a STORE operation (initi-
ated via any means) is in progress within the chip.
When driven low by external circuitry for longer than
CAP
V
V
, the part will automatically disconnect the
SWITCH
CAP
pin from V
and initiate a STORE operation.
CCX
Figure 1 shows the proper connection of capacitors for
automaticstoreoperation. Thechargestoragecapaci-
tor should have a capacity of at least 100µF (± 20%) at
6V. Each STK12C68-M must have its own 100µF
capacitor. Each STK12C68-M must have a high
quality, high frequency bypass capacitor of 0.1µF
t
, the chip will conditionally initiate a STORE
ASSERT
operation after t
.
DELAY
READ and WRITE operations that are in progress when
HSB is driven low (either by internal or external cir-
cuitry) will be allowed to complete before the STORE
operation is performed, in the following manner. After
HSB goes low, the part will continue normal SRAM
connected between V
traces that are as short as possible.
and V , using leads and
CAP
SS
If the AutoStore™ function is not required, then V
should be tied directly to the power supply and V
operations for t
. During t
, a transition on
CAP
CCX
DELAY
DELAY
any address or control signal will terminate SRAM
operation and cause the STORE to commence. Note
that if an SRAM write is attempted after HSB has been
forced low, the write will not occur and the STORE
operation will begin immediately.
should be tied to ground. In this mode, STORE opera-
tions may be triggered through software control or the
HSB pin. In either event, V
have a proper bypass capacitor connected to it.
(Pin 1) must always
CAP
In order to prevent unneededSTORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
Hardware-Store-Busy (HSB) is a high speed, low drive
capability bi-directional control line. In order to allow a
bankofSTK12C68-MstoperformsynchronizedSTORE
functions, the HSB pin from a number of chips may be
4-60
STK12C68-M
WRITE operationhastakenplacesincethemostrecent access cycle time is longer than 55ns. Figure 2 below
STORE cycle. NotethatifHSBisdrivenlowviaexternal shows the relationship between I and access times
CC
circuitry and no WRITEs have taken place, the part will for READ cycles. All remaining inputs are assumed to
still be disabled until HSB is allowed to return HIGH. cycle, and current consumption is given for all inputs at
SoftwareinitiatedSTORE cyclesareperformedregard- CMOS orTTLlevels. Figure3showsthesamerelation-
less of whether or not a WRITE operation has taken ship for WRITE cycles. When E is HIGH, the chip
place.
consumes only standby currents, and these plots do
not apply.
PREVENTING AUTOMATIC STORES
The cycle time used in Figure 2 corresponds to the
length of time from the later of the last address transi-
tion or E goingLOW to the earlier of E going HIGH or the
next address transition. W is assumed to be HIGH,
while the state of G does not matter. Additional current
is consumed when the address lines change state
while E is asserted. The cycle time used in Figure 3
corresponds to the length of time from the later of W or
E going LOW to the earlier of W or E going HIGH.
The AutoStore™ function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15mA at a VOH of at least 2.2V as it will have to
overpower the internal pull-down device that drives
HSB low for 50ns at the onset of an AutoStore™.
When the STK12C68-M is connected for
AutoStore™operation(systemV connectedtoV
CC
CCX
and a 100uF capacitor on V
) and V
crosses
CAP
CC
V
on the way down, the STK12C68 will attempt
SWITCH
topullHSB LOW;ifHSBdoesn'tactuallygetbelowV ,
IL
Theoverallaveragecurrentdrawnbythepartdepends
on the following items: 1) CMOS or TTL input levels; 2)
the time during which the chip is disabled (E HIGH); 3)
the cycle time for accesses (E LOW); 4) the ratio of
reads to writes; 5) the operating temperature; 6) the
the part will stop trying to pull HSB LOW and abort the
AutoStore™attempt.
LOW AVERAGE ACTIVE POWER
The STK12C68-M has been designed to draw signifi-
cantlylesspowerwhenEisLOW (chipenabled)butthe
V
level; and 7) output load.
CC
V
CAP
V
CCX
Power
Supply
100
80
100
80
1
28
26
10K Ohms
(optional)
HSB
60
60
40
+
100uF
± 20%
0.1uF
Bypass
nvSRAM
40
20
0
TTL
TTL
CMOS
150 200
20
0
CMOS
V
SS
14
50
100
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2
(Max) Reads
Figure 3
(Max) Writes
Figure 1
Schematic Diagram
I
CC
I
CC
Note: Typical at 25° C
4-61
STK12C68-M
ORDERING INFORMATION
STK12C68 - 5 C 40 M
Temperature Range
M = Military (-55 to 125 degrees C)
Access Time
40 = 40ns
45 = 45ns
55 = 55ns
Package
C = Ceramic 28 pin 300-mil DIP with gold lead finish
K = Ceramic 28 pin 300-mil DIP with solder DIP finish
L = Ceramic 28 pin LCC
Retention / Endurance
10 years / 100,000 cycles
5962-94599 01 MX X
Lead Finish
A =Solder DIP lead finish
C =Gold lead DIP finish
X =lead finish "A" or "C" is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
01 = 55ns
02 = 45ns
4-62
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