6P29P [ETC]

Analog IC ; 模拟IC\n
6P29P
型号: 6P29P
厂家: ETC    ETC
描述:

Analog IC
模拟IC\n

模拟IC
文件: 总4页 (文件大小:168K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Product Data Sheet  
5V TO 3.3V,  
AND PROGRAMMABLE DC/DC CONVERTER  
WITH PARALLELABLE BOOST MODULES  
6-PAK  
DESCRIPTION  
The 6-PAK™ is a modular system of control and boost  
SIPs.Each 6A control SIP can also drive up to 8 additional  
6A boost SIPs in parallel, for a total of 54A. Each SIP  
accepts a regulated 5V input (+10%) and provides 1.8V to  
3.6Vdc output. The circuit is optimized for high efficiency  
and fast load transient response needed by telecom, DSP  
and microprocessor applications.  
Advanced thermal design, monolithic power circuitry and  
FEATURES  
synchronous rectification result in outstanding performance  
and value.With integrated input filter and output capacitors,  
the 6-PAK system makes a complete power supply which  
requires no external components over the specified  
operating range. Pins are staked for wave solderability.  
!
!
Small SIP Design  
Parallelable Boost SIP  
One stocking part meets a variety of loads  
Programmable Control SIP  
Control/Boost Pair extremely configurable  
Fast Transient Response  
No need for large external capacitors  
Extremely small footprint  
Low Component Count  
Low cost, high reliability  
Staked Pins  
!
!
!
!
!
Wave solderable  
Integrated Input Filter  
Low input ripple  
APPLICATION NOTE  
!
DCAN-34 - 6-PAK Demo Board  
Downloadable from our website -  
cdpowerelectronics.com  
More product information and application notes are available  
on our website at www.cdpowerelectronics.com  
Power Electronics Division, United States  
3400 E Britannia Drive, Tucson, Arizona 85706  
Phone: 520.295.4100 Fax: 520.770.9369  
Power Electronics Division, Europe  
C&D Technologies (Power Electronics) Ltd.  
132 Shannon Industrial Estate, Shannon, Co. Clare, Ireland  
Tel: +353.61.474.133  
Fax:+353.61.474.141  
6-PAK 11/99 REV D  
Page 1  
Electrical Specifications  
Unless otherwise specified, operating conditions are as follows:Vin=5V, Vo=3.3V, Io=6A, TA=25°C, Cin=100µF, C o=µF.  
Parameter  
Input  
Conditions  
Min  
4.5  
0
Typ  
Max  
Units  
Input Voltage  
Input Current Ripple  
Required Capacitance  
Output  
Vin  
Cin  
Vo  
Io  
5.0  
200  
100  
5.5  
VDC  
mARMS  
µF  
Note 1  
Output Voltage  
Nominal  
Note 2  
3.25  
1.8  
0
3.3  
3.35  
3.6  
6
VDC  
VDC  
Output Program Range  
Output Current  
TA=25°C  
20Mhz BW  
Amps  
mVp-p  
µS  
Output Ripple  
50  
Output RiseTime  
Tr  
12  
Output Capacitance Range Co  
Line Regulation  
0
5000  
µF  
+0.5  
+0.5  
0.01  
%
Load Regulation  
Io min - Io max  
%
Temperature Coefficient  
CombinedVariation  
Tc  
%/°C  
Vin min-max &/or Io min-max  
TA=25°C- 85°C  
-2  
+2  
%
Protection  
General  
Note 3  
Switching Frequency  
Dynamic Response  
800  
kHz  
IO/t = 1A/10!sec, Vi = 5.0V, TA = 25°C  
Load Change from IO = 0% to IO = 100%  
Peak Deviation  
60  
mV  
Settling time (VO<10% Peak Deviation)  
Load change from IO = 100% to IO = 0%  
Peak Deviation  
150  
µsec  
90  
mV  
Settling time (VO<10% Peak Deviation)  
100  
µsec  
Temperature  
Operating Temperature  
Storage Temperature  
Note 4  
-40  
+60  
°C  
°C  
+125  
Notes  
1. Input source<3from 6-PAK, load transient <3A per SIP. 100µF low ESR capacitor for load transients >3A per  
SIP.  
2. Optional programming 1.8 - 3.6 or +10% available. See Table.  
3. Short circuit and thermal protection.  
4. 100 lfm air, Vo=3.3V, Io=6A. See Thermal Design Guide for other conditions.  
Page 2  
6-PAK 11/99 REV D  
Programming  
Thermal Design Guide  
The 6-PAKis programmed through the Control SIP. All  
connected Power Boosters follow the Control SIP  
programming. To program the 6-PAKfor Vout<3.3,  
connect a resistor across the TRIM and Vo pins. For  
Vout>3.3, resistor is connected across TRIM and GND.  
Locate your operating current, read the junction temp rise  
from the graph and add to your maximum ambient. 135°C  
is the maximum allowable operating junction temperature.  
Test conditions: Device soldered into 4X 4: PCB, 2-sided  
with power and ground planes for heat conduction. Due to  
the difficulty in predicting the thermal effects of airflow  
velocity and direction, and thermal conduction through  
ground planes, it is important that the 6-PAKbe evaluated  
thermally in each application.For high ambient temperature/  
high current application, please request our Application  
Note, Accurate Measurements of 6-PAKJunction  
Temperature.”  
Table 2  
Vout  
Resistor Value  
Vout  
Resistor Value  
1.8  
1.9  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
0Ω  
15.6Ω  
34Ω  
55.6Ω  
80.6Ω  
110Ω  
147Ω  
196Ω  
255Ω  
332Ω  
2.8  
2.9  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
442Ω  
604Ω  
866Ω  
1.37k  
2.80k  
Open  
2.32k  
1.00k  
649Ω  
T
j
Rise vs. I  
o
(JunctionTemp Rise vs. Output Current)  
Transient Response  
Operating conditions are as follows: Vin=5V, Vo=3.3V, Load  
change from Io=0% to Io=100%, TA=25°C, Cin=0F, Co=µF.  
Output Current - Amps  
Efficiency  
Operating conditions are as follows: Vin=5V, Vo=3.3V, Load  
change from Io=100% to Io=0%, TA=25°C, Cin=0F, Co=µF.  
Output Current - Amps  
Ordering Information  
Typical examples:  
6P  
6P  
25  
-
C
P
6A Control SIP  
25 -  
6A Power Booster SIP  
6-PAK 11/99 REV D  
Page 3  
Mechanical Outline  
TOLERANCES  
+.008for 3 place decimals  
+ .02for 2 place decimals  
+ .002for pin diameter  
Pin Out  
System Interconnection Guidelines  
1. Each SIP must have input, ground and output pins  
sunk into common input ground and output planes in  
the host PC board.  
Pin  
1
2
3
4
5
6
7
8
Function  
Vo  
Description  
Output Voltage  
Output Voltage  
Output Adjust*  
Ground  
InterModule 1  
Ground  
InterModule 2  
5V Input Voltage  
5V Input Voltage  
Vo  
2. Two additional common signal traces are required to  
interconnect INT1 and INT2 pins. These traces must  
be a least 0.06wide and make a straight connection  
among the modules.  
3. Power Booster SIP must be adjacent to the Control  
SIP located in the center of the layout, as shown in  
the Typical Example figure. Recommended distance  
between SIP pin centers is 0.5.  
TRIM  
GND  
INTI  
Gnd  
INT2  
Vi  
9
Vi  
* not connected on Boosters  
Standard Options are shown, consult factory for other available options.  
The information provided herein is believed to be reliable; however, C&D TECHNOLOGIES assumes no responsibility for inaccuracies or omissions. C&D TECHNOLOGIES assumes  
no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No  
patent rights or licenses to any of the circuits described herein are implied or granted to any third party. C&D TECHNOLOGIES does not authorize or warrant any C&D TECHNOLOGIES  
product for use in life support devices/systems or in aircraft control applications.  
Page 4  
6-PAK 11/99 REV D  

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