73M2921-IG [ETC]
Advanced Single Chip Modem; 先进的单芯片调制解调器
| 型号： | 73M2921-IG |
| 厂家： | 
ETC |
| 描述： | Advanced Single Chip Modem |
| 文件： | 总41页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
73M2921
Advanced Single
Chip Modem
Advanced Information
February 1999
DESCRIPTION
FEATURES
The 73M2921 is a CMOS integrated circuit which
provides all the modem “Data Pump” functions
required to implement a V.22bis data modem. It
consists of a DSP (Digital Signal Processor) core
with RAM and ROM data memory, ROM instruction
memory, and register mapped input/output functions
including timers, interrupts, Σ∆ ADC and DAC ports
and Serial Data I/O.
•
•
Automatic handshaking for all data modes
Data Speeds:
V.22bis - 2400 b/s
V.22, Bell 212 - 1200 b/s
V.21, Bell 103 - 300 b/s
V.23 1200 b/s - 75 b/s
Bell 202 1200 b/s
Once the 73M2921 has been initialized, all call
progress and modem handshaking is automatic.
The default conditions may be changed as required
for country specific or custom applications.
•
Facsimile Speeds:
V.29 - 9600, 7200 b/s
V.27ter - 4800, 2400 b/s
V.21 ch 2 - 300 b/s
The 73M2921 provides DTMF tone generation and
detection, precise call progress detect and ADSI
functions such as CAS tone detection.
•
•
•
•
•
V.8bis applications
Designed for 3.3 and 5-Volt systems.
Low operating power.
Other features include a parallel interface control
port between the host processor and the 73M2921.
A
synchronous serial data channel provides
Speaker monitor output
synchronizing clocks RXCLK and TXCLK from the
modem pump to the controller.
Provides 2 tone generators for single tone or
DTMF generation
The 73M2921 contains an oscillator and power
control features.
•
•
Provides DTMF tone detection
Provides 4 precise and 1 imprecise call
progress filters and corresponding detect
The host controller function can be implemented with
a 73M2910 communications micro controller or
another commercial microcontroller (such as the
68302). The 73M2921 has been optimized to work
with the 73M2910 synchronous serial port.
bits with programmable
frequencies
thresholds and
•
•
•
•
Provides CAS tone detection for ADSI and
CLASS feature support
Supports parallel (8 bit) control, and
synchronous serial data I/O
73M2921 provides a microcontroller inter-
rupt
Packaging: The 73M2921 is available in a
QFP production package. A PGA package is
available for prototyping
Rev M
73M2921
Advanced Single
Chip Modem
VPD
VPA
VND
VPA
PWR UP
CLK CNTRL
VBG
VREF
VOLTAGE
REFERENCE
UA[0-1]
CR0
P
UD[0-7]
PORT
MAILBOX
,
READ THE
MAILBOX
PWR UP
DSP
RAM/
ROM
SERIAL
DATA
POWER
UP
INTERRUPTS
CTRL
ANALOG
RESET
DIGITAL
BIT STREAM
CLK CTRL
XTALI
14.4 KHz Samples
INPA
INNA
TIMER
CLOCKS
XTALO
(MODULATOR & DECIMATOR)
OUTPA
OUTNA
(ADC &DAC)
SERIAL CLOCKS
MON
MICCLK
RXD TXD
TXCLK
RXCLK
FIGURE 1 - Block Diagram
Page 2 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
PIN DESCRIPTION
POWER
NAME
VPD
PIN
TYPE
DESCRIPTION
3, 23,
I
DIGITAL POWER: Positive Digital Power.
51, 82
VND
4, 20,
I
DIGITAL POWER: Negative Digital Power.
52, 74
VPA
29, 36
27, 37
32
I
I
ANALOG POWER: Positive Analog Power.
ANALOG POWER: Negative Analog Power.
VNA
VREF
O
VREF: Analog voltage reference for biasing of off chip analog function.
Maximum output current is +/- 20µA.
VBG
33
O
BANDGAP VOLTAGE: Bandgap voltage pin used as a connection point
for an external capacitor for noise reduction only.
CLOCKS AND RESETS
NAME
XTALI
PIN
TYPE
DESCRIPTION
22
I
CRYSTAL INPUT: Onboard crystal oscillator input, or the master clock
input to the 73M2921 if the crystal oscillator is not used.
XTALO
MICCLK
RESET
21
19
40
I
O
I
CRYSTAL OUTPUT: Onboard crystal oscillator output should be left
unconnected if the crystal oscillator on the 73M2921 is not used. Along
with XTALI and proper loading capacitors, these pins include an inverter
for use with parallel resonant mode crystals.
MICROCONTROLLER CLOCK: Programmable clock output for use
when the system oscillator is on the 73M2921. May be used to drive the
system controller. The output frequency is controlled by CR0 bits D11-
D9 (MCLK [2:0]).
MASTER CHIP RESET: Active High Input with hysteresis. Resets the
73M2921 and the control registers. If not used as a reset source, this
pin must be tied low.
February 99 Rev M
TDK Semiconductor
Page 3 of 41
73M2921
Advanced Single
Chip Modem
PIN DESCRIPTION (continued)
POWER CONTROL
NAME
'7,ꢀ
PIN
TYPE
DESCRIPTION
26
I
DATA TERMINAL INTERRUPT 0: Active Low Input with hysteresis.
Power up signal. The action of this pin can be masked by the PSDIS[1]
register bit. This pin would connect to EIA-232 connection DTR in many
applications. Requires a 50KΩ external pull up.
5,1*
24
39
I
RING DETECT: Active Low Input with hysteresis. Power up signal. The
action of this pin can be masked by the PSDIS[0] register bit. This pin
would connect to the ring detect circuitry or the control microcontroller in
many applications. Requires a 50KΩ external pull up.
:$.(
O
WAKE: Active Low Output. Indicates that a power up pin (5,1* or
'7,ꢀ) has been activated when the 73M2921 is in slave mode. The
latched signal remains true until a reset of the wake function by a write to
CR0 LSByte, or a chip reset. Requires a 50KΩ external pull up.
MICROCONTROLLER INTERFACE
NAME
&6
PIN
TYPE
DESCRIPTION
15
I
CHIP SELECT: Active Low Input. Enables data transfers on the µP
parallel interface. Requires a 50KΩ external pull up.
5'
17
16
I
I
I
READ: Active Low Input. Read enable signals for the mailbox/control
register interface.
:5
WRITE: Active Low Input. Write enable signals for the mailbox/control
register interface.
UA[0:1]
13-14
ADDRESS: Address bits that are used by the µP to communicate with
the 73M2921 mailbox and CR0.
UD [0:7]
5-12
18
I/O
O
DATA: Parallel data bus for the mailbox/CR0 interface.
8,17
INTERRUPT: µC interrupt Active Low Output. Used as an interrupt to
the microcontroller indicating that the 73M2921 needs data or has a
request for the µC. It is activated when the 73M2921 writes to the
mailbox and cleared when the µC reads the mailbox LSByte. Requires a
50KΩ external pull up.
Page 4 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
PIN DESCRIPTION (continued)
SERIAL DATA INTERFACE
NAME
PIN
TYPE
DESCRIPTION
RXCLK
45
O
RECEIVE CLOCK: Receive clock for the serial data interface. Data is
transferred from the 73M2921 on the rising edge of the clocks.
TXCLK
42
O
TRANSMIT CLOCK: Transmit clock for the serial data interface. Data is
transferred to the 73M2921 on the rising edge of the clocks.
RXD
TXD
44
41
O
I
RECEIVE DATA: Receive Digital Data.
TRANSMIT DATA: Transmit Digital Data.
AUXILIARY FUNCTIONS
NAME
MON
PIN
TYPE
DESCRIPTION
38
O
MONITOR: Speaker driver. PCM output under software control. See
app note concerning the use of this pin.
PEXT
50
I
EXTERNAL PROGRAM ENABLE: This pin must be tied low for normal
operation.
ANALOG I/O
NAME
PIN
TYPE
DESCRIPTION
INPA,
INNA
34,
35
I
ANALOG INPUT: Differential analog input to a high resolution ADC.
OUTPA,
OUTNA
31,
30
O
ANALOG OUTPUT: Differential analog output from a high resolution
DAC.
HARDWARE REQUIREMENTS
The 73M2921 chip is designed for a single +3.3 or 5 Volt supply and for minimum power consumption
(~100mW @ 3.3V). It supports power down (idle) mode via microcontroller software control. It will also accept
a request for power down from the DTE via hardware control. The device operates from internal ROM/RAM,
but may be configured for external ROM operation and external RAM access (for custom applications) using
either the prototype or the production packages.
LINE/HYBRID INTERFACE
The 73M2921 chip provides a differential analog input and output. This interface will drive a standard Data
Access Arrangement (DAA). The system controller provides additional control such as hook, phone and
auxiliary relay, parallel pickup and in-use detect, and ring detect.
The Internal DAC provides a differential output signal with a maximum output swing of 1.2Vpp, capable of
driving a 50KΩ load. One output can be used alone for a single ended output (with possible performance
degradation).
The internal ADC has a differential input maximum of 1.2Vpp, and provides a biasing resistor to Vref for AC
coupling. One input can be driven while leaving the other floating for a single ended input (with possible
performance degradation). The signal passes through a passive anti-aliasing filter.
February 99 Rev M
TDK Semiconductor
Page 5 of 41
73M2921
Advanced Single
Chip Modem
POWER CONTROL
The power control circuit determines the state of the 73M2921 when powered down, and the means for waking
up the chip. The function is related to the chip and DSP reset functions and is controlled by various input pins
and register bits. The chip pins are 5,1*ꢁ '7,ꢀ, and RESET. The CR0 register bits that control power circuit
function are RSTCHIP, RSTDSPB, ENOSC, ENDSPCK, ENMCLK, and PSDIS (1:0).
POWER CONTROL CIRCUIT FUNCTION
Power consumption can be reduced by turning off or slowing down specific circuit functions in register CR0.
•
•
EN DSP=0: stops DSP clock.
EN MCLK=0: turns off uC clock. MCLK=000: state gives lowest µC clock frequency.
•
•
EN OSC=0: turns off oscillator and analog bias currents.
DSPCK=000: state gives lowest DSP clock frequency.
The 73M2921 has a power-down mode. Access to this mode is described below.
Power Down Mode: To achieve power down first set RSTDSP to 0 in CR0 (bit 0). Second, set ENDSPCK,
ENMCLK, and ENOSC to 0 in CR0 (bits 12, 8, and 7 respectively). Writing a one to ENDSPCK, ENMCLK, and
ENOSC will bring the 73M2921 back to its previous power mode.
Powering up: Toggling the RESET pin, '7,ꢀ, or 5,1* will power the 73M2921 up to Normal mode. Similar
results can be achieved by writing to the reset pin in CR0 (00b, bit 3).
The following is a functionality chart for the power control circuitry. It shows all inputs and describes the effect
on various 73M2921 functions.
INPUT
PIN
AFFECTED SIGNAL OR FUNCTION
5,1*
These are the two pins used to bring the chip out of a power
down state. Their function can be masked by the PSDIS bits
in register CR0.
(Pin 24)
'7,ꢀ
(Pin 26)
CR0 bits
ENDSPCK
(CR0 D12)
Either of these bits in CR0 set to ONE inhibits the generation of a pulse that
will reset the DSP.
ENOSC
(CR0 D7)
PSDIS1
(CR0 D2)
Masks '7,ꢀ input when set.
Masks 5,1* when set.
PSDIS0
(CR0 D1)
Table 4 - Power Control Functions
Page 6 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
POWER CONTROL TIMING
DESCRIPTION
MIN
250
50
TYP
MAX
UNIT
µs
Powerup input to active state
Powerup input to inactive state
µs
Table 5 - Power Control Timing
DCE-DTE INTERFACE
The 73M2921 is designed to interface with a synchronous port such as that found on the TDK 73M2910. It also
provides a parallel control interface. This parallel interface appears as an 8 bit memory mapped peripheral to the
host controller.
SERIAL DATA INTERFACE
The serial data interface is a four pin bi-directional port. It consists of the TXD and RXD data paths (LSBit
shifted in and out first, respectively), the TXCLK and RXCLK serial clock outputs associated with the data pins.
SYMBOL
TXDS
DESCRIPTION
MIN
TYP
Tbd
Tbd
Tbd
MAX
UNIT
ns
DATA to TXCLK
TXDH
TRD
TXCLK to Data Hold
RXCLK to RXD Delay
ns
ns
Table 3 - Serial Data Interface Timing
Synchronous Mode
TXD, RXD
tXDS
tXDS
tXDH
tRD
TXCLK or
RXCLK
Sample Time
FIGURE 7 - Serial Data Interface Timing Diagram
MICROCONTROLLER TO 73M2921 PARALLEL INTERFACE
The interface between the microcontroller (µC) and the 73M2921 is accomplished through the 2 bit address
UA[1:0] and 8 bit data bus UD[7:0], 5', :5, and &6. The 73M2921 chip provides an interrupt output to the µC
(8,17). The 73M2921 and the µC communicate through two 16 bit registers, CR0 and the Mailbox; all µC
accesses are 8 bit transfers. All reading and writing functions to and from the 73M2921 internal registers as well
February 99 Rev M
TDK Semiconductor
Page 7 of 41
73M2921
Advanced Single
Chip Modem
as to internal RAM are performed through these four bytes of memory (see Table 1).
There are 5 separate types of register access possible through the microcontroller interface. These are:
1. Access to CR0.
2. Configuration register access (CR1, CR2), via the Mailbox.
3. Access to the 8-bit General register set via the Mailbox.
4. Unsolicited Response status, via the Mailbox.
5. Memory Block Transfer, via the Mailbox (Not described in this document, please refer to application note
“Using the Mailbox on the 73M2921”).
The host controller initiates all communications over the data bus by sending a command to either read or write to
a location. CR0 is a special case in that it is accessed directly by way of the address bits and does not generate
a response from the 73M2921. All other registers are accessed indirectly by way of a “mailbox” register and will
generate a response from the 73M2921.
UA [1:0]
0 0
ADDRESS
DESTINATION/SOURCE
0
1
2
3
Direct hardware control of CR0 (MSB)
Direct hardware control of CR0 (LSB)
Mailbox function – Control Byte/High Byte
Mailbox function – Data Byte/Low Byte
Write Only
Write Only
Read/Write
Read/Write
0 1
1 0
1 1
Table 1 – Interface Register Address
(1) CONTROL REGISTER CR0 DESCRIPTION
Control Register 0 (CR0) is a 16 bit register that defines functions of general importance to the modem system.
CR0 can be written to directly from the microcontroller interface, and is read/write accessible by the internal DSP.
Control of a number of DSP functions is accomplished by writing two 8 bit bytes to this 16 bit wide register. UA
Address 00b accesses bits D15 through D8 and address 01b is for bits D7 through D0. Writing to these locations
directly access CR0. Writing to the CR0 Register sets an internal bit notifying the internal DSP firmware that the
host microcontroller has issued a command. Access to CR0 does not return a response to the host controller.
Table 2 shows the state of CR0 after various reset conditions. Note that a reset from the register bit D3 (Reset
Chip) does not alter the power-up source mask bit D2 and D1 and they remain unchanged from the previous state
(U = unchanged).
CONDITION D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
D9
1
D8
0
D7
1
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
1
Reset from
Reset Pin
1
1
1
1
1
1
Reset from
CR0 bit D3
1
1
1
1
1
1
1
0
1
0
1
1
0
U
U
1
Table 2 - CR0 State After Reset
State of CR0 after reset from the reset pin and CR0 Reset bit (U = unchanged from previous state)
Page 8 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
REGISTER NAME:
D15 D14 D13
DSPCK (2:0)
CR0
D12
ADDRESS: UA00, 01h
(WRITE ONLY)
D6 D5 D4 D3
MAINCK (2:0) RESET
D11 D10 D9
D8
D7
D2 D1
D0
EN
DSPCK
MCLK (2:0)
EN
EN
PSDIS
(1:0)
567'63
MCLK
OSC
BIT NO.
NAME
567'63
CONDITION
DESCRIPTION
D0
1
Set to a logic 1 by the RESET pin, the RESET CHIP bit, or
by powering up the chip. To enable the DSP, the 567'63
bit must be high.
0
Causes a RESET interrupt to be continuously held for the
DSP. While low, the DSP will remain at instruction location
0x0000.
D1, D2 Power Up
Source
Used to mask the external power up source pins, '7,ꢀ and
5,1*.
Disable[1,0]
A logical 1 on PSDIS[1] masks '7,ꢀ. A logical 1 on
PSDIS[0] masks 5,1*.
D3
Reset Chip
Resets the state of the 73M2921 putting it into a known
state. The function of this bit is similar to that of the RESET
pin, except that this bit does NOT change the setting of the
POWERUP SOURCE DISABLE bits. See Table 2.
D4,
D5,
D6
Main Timer
Clock Divisor
D6 D5 D4
Must be set to provide 4.608MHz to the timer. Default
values
shown
should
be
used
with
the
0
1
1
18.432 MHz oscillator frequency.
D7
Enable
Oscillator
1
Enables the master oscillator. (Must be set to run)
Disables the oscillator and stops all chip activity.
0
D8
Enable Micro-
processor
Clock
For a clean MICCLK transition when stopping the clock (EN
MCLK=0), the EN MCLK bit must be turned off prior to the
oscillator (EN OSC) being disabled.
MICCLK enabled.
MICCLK disabled (Set to 0 if not using MICCLK).
1
0
D9,
D10,
D11
Microcontroller
Clock Divisor
Controls the frequency of the MICCLK output as a function
of the oscillator frequency. Default values shown should be
used with the 18.432 oscillator frequency. Set these to 0 if
not using MICCLK (See Table 3).
D11 D10 D9
1
1
1
D12
Enable DSP
Clock
Set by the RESET pin, the RESET CHIP bit, or by powering
up the chip.
DSP clock enabled. (Must be set to run)
DSP clock disabled.
1
0
D13,
D14,
D15
DSP Clock
Controls the internal DSP clock frequency as a function of the
oscillator frequency. Default values shown should be used with
the 18.432 MHz oscillator frequency.
D15 D14 D13
1
1
1
For a clean DSPCK transition when stopping the DSP (567'63=0), the 567'63 bit must be set low prior to the
oscillator (ENOSC) being disabled.
For a clean DSPCK transition when starting the DSP (567'63=1), the 567'63 bit must be set high after the
oscillator (ENOSC) is enabled. This happens automatically after reset or power up.
February 99 Rev M
TDK Semiconductor
Page 9 of 41
73M2921
Advanced Single
Chip Modem
MCLK
[2:0]
Divisor
MICCLK Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
12
6
1.536
3.072
6.144
12.288
2.304
4.608
9.216
18.432
3
1.5
8
4
2
1
Table 4 - µP clock (MHz) vs. Divisor
USING THE MAILBOX REGISTER1
The mailbox function uses the same data interface as when accessing CR0 but has a different physical
addresses (UA1:0 = 10b, 11b). The Mailbox is configured as two 8-bit bytes which are separated into a Control
byte at address 10b and the Data byte at address 11b.
The 8,17 interrupt is closely coupled to the use of the Mailbox. An interrupt from 8,17 (DSP to microcontroller
interrupt) indicates that the host controller should read the mailbox. This interrupt can be the result of the host
accessing the Mailbox or an “unsolicited interrupt” indicating there has been a change in one of the status
registers. The µC reads the MSB first, then the LSB. Reading the LSB sets 8,17 high and clears the 73M2921
internal mail full flag bit, allowing the 73M2921 to write new data to the mailbox. Mailbox data is not explicitly
formatted. The microcontroller and 73M2921 firmware define the control exchange format.
(2) CONFIGURATION REGISTER ACCESS (CRA)
The configuration registers, CR1 and CR2 control some of the basic operating conditions. Some of the bits in
these registers are for factory use only and should only be set to zero. Others, as noted, must be set to one for
normal operation. Descriptions of CR1 and CR2 follow the programming section.
For Configuration Register Access, the Mailbox Control byte must be set up as follows:
Mailbox Control Byte for Configuration Register Access
D7
RES
0
D6
WT/%7
1
D5
R/:
1/0
D4
D3
0
D2
0
D1
0
D0
1
1
•
•
•
Res = Reserved for DSP use.
WT/BT = Word Transfer/Byte Transfer. Should be 1 (word transfer) for CRA.
R/: = Read/Write. Read = 1, Write = 0
For Configuration Register Access, the Mailbox Data byte specifies CR1 or CR2 as follows:
Mailbox Data Byte for CR1 Access
ꢀ
Page 10 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
D7
1
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
0
Mailbox Data Byte for CR2 Access
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
Reading and writing to the Configuration registers is a four step process for the host processor.
(1) The host processor writes to the Mailbox Control byte:
(a) When writing data to the configuration registers the control byte 051h should be written to UA address
10b.
(b) When reading data from the configuration registers the control byte 071h should be written to UA address
10b.
(2) The Host writes to the Mailbox Data byte (at UA address 11b, write either B0h to access CR1 or D0h to
access CR2). Order is important as the writing of the Data byte triggers an internal interrupt in the DSP
indicating that new mail is present. The 73M2921 will respond through the mailbox. The contents of the
response are not important to the host.
(3) The host reads/writes the high byte of CR1/CR2 at UA address 10b.
(4) The host reads/writes the low byte of CR1/CR2 at UA address 11b.
UA1:0
10
11
XX
10
11
XX
UD[0-7]
MS Byte
LS Byte
DSP Use
MS Byte
LS Byte
FIGURE 2: Interface Bus Activity for Configuration Register Access
February 99 Rev M
TDK Semiconductor
Page 11 of 41
73M2921
Advanced Single
Chip Modem
COMMAND FROM HOST
Control Byte
WRITE TO
MSB
0
CONFIGURATION
REGISTERS
1
0
0
1
1
0
0
0
0
0
1
0
DATA
Data Byte
CHOOSE
CR1
1
1
0
LSB
RESPONSE FROM 73M2921
MSB
X
X
1
0
X
X
0
0
X
X
0
0
X
X
X
X
0
0
X
X
0
0
X
X
0
0
DATA
LSB
X
X
CR DATA FROM HOST
MSB
HIGH BYTE
OF CR1
1
0
DATA
LSB
0
0
LOW BYTE
OF CR1
FIGURE 3: Write Command and Response
An example of a Configuration Register write cycle is shown in figures 2 and 3. Figure 2 shows the activity on the
interface register data pins and 8,17. First there are two command bytes sent by the host processor. The
73M2921 responds (the contents of this response are not important to the host). Then the host writes the high
and low byte of the Configuration register to the 73M2921.
An example of the Control and Data bytes for a CRA write is shown in Figure 3. In this example we will write 90
00h to Configuration register one (CR1). This turns on the digital portion of the 73M2921.
The Control byte shows D6 set to indicate that a word size transfer will take place. D5 is zero to indicate a write
will occur. D4 is set to specify Configuration Register Access. D0 of the Control byte is always 1h for
Configuration Register Access. The data byte shows D7 and D5 set to indicate that CR1 is to be accessed. D4 is
always set for configuration register access. D3:0 are always zero for configuration register access.
The response from the 73M2921 will not be defined.
The word size transfer of CR1 data is also shown in figure 3. The MS byte is 90h. This enables the digital portion
of the 73M2921. The LS byte is 0h. Refer to the configuration register description on pages 10 and 11 for further
information.
Page 12 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
REGISTER NAME:
CR1 Configuration Register 1
ADDRESS: 05H (101b)
CR1 controls Diagnostic modes, data wait, 5V power supply detect, speaker volume, ADC/DAC sampling rate,
slave sync, digital loopback, digital interface loopback, enable digital interface, and enable timer. It also has bits
that are reserved for test modes.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EN
TIMER
TEST
3
TEST
2
EN
DIGI
TDK
TDK
0
0
SLAVE
SYNC
16
KHZ
SPKR VOL
(1:0)
0
5V
DETECT
DATA
WAIT
DIAG
MODE
BIT NO.
NAME
CONDITION
DESCRIPTION
D0
Diagnostic
Mode
(Test Mode)
Always 0
DIAGNOSTIC MODE: Must be zero.
Must be zero.
D1
D2
Data Wait
(Test Mode)
Always 0
5V Detect
(output)
This is a logical 1 if the power supply to the 73M2921 is in the
5V range. Note, this signal is valid only when EN ANALOG
(CR2: D10) is enabled.
D3
0
Not Used.
D4,D5
Speaker
1
1
0
0
1
0
1
0
High Volume
Medium Volume
Low Volume
Speaker off
Volume (1:0)2
D6
D7
16KHz
1
0
1
The ADC/DAC sampling rates are 16.0KHz
The ADC/DAC sampling rates are 14.4KHZ (Default)
Slave Sync
(modem test
mode)
The phase error register measures the time between the rising
edge of RXC and the rising edge of TXC
0
The phase error register measures the time between the rising
edge of EXC and the rising edge of TXC
D8,D9
D10
0
Not Used
TDK
TDK
Always 0
Always 0
1
TDK proprietary.
TDK proprietary.
D11
D12
Enable Digital
Interface
Enables the digital serial interface. Pins TXCLK, RXCLK, TXD,
and RXD are enabled. Must be set to one for normal operation.
0
Tri-states pins TXCLK and RXCLK (with a weak pull-down to 0).
RXD pin is driven to a 1, TXD is disabled at the input pin, and
the timer baud clocks are forced low.
D13
D14
D15
Test 2
Test 3
0
0
1
Must be zero.
Must be zero.
Enable Timer
When set to 1, sample, bit, and clocks for transmit and receive
are running. Baud (provided that EN DIGI is true).
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February 99 Rev M
TDK Semiconductor
Page 13 of 41
73M2921
Advanced Single
Chip Modem
REGISTER NAME:
CR2 Configuration Register 2
ADDRESS: 06H (110b)
CR2 controls analog port enable, analog loopback, ADC receive gain, VREF voltage, charge pump, and wide
transmit bandwidth. It also has bits that are reserved for test modes.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6 D5 D4 D3 D2 D1 D0
WIDE
N/A
VREF
N/A
TDK
EN
TEST TEST
0
0
0
0
0
0
0
0
TX BW
ANALOG
5
4
BIT NO.
D0 – D7
D8
NAME
N/A
CONDITION
DESCRIPTION
Not Used.
0
0
0
1
Test 4
Test 5
Must be zero.
Must be zero.
D9
Analog port turned on. The timer must also be enabled (CR1:D15).
D10
Enable
Analog
NOTE: When the analog port is enabled and the timer is disabled, the
ADC output is looped to the DAC input.
Analog port turned off. All analog currents are off, including the
bandgap generator. The setting of the ENOSC register bit to the
disabled state also forces all analog power to be turned off.
0
0
D11
D12
D13
TDK
N/A
TDK proprietary.
Not used.
VREF
Selects the voltage reference voltage
Set to 0
1.25V DSP detectors require this setting on this version.
Not used.
D14
D15
N/A
1
1
0
Wide Transmit
Bandwidth
Sets the transmit filter to pass 10KHz
Sets the transmit filter to pass 3KHz (default)
(3) GENERAL REGISTER ACCESS (GRA)
For General Register Access (GRA), the mailbox the Control byte from the host controller is broken down into
bit segments as follows:
General Register Access Control Byte: Microcontroller to 73M2921
BIT 7
Res
0
BIT 6
WT/%7
0
BIT 5
R/:
1/0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
---------- Register Address Bits --------------
Res = Reserved
WT/%7 = Word Transfer/Byte Transfer. Should be 0 (byte transfer) for GRA.
R/: = Read / Write. 1 = Read, 0 = Write
Register Address Bits = 5 bit address for the register being accessed. See General Register descriptions in the
following section.
(Register address 00000b is reserved CR0 location)
Reading and writing to the General Registers via the Mailbox is a four step process for the µC.
Page 14 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
(1) The µC writes a Control byte (UA1:0 = 10b) to the mailbox with the R/: bit in the appropriate state for a read
or a write.
(2) Then the µC writes a Data byte (UA1:0 = 11b). The Data byte contains the data to be written or null (00h) if a
read is performed. Order is important as the Data byte triggers an internal interrupt in the 73M2921 firmware
indicating new mail present. The 73M2921 then:
(a) reads the mailbox
(b) writes back to the mailbox register the Control Byte.
(c) writes a response code (if R/: = 0) or data (if R/: = 1) to the Data Byte. The response code will be 00h
for OK and 01h for ERROR
(d) Lowers 8,17 to interrupt the µC indicating that data is in the Mailbox from the 73M2921.
The response from the 73M2921 can either be polled by the host controller or interrupt-driven. In the interrupt-
driven response, an interrupt is issued by the 73M2921 from 8,17 when the response data is available, at which
time the microcontroller reads two bytes (Control, Data) from the 73M2921. Reading valid Data clears the 8,17
interrupt for the next command. All reads and writes to the General registers will get an immediate response. In a
polled mode of operation, if data is not ready, the Control and Data byte will both be zero. When the Control byte
is non-zero, data is available.
(3) The µC reads the Control byte (UA1:0 = 10b).
(4) The µC reads the Data byte (UA1:0 = 11b). The data is the response code if the µC had requested a write, or
the contents of the General Register in the Control address field if the µC had requested a read. This clears
the 8,17 to a high state. The ERROR indicator byte should never be received when communications
between the µC and the 73M2921 are working properly.
The Control byte returned by the 73M2921 is broken down into bit segments as follows:
Control byte 73M2921 to Microcontroller
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UR
1/0
WT/%7
R/:
---------- Register Address Bits --------------
0
1/0
UR = Unsolicited Response. Set if data is not response to last command.
WT/%7 = Word Transfer/Byte Transfer. Should be 0 (byte transfer) for GRA.
R/: = Read = 1, Write = 0.
Register Address shadows last operation.
February 99 Rev M
TDK Semiconductor
Page 15 of 41
73M2921
Advanced Single
Chip Modem
UA XX
10
11
10
11
XX
COMMAND FROM HOST
RESPONSE FROM 73M2921
UD[0-7]
MS Byte
LS Byte
MS Byte
LS Byte
FIGURE 4 – Interface Bus Data Activity
COMMAND FROM HOST CONTROLLER
WRITE TO
H/S REG.
MSB
LSB
0
0
0
0
0
0
0
0
0
0
1
0
DATA
V.22 bis
H/S
0
0
0
1
RESPONSE FROM 73M2921
MSB
LSB
ECHO
OF COMMAND
0
0
0
0
0
0
0
0
0
0
0
0
1
0
DATA
0
0
OK
FIGURE 5 – Write Command and Response
An example of a write cycle is shown in Figure 4 and 5. Figure 4 shows the activity on the interface data pins and
8,17. First there are two command bytes sent by the host controller, then an interrupt is generated in 8,17
telling the host to read the response data, then the controller reads back the response from the 73M2921. The
8,17 interrupt is reset when the LS byte is read.
An example of the Control and Data register data in a write command process is shown in Figure 5. In this
example we will write data to the Handshake Register telling it to perform a V.22bis handshake. The Control byte
shows bit 5 low indicating a write process and the lower 5 address bits are set to address 00001b, the Handshake
register. The Data byte contains the new contents for the Handshake register, in this case 04h, indicating a V.22
handshake will be performed. The 73M2921 processes this command and generates an interrupt on 8,17. The
host then reads the data from the Control register, which echoes the command sent and the Data register which
contain all zeros, or a successful operation. 8,17 is cleared when the Data byte is read.
Page 16 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
UNSOLICITED RESPONSE
A 8,17 (low) interrupt can be the result of the µC doing a General register access (GRA, previously described), or an
Unsolicited Response indicating there has been a change in one of the status registers. An Unsolicited Response is
defined as any response or information sent from the 73M2921 to the mailbox, which was the result of an unsolicited
interrupt from the internal DSP. The general register set 8,17 interrupt service routine must always check bit 7 of the
Control byte to determine whether the interrupt was the result of a GRA in progress or an Unsolicited Response from the
General register set status registers. An Unsolicited Response must always be serviced first, then the GRA in progress
can be resumed. The data received from the 73M2921 is broken into Control and Data fields. Address 10b is the Control
byte and Address 11b is the Data byte.
As an example, the user can enable each individual bit in each Detect Register to create an interrupt every time a
detect bit has changed state. Once a detect bit is enabled, any change in state for that bit will trigger an Unsolicited
Interrupt which sets bit 7 of the control byte to a one and the address bits of the Control byte to the address of the
register which contains the bit that changed state. The Data byte will contain the contents of that register. Reading the
mailbox clears the interrupt from the 73M2921 and allows further interrupts to occur.
The Control byte is broken down into bit segments as follows:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UR
WT/%7
R/:
---------- General Register Address --------------
UR = Unsolicited Response. Set if data is not response to last command.
WT/%7 = Word Transfer/Byte Transfer. Will always be zero (byte transfer) during Unsolicited Interrupt.
R/: = Read/Write. Shadows last command. (Don’t care).
The General Register Address holds detect register address which triggered the interrupt.
In the example shown in Figure 6, the UR bit 7 will be set informing the microcontroller that this is an unsolicited
response. The WT/%7 bit is clear as this is a byte transfer. The address bits hold the address of Detect Register
1 (09h), which generated the interrupt. The Data byte contains the Detect register information. In this case an S1
signal is being received.
UNSOLICITED RESPONSE READ OPERATION
UA XX
10
11
XX
UD[0-7]
MS Byte
LS Byte
CONTROL BYTE
1
X
1
X
0
1
0
0
0
1
0
MSB
LSB
DETECT REGISTER 1 INFORMATION
0
0
0
0
0
X = Don't Care
FIGURE 6 – Unsolicited Interrupt Example
February 99 Rev M
TDK Semiconductor
Page 17 of 41
73M2921
Advanced Single
Chip Modem
2921 GENERAL REGISTER SET SUMMARY
NAME
R/W
FIVE BIT
ADDRESS
(HEX)
COMMENT
Data Mode
Handshake
R/W
01h
Selects automatic handshake to be performed
Connection Detect
DTMF Dial
R
02h
03h
04h
05h
06h
Read Only, indicates successful handshake in Data mode
Sets DTMF digit and twist for transmission
R/W
R
DTMF Detect
Read only, indicates DTMF digit received
Data Mode Control
Test Control
R/W
R/W
Selects answer/originate and retrain modes allowed
Selects test patterns, test mode handshaking,
scrambler/descrambler operation.
Version
R
07h
08h
Read only, revision level of the 73M2921
Detect 1 Enable
R/W
Enables interrupts on changes of state from Detect Reg.
1 status bits.
Detect Register 1
Detect 2 Enable
Detect Register 2
Transmit Control
R
09h
0Ah
0Bh
0Ch
Read only, indicates status of detectors used during
handshaking for various modes.
R/W
R
Enables interrupts on changes of state from Detect Reg.
2 status bits.
Read only, indicates status of detectors used during
handshaking for various modes.
R/W
Selects data format or FSK, carrier transmission in DATA
mode or DTMF transmit enable in CALL PROGRESS
mode.
General Control
R/W
0Dh
Controls transmit power level, idle mode power
consumption, receive gain boost, clock out enable
Fax Handshake
Reserved
R/W
X
0Eh
0Fh
Controls Fax speed and transmit or receive mode
Reserved
Mode Control
R/W
010h
Controls Call Progress, Data or Idle Mode selection. Also
controls method of initialization and modification of
default settings. Affects operation of all registers.
MSE0
MSE1
CPTX
R
R
011h
012h
Read only, Least Significant Byte of the DSP error signal.
Indication of signal quality.
Read only, Most Significant Byte of the DSP error signal.
Indication of signal quality.
R/W
R/W
014h
018h
Controls Call Progress transmit functions.
PCPD Detect
Enable
Enables interrupts on changes of state from PCPD detect
bits.
PCPD Detect
R
019h
Read only, indicates detection of precise call progress
tones.
Note: Reserved bits should never be programmed to a 1 state.
Page 18 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
HANDSHAKE REGISTER
ADDRESS: 01H (01d, 00001b) MODE: DATA
BIT D7
V.23
BIT NO.
D0
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
BIT D1
BIT D0
V.21
Bell 103
Bell 212
V.22
V.22bis
Bell 202
Res.
NAME
CONDITION
DESCRIPTION
Reserved for future use.
Reserved
Bell 202
V.22bis
V.22
1
1
1
1
1
1
1
1
D1
Instructs the modem to attempt a Bell 202 handshake
Instructs the modem to attempt a V.22bis handshake
Instructs the modem to attempt a V.22 handshake
Instructs the modem to attempt a Bell 212 handshake
Instructs the modem to attempt a Bell 103 handshake
Instructs the modem to attempt a V.21 handshake
Instructs the modem to attempt a V.23 handshake
D2
D3
D4
Bell 212
Bell 103
V.21
D5
D6
D7
V.23
Note: The Handshake register defines the handshake methods allowed during the connection phase of a
communication session. Only one bit can be set at a given time except for automatic V.22bis fallback to V.22 or
Bell 212A which requires both BIT D2 and BIT D3 to be set. The master transmit enable, TXEN, BIT D7 of the
TRANSMIT CONTROL REGISTER (0CH) must be set for the handshake transmit functions to operate.
CONNECTION DETECT REGISTER (READ ONLY) ADDRESS: 02h (02d, 00010b) MODE: DATA, FAX
BIT D7
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
BIT D1
BIT D0
V.23 (data)
V.29 (fax)
V.21 (data)
V.21 CH2 (fax)
Bell 103
Bell 212
V.22 (data)
V.27ter (fax)
V.22bis
Bell 202
Res.
BIT
NAME
CONDITION
DESCRIPTION
NO.
D0
D1
D2
D3
Reserved
Bell 202
V.22bis
Reserved for future use.
Informs processor Bell 202 was detected.
Informs processor of a successful V.22bis connection.
Informs processor of a successful V.22 connection.
Informs processor of a successful V.27ter connection.
Data Mode
Fax Mode
V.22
V.27ter
Bell 212
Bell 103
D4
D5
D6
Informs processor of a successful Bell 212A connection.
Informs processor of a successful Bell 103 connection.
Informs processor of a successful V.21 connection.
Informs processor of a successful V.21 CH2 connection.
Data Mode
Fax Mode
V.21
V.21 CH2
D7
Data Mode
Fax Mode
Informs processor of a successful V.23 connection.
Informs processor of a successful V.29 connection.
V.23
V.29
Note: All bits are zero until a successful connection has been established (carrier detect valid, data mode active).
Then the appropriate bit will be set. This register is shared between fax and data modes. Only bits D3, D6, and
D7 are valid when in fax mode.
February 99 Rev M
TDK Semiconductor
Page 19 of 41
73M2921
Advanced Single
Chip Modem
DTMF DIAL REGISTER
ADDRESS: 03h (03d, 00011b) MODE: CALL PROGRESS
BIT D7
BIT D6
BIT D5
BIT D4
TWIST0
BIT D3
BIT D2
BIT D1
BIT D0
RES
TWIST2
TWIST1
DTMF3
DTMF2
DTMF1
DTMF0
BIT NO.
D3, D2, D1, D0
NAME
CONDITION
DESCRIPTION
DTMF 3-0
Digit
D3 D2 D1 D0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Transmits 697 Hz & 1209 Hz
Transmits 697 Hz & 1336 Hz
Transmits 697 Hz & 1477 Hz
Transmits 770 Hz & 1209 Hz
Transmits 770 Hz & 1336 Hz
Transmits 770 Hz & 1477 Hz
Transmits 852 Hz & 1209 Hz
Transmits 852 Hz & 1336 Hz
Transmits 852 Hz & 1477 Hz
Transmits 941 Hz & 1336 Hz
Transmits 941 Hz & 1209 Hz
Transmits 941 Hz & 1477 Hz
Transmits 697 Hz & 1633 Hz
Transmits 770 Hz & 1633 Hz
Transmits 852 Hz & 1633 Hz
Transmits 941 Hz & 1633 Hz
Relative Level
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
Twist 2-0
D6 D5 D4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 dB (Same levels)
1 dB Low tone below the high tone
2 dB Low tone below the high tone (Default)
3 dB Low tone below the high tone
4 dB Low tone below the high tone
5 dB Low tone below the high tone
6 dB Low tone below the high tone
7 dB Low tone below the high tone
Reserved for future use.
D7
Reserved
The TXDT BIT 3 of the TRANSMIT CONTROL REGISTER (0Ch) must be set for DTMF tone transmission. TXDT
is gated on and off during the transmission of tones when dialing DTMF digits.
Page 20 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
DTMF DETECT REGISTER
ADDRESS: 04h (04d, 00100b) MODE: CALL PROGRESS
BIT D7
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
BIT D1
BIT D0
Det. Valid
RES.
RES.
RES.
DTDET
3
DTDET
2
DTDET
1
DTDET
0
BIT NO.
NAME
CONDITION
DIGIT
DESCRIPTION
D3, D2, D1, D0
DTMF
Detect 3-0
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2 D1
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
2
3
4
5
6
7
8
9
0
*
Detects 697 Hz & 1209 Hz
Detects 697 Hz & 1336 Hz
Detects 697 Hz & 1477 Hz
Detects 770 Hz & 1209 Hz
Detects 770 Hz & 1336 Hz
Detects 770 Hz & 1477 Hz
Detects 852 Hz & 1209 Hz
Detects 852 Hz & 1336 Hz
Detects 852 Hz & 1477 Hz
Detects 941 Hz & 1336 Hz
Detects 941 Hz & 1209 Hz
Detects 941 Hz & 1477 Hz
Detects 697 Hz & 1633 Hz
Detects 770 Hz & 1633 Hz
Detects 852 Hz & 1633 Hz
Detects 941 Hz & 1633 Hz
#
A
B
C
D
D4, D5, D6
D7
Reserved
Reserved for future use
Valid
DTMF
Detect
1
0
Indicates a valid DTMF detection
Indicates no detect for polled applications
February 99 Rev M
TDK Semiconductor
Page 21 of 41
73M2921
Advanced Single
Chip Modem
DATA MODE CONTROL REGISTER
ADDRESS: 05h (05d, 00101b)
MODE: DATA
BIT D7
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
BIT D1
BIT D0
RESERVED
ANS
GTEN
GTONE
RESERVED
RESERVED
RESERVED
RT FORCE
BIT NO.
NAME
CONDITION
DESCRIPTION
D0
Retrain
Force
1
Forces a retrain request. Cleared by 73M2921.
D1
D2
D3
D4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Guard
Tone
1
0
1
Sets the guard tone to 550 Hz
Sets the guard tone to 1800 Hz
Enables the guard tones
D5
D6
Guard
Tone
Enable
Answer/
Originate
1
Sets the modem to be in Answer mode. When
Modulation is set for V.23, the 73M2921 transmits in
main channel @ 1200 b/s and Receives in back
channel @ 75 bps. When Modulation is set for Bell
202, the 73M2921 transmits @ 1200 bps.
(Main
Channel
Selection)
Sets the modem into Originate mode. When
Modulation is set for V.23, the 73M2921 receives in
main channel @ 1200 bps and Transmits in back
channel @ 75 bps. When Modulation is set for Bell
202, the 73M2921 receives at 1200 bps.
0
D7
Reserved
Reserved for future use
Page 22 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
TEST CONTROL REGISTER
ADDRESS: 06h (06d, 00110b)
MODE: DATA*
BIT D7
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
SDP2
BIT D1
BIT D0
ALB
RDLB
DSD1
SCD1
SDP3
SDP1
SDP0
BIT NO.
NAME
CONDITION
DESCRIPTION
D3 D2
D1
0
D0
0
D3, D2, D1, D0
Send Data
Pattern
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
Send Data
Send Marks
Send Space
0
1
1
0
1
1
Send Dotting Pattern (Not valid for FSK)
Send S1 (Not valid for FSK)
Send S0 (Not valid for FSK)
Reserved
0
0
0
1
1
0
1
1
Reserved
X
X
Reserved
D4
D5
D6
Scrambler
Disable
1
1
1
Disables the scrambler
(V.22bis, V.22, Bell212)
Disables the Descrambler
(V.22bis, V.22, Bell212)
Descrambler
Disable
Remote
Digital
Loopback
Instructs the modem to perform a
Remote Digital Loopback connection
(V.22bis, V.22, Bell212)
D7
Analog
Loopback
1
Instructs the modem to perform an
Analog Loopback connection
(V.22bis, V.22, Bell212, Bell 103,
V.21)
VERSION REGISTER (READ ONLY)
ADDRESS: 07h (07d, 00111b)
MODE: ALL MODES
BIT D7
0
BIT D6
1
BIT D5
0
BIT D4
1
BIT D3
1
BIT D2
0
BIT D1
0
BIT D0
0
This register contains 8 bit firmware version number.
* Changes can be made to this register during DATA MODE. Changes will be activated immediately.
February 99 Rev M
TDK Semiconductor
Page 23 of 41
73M2921
Advanced Single
Chip Modem
DETECT 1 ENABLE REGISTER
ADDRESS: 08h (08d, 01000b)
MODE: SEE DET REG 1
BIT D7
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
BIT D1
BIT D0
CAS
S1
RES
EGY
HIP
CAR
RDLBD
RES
This is the enable register for Detect 1. Setting bits TO 1 in this register enables the unsolicited interrupt feature.
These bits have a 1 to 1 correspondence with Detect Register 1. The default value is “0”. See Detect Register 1.
DETECT REGISTER 1 (READ ONLY)
ADDRESS: 09h (09d, 01001b)
MODE: SEE BELOW
BIT D7
CAS
BIT NO.
D0
BIT D6
S1
BIT D5
BIT D4
BIT D3
HIP
BIT D2
BIT D1
RDLBD
BIT D0
RES
EGY
CAR
RES
NAME
CONDITION
DESCRIPTION
Reserved.
RDLB Detect
Reserved
RDLBD
Carrier Detect
D1
Valid in Data Mode
Valid in Data Mode
D2
This bit will be set when conditions for V.24 circuit 104
are met by the modulation mode being used (Modem in
data mode).
D3
Handshake in
progress
Valid in Data Mode
This bit will be set if a handshake is currently in progress.
This bit is cleared by the 73M2921 when either a
handshake has been successful and the 73M2921 has
entered DATA mode, or when a handshake has been
aborted and the 73M2921 is placed into IDLE mode.
D4
Energy Detect Valid in call Progress This bit will be set if receive level is above a
Mode
predetermined threshold.
D5
D6
Reserved
S1 Detect
Reserved.
Valid in Data Mode
This bit will be set if S1 (Unscrambled 1100 @ 1200b/s)
is detected. This bit is also used to detect a Retrain
request if connected V.22bis or V.22 and S1 is detected.
D7
CAS Tone
Detect
Valid in All Modes
This bit will be set if the CAS tone (2130Hz + 2750 Hz) is
detected.
Page 24 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
DETECT 2 ENABLE REGISTER
ADDRESS: 0Ah (010d, 01010b)
MODE: SEE DET REG 2
BIT D7
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
BIT D1
BIT D0
2250Hz
V21
2225Hz
2100Hz
1100Hz
1300Hz
RES.
CPD1
This is the enable register for Detect 2. Setting bits in this register enables the unsolicited interrupt feature.
These bits have a 1 to 1 correspondence with Detect Register 2. A “1” in each bit location would enable the
detect register bit of the same name. The default value is “0”. See Detect Register 2.
DETECT REGISTER 2 (READ ONLY) ADDRESS: 0Bh (011d, 01011b)
MODE: SEE BELOW
BIT D7
2250Hz
BIT NO.
D0
BIT D6
BIT D5
BIT D4
2100Hz
BIT D3
BIT D2
BIT D1
BIT D0
V21
2225Hz
1100Hz
1300Hz
RES.
CPD1
NAME
CONDITION
DESCRIPTION
Call Progress
Filter 1
Valid in Call
Progress Mode
Imprecise call progress detector, energy detected in
the 350-600 Hz band.
D1
D2
Reserved
Reserved for future use.
1300 Hz Detect
Valid in Call
Progress Mode
Answer Only
This bit will be set if 1300 Hz Data Modem Calling
Tone is detected.
D3
D4
D5
1100 Hz Detect
2100 Hz Detect
2225 Hz Detect
Valid in Call
Progress Mode
Answer Only
This bit will be set if 1100 Hz Fax Modem Calling
Tone is detected.
Valid in Call
Progress Modes
Originate Only
This bit will be set if 2100 Hz Answer Tone is
detected.
Valid in Call
Progress Modes
This will be set if 2225 Hz Answer Tone is detected.
This bit will be set if V.21 channel 2 tone is detected.
Originate Only
D6
D7
V21 Detect
(High Band)
Valid in Call
Progress Modes
Originate Only
2250 Hz Detect
Valid in Call
Progress Modes
Originate Only
This bit will be set if the 2250Hz component of S0
(unscrambled mark) is detected.
February 99 Rev M
TDK Semiconductor
Page 25 of 41
73M2921
Advanced Single
Chip Modem
TRANSMIT CONTROL REGISTER
ADDRESS: 0Ch (012d, 01100b)
MODE: SEE BELOW
BIT D7
BIT D6
BIT D5
BIT D4
Res.
BIT D3
BIT D2
BIT D1
MOD1
BIT D0
TXEN
Res.
Res.
TXDT
MOD2
MOD0
NAME
CONDITION
D2 D1 D0
DESCRIPTION
D0, D1,D2
Modulation
Type
Valid in Data Modes
Internal Sync
Reserved
0
0
0
0
0
0
1
1
0
1
0
1
Slave Sync
Reserved
1
1
0
0
0
1
Reserved
Reserved
1
1
1
1
0
1
Reserved
FSK
D3
Transmit DTMF
Tones
Valid in Call
Progress Mode
Transmits tone set in DTMF Dial Register.
D4,D5,D6
D7
Reserved
Reserved for future use.
Master
Transmit
Enable
Valid in Data
Mode
Enables Transmitter in Data Mode. Must be set prior to
Data Mode. The DSP ignores bit changes after Data
Mode transitions.
Page 26 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
GENERAL CONTROL REGISTER
ADDRESS: 0Dh (013d, 01101b)
MODE: ALL MODES
BIT D7
Res.
BIT D6
BIT D5
BIT D4
BIT D3
TXAT3
BIT D2
BIT D1
BIT D0
Res.
Res.
RESERVED
TXAT2
TXAT1
TXAT0
BIT NO.
NAME
CONDITION
D3 D2 D1 D0
DESCRIPTION
D0,
D1,D2,
D3
Transmit
Attenuation
Allows for 16 levels in all transmit modes
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+ 7 dB
+ 6 dB
+ 5 dB
+ 4 dB
+ 3 dB
+ 2 dB
+ 1 dB
Nominal
- 1 dB
- 2 dB
- 3 dB
- 4 dB
- 5 dB
- 6 dB
- 7 dB
- 8 dB
D4
D5
D6
D7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved for future use
-
February 99 Rev M
TDK Semiconductor
Page 27 of 41
73M2921
Advanced Single
Chip Modem
FAX HANDSHAKE REGISTER
ADDRESS: E0h (014d, 01110b)
MODE: FAX
BIT D7
T/5
BIT D6
BIT D5
BIT D4
BIT D3
FM3
BIT D2
BIT D1
BIT D0
Res.
Res.
Res.
FM2
FM1
FM0
BIT NO.
D0, D1,D2, D3
NAME
CONDITION
D3 D2 D1 D0
DESCRIPTION
Fax Connect
Mode
Defines Modulation for transmit or receive
V.21 channel 2 connection
V.27ter 2400 b/s connection
V.27ter 4800 b/s connection
V.29 7200 b/s connection
0
0
0
0
0
1
0
0
0
0
1
x
0
0
1
1
0
x
0
1
0
1
0
x
V.29 9600 b/s connection
Reserved for future use
D4,D5,D6
D7
Reserved
Transmit
Reserved for future use
1
0
Indicates a transmit operation
Indicates a receive operation
Page 28 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
MODE CONTROL REGISTER
ADDRESS: 010h (016d, 10000b)
MODE: ALL MODES
BIT D7
RES
BIT D6
BIT D5
BIT D4
BIT D3
ICMP
BIT D2
BIT D1
BIT D0
HINIT
SRUN
SINIT
FAX
DATA
CP
BIT NO.
D2, D1, D0
NAME
CONDITION
D2 D1 D0
DESCRIPTION
DSP
Mode3
0
0
0
1
0
0
1
0
0
DSP in IDLE Mode
0
DSP in Call Progress Mode
DSP in Data Mode
DSP in Fax Mode
DSP Error
1
0
Any other
14
D3
Initialization
Complete
Indicates the completion of the initialization routines in call
progress, and data modes.
(Read Only)
Initialization not complete.
0
D5, D4
Soft Init /
Soft Run5
D5
D4
Used with MBT
0
0
0
1
Perform both init and run functions.
Perform only the INITIALIZATION functions. This allows
the µP to go back to idle and modify any initialization
parameters.
Perform only the RUN functions assuming the init function
are complete. DO NOT attempt to run without initialization.
1
1
0
1
Perform init and run functions. This will init all functions to
their default values and then perform the run functions.
D6
D7
Hard Init4
Reserved
1
0
Forces a hard initialization of all state machine timing and
control variables.
Allows normal operation.
Reserved
Allows normal operation. Valid for V.22 and
V.22 bis only
0
3
µ
4
5
February 99 Rev M
TDK Semiconductor
Page 29 of 41
73M2921
Advanced Single
Chip Modem
MSE0 REGISTER (LSB)
ADDRESS: 011h (017d, 10001b)
BIT D5 BIT D4 BIT D3
MODE: ALL MODES
BIT D2 BIT D1 BIT D0
BIT D7
BIT D6
This register returns the Least Significant Byte of the Mean Squared Error number from the DSP. Used to
determine Signal Quality.
MSE1 REGISTER (MSB)
BIT D7 BIT D6
ADDRESS: 012h (018d, 10010b)
BIT D5 BIT D4 BIT D3
MODE: ALL MODES
BIT D2 BIT D1
BIT D0
This register returns the Most Significant Byte of the Mean Squared Error number from the DSP. Used to
determine Signal Quality.
CALL PROGRESS TRANSMIT REGISTER ADDRESS: 014 h (020d, 10100b) MODE: CALL PROGRESS
BIT D7
CPDIR
BIT NO.
D0
BIT D6
BIT D5
BIT D4
TX2225
CONDITION
1
BIT D3
BIT D2
BIT D1
BIT D0
Res.
Res.
TX2100
TX1300
TX1100
CPTE
NAME
DESCRIPTION
Call Progress
Transmit Enable
Enables Call Progress Transmit. This bit must be set
to transmit a tone.
D1
D2
Transmit 1100 Hz
D7 = 0
D7 = 0
Transmits 1100 Hz Fax Calling Tone. Only active
when D7 = 0
Transmit 1300 Hz
Transmits 1300 Hz Modem Calling Tone. Only active
when D7 = 0
D3
D4
Transmit 2100 Hz
Transmit 2225 Hz
Reserved
D7 = 1
Transmits 2100 Hz CCITT Answer Tone.
Transmits 2225 Hz Bell Answer Tone.
Reserved for future use
D7 = 1
D5,D6
D7
-
Call Progress
Direction
1
Call Progress Answer. D1 & D2 are disabled
Call Progress Originate. D3 & D4 are disabled
0
NOTE: When using bits D1-D4, only one may be active at a time.
Page 30 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
PRECISE CPD ENABLE REGISTER
BIT D7 BIT D6 BIT D5
ADDRESS: 18h (024d, 11000b)
BIT D4 BIT D3
MODE: CALL PROG.
BIT D2
BIT D1
BIT D0
This register enables the precise CPD register. Setting bits in this register enables the unsolicited interrupt
feature. These bits have a 1 to 1 correspondence with the Precise CPD register. The default value is “0”. See
Precise CPD register.
PRECISE CPD REGISTER
ADDRESS: 19h (025d, 11001b) MODE: CALL PROG. ORIGINATE ONLY
BIT D7
Res.
BIT NO.
D0
BIT D6
BIT D5
BIT D4
BIT D3
BIT D2
BIT D1
BIT D0
Res.
2750 Hz
2130 Hz
620 Hz
480 Hz
440 Hz
350 Hz
NAME
CONDITION
DESCRIPTION
Detect 350 Hz
Detect 440 Hz
Detect 480 Hz
Detect 620 Hz
Detect 2130 Hz
1
1
1
1
1
Indicates detection of 350 Hz tone
Indicates detection of 440 Hz tone
Indicates detection of 480 Hz tone
Indicates detection of 620 Hz tone
D1
D2
D3
D4
Indicates detection of 2130 Hz tone (component of
CAS tone)
D5
Detect 2750 Hz
Reserved
1
-
Indicates detection of 2750 Hz tone (component of
CAS tone)
D6, D7
Reserved for future use
February 99 Rev M
TDK Semiconductor
Page 31 of 41
73M2921
Advanced Single
Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to this device.
PARAMETER
RATING
VDD Supply Voltage
Storage Temperature
Applied Voltage
7V
-65 to 150°C
-0.3 to (VDD + 0.3V)
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-
circuit protected.
RECOMMENDED OPERATING CONDITIONS (TA = -40°C to 85°C VDD 3.3V ± .3V except as noted)
PARAMETER
CONDITION
VNA & VND = 0V
VPA & VPD = 3.3V
MIN
NOM
MAX
UNIT
Supply Voltage (VPD, VPA)
Supply Current (IPA+IPD)
3.0
3.3
3.6
V
Outputs unloaded CMOS
input levels
18
6
30
50
mA
Running internal code
In power down mode, CR0
CLK turned off
µA
RECOMMENDED OPERATING CONDITIONS (TA = -40°C TO 85°C VDD 5V ± .5V except as noted)
PARAMETER
CONDITION
VNA & VND = 0V
VPA & VPD = 5.0V
MIN
NOM
MAX
UNIT
Supply Voltage (VPD, VPA)
Supply Current (IPA+IPD)
4.5
5.0
5.5
V
Outputs unloaded CMOS
input levels
30
6
40
50
mA
Running internal code
In power down mode, CR0
CLK turned off
µA
VIH Input High
0.75* VP
V
VIL Input Low
0.25*VP
1
V
µA
µA
V
Input Current (digital)
Input Current
0 < VIN < VP
-1
-100
0
0 < VIN < VP
1
100
0.5
VOL Output Low
VOH Output High
Clock Variation
IOL = +3mA
IOH = -3mA
VP-0.5
-0.01
-40
VP
V
Crystal or external clock
+0.01
85
%
°C
TA, Operating Temperature
Page 32 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
ANALOG VOLTAGE REFERENCE AND REGULATION (TA = -40°C to 85°C VDD 5V ± .5V except as noted)
PARAMETER
CONDITION
MIN
NOM
1.25
1.25
MAX
UNIT
V
Vbg
Vref
VPA, VPD = 5V, VREF HIGH = 0
1.1
1.4
V
ANALOG VOLTAGE REFERENCE AND REGULATION (TA = -40°C to 85°C VDD 5V ± .5V except as noted)
PARAMETER
Input Impedance
Offset Voltage
DC Gain
CONDITION
MIN
50
NOM
MAX
UNIT
KΩ
INPA & INNA
DAC min scale
DAC max scale
Output load = 50 KΩ
Vref = 1.25V
-100
-0.5
0
0
100
0.5
mV
dB
Input Level
Differential analog
INPA, INNA
0.450
0.6
V
pk
1 KHz sine wave
Analog Output Level
(OUTPA-OUTNA or
OUTNA-OUTPA)
Vref = 1.25V
0.5
0.55
-65
V
pk-pk
DAC max scale
Output load = 50 KΩ
0.3KHz - 3.0KHz
Idle Channel Noise
Output THD
dBm
dB
1KHz sine max scale into DAC
Output load = 50 KΩ
-50
(OUTPA-OUTNA)
Input THD (INPA-INNA)
-50
dB
1KHz sine at 1.25V=Vref &1V
pk-pk
Intermodulation Distortion
1.0KHz & 1.2KHz at ±18,876 counts
(full scale signal) into DAC,
-50
dB
Output load = 50 KΩ
DYNAMIC CHARACTERISTICS AND TIMING (TA = -40°C to 85°C VDD 5V ± .5V,differential mode, except as noted)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
QAM/DPSK Modulator
Output Amplitude
Output load 50KΩ max
TX scrambled marks (Vcc = 5V)
Transmit Attenuator set to 0000
-10.0
-9.0
dBm0
FSK Modulator
Transmit Level
Transmit Dotting Pattern
(Vcc = 5V, Vref = 1.25V)
-10.0
-9.0
dBm0
ANSWER TONE GENERATOR
(2100 or 2225 Hz)
CONDITION
MIN
NOM
MAX
UNIT
Output Amplitude
Output Distortion
Vcc = 5V
11.5
-10.0
-9.0
-40
dBm0
dB
Distortion products in
receive band
February 99 Rev M
TDK Semiconductor
Page 33 of 41
73M2921
Advanced Single
Chip Modem
DTMF GENERATOR6
Frequency Accuracy
Output Amplitude Low Band
Output Amplitude High Band
Twist
CONDITION
MIN
NOM
MAX
UNIT
%
-0.1
0.1
Vcc = 5V
-9
-7
2
dBm
dBm
dB
Vcc = 5V
Adjustable in firmware
IMPRECISE CALL PROGRESS
DETECTOR
IN CALL PROGRESS
MODE
MIN
NOM
MAX
UNIT
350 - 600 Hz
Detect Level
Reject Level
Delay Time
460 Hz test signal
460 Hz test signal
-53.0
dBm
dBm
ms
-53.0
-70 dBm0 to -30 dBm0 level
change
60
70
Hold Time
-30 dBm0 to -70 dBm0 level
change
ms
CARRIER DETECT
Threshold
CONDITION
All Modes
All Modes
MIN
-48.0
2.0
NOM
MAX
UNIT
dBm
dBm
-43.0
Hysteresis
Delay Time
All Modes
-70 dBm0 to -6 dBm0 level
change
40
40
ms
ms
Hold Time
All Modes
-70 dBm0 to -6 dBm0 level
change
ANSWER TONE DETECTOR
Detect Level Threshold
Detect Time
CALL PROGRESS MODE
MIN
NOM
MAX
UNIT
dBm
ms
-48.0
-43.0
2100 or 2225 Hz
60
Hold Time
100
ms
6 Do not transmit DTMF levels higher than -3.0dBm600.
Page 34 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
MAXIMUM OUT OF BAND
ENERGY TRANSMIT
CONDITION
MIN
NOM
MAX
UNIT
4 kHz, Guard Tones Off
10 kHz, Guard Tones Off
12 kHz, Guard Tones Off
-35
-55
-65
dBm
dBm
dBm
GUARD TONE GENERATOR
Tone Level
(Below QAM/DPSK Output)
CONDITION
550 Hz
MIN
-4.5
-7.5
NOM
-3
MAX
-1.5
-4.5
-50
UNIT
dB
1800 Hz
-6.1
dB
Harmonic Distortion
(700 to 2900 Hz)
550 Hz and 1800Hz
dB
CONTROL INTERFACE TIMING
SYMBOL
tCW
tWC
tWH
tWS
DESCRIPTION
&6 to :5 Low
MIN
50
TYP
MAX
UNIT
ns
:5 High to &6 High
Write Hold Time
Write Setup Time
:5 width
20
ns
20
ns
150
185
20
ns
tWW
tRC
ns
5' High to &6 High
5' width
ns
tRW
tRH
185
5
ns
Read Hold Time
Read High-Z Time
ns
tRZ
20
ns
Table 6 - µC Parallel Interface Timing
11
00
01
10
UA[0:1]
UD[0-7]
t
t
WC
RC
t
RH
t
t
RW
RZ
t
WH
t
t
WW
WS
FIGURE 8 - µC Parallel Interface Timing Diagram
February 99 Rev M
TDK Semiconductor
Page 35 of 41
73M2921
Advanced Single
Chip Modem
DESIGN CONSIDERATIONS
TDK Semiconductor’s single chip modem solutions include all the basic modem functions. This makes these
devices adaptable to a variety of applications, and as easy to control as conventional digital bus peripherals.
Unlike digital logic circuitry, modem designs must contend with precise frequency tolerances and verify low level
analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally
result in a sound design. The crystal oscillator should be held to a 50ppm tolerance. Following are additional
recommendations that should be taken into consideration when starting new designs. Additional information is
available in the 73M2921 Design Guide.
LAYOUT CONSIDERATIONS
Good analog/digital design rules must be used to control system noise in order to obtain high performance in
modem designs. The more digital circuitry present on the PC board, the more attention to noise control is needed.
The 73M2921 should be considered a high performance analog device. A 10µF electrolytic capacitor in parallel
with a 0.1µF Ceramic capacitor should be placed between VPD and VND as well as between VPA and VNA. A
0.1µF ceramic capacitor should be placed between VREF and VNA as well as VBG and VNA. Liberal use of
ground planes and large traces on power are also highly recommended. High speed, digital circuits tend to
generate a significant amount of EMI (Electro-Magnetic Interference) which must be minimized in order to meet
regulatory agency limitations.
To accomplish this, high speed, digital devices should be locally bypassed, and the telephone line interface and
the modem should be located next to each other near where the telephone line connection is accessed. To avoid
problems, power supplies and ground traces should be routed separately to the analog and digital portions on the
board. Digital signals should not be routed near low level analog or high impedance analog traces.
MODEM PERFORMANCE CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions typical of those
encountered over public service telephone lines.
BER vs. SNR (see Figure 9)
This test represents the ability of the modem to operate over noisy lines with a minimum amount of data transfer
errors. Since some noise is generated in the best dial up lines, the modem must operate with the lowest signal to
noise ratio (SNR) possible. Better modem performance is indicated by test curves that are closest to the BER
axis. A narrow spread between curves representing the four line parameters indicates minimal variation in
performance while operating over a range of aberrant operating conditions. Typically a DPSK modem will exhibit
better BER performance test curves receiving in the low band (answer mode) than in the high band (originate
mode).
BER vs. RECEIVE LEVEL
This test measures the dynamic range of the modem. Because signal levels vary widely over dial up lines, the
widest possible dynamic range possible is desirable. The minimum Bell specification calls for 36dB of dynamic
range. The SNR is held constant at the indicated values as the Receive level is lowered from very a very high to
a very low signal level. The width of the bowl of these curves, taken at the BER point is the measure of the
dynamic range.
Page 36 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
1.00E-01
1.00E-02
Answer Flat
Originate Flat
Answer 3002
Originate 3002
1.00E-03
1.00E-04
1.00E-05
1.00E-06
-9 -10 -11 -12 -13 -14 -15 -16 -17 -18
SNR (Rx Signal/3k Hz) (dB)
FIGURE 9 - 2400 BPS QAM SNR vs. BER
February 99 Rev M
TDK Semiconductor
Page 37 of 41
73M2921
Advanced Single
Chip Modem
3002 Line
1.00E-01
Answer
Originate
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
-6 -10 -14 -18 -22 -26 -30 -34 -38 -42
2400 BPS QAM Power Input Level Ans./Orig. Mode
FIGURE 10 – Power Input Level vs. BER
Page 38 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
PINOUT
100 PIN QFP - PRODUCTION PACKAGE PINOUT
QFP Pin
Pin Name Pin Description
QFP Pin
Pin Name Pin Description
1
2
n/c
n/c
35
36
37
38
39
INNA
VPA
analog negative input
analog positive power supply
analog negative power supply
speaker driver output
3
VPD
VND
digital positive power supply
VNA
4
digital negative power supply
MON
:$.(
5-12
UD[0-7]
8 bit microcontroller data
bus, bidirectional
microcontroller wake-up
output
13,14
15
UA[0, 1]
2 bit microcontroller
address
40
41
RESET
TXD
reset chip input
&6
microcontroller chip select
input
transmit serial data input
transmit data clock output
16
17
18
19
20
:5
5'
µP write enable input
µP read enable input
µP interrupt output
42
43
TXCLK
n/c
8,17
MICCLK
VND
44
RXD
receive serial data output
receive data clock output
microcontroller clock output
45
RXCLK
digital negative power
supply
46-49
for factory use, make no
connections
21
22
XTALO
XTALI
crystal oscillator output
50
51
PEXT
VPD
for factory use; tie to ground
digital positive power supply
crystal oscillator (clock)
input
23
24
25
VPD
5,1*
n/c
digital positive power supply
ring detect input
52
VND
n/c
digital negative power supply
53-57
58-73
for factory use, make no
connections
26
27
'7,ꢀ
data transition 0 input
74
VND
n/c
digital negative power supply
VNA
analog negative power
supply
75-81
28
29
n/c
82
83
VPD
n/c
digital positive power supply
VPA
analog positive power
supply
30
OUTNA
analog negative output
84-90
for factory use, make no
connections
31
32
OUTPA
VREF
analog positive output
91
n/c
analog voltage reference
output
92-100
for factory use, make no
connections
33
34
VBG
bandgap bypass point
analog positive input
INPA
February 99 Rev M
TDK Semiconductor
Page 39 of 41
73M2921
Advanced Single
Chip Modem
CAUTION: Use handling procedures necessary for
PACKAGE PIN DESIGNATIONS
(Top View)
a static sensitive component.
n/c
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
n/c
n/c
VPD
2
n/c
3
n/c
VND
4
n/c
UD[0]
UD[1]
UD[2]
UD[3]
UD[4]
UD[5]
UD[6]
UD[7]
UA[0]
UA[1]
CSB
5
n/c
6
n/c
7
VND
8
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
MAKE NO CONNECTIONS
n/c
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
WRB
RDB
UINTB
MICCLK
VND
XTALO
XTALI
VPD
RNGB
n/c
n/c
DTIB
VNA
n/c
n/c
n/c
n/c
VPA
VND
OUTNA
VPD
100 Pin QFP
73M2921-IG
Page 40 of 41
TDK Semiconductor
February 99 Rev M
73M2921
Advanced Single
Chip Modem
MECHANICAL SPECIFICATIONS
PIN No. 1
Indicator
19.62 (0.772)
20.12 (0.792)
+
0.30 (0.012)
0.40 (0.016)
23.77 (0.936)
24.03 (0.946)
13.62 (0.536)
14.12 (0.556)
0.70 (0.028)
0.90 (0.035)
2.6 (0.102)
2.8 (0.110)
0.65 (0.026) Typ.
0.15 (0.006)
0.50 (0.020)
17.77 (0.700)
18.03 (0.710)
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGING MARK
73M2921
100-Pin QFP
73M2921-IG
73M2921-IG
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks
or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK
Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the
reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our web site at
http://www.tsc.tdk.com or contact your local TDK Semiconductor representative.
TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tsc.tdk.com
February 99 Rev M
TDK Semiconductor
Page 41 of 41
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