7470/7471/7477/7478 [ETC]
7470/7471/7477/7478 Group T Version USER＇S MANUALHardware Manual & Device User＇s Manual 4719K/NOV.01.96 ; 7470/7471/7477/7478组T版用户的MANUALHardware手册和设备操作手册4719K / NOV.01.96\n
| 型号： | 7470/7471/7477/7478 |
| 厂家： | 
ETC |
| 描述： | 7470/7471/7477/7478 Group T Version USER＇S MANUALHardware Manual & Device User＇s Manual 4719K/NOV.01.96
|
| 文件： | 总361页 (文件大小：4667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 7470 SERIES
Group
Use r’s Ma nua l
keep safety first in your circuit designs !
●Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
●These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
●Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
●Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.
●The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
●If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.
●Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Table of contents
Table of contents
CHAPTER 1. HARDWARE
1.1 Description .............................................................................................................................. 1-2
1.2 Group expansion ................................................................................................................... 1-3
1.3 Performance overview .......................................................................................................... 1-6
1.4 Pin configuration .................................................................................................................1-10
1.5 Pin description ..................................................................................................................... 1-14
1.6 Functional block diagram ..................................................................................................1-17
1.7 Central processing unit (CPU) .........................................................................................1-23
1.7.1 Accumulator (A) ...........................................................................................................1-24
1.7.2 Index register X (X), Index register Y (Y) .............................................................. 1-24
1.7.3 Stack pointer (S) .........................................................................................................1-24
1.7.4 Program counter (PC).................................................................................................1-26
1.7.5 Processor status register (PS) ..................................................................................1-26
1.8 Access area .......................................................................................................................... 1-28
1.8.1 Zero page (Addresses 000016 to 00FF16) .............................................................. 1-29
1.8.2 Special page (Addresses FF0016 to FFFF16) ........................................................ 1-29
1.9 Memory allocation ...............................................................................................................1-30
1.10 I/O pins .................................................................................................................................. 1-35
1.10.1 I/O port ....................................................................................................................... 1-35
1.10.2 Port block diagram ....................................................................................................1-40
1.10.3 Notes on use .............................................................................................................1-45
1.11 Interrupts ............................................................................................................................... 1-48
1.11.1 Description of interrupt source ............................................................................... 1-48
1.11.2 Operation description................................................................................................1-52
1.11.3 Interrupt control .........................................................................................................1-55
1.11.4 Notes on use .............................................................................................................1-57
1.11.5 Related registers .......................................................................................................1-59
1.12 Timers..................................................................................................................................... 1-62
1.12.1 Operation description................................................................................................1-64
1.12.2 Description of modes................................................................................................1-65
1.12.3 Input latch function ...................................................................................................1-79
1.12.4 Updating of contents of Timer and Timer latch................................................... 1-80
1.12.5 Notes on use .............................................................................................................1-82
1.12.6 Related registers .......................................................................................................1-83
1.13 Serial I/O ................................................................................................................................ 1-89
1.13A 7470/7471 group part ..............................................................................................1-90
1.13A.1 Operation description .............................................................................................1-90
1.13A.2 Byte specification mode .........................................................................................1-98
1.13A.3 Pins .........................................................................................................................1-101
7470/7471/7477/7478 GROUP USER’S MANUAL
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Table of contents
1.13A.4 Notes on use.........................................................................................................1-101
1.13A.5 Related registers...................................................................................................1-102
1.13B 7477/7478 group part ........................................................................................... 1-105
1.13B.1 Operation description .......................................................................................... 1-105
1.13B.2 Pins .........................................................................................................................1-127
1.13B.3 Notes on use.........................................................................................................1-128
1.13B.4 Related registers...................................................................................................1-131
1.14 A-D converter .....................................................................................................................1-139
1.14.1 A-D conversion method ......................................................................................... 1-140
1.14.2 Pins ...........................................................................................................................1-144
1.14.3 Notes on use ...........................................................................................................1-144
1.14.4 References ...............................................................................................................1-145
1.14.5 Related registers .....................................................................................................1-147
1.15 Reset..................................................................................................................................... 1-149
1.15.1 Operation description ............................................................................................. 1-149
1.15.2 Internal status immediately after reset release ................................................. 1-151
1.15.3 Notes on use ...........................................................................................................1-152
1.16 Oscillation circuit ..............................................................................................................1-153
1.16.1 Oscillation circuit .....................................................................................................1-153
1.16.2 Sub-clock oscillation circuit................................................................................... 1-155
1.16.3 Oscillation operation ...............................................................................................1-156
1.16.4 Oscillation stabilizing time..................................................................................... 1-158
1.16.5 Notes on use ...........................................................................................................1-159
1.17 Low-power dissipation function.................................................................................... 1-160
1.17.1 Stop mode ................................................................................................................1-162
1.17.2 Wait mode ................................................................................................................1-166
1.17.3 Notes on use ...........................................................................................................1-169
1.17.4 Related register .......................................................................................................1-170
1.18 State transitions ................................................................................................................1-171
1.19 Built-in PROM version......................................................................................................1-175
1.19.1 EPROM mode ..........................................................................................................1-176
1.19.2 Pin description .........................................................................................................1-182
1.19.3 Writing, reading, and erasing to built-in PROM ................................................ 1-185
1.19.4 Notes on use ...........................................................................................................1-186
1.20 Emulator MCU ....................................................................................................................1-188
1.21 Electrical characteristics .................................................................................................1-189
1.21.1 Electrical characteristics ........................................................................................ 1-189
1.21.2 Timing requirements, switching characteristics.................................................. 1-201
1.21.3 Power source current standard characteristics.................................................. 1-203
1.21.4 Port standard characteristics ................................................................................ 1-208
1.21.5 A-D conversion standard characteristics ............................................................ 1-213
7470/7471/7477/7478 GROUP USER’S MANUAL
ii
Table of contents
CHAPTER 2. APPLICATION
2.1 I/O pins .................................................................................................................................... 2-2
2.1.1 I/O port ........................................................................................................................... 2-2
2.1.2 Notes on use ................................................................................................................. 2-5
2.2 Interrupts ................................................................................................................................. 2-7
2.2.1 Memory allocation ......................................................................................................... 2-7
2.2.2 Processor status register (PS) ....................................................................................2-8
2.2.3 Application example ...................................................................................................... 2-9
2.2.4 Notes on use ................................................................................................................. 2-9
2.3 Timers..................................................................................................................................... 2-10
2.3.1 Memory allocation .......................................................................................................2-10
2.3.2 Application example ....................................................................................................2-11
2.3.3 Notes on use ...............................................................................................................2-22
2.4 Serial I/O ................................................................................................................................ 2-23
2.4.1 7470/7471 group memory allocation ....................................................................... 2-23
2.4.2 Application example ....................................................................................................2-24
2.4.3 7477/7478 group memory allocation ....................................................................... 2-29
2.4.4 Application examples ..................................................................................................2-30
2.4.5 Notes on use ...............................................................................................................2-34
2.5 A-D converter ....................................................................................................................... 2-35
2.5.1 Memory allocation .......................................................................................................2-35
2.5.2 Application examples ..................................................................................................2-36
2.5.3 Notes on use ...............................................................................................................2-38
2.6 Reset....................................................................................................................................... 2-39
2.6.1 Reset circuit .................................................................................................................2-39
2.6.2 Notes on use ...............................................................................................................2-39
2.7 Oscillation circuit ................................................................................................................2-40
2.8 Low-power dissipation function.......................................................................................2-41
2.8.1 CPU mode register .....................................................................................................2-41
2.8.2 Application examples ..................................................................................................2-42
2.8.3 Notes on use ...............................................................................................................2-47
2.9 Countermeasures against noise ......................................................................................2-48
2.9.1 Shortest wiring length .................................................................................................2-48
2.9.2 Connection of a bypass capacitor across the VSS line and the VCC line ......... 2-51
2.9.3 Wiring to analog input pins........................................................................................2-51
2.9.4 Consideration for oscillator ........................................................................................2-52
2.9.5 Setup for I/O ports ......................................................................................................2-53
2.9.6 Providing of watchdog timer function by software ................................................ 2-54
2.10 Notes on programming ......................................................................................................2-56
2.10.1 Processor status register .........................................................................................2-56
2.10.2 Decimal calculations .................................................................................................2-57
2.11 Differences between 7470/7471 group and 7477/7478 group .................................. 2-58
7470/7471/7477/7478 GROUP USER’S MANUAL
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Table of contents
2.12 Example of application circuit .........................................................................................2-59
CHAPTER 3. APPENDIX
3.1 Control registers.................................................................................................................... 3-2
3.2 Mask ROM ordering method .............................................................................................3-14
3.3 ROM programming ordering method ............................................................................. 3-46
3.4 Mark specification form .....................................................................................................3-62
3.5 Package outline ................................................................................................................... 3-67
3.6 SFR memory map ................................................................................................................3-69
3.7 Pin configuration .................................................................................................................3-70
7470/7471/7477/7478 GROUP USER’S MANUAL
iv
CHAPTER 1
HARDWARE
1.1 Description
1.2 Group expansion
1.3 Performance overview
1.4 Pin configuration
1.5 Pin description
1.6 Functional block diagram
1.7 Central processing unit (CPU)
1.8 Access area
1.9 Memory allocation
1.10 I/O pins
1.11 Interrupts
1.12 Timers
1.13 Serial I/O
1.14 A-D converter
1.15 Reset
1.16 Oscillation circuit
1.17 Low-power
dissipation function
1.18 State transitions
1.19 Built-in PROM version
1.20 Emulator MCU
1.21 Electrical characteristics
HARDWARE
1.1 Description
1.1 Description
The 7470/7471/7477/7478 group is an 8-bit single-chip microcomputer which utilizes a silicon gate CMOS
processing and has a simple instruction system of the 740 family using the same memory space for ROM,
RAM and I/O.
7470/7471/7477/7478 GROUP USER’S MANUAL
1-2
HARDWARE
1.2 Group expansion
1.2 Group expansion
The 7470/7471/7477/7478 group develops with the M37470M2-XXXSP as the base chip in the 7470 series.
The classification of the 7470 series is as follows.
7470 series
7470 group
7471 group
7477 group
7478 group
7480 group**
7481 group**
**:Under development
In this manual, when multiple models are described collectively, their names are arranged by putting
“/” among them for separation.
7470 group, 7471 group → 7470/7471 group
7477 group, 7478 group → 7477/7478 group
7470 group, 7477 group → 7470/7477 group
7471 group, 7478 group → 7471/7478 group
The 7470/7471/7477/7478 group permits group expansion as shown in Figure 1.2.1. This group expansion
is all performed only by differences in memory type and capacity and the number of ports. This allows the
user to select optimum elements according to the user's system.
The 7470/7471/7477/7478 group supports the following in addition to the mask ROM version.
(1) Support of One Time PROM version
The One Time PROM version is a programmable microcomputer and can perform a one-time write
operation to the built-in programmable ROM (PROM).
For the details, refer to “1.19 Built-in PROM version.”
(2) Support of EPROM version (with window)
The built-in EPROM version is a programmable microcomputer with window and can perform write
and erase operations to the built-in EPROM.
For the details, refer to “1.19 Built-in PROM version.”
(3) Support of emulator MCU
The emulator MCU is a microcomputer designed for program development which facilitates program
development and is an optimum element for system evaluation.
For the details, refer to“1.20 Emulator MCU.”
Table 1.2.1 shows the products which the 7470/7471/7477/7478 group supports.
7470/7471/7477/7478 GROUP USER’S MANUAL
1-3
HARDWARE
1.2 Group expansion
Memory Expansion Plan of 7470/7471 group
•
ROM size
(bytes)
M37470M8/E8-XXXSP
M37471M8/E8-XXXSP/FP
M37471E8SS
16K
12K
8K
M37470M4/E4-XXXSP
M37471M4/E4-XXXSP/FP
M37470M2-XXXSP
M37471M2-XXXSP/FP
4K
0
128
192
256
384
RAM size
(bytes)
Memory Expansion Plan of 7477/7478 group
•
ROM size
(bytes)
M37477M8/E8-XXXSP/FP
M37477M8T/E8TXXXSP/FP
M37478M8/E8-XXXSP/FP
M37478M8T/E8TXXXSP/FP
M37478E8SS
16K
12K
M37477M4-XXXSP/FP
M37477M4TXXXSP/FP
M37478M4-XXXSP/FP
M37478M4TXXXSP/FP
8K
4K
M37477M2TXXXSP/FP
M37478M2TXXXSP/FP
0
128
192
256
384
RAM size
(bytes)
: Mass product
: New product
: Under development
Fig. 1.2.1 Memory expansion plan of 7470/7471/7477/7478 group
(As of July 1996)
7470/7471/7477/7478 GROUP USER’S MANUAL
1-4
HARDWARE
1.2 Group expansion
Table 1.2.1 List of supported products
(As of July 1996)
ROM
(bytes) (bytes)
RAM
Product
Package
32P4B
Remarks
I/O Port
4096
8192
128
192
M37470M2-XXXSP
M37470M4-XXXSP
M37470E4-XXXSP
M37470M8-XXXSP
M37470E8-XXXSP
M37471M2-XXXSP
M37471M2-XXXFP
M37471M4-XXXSP
M37471M4-XXXFP
M37471E4-XXXSP
M37471E4-XXXFP
M37471M8-XXXSP
M37471M8-XXXFP
M37471E8-XXXSP
M37471E8-XXXFP
M37471E8SS
I/O ports: 22
(Including 4 analog
input pins.)
Mask ROM version
One Time PROM version
Mask ROM version
One Time PROM version
16384
4096
384
128
Input ports: 4
42P4B
56P6N-A
42P4B
56P6N-A
42P4B
56P6N-A
42P4B
56P6N-A
42P4B
56P6N-A
42S1B-A
Mask ROM version
8192
192
384
I/O ports: 28
(Including 8 analog
input pins.)
One Time PROM version
Mask ROM version
Input ports: 8
16384
One Time PROM version
EPROM version
63.5K
(Note)
42S1M
Emulator MCU
M37471RSS
384
128
M37477M2TXXXSP
M37477M2TXXXFP
M37477M4-XXXSP
M37477M4-XXXFP
M37477M4TXXXSP
M37477M4TXXXFP
M37477M8-XXXSP
M37477M8-XXXFP
M37477M8TXXXSP
M37477M8TXXXFP
M37477E8-XXXSP
M37477E8-XXXFP
M37477E8TXXXSP
M37477E8TXXXFP
M37478M2TXXXSP
M37478M2TXXXFP
M37478M4-XXXSP
M37478M4-XXXFP
M37478M4TXXXSP
M37478M4TXXXFP
M37478M8-XXXSP
M37478M8-XXXFP
M37478M8TXXXSP
M37478M8TXXXFP
M37478E8-XXXSP
M37478E8-XXXFP
M37478E8TXXXSP
M37478E8TXXXFP
32P4B
32P2W-A
32P4B
32P2W-A
32P4B
32P2W-A
32P4B
32P2W-A
32P4B
32P2W-A
32P4B
32P2W-A
32P4B
32P2W-A
42P4B
56P6N-A
42P4B
56P6N-A
42P4B
56P6N-A
42P4B
56P6N-A
42P4B
56P6N-A
42P4B
56P6N-A
4096
Mask ROM version*
Mask ROM version
8192
192
I/O ports: 18
Input ports: 8
(Including 4 analog
input pins.)
Mask ROM version*
Mask ROM version
Mask ROM version*
One Time PROM version
One Time PROM version*
Mask ROM version*
Mask ROM version
16384
384
4096
8192
128
192
Mask ROM version*
Mask ROM version
I/O ports: 20
Input ports: 16
(Including 8 analog
input pins.)
Mask ROM version*
One Time PROM version
One Time PROM version*
16384
16384
384
42P4B
56P6N-A
I/O ports: 20
384
384
42S1B-A EPROM version
M37478E8SS
M37478RSS
Input ports: 16
(Including 8 analog
input pins.)
63.5K
(Note)
42S1M
Emulator MCU
Note: Address space usable as a ROM area.
: Extended operating temperature version.
*
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.3 Performance overview
1.3 Performance overview
Tables 1.3.1 to 1.3.4 show the performance overview of 7470/7471/7477/7478 group.
Table 1.3.1 Performance overview of 7470 group
Functions
Parameter
71 (69 basic instructions of 740 family and 2 multiplication
and division instructions)
Number of basic instructions
0.5 µ s (the minimum instructions, at 8 MHz clock input
oscillation frequency)
Instruction execution time
Clock input oscillation frequency
M37470M2
8 MHz (max.)
4096 bytes
8192 bytes
ROM
M37470M4/E4
Memory
size
16384 bytes
128 bytes
M37470M8/E8
M37470M2
192 bytes
RAM
M37470M4/E4
384 bytes
M37470M8/E8
8-bit
8-bit
4-bit
2-bit
P0
P1
P2
P4
P3
Input/
Output
port
I/O
4-bit
Input
8-bit ✕ 1
8-bit timer ✕ 4
1 (in common with 2 timer)
8-bit ✕ 1 (4 channels)
Serial I/O
Timers
PWM
A-D converter
64 levels max.
M37470M2
96 levels max.
192 levels max.
Subroutine nesting
M37470M4/E4
M37470M8/E8
5 external interrupts, 6 internal interrupts, 1 software interrupt
Built-in circuit with internal feedback resistor (an external
ceramic resonator or a quartz-crystal oscillator)
2.7 V to 4.5 V
Interrupt
Clock generating circuit
(at (2.2 VCC–2) MHz clock input oscillation frequency)
4.5 V to 5.5 V
Power source voltage
(at 8 MHz clock input oscillation frequency)
35 mW typ.
(at 8 MHz clock input oscillation frequency)
5 V
Power dissipation
Input/Output
Input/Output withstand voltage
characteristics
Operating temperature
Device structure
Package
Output current
–5 mA to +10 mA (P0, P1, P2, P4: CMOS 3-state)
–20 °C to +85 °C
CMOS silicon gate
32-pin shrink plastic molded DIP
M37470Mx/Ex-XXXSP
7470/7471/7477/7478 GROUP USER’S MANUAL
1-6
HARDWARE
1.3 Performance overview
Table 1.3.2 Performance overview of 7471 group
Parameter
Functions
71 (69 basic instructions of 740 family and 2 multiplication
and division instructions)
0.5 µs (the minimum instructions, at 8 MHz clock input
oscillation frequency)
Number of basic instructions
Instruction execution time
Clock input oscillation frequency
M37471M2
8 MHz (max.)
4096 bytes
ROM
M37471M4/E4
8192 bytes
Memory
size
M37471M8/E8
M37471M2
16384 bytes
128 bytes
RAM
M37471M4/E4
192 bytes
M37471M8/E8
384 bytes
P0
P1
P2
P4
P3
P5
8-bit
8-bit
8-bit
4-bit
4-bit
4-bit
Input/
Output
port
I/O
Input
Serial I/O
Timers
PWM
8-bit ✕ 1
8-bit timer ✕ 4
1 (in common with 2 timer)
8-bit ✕ 1 (8 channels)
A-D converter
M37471M2
64 levels max.
Subroutine nesting
M37471M4/E4
M37471M8/E8
96 levels max.
192 levels max.
Interrupt
5 external interrupts, 6 internal interrupts, 1 software interrupt
Built-in circuit with internal feedback resistor (an external
ceramic resonator or a quartz-crystal oscillator)
Built-in circuit with internal feedback resistor (a guartz-
crystal oscillator)
2.7 V to 4.5 V
(at (2.2 VCC–2) MHz clock input oscillation frequency)
4.5 V to 5.5 V
Clock generating circuit
Sub-clock generating circuit
Power source voltage
Power dissipation
(at 8 MHz clock input oscillation frequency)
35 mW typ.
(at 8 MHz clock input oscillation frequency)
Input/Output withstand voltage
5 V
Input/Output
characteristics
Operating temperature
Device structure
Output current
–5 mA to +10 mA (P0, P1, P2, P4: CMOS 3-state)
–20 °C to +85 °C
CMOS silicon gate
42-pin shrink plastic molded DIP
56-pin plastic molded QFP
42-pin shrink ceramic DIP
M37471Mx/Ex-XXXSP
M37471Mx/Ex-XXXFP
M37471E8SS
Package
7470/7471/7477/7478 GROUP USER’S MANUAL
1-7
HARDWARE
1.3 Performance overview
Table 1.3.3 Performance overview of 7477 group
Parameter
Functions
71 (69 basic instructions of 740 family and 2 multiplication
and division instructions)
0.5 µs (the minimum instructions, at 8 MHz clock input
oscillation frequency)
Number of basic instructions
Instruction execution time
Clock input oscillation frequency
M37477M2
8 MHz (max.)
4096 bytes
M37477M4
8192 bytes
ROM
Memory
size
M37477M8/E8
M37477M2
16384 bytes
128 bytes
M37477M4
192 bytes
RAM
M37477M8/E8
384 bytes
P0
P1
P4
P2
P3
8-bit
8-bit
2-bit
4-bit
Input/
Output
port
I/O
Input
4-bit
8-bit ✕ 1 (operable in UART mode)
8-bit timer ✕ 4
1 (in common with 2 timer)
8-bit ✕ 1 (4 channels)
Serial I/O
Timers
PWM
A-D converter
64 level max.
M37477M2
96 level max.
Subroutine nesting
M37477M4
192 level max.
M37477M8/E8
5 external interrupts, 7 internal interrupts, 1 software interrupt
Built-in circuit with internal feedback resistor (an external
ceramic resonator or a quartz-crystal oscillator)
2.7 V to 4.5 V
Interrupt
Clock generating circuit
(at (2.2 VCC–2) MHz clock input oscillation frequency)
4.5 V to 5.5 V
(at 8 MHz clock input oscillation frequency)
35 mW typ.
(at 8 MHz clock input oscillation frequency)
5 V
Power source voltage
Power dissipation
Input/Output
Input/Output withstand voltage
–5 mA to +10 mA (P0, P1, P4: CMOS 3-state)
–20 °C to +85 °C (–40 °C to +85 °C for extended operating temperature version)
CMOS silicon gate
characteristics
Operating temperature
Device structure
Output current
M37477Mx/E8-XXXSP
M37477Mx/E8TXXXSP
M37477Mx/E8-XXXFP
M37477Mx/E8TXXXFP
32-pin shrink plastic molded DIP
32-pin plastic molded SOP
Package
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.3 Performance overview
Table 1.3.4 Performance overview of 7478 group
Parameter
Functions
71 (69 basic instructions of 740 family and 2 multiplication
and division instructions)
0.5 µs (the minimum instructions, at 8 MHz clock input
oscillation frequency)
Number of basic instructions
Instruction execution time
Clock input oscillation frequency
M37478M2
8 MHz (max.)
4096 bytes
8192 bytes
16384 bytes
128 bytes
192 bytes
384 bytes
8-bit
8-bit
4-bit
ROM
RAM
I/O
M37478M4
M37478M8/E8
M37478M2
M37478M4
Memory
size
M37478M8/E8
P0
P1
P4
P2
P3
P5
Input/
Output
port
8-bit
4-bit
4-bit
Input
8-bit ✕ 1 (operable in UART mode)
8-bit timer ✕ 4
1 (in common with 2 timer)
8-bit ✕ 1 (8 channels)
Serial I/O
Timers
PWM
A-D converter
64 level max.
M37478M2
Subroutine nesting
96 level max.
M37478M4
192 level max.
M37478M8/E8
Interrupt
5 external interrupts, 7 internal interrupts, 1 software interrupt
Built-in circuit with internal feedback resistor (an external
ceramic resonator or a quartz-crystal oscillator)
Built-in circuit with internal feedback resistor (a quartz-
crystal oscillator)
2.7 V to 4.5 V
(at (2.2 VCC–2) MHz clock input oscillation frequency)
4.5 V to 5.5 V
Clock generating circuit
Sub-clock generating circuit
Power source voltage
(at 8 MHz clock input oscillation frequency)
35 mW typ.
(at 8 MHz clock input oscillation frequency)
5 V
Power dissipation
Input/Output
Input/Output withstand voltage
characteristics
Operating temperature
Device structure
–5 mA to +10 mA (P0, P1, P4: CMOS 3-state)
–20 °C to +85 °C (–40 °C to +85 °C for extended operating temperature version)
CMOS silicon gate
Output current
M37478Mx/E8-XXXSP
M37478Mx/E8TXXXSP
M37478Mx/E8-XXXFP
M37478Mx/E8TXXXFP
M37478E8SS
42-pin shrink plastic molded DIP
Package
56-pin plastic molded QFP
42-pin shrink ceramic DIP
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.4 Pin configuration
1.4 Pin configuration
Figures 1.4.1 to 1.4.4 show a pin configuration of “7470/7471/7477/7478 group.”
For pin connections in the EPROM mode of the built-in programmable ROM version, refer to “Figures
1.19.1 to 1.19.6 Pin connections in EPROM mode.”
PIN CONFIGURATION (TOP VIEW)
1
2
32
31
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
P07
P06
P05
P04
P03
P02
P01
P00
3
4
30
29
5
6
28
27
26
25
24
23
22
21
7
8
P10
9
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
P40
10
11
12
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
13
14
20
19
18
XIN
XOUT
VSS
15
16
17
Outline 32P4B (Note)
Note: The M37470M2-XXXSP and M37470M4/E4-XXXSP are included in the 32P4B package. All of
these products are pin-compatible.
Fig. 1.4.1 Pin configuration of 7470 group
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.4 Pin configuration
PIN CONFIGURATION (TOP VIEW)
42
41
1
2
3
P53
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
P52
P07
P06
P05
P04
P03
P02
P01
40
39
38
37
4
5
6
7
36
35
34
8
9
P10
P00
10
11
12
13
14
33
32
31
30
29
28
27
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P43
P42
P41
P40
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
15
16
17
26
25
24
23
22
18
19
20
21
XIN
XOUT
VSS
P51/XCOUT
P50/XCIN
VCC
Outline 42P4B (Note 1)
42S1B-A (M37471E8SS)
45
28
RESET
NC
P05
P06
P07
P52
NC
VSS
P53
46
27
26
NC
47
P51/XCOUT
P50/XCIN
NC
VCC
VSS
AVSS
NC
XOUT
XIN
48
25
24
49
50
M37471M8-XXXFP
M37471E8-XXXFP
23
22
21
20
51
52
53
P17/SRDY
P16/CLK
P15/SOUT
54
19
18
17
55
56
NC
NC
NC: No connection
Outline 56P6N-A (Note 2)
Notes 1 : The M37471M2-XXXSP and M37471M4/E4-XXXSP are included in the 42P4B package. All of these
products are pin-compatible.
2 : The M37471M2-XXXFP and M37471M4/E4-XXXFP are included in the 56P6N-A package. All of
these products are pin-compatible.
3 : The only differences between the 42P4B package product and the 56P6N-A package product are
package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
Fig. 1.4.2 Pin configuration of 7471 group
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.4 Pin configuration
PIN CONFIGURATION (TOP VIEW)
1
2
32
31
P1
P1
P1
P1
P1
P1
7
/
S
RDY
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
1
0
6
/SCLK
/T
/R
3
4
30
29
5
X
D
D
4
X
5
6
28
27
3
2
/T
/T
1
0
1
0
3
2
1
0
7
8
26
25
P1
P1
/IN
/IN
/IN
/IN
9
24
23
P2
3
10
P2
P2
P2
2
11
12
13
14
15
16
22
21
1
/CNTR
/CNTR
1
0
0
20
19
V
REF
IN
OUT
SS
/INT
/INT
1
0
X
18
17
X
RESET
V
V
CC
Outline 32P4B (Note 1)
1
2
32
31
P1
P1
P1
P1
P1
P1
7
/
S
RDY
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
1
0
6
/SCLK
/T
/R
3
30
29
5
X
D
D
4
4
X
5
28
27
3
2
/T
/T
1
0
1
0
3
2
1
0
6
7
26
25
P1
P1
/IN
/IN
/IN
/IN
8
9
24
23
P2
3
10
11
12
13
14
15
16
P2
P2
P2
2
22
21
1
/CNTR
/CNTR
1
0
0
20
19
V
REF
IN
OUT
SS
/INT
/INT
1
X
0
18
17
X
RESET
V
V
CC
Outline 32P2W-A (Note 2)
Notes 1 : The M37477M2TXXXSP, M37477M4-XXXSP and M37477M4TXXXSP are included in the 32P4B package.
These products are pin-compatible.
2 : The M37477M2TXXXFP, M37477M4-XXXFP and M37477M4TXXXFP are included in the 32P2W-A package.
These products are pin-compatible.
3 : The only differences between the 32P4B package product and the 32P2W-A package product are
package shape and absolute maximum ratings.
Fig. 1.4.3 Pin configuration of 7477 group
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.4 Pin configuration
PIN CONFIGURATION (TOP VIEW)
1
2
42
41
40
P5
3
P5
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P4
P4
P3
P3
P3
P3
2
7
6
5
4
3
2
1
0
3
2
1
0
3
2
1
0
P1
P1
P1
P1
P1
P1
7
/
S
RDY
3
6
/SCLK
4
5
39
5
/T
/R
X
D
D
38
37
4
X
6
7
3
2
/T
/T
1
0
1
0
7
6
5
4
3
2
1
0
36
35
34
8
9
P1
P1
/IN
/IN
/IN
/IN
/IN
/IN
/IN
/IN
33
10
11
12
P2
7
6
5
4
3
2
1
0
V
32
31
30
P2
P2
P2
P2
P2
P2
P2
13
14
29
28
27
26
/CNTR
/CNTR
1
0
15
16
/INT
1
17
/INT
0
25
24
23
18
19
20
21
RESET
REF
IN
OUT
SS
X
P5
P5
1
0
/XCOUT
/XCIN
X
22
V
V
CC
Outline 42P4B (Note 1)
42S1B-A (M37478E8SS)
45
28
RESET
NC
NC
46
47
27
26
P0
P0
P0
P5
5
6
7
2
P5
1
/XCOUT
/XCIN
48
49
25
24
23
22
21
20
19
P5
0
M37478M8-XXXFP
M37478E8-XXXFP
M37478M8TXXXFP
M37478E8TXXXFP
NC
50
NC
V
V
CC
51
52
V
SS
SS
P53
AVSS
NC
53
54
P1
P1
P1
7/SRDY
/SCLK
X
X
OUT
6
55
56
18
17
IN
5
/T
X
D
NC
NC
Outline 56P6N-A (Note 2)
NC: No connection
Notes 1 :The M37478M2TXXXSP, M37478M4-XXXSP and M37478M4TXXXSP are included in the 42P4B package.
These products are pin-compatible
2 :The M37478M2TXXXFP, M37478M4-XXXFP and M37478M4TXXXFP are included in the 56P6N-A package.
These products are pin-compatible
3 :The only differences between the 42P4B package product and the 56P6N-A package product are package
shape, absolute maximum ratings and the fact that the 56P6N-A package product has an
AVSS pin.
Fig. 1.4.4 Pin configuration of 7478 group
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.5 Pin description
1.5 Pin description
Tables 1.5.1 to 1.5.3 show a pin description.
For pin functions in the EPROM mode of the built-in programmable ROM version, refer to “1.19.2 Pin
description.”
Table 1.5.1 Pin description (1)
Input/
Output
Pin
Name
Power source
Functions
VCC, VSS
• Apply the following voltage to the VCC pin:
2.7 V to 4.5 V
(at f(XIN) = (2.2 VCC–2) MHz clock input oscillation frequency)
or
4.5 V to 5.5 V
(at f(XIN) = 8 MHz clock input oscillation frequency).
• Apply 0 V to the VSS pin.
AVSS
VREF
Analog power source
Reference voltage input
Reset input
• Ground level input pin for the A-D converter.
• Apply the same voltage as VSS pin to the AVSS pin.
Note:This pin is dedicated to 56P6N-A package
products among the 7471/7478 group.
• Reference voltage input pin for the A-D converter.
• When using the A-D converter, apply 0.5 VCC (Q
2) to VCC [V].
Input
Input
• When not using the A-D converter, connect to VCC.
• Reset input pin
RESET
• The microcomputer is put into a reset state by
keeping the RESET pin at “L” for 2 µs or more,
and the reset state is released by returning the
RESET pin to “H.”
XIN
Clock input
Clock output
I/O port P0
Input
Output
I/O
• An input pin and an output pin for the main clock
generating circuit.
• Connect a ceramic resonator or a quartz-crystal
oscillator between pins XIN and XOUT.
• A feedback resistor is incorporated between the
XIN and the XOUT pins.
• To use an external clock input, connect the clock
oscillation source to the XIN pin and leave the
XOUT pin open.
XOUT
P00–P07
• Port P0 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, a pull-up transistor is connectable
in units of one bit.
• In input mode, a key-on wake up function is pro-
vided.
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HARDWARE
1.5 Pin description
Table 1.5.2 Pin description (2)
Input/
Output
I/O
Pin
Name
I/O port P1
Functions
P10–P17
• Port P1 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be connected
in units of 4-bit.
• Pins P12 and P13 are in common with timer out-
put pins T0, T1 respectively.
• In the case of the 7470/7471 group, P14–P17 are
in common with serial I/O pins SIN, SOUT, CLK,
SRDY respectirely.
• In the case of the 7470/7471 group, the outputs
of pins SOUT and the SRDY can be N-channel open
drain outputs.
• In the case of the 7477/7478 group, P14–P17 are
in common with serial I/O pins RXD, TXD, SCLK,
SRDY, respectively.
P20–P27
I/O port P2
I/O
• Port P2 is an 8-bit I/O port.
(7470/7471 group)
• The output structure is CMOS output.
• In input mode, pull-up transistor can be connected
in units of 4-bit.
• Pins P20–P27 are in common with analog input
pins IN0–IN7 respectively.
Note: The 7470 group has only the 4 pins P20–P23
(IN0–IN3).
Input port P2
Input
• Port P2 is an 8-bit input port.
(7477/7478 group)
• It is impossible to connect a pull-up transistor.
• Pins P20–P27 are in common with analog lnput
pins IN0–IN7 respectively.
Note: The 7477 group has only the 4 pins P20–P23
(IN0–IN3).
P30–P33
P40–P43
Input port P3
I/O port P4
Input
I/O
• Port P3 is a 4-bit input port.
• Pins P30, P31 are in common with external inter-
rupt input pins INT0, INT1 respectively.
• Pins P32, P33 are in common with timer input pins
CNTR0, CNTR1 respectively.
• Port P4 is a 4-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be connected
in units of 4-bit.
Note: The 7470/7477 group has only 2 pins P40
and P41.
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.5 Pin description
Table 1.5.3 Pin description (3)
Input/
Output
Input
Pin
Name
Input port P5
Functions
P50–P53
• Port P5 is a 4-bit input port.
• Pull-up transistor can be connected in units of
4-bit.
• Pins P50, P51 are in common with input/output
pins for sub-clock generating circuit XCIN, XCOUT
respectively.
• When using pins P50 and P51 as pins XCIN and
XCOUT, connect a quartz-crystal oscillator between
pins XCIN and XCOUT.
• When using pins P50 and P51 as pins XCIN and
XCOUT, a feedback resistor is connected between
pins XCIN and XCOUT.
• To use an external clock input, connect the clock
oscillation source to the XCIN pin and leave the
XCOUT pin open.
Note: Only the 7471/7478 group has pins P50–P53.
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HARDWARE
1.6 Functional block diagram
1.6 Functional block diagram
The functional block diagram of 7470/7471/7477/7478 group is shown in Figure 1.6.1 to Figure 1.6.6.
Fig. 1.6.1 M37470MX/EX-XXXSP functional block diagram
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.6 Functional block diagram
Fig. 1.6.2 M37471MX/EX-XXXSP, M37471E8SS functional block diagram
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.6 Functional block diagram
Fig. 1.6.3 M37471MX/EX-XXXFP functional block diagram
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.6 Functional block diagram
Fig. 1.6.4 M37477MX/E8-XXXSP/FP, M37477MX/E8TXXXSP/FP functional block diagram
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.6 Functional block diagram
Fig. 1.6.5 M37478MX/E8-XXXSP, M37478MX/E8TXXXSP, M37478E8SS functional block diagram
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.6 Functional block diagram
Fig. 1.6.6 M37478MX/E8-XXXFP, M37478MX/E8TXXXFP functional block diagram
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.7 Central processing unit (CPU)
1.7 Central processing unit (CPU)
The CPU of 7470/7471/7477/7478 group has the following 6 registers (referred as “CPU registers”).
● Accumulator (A) ··························································8-bit
● Index register X (X) ···················································8-bit
● Index register Y (Y) ···················································8-bit
● Stack pointer (S) ························································8-bit
● Processor status register (PS) ·································8-bit
● Program counter (PC)··············································16-bit
high-order (PCH) ·········· 8-bit
low-order (PCL) ············ 8-bit
Figure 1.7.1 shows a structure of CPU registers.
7
7
7
7
7
7
0
0
0
0
0
0
A
X
Accumulator
Index Register X
Y
Index Register Y
S
Stack Pointer
15
8
PCH
PCL
Program Counter
N V T B D I Z C
Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 1.7.1 Structure of CPU registers
7470/7471/7477/7478 GROUP USER’S MANUAL
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HARDWARE
1.7 Central processing unit (CPU)
The CPU register states provided immediately after hardware reset are described below.
● The interrupt disable flag (I) of the Processor status register (PS) is set to “1.”
● The high-order 8 bits (PCH) of the Program counter (PC) become the contents of address FFFF16 and
the low-order 8 bits (PCL) become the contents of address FFFE16.
The contents of the other CPU registers are undefined, so be sure to initialize the CPU registers with
the program.
1.7.1 Accumulator (A)
The Accumulator is the central of microcomputer and is an 8-bit register. This accumulator is used for
arithmetic operations, data transfer, temporary storage, condition judgment, and is a general-purpose
register with the highest frequency of use.
1.7.2 Index register X (X), Index register Y (Y)
The Index register X and the Index register Y are 8-bit registers.
In the addressing mode using these Index registers, a value resulting from adding the contents of this
register to the operand becomes a real specified address. This addressing mode is used to make reference
to a subroutine table or a memory table. The Index registers are provided with increment, decrement,
comparison and data transfer functions and can also be used as a simplified accumulator.
In the Index register X, when the index X mode flag (T) of the Processor status register is “1,” the contents
of the Index register become an operand address.
1.7.3 Stack pointer (S)
The Stack pointer is an 8-bit register which is used to call a subroutine or generate an interrupt.
For a branch from a routine being executed to a subroutine or an interrupt processing routine, it is
necessary to temporarily store (push) in memory the return address at the termination of this processing.
Usually, the internal RAM is used as the push destination, and this area is called a stack area. The stack
pointer indicates an address in the stack area to which the data will be pushed next.
Figure 1.7.2 shows a push operation to the stack area of the register and a pop operation from the Stack
area of the register.
The Program counter and registers other than the Processor status register are not automatically pushed.
Accordingly, be sure to push necessary registers with the program.
The PHA instruction and the PLA instruction are used for push and pop operations of the Accumulator and
the PHP instruction and the PLP instruction are used for push and pop operations of the Processor status
register.
In the 7470/7471/7477/7478 group, the RAM in 0 page or 1 page is available as a stack area. Select it
by the stack page bit (bit 2) of the CPU mode register (address 00FB16), which will be described later (“0”
for 0 page or “1” for 1 page). In some products whose RAM capacity is 192 bytes or less, RAM does not
exist on 1 page, so be sure to set this bit to “0.”
The stack pointer is in an undefined state immediately after hardware reset. Be sure to initialize so as not
to destroy the data arranged in the RAM area.
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HARDWARE
1.7 Central processing unit (CPU)
On-going routine
•
• • • • •
When an interrupt is accepted
M(S) (PCH)
Interrupt request (Note)
(S) (S)–1
Push return address
on stack
M(S) (PCL)
•
• • • • •
(S) (S)–1
Push contents of
M(S) (PS)
Execute JSR
When a subroutine is called
M(S) (PCH)
Processor status
register on stack
(S) (S)–1
Interrupt Service
Routine
I Flag is set from
“0” to “1”
Fetch the Jump
Vector
Push return
address on
stack
•
•
•
(S) (S)–1
M(S) (PCL)
(S) (S)–1
•
•
•
•
•
•
Execute RTI
Subroutine
Pop contents of
Processor status
register from stack
(S) (S)+1
(PS) M(S)
(S) (S)+1
(PCL) M(S)
(S) (S)+1
(PCH) M(S)
•
•
•
Pop return
address from stack
Execute RTS
(S) (S)+1
(PCL) M(S)
(S) (S)+1
Pop return
address from
stack
(PCH) M(S)
: Operation instructed by software
: Operation which is automatically performed by hardware
Note : Condition for acceptance of an interrupt • • •
Interrupt disable flag is “0” (enable state)
Interrupt enable bit is “1” (enable state)
Fig. 1.7.2 Register push and pop at interrupt generation and subroutine call
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HARDWARE
1.7 Central processing unit (CPU)
1.7.4 Program counter (PC)
The Program counter is a 16-bit counter consisting of an 8-bit register PCH and an 8-bit register PCL. This
counter indicates the address at which the next instruction to be executed is stored.
The contents of this counter are automatically pushed to the stack when a subroutine is called or an
interrupt occurs.
The high-order 8 bits (PCH) of the program counter become the contents of address FFFF16 and the low-
order 8 bits (PCL) become the contents of address FFFE16 immediately after hardware reset.
1.7.5 Processor status register (PS)
The Processor status register is an 8-bit register consisting of 5 flags to indicate the state immediately
after arithmetic processing and 3 flags to determine an operation for the CPU.
Each bit of the Processor status register is described below.
(1) Carry flag (C) ...................................................... Bit 0
The carry flag holds the carry or borrow from the arithmetic logical unit after arithmetic processing.
This flag is also changed by the Shift instruction or Rotate instruction.
This flag is set to “1” by the SEC instruction and cleared to “0” by the CLC instruction.
(2) Zero flag (Z) ........................................................ Bit 1
The zero flag is set to “1” when the arithmetic processing or data transfer result is “0” and cleared
to “0” in all other cases. In the decimal operation mode, this flag is invalidated.
There is no instruction to change the contents of this flag.
(3) Interrupt disable flag (I) ................................... Bit 2
The interrupt request flag disables all instructions (except an interrupt by the BRK instruction). When
this flag is “1,” the interrupt disable state is provided. This flag is set to “1” by accepting an interrupt,
thereby disabling a multi-interrupt.
This flag is set to “1” by the SEI instruction and cleared to “0” by the CLI instruction.
This flag is set to “1” (interrupt disable state) immediately after hardware reset.
(4) Decimal mode flag (D) ...................................... Bit 3
The decimal mode flag determines whether addition and subtraction should be performed in binary
or decimal notation. When the contents of this flag are “0,” an ordinary binary operation is performed.
When they are “1,” an arithmetic operation is performed assuming that one word is a 2-digit decimal
number. In a decimal operation, decimal compensation is automatically performed (decimal operation
can be performed only by the ADC instruction and the SBC instruction).
This flag is set to “1” by the SED instruction and cleared to “0” by the CLD instruction.
This flag is put in an undefined state immediately after hardware reset. As this flag directly affects
arithmetic operations, be sure to initialize it.
(5) Break flag (B) ...................................................... Bit 4
The break flag identifies whether or not an interrupt has been caused by the BRK instruction. The
BRK instruction is used for program debugging and performs the same operation as an interrupt is
performed by executing the BRK instruction.
The Processor status register is pushed to the stack, after the B flag is automatically set to “1” in
case of the BRK instruction interrupt, or after the B flag is automatically cleared to “0” in case of the
other interrupts.
There is no instruction to change the contents of this flag.
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HARDWARE
1.7 Central processing unit (CPU)
(6) Index X mode flag (T) ....................................... Bit 5
When the Index X mode flag is “0,” arithmetic operations are performed between the Accumulator
and the memory. When this flag is “1,” direct arithmetic operations and direct data transfer between
one memory and another, between a memory and an I/O, or between one I/O and another without
passing through the accumulator. An arithmetic operation result between memory 1 directly specified
by the Index register X and memory 2 specified by an operand is stored into memory 1.
1
2
When the T flag is “0”
When the T flag is “1”
A
M1
←
←
A
✽ M2
M1 ✽ M2
✽
A
: Denotes an arithmetic operation
: Content of accumulataor
M1 : Contents of memory 1 directly specified by the Index register X
M2 : Contents of memory 2 specified by the operand
This flag is set to "1" by the SET instruction and cleared to "0" by the CLT instruction. This flag is
in the undefined state immediately after hardware resetting. This flag has a direct effect on arithmetic
operations. Accordingly, be sure to initialize it.
(7) Overflow flag (V) ................................................ Bit 6
The contents of the overflow flag have significance when addition and subtraction are performed
assuming that one word is a signed binary number. When an addition or subtraction result exceeds
the range of +127 to –128, this flag is set to “1.” When the BIT instruction is executed for other
cases, the contents of bit 6 of the executed memory are put into the overflow flag.
This flag is cleared to “0” by the CLV instruction, but there is no instruction to set this flag to “1.”
In the decimal operation mode, this flag is invalidated.
(8) Negative flag (N) ................................................ Bit 7
The negative flag is set to “1” when an arithmetic processing or data transfer result is negative (bit
7 is “1”). The contents of bit 7 of the executed memory are put into this flag when the BIT instruction
is executed.
There is no instruction to change the contents of this flag.
In the decimal operation mode, this flag is invalidated.
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HARDWARE
1.8 Access area
1.8 Access area
In the 7470/7471/7477/7478 group, all ROM, RAM and I/O and the various control registers are located in
the same memory area. Accordingly, the same instructions are used for data transfer and arithmetic
operations without discriminating between a memory and an I/O.
The Program counter consists of 16 bits and the access space is 64K-byte of memory area: addresses
000016 to FFFF16.
The area of the least significant 256 bytes (addresses 000016 to 00FF16) is called the “zero page,” and
memories with a high frequency of use such as internal RAM, I/O ports and timers are located here. The
area of the most significant 256 bytes (addresses FF0016 to FFFF16) is called the “special page,” and an
internal ROM and interrupt vectors are located here.
The zero page and the special page can be accessed with 2 bytes by using each special addressing mode.
Figure 1.8.1 shows an outline of accsess area.
000016
RAM
Zero page
00C016
00FF16
SFR area
RAM
FF0016
ROM
Special page
Interrupt vector area
FFFF16
Fig. 1.8.1 Access area
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HARDWARE
1.8 Access area
1.8.1 Zero page (Addresses 000016 to 00FF16)
The area of 256 bytes from addresses 000016 to 00FF16 is called the zero page. The internal RAM and
the special function register (SFR) are located in this area.
To specify a memory or a register in this area, use the addressing mode shown in Table 1.8.1. In this
area, especially, it is possible to access this area in a shorter instruction cycle by using the zero addressing
mode.
1.8.2 Special page (Addresses FF0016 to FFFF16)
The area of 256 bytes from addresses FF0016 to FFFF16 is called the special page. The internal ROM
and the interrupt vector area are located in this area.
To specify a memory or subroutine in this area, use the addressing mode shown in Table 1.8.1. In this
area, especially, it is possible to jump to this area in a shorter instruction cycle by using the special page
addressing mode.
Ordinary, subroutines with high frequency of use are located in this area.
Table 1.8.1 Addressing mode accessible to each area
Zero page reference
Addressing mode (bytes required)
Special page reference Other area reference
Zero page (2)
—
—
—
—
—
—
,
—
—
—
—
—
—
,
,
,
,
,
,
,
Zero page indirect (2)
Zero page X (2)
Zero page Y (2)
Zero page bit (2)
Zero page bit relative (3)
Absolute (3)
,
Absolute X (3)
Absolute Y (3)
Relative (2)
,
,
,
,
,
,
,
,
,
Indirect (3)
,
,
,
Indirect X (2)
,
,
,
Indirect Y (2)
,
,
,
—
Special page (2)
—
,
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HARDWARE
1.9 Memory allocation
1.9 Memory allocation
Figure 1.9.1 and Figure 1.9.2 show the memory allocation of 7470/7471/7477/7478 group.
The memories, I/Os and others located in the access area are explained below.
● RAM
An internal RAM is located in each area shown in Table 1.9.1. The internal RAM is used as a data
storage area and a stack area for subroutine call and interrupt occurrence.
When the RAM is used as a stack area, be careful about subroutine nesting depth and interrupt levels
so that the data in the RAM is not destroyed.
● Special function register (SFR) (Addresses 00C016 to 00FF16)
The area from addresses 00C016 to 00FF16 is assigned to the SFR (Special Function Register).
Various control registers such as I/O ports, timers, serial I/Os, A-D converters and interrupts are
located in this SFR.
Figure 1.9.3 shows the special function register (SFR)memory map.
● ROM
An internal ROM is located in each area shown in Table 1.9.2.
The internal ROM is used to store data tables and programs. In the internal ROM, a vector area to
store jump destination addresses upon a reset or occurrence of interrupt are assigned to addresses
FFEA16 to FFFF16 in the 7470/7471 group and to addresses FFE816 to FFFF16 in the 7477/7478 group.
Figure 1.9.4 shows the interrupt vector memory map.
Table 1.9.1 RAM area
Product
M3747xM2
M3747xM4/E4
M3747xM8/E8
Range
Addresses 000016 to 007F16
Addresses 000016 to 00BF16
Addresses 000016 to 00BF16, Addresses 010016 to 01BF16 384 ✕ 8-bit
Memory size
128 ✕ 8-bit
192 ✕ 8-bit
Table 1.9.2 ROM area
Product
Memory type
Mask ROM
Mask ROM
Programmable ROM
Mask ROM
Range
Memory size
04K ✕ 8-bit
M3747xM2
M3747xM4
M3747xE4
M3747xM8
M3747xE8
Addresses F00016 to FFFF16
Addresses E00016 to FFFF16 08K ✕ 8-bit
Addresses C00016 to FFFF16 16K ✕ 8-bit
Programmable ROM
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HARDWARE
1.9 Memory allocation
M37470M2
M37471M2
M37470M4/E4
M37471M4/E4
M37470M8/E8
M37471M8/E8
000016
007F16
000016
007F16
000016
007F16
RAM
(192 bytes)
RAM
(192 bytes)
RAM
(128 bytes)
Zero page
Not used
SFR area
00C016
00FF16
00C016
00FF16
00C016
00FF16
010016
SFR area
SFR area
RAM
(192 bytes)
01BF16
Not used
Not used
Not used
C00016
E00016
F00016
FF0016
ROM
(4096 bytes)
ROM
(8192 bytes)
ROM
(16384 bytes)
FF0016
FF0016
Special
page
FFEA16 Interrupt vector
FFEA16 Interrupt vector
FFEA16 Interrupt vector
area
area
area
FFFF16
FFFF16
FFFF16
Fig. 1.9.1 Memory allocation of 7470/7471 group
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HARDWARE
1.9 Memory allocation
M37477M4
M37478M4
M37477M8/E8
M37478M8/E8
M37477M2
M37478M2
000016
000016
007F16
000016
RAM
(192 bytes)
RAM
(192 bytes)
RAM
(128 bytes)
007F16
007F16
Zero page
Not used
00C016
00FF16
00C016
00FF16
010016
00C016
SFR area
00FF16
SFR area
SFR area
RAM
(192 bytes)
01BF16
Not used
Not used
Not used
C00016
E00016
F00016
ROM
ROM
ROM
(8192 bytes)
(16384 bytes)
(4096 bytes)
FF0016
FF0016
FF0016
FFE816
FFFF16
Special
page
Interrupt vector
area
FFE816 Interrupt vector
FFE816 Interrupt vector
area
area
FFFF16
FFFF16
Fig. 1.9.2 Memory allocation of 7477/7478 group
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HARDWARE
1.9 Memory allocation
Port P0
Transmit/receive buffer register
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
Port P0 direction register
Port P1
Serial I/O status register
Serial I/O control register
UART control register
Baud rate generator
(Note 5)
Port P1 direction register
Port P2
Port P2 direction register (Note 1)
Port P3
00C816 Port P4
Port P4 direction register
00C916
00CA16 Port P5 (Note 2)
00CB16
00CC16
00CD16
00CE16
00CF16
Port P0 pull-up control register
Port P1-P5 pull-up control register (Note 3)
Timer 1
Timer 2
Timer 3
Timer 4
00D016
00D116
00D216
00D316
00D416 Edge polarity selection register
00D516
Input latch register
00D616
00D716
00D816
00D916
00F716 Timer FF register
Timer 12 mode register
Timer 34 mode register
00F816
00F916
A-D control register
00DA16 A-D conversion register
00DB16
00FA16 Timer mode register 2
CPU mode register
00FB16
00FC16
Serial I/O mode register
Interrupt request register 1
00DC16
(Note 4)
00DD16 Serial I/O register
00FD16 Interrupt request register 2
Interrupt control register 1
00FF16 Interrupt control register 2
00DE16
00DF16
00FE16
Serial I/O counter Byte counter
Notes 1: In the 7477/7478 group, this register is not located.
2: In the 7470/7477 group, this register is not located.
3: This address is allocated P1-P4 pull-up control register for the 7470/7477 group.
4: In the 7477/7478 group, this register is not located.
5: In the 7470/7471 group, this register is not located.
Fig. 1.9.3 Special function register (SFR) memory map
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HARDWARE
1.9 Memory allocation
FFE816
FFE916
FFEA16
FFEB16
FFEC16
FFED16
FFEE16
FFEF16
FFF016
FFF116
FFF216
FFF316
FFF416
FFF516
FFF616
FFF716
FFF816
FFF916
FFFA16
FFFB16
FFFC16
FFFD16
FFFE16
FFFF16
BRK instruction interrupt
A-D conversion completion interrupt
Serial I/O transmit interrupt
Serial I/O receive interrupt
Timer 4 interrupt
FFEA16
BRK instruction interrupt
FFEB16
FFEC16
FFED16
FFEE16
FFEF16
FFF016
FFF116
FFF216
FFF316
FFF416
FFF516
FFF616
FFF716
FFF816
FFF916
FFFA16
FFFB16
FFFC16
FFFD16
FFFE16
FFFF16
A-D conversion completion interrupt
Serial I/O interrupt
Timer 4 interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Timer 1 interrupt
CNTR0 interrupt or CNTR1 interrupt
INT1 interrupt or key on wake up interrpt
CNTR0 interrupt or CNTR1 interrupt
INT1 interrupt or key on wake up interrpt
INT0 interrupt
RESET
INT0 interrupt
RESET
7477/7478 group
7470/7471 group
Fig. 1.9.4 Interrupt vector memory map
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HARDWARE
1.10 I/O pins
1.10 I/O pins
The 7470/7471/7477/7478 group is provided with the following I/O pins.
● I/O port (P0 to P5)
● Reset input (RESET)
● Clock input/output (XIN, XOUT, XCIN, XCOUT)
● A-D convesion reference voltage input (VREF)
● Power supply voltage input (VCC, VSS, AVSS)
Notes 1: The 7470/7477 group is not provided with port P5 and pins XCIN and XCOUT.
2: The AVSS pin is dedicated to the 56P6N-A package product.
For an outline of each pin, refer to “1.5 Pin description.”
1.10.1. I/O port
(1) I/O port writing and reading
2 The input-only pin and the programmable I/O port set as input port
The values (pin states) which input to the input-only pin and to the programmable I/O port set as
input port can be read in by reading the Port register corresponding to each port.
When data is written into the Port register corresponding to each port, it can be only written in the
Port register and has no effect on the pin state.
2 The programmable I/O port set as an output port
The value written into the Port register corresponding to the programmable I/O port set as an
output port is output to the outside by way of a transistor.
When the Port register corresponding to each port has been read, each pin state is not read in
but the value written into the Port register is read. Accordingly, if the output “H” voltage has been
reduced or the output “L” voltage has been increased by an external load, the previous output
value can be correctly read.
Figure 1.10.1 shows the I/O port writing and reading and Table 1.10.1 shows the port register
address allocation.
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HARDWARE
1.10 I/O pins
At input : A write operation is enabled to the
At output : An output value can be set by writing to the
Port register. The Port register can be read out.
Port register.
Each pin state can be read in by
reading the Port register.
“H” level output
Port direction
register
*
( “0” )
Port direction
register
( “1” )
Port register
(When Writing)
Port register
“L” level output
Port register
(When Reading)
:
The P channel transistor and the N channel transistor are in a cut-off state.
*
Fig. 1.10.1 I/O port writing and reading
Table 1.10.1 Port register address allocation
Port register
Address
00C016
00C216
00C416
00C616
00C816
00CA16
P0
P1
P2
P3
P4
P5 (Note)
Note: The 7470/7477 group is not provided
with P5.
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HARDWARE
1.10 I/O pins
(2) Input/output selection of the programmable I/O ports
An input/output selection of the programmable I/O ports is made by the Port direction register
corresponding to each port.
Figure 1.10.2 shows a structure of Port Pi (i = 0, 1, 2, 4) direction register.
Note: Each direction register is initialized into “0016” at reset, so that the I/O ports are put into an
input state.
Port Pi direction register
b7 b6 b5 b4 b3b2 b1 b0
Port Pi direction register (PiD) (i = 0,1,2,4)
[Address 00C116, 00C316, 00C516, 00C916]
At reset
R W
B
0
Name
Function
0 : Port Pi0 input mode
1 : Port Pi0 output mode
Port Pi direction
register
0
0
0
0
0
0
0
0
0 : Port Pi1 input mode
1 : Port Pi1 output mode
1
2
3
4
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
5
6
0 : Port Pi6 input mode
1 : Port Pi6 output mode
7
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Notes 1: The 7477/7478 group is not provided with the port P2
direction register (input only).
2: The Port P4 is provided as below:
•7470/7477 group has 2 bits of P4 0 and P41.
•7471/7478 group has 4 bits of P4 0 to P43.
Fig. 1.10.2 Structure of Port Pi direction register (i=0, 1, 2, 4)
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HARDWARE
1.10 I/O pins
(3) Pull-up control
When input has been selected by the Port direction register, pull-up control can be exerted in bit units
shown in Table 1.10.1 by the Port P0 pull-up control register (address 00D016) or the Port P1–P5
pull-up control register* (address 00D116). At this time, control is exerted by turning on and off the
pull-up transistor.
*: The Port P1–P4 pull-up control register is arranged in the 7470/7477 group.
Note: Ports other than P0 cannot be controlled in one-bit units. For example, when P10 is pulled up
at P1 (pull-up control in units of 4 bits), P11 to P13 are also pulled up.
Figure 1.10.3 shows a structure of Port P0 pull-up control register, and Figure 1.10.4 shows a
structure of Port P1–P5 pull-up control register.
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register
[Address 00D016]
Function
At reset
B
Name
R W
Port P00 pull-up
control bit
0 : No pull-up
1 : Pull-up
0
1
2
3
4
0
Port P01 pull-up
control bit
0 : No pull-up
1 : Pull-up
0
0
0
0
0
0
0
Port P02 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P03 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P04 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P05 pull-up
control bit
0 : No pull-up
1 : Pull-up
5
6
Port P06 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P07 pull-up
control bit
0 : No pull-up
1 : Pull-up
7
Fig. 1.10.3 Structure of Port P0 pull-up control register
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HARDWARE
1.10 I/O pins
Ports P1 to P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Ports P1 to P5 pull-up control register [Address 00D116]
At reset
b
0
Function
0 : No pull-up
1 : Pull-up
Name
R W
Ports P10 to P13
pull-up control bit
Ports P14 to P17
pull-up control bit
0
0
0
0
0
?
0 : No pull-up
1 : Pull-up
1
Ports P2
0
to P2
3
pull-up
(Note 2)
0 : No pull-up
1 : Pull-up
2
3
control bit
0 : No pull-up
1 : Pull-up
Ports P2
control bit
Ports P4
control bit
4
to P2
7
pull-up
(Notes 2, 3)
0 : No pull-up
1 : Pull-up
0
to P4
3
pull-up
(Note 4)
4
5
6
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
✕
✕
?
?
Ports P5
0
to P5
3
pull-up
(Note 3)
0 : No pull-up
1 : Pull-up
0
?
control bit
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
7
Notes
1 : In the 7470/7477 group, the P1 to P4 Pull-up control register
is provided.
2 : In the 7477/7478 group, nothing is allocated to these bits.
They are undefined at reading.
3 : In the 7470/7477 group, nothing is allocated to these bits.
They are undefined at reading.
4 : The 7470/7477 group is provided with only P40 and P41.
Fig. 1.10.4 Structure of Ports P1 to P5 pull-up control register
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HARDWARE
1.10 I/O pins
1.10.2 Port block diagram
Figure 1.10.5 to Figure 1.10.9 show the block diagram of I/O ports.
Port P0
Pull-up
control register
Tr1
Direction register
Data bus
Port latch
Port P0
Port P1
Interrupt control circuit
T34M7
Pull-up
control register
Data bus
Tr2
Direction register
Port latch
Data bus
Port P13
T1
Tr3
T12M3
Direction register
Port latch
Data bus
Port P12
T0
Tr4
Direction register
Port latch
Data bus
Port P11
Tr5
Direction register
Port latch
Data bus
Port P10
Tr1-Tr5 are pull-up transistors
Fig. 1.10.5 Block diagram of Ports P0, P10 to P13
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HARDWARE
1.10 I/O pins
SM
7
Port P14-P1
7
Tr
6
SM
4
Direction register
Port latch
Data bus
Port P1
7
S
RDY
SM
SM
2
3
Tr
7
Direction register
Port latch
Data bus
Port P1
6
CLK output
CLK input
SM
3
Tr8
SM
7
Direction register
Port latch
Data bus
Port P1
5
S
OUT
Tr9
Direction register
Port latch
Data bus
Data bus
Port P1
4
S
IN
Pull-up control register
Tr6-Tr9 are pull-up transistors
Fig. 1.10.6 Block diagram of Ports P14 to P17 (7470/7471 group)
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HARDWARE
1.10 I/O pins
Port P14-P17
SIOE
SIOM
SRDY
Tr6
Direction register
Port latch
Data bus
Data bus
Data bus
Port P1
7
6
5
4
S
RDY
SCS
SIOE
SIOM
SIOE
Tr7
Direction register
Port latch
Port P1
S
CLK output
S
CLK input
SIOE
TE
Tr8
Direction register
Port latch
Port P1
TXD
SIOE
RE
Tr9
Direction register
Port latch
Data bus
Data bus
Port P1
RXD
Pull-up
control register
T
r6-Tr9 are pull-up transistors
Fig. 1.10.7 Block diagram of Ports P14 to P17 (7477/7478 group)
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HARDWARE
1.10 I/O pins
Port P2 (7470/7471 group)
:
Control in units of 4-bit
*
Pull-up
control register
Data bus
*
Tr10
Direction register
Port latch
Data bus
Port P2
Multi-
plexer
A-D conversion circuit
Port P2 (7477/7478 group)
Data bus
Port P2
Multi-
plexer
A-D conversion circuit
Port P3
Data bus
Port P3
INT
CNTR
0
, INT
1
0
, CNTR1
:
Control in units of 4-bit (Control in units of 2-bit for 7470/7477 group
)
*
Port P4
Pull-up
control register
Data bus
*
Tr11
(7470/7471 group)
Tr10
(7477/7478 group)
Direction register
Port latch
Data bus
Port P4
Tr10 and Tr11 are pull-up transistors
Fig. 1.10.8 Block diagram of Ports P2 to P4
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HARDWARE
1.10 I/O pins
Port P5 (7471/7478 group)
Pull-up
control register
Data bus
Data bus
(7471 group)
Tr
12
T
r11 (7478 group)
Port P5
3
Tr
13 (7471 group)
Tr12 (7478 group)
Data bus
Port P5
2
CM
4
(7471 group)
Tr
14
Tr13 (7478 group)
Data bus
Port P5
1
CM
4
CM
4
X
CIN
CM
4
T
r
15 (7471 group)
(7478 group)
Tr14
Data bus
Port P5
0
Tr11-Tr15 are pull-up transistors
Fig. 1.10.9 Block diagram of Port P5
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HARDWARE
1.10 I/O pins
1.10.3 Notes on use
When using I/O ports, note the following.
(1) Modify of the content of I/O port latch
When the content of the port latch of an I/O port is modified with the bit managing instruction*, the
value of the unspecified bit may be changed.
Reason
The bit managing instruction is read-modify-write instruction for reading and writing data by a byte
unit. Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the
following is executed to all bits of the port latch.
●As for a bit which is set as an input port: The pin state is read in the CPU, and is written to this
bit after bit managing.
●As for a bit which is set as an output port: The bit value is read in the CPU, and is written to this
bit after bit managing.
Make sure the following:
●Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
●Even when a bit of a port latch which is set as an input port is not specified with a bit managing
instruction, its value may be changed in case where content of the pin differs from a content of
the port latch.
bit managing instructions: SEB and CLB instruction
(2) Pull-up control
To pull-up ports by software, note the following.
●When P1 is used in the serial I/O mode, the pull-up settings corresponding to P14 to P17 are
invalidated (pull-up is impossible).
Refer to the port block diagram for details.
●When a port is set in the output mode, the pull-up setting corresponding to the port is invalidated
(pull-up is impossible).
●Ports other than P0 cannot be controlled in one-bit units. For example, when P10 is pulled up at
P1 (pull-up control in units of 4 bits), P11 to P13 are also pulled up.
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HARDWARE
1.10 I/O pins
(3) Fix of a port input level in stand-by state
Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by
state , especially for the I/O ports of the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, make sure the following:
●External circuit
●Variation of output levels during the ordinary operation
: “Stand-by state”:The stop mode by execution of the STP instruction or the wait mode by execution
of the WIT instruction:
Reason
Even when setting as an output port with its direction register, in the following state:
• N-channel ....... when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make
sure that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state
that input levels of an input and an I/O port are “undefined.” This may cause power source current.
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HARDWARE
1.10 I/O pins
(4) Termination of unused pins
Table 1.10.2 shows a termination of unused pins.
Table 1.10.2 Termination of unused pins
Terminations
Pull down (connect to Connect Connect
Pull-up (connect to VCC)
Port
Open
Note 1)
VSS) ports through a
resistor (Note 2)
to
to
VSS
ports through a resistor
(Note 2)
(
V
CC
P0
P10 to P13
P15, P17
P2 (7470/7471 group)
P4
,
,
,
,
×
×
×
(Note 5)
(Note 4)
,
,
P14, P16
×
(Note 3)
(Note 5)
(Note 4)
,
,
,
,
P2 (7477/7478 group)
P30 to P33
×
(Note 6)
(Note 6) (Note 6)
(Note 6)
,
(Note 6)
,
,
,
×
(Note 6)
(Note 6) (Note 6)
P5
,
,
×
×
×
,
(Note 7)
VREF
AVSS
(Note 8)
×
×
×
×
,
×
×
×
,
Notes 1: A pin that can be opened at the unused time has a circuit that does not allow a current to flow
into itself unless any read signal is internally input even if a medium-level input is applied at the
open state.
2: For programmable I/O ports, do not connect two or more ports together through a resistor to VCC
or VSS.
3: Note the following when setting them to the output mode and making the pins open.
• The ports function as input ports in the period from reset release till switching the ports to the
output mode by software. Accordingly, the power source current may be increased depending
on the input levels of the pins.
• If the Port direction register has been changed into the input mode by runaway or noise, re-set
the Port direction register to the output mode periodically by software.
4: To pull up a pin, set the Port direction register and the Port latch so that this pin may be into the
input mode or “H” output state.
5: To pull down a pin, set the Port direction register, the Port pull-up control register and the Port
latch so that this pin may be put in the no pull-up transistor state in the input mode or in the “L”
output state.
6: These pins are connect to the VCC or VSS without a resistor when the wiring is the shortest.
However, they are connect to the VCC or VSS through a resistor. In addition, the P33 pin of the
built-in programmable ROM version is used in common with the VPP pin, insert a resistor of about
5 kΩ in series and connect by the shortest wiring.
7: When using neither the P50 pin nor the P51 pin (used in common with the XCIN and XCOUT pin),
set bit 4 of the CPU mode register to “0” (P50 and P51 functions).
8: To pull down a pin, set the port pull-up control register so that a pull-up transistor will not be
provided for this pin.
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HARDWARE
1.11 Interrupts
1.11 Interrupts
Interrupts are used in the following cases.
● When it is requested to execute higher-priority processing than the processing routine being executed.
● When it is necessary to observe any timing for processing.
The 7470/7471 group can generate interrupts from 12 sources and the 7477/7478 group can generate
interrupts from 13 sources.
1.11.1 Description of interrupt source
2
Priority of interrupt
The interrupts are vector interrupts with a fixed priority sequence. When two or more interrupt
requests occur at the same sampling time, they are accepted starting with the highest-priority interrupt.
This priority is determined by hardware. However, a variety of priority processing can be executed
by software when the interrupt control flags (interrupt enable bit and interrupt disable flag) are used.
2
Acceptance of interrupt
The corresponding interrupt request bit is set to “1” upon occurrence of an interrupt. When the
following conditions are satisfied in this state, this interrupt is accepted.
For the details, refer to “1.11.3 Interrupt control.”
1
2
When the interrupt disable flag is cleared to “0” (interrupt enable state)
When the interrupt enable bit is set to “1” (interrupt enable state)
Table 1.11.1 shows an interrupt priority, interrupt sources and vector addresses.
Table 1.11.1 Interrupt sources and priority
Interrupt source
Vector address
Remark
Non-maskable
Polarity programmable
INT1: polarity programmable
Polarity programmable
Priority
7470/7471 group
Reset (Note)
7477/7478 group
High
FFFF16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
Lower
FFFE16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
1
2
3
4
5
6
7
8
9
INT0 interrupt
INT1 interrupt or key-on wake up interrupt
CNTR0 interrupt or CNTR1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 4 interrupt
Serial I/O interrupt
Serial I/O receive interrupt
Serial I/O transmit interrupt
A-D conversion
completion interrupt
BRK instruction interrupt
A-D conversion completion interrupt
10
11 BRK instruction interrupt
BRK instruction interrupt is non-
maskable software interrupt
FFEB16
FFE916
FFEA16
FFE816
12
Note: A reset operation is performed in the same way as an interrupt, so it is described in the table.
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HARDWARE
1.11 Interrupts
(1) INT interrupt
When detecting a rising edge or a falling edge of each INT pin (INT0, INT1), the microcomputer
generates an INT interrupt request.These polarity is selected by the edge polarity selection register
(EG: Address 00D416).
2
P30, P31 pins
The INT0 and INT1 pins are used in common with the P30 and P31 pins and always detect the
levels of P30 and P31.
2
2
In the stop mode/wait mode
When bit 5 of the Edge polarity selection register is “0,” a restoration can be attained by the INT
interrupt from the stop mode/wait mode state provided by the STP/WIT instruction. For the details,
refer to “1.17 Low-power dissipation function.”
After reset
At reset release, the Edge polarity selection register is cleared to “0016,” so the INT0 and INT1
interrupts generate the interrupt request by detecting a falling edge. At reset release, however, the
Interrupt control register is put into the interrupt disable state, so any interrupt is not accepted.
Note: The INT0 and INT1 pins are used in common with input port P30 and P31, however, there is
no register for switching between the INT pins and the ports, so the active edges of P30 and
P31 are always detected. When these pins are used as ports, put the corresponding INT
interrupt into the disable state.
In the INT interrupt enable state, the INT interrupt is generated by a pin level change, thereby
causing a program run away.
(2) Key-on wake up interrupt
When bit 5 of the Edge polarity selection register is “1,” the key-on wake up interrupt request is
generated by applying the “L” level to any pin of P0 being an input port in the stop mode/wait mode
provided by the STP/WIT instruction, so that a recovery can be attained from the stop mode/wait
mode.
2
After reset
At reset release, bit 5 of the Edge polarity selection register is cleared to “0” so that the key-on
wake up interrupt request does not occur in the stop mode/wait mode.
Notes 1: In modes other than the stop mode/wait mode, the key-on wake up interrupt is disabled.
2: To select the stop mode/wait mode by the STP/WIT instruction when the interrupt disable
flag is cleared to “0” and bit 5 of the Edge polarity selection register is set to “1,” set every
input to P0 to “H.”
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HARDWARE
1.11 Interrupts
Figure 1.11.1 shows a block diagram of interrupt input and key-on wake up circuit.
P3
P3
3
/CNTR
/CNTR
1
Port P3
3 data read circuit
CNTR interrupt request signal
EG
3
2
EG
4
EG
2
0
Port P3
2
data read circuit
data read circuit
X
CIN
1/2
XIN 1/2
P3
P3
0
1
/INT
/INT
0
1
CM
7
Port P3
Port P3
0
Noise elimination
circuit
EG
0
INT
0
interrupt request signal
1
data read circuit
Noise elimination
circuit
EG
1
EG
5
INT1 interrupt request signal
CPU stop state signal
Pull-up control register
Direction register
P0
7
Pull-up control
register
Direction register
P0
P0
1
0
Port P0 data read circuit
Pull-up control
register
Direction register
X
CIN pin.
Note: The 7470/7477 group is not provided with the
Fig. 1.11.1 Block diagram of interrupt input and key-on wake up circuit
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HARDWARE
1.11 Interrupts
(3) CNTR interrupt
When detecting a rising edge or a falling edge of each CNTR pin (CNTR0, CNTR1), the microcomputer
generates an CNTR interrupt. For selecting the active edge of interrupt and the CNTR0/CNTR1 pin,
the Edge polarity selection register (EG) is used.
2
After reset
At reset release, the Edge polarity selection register is cleared to “0016,” so the CNTR0 interrupts
generate the interrupt request by detecting a falling edge. At reset release, however, the Interrupt
control register is put into the interrupt disable state, so any interrupt is not accepted.
Note: The CNTR0 and CNTR1 pins are used in common with input port P32 and P33, however there
is no register for switching between the CNTR pins and the ports, so the active edges of P32
and P33 are always detected. When these pins are used as ports, put the corresponding CNTR
interrupt into the disable state. In the CNTR interrupt enable state, the CNTR interrupt is
generated by a pin level change, thereby causing a program run away.
(4) Timer interrupt
The microcomputer generates the interrupt request at the rise of the next count source after the
respective timer overflows.
For the details of the timer interrupt, refer to “1.12 Timers.”
(5) Serial I/O interrupt
There is a difference in the serial I/O interrupt between the 7470/7471 group and the 7477/7478
group.
2
Serial I/O interrupt of 7470/7471 group
An interrupt request is generated upon termination of the serial I/O transmit/receive.
Serial I/O interrupt of 7477/7478 group
2
The serial I/O transmit interrupt and the serial I/O receive interrupt are available.
● Serial I/O transmit interrupt
For the Serial I/O transmit interrupt, interrupt request generation timing can be selected by bit 3
of the Serial I/O control register (SIOCON: Address 00E216) as shown below.
0: The data written in the Transmit buffer is transferred to the Transmit shift register, and when
the Transmit buffer becomes empty, the interrupt request is generated.
1: The interrupt request is generated when a shift operation of the Transmit shift register terminates.
Note: When the transmit enable bit is set to the enable state, the Transmit buffer becomes empty
and the transmit shift terminates. Accordingly, the interrupt request can be generated by
selecting one of these sources. To use the transmit interrupt, set the transmit enable bit to “1,”
clear the transmit interrupt request bit to “0,” and then set the transmit interrupt enable bit to
the enable state.
● Serial I/O receive interrupt
When all data has been put in the Receive shift register and the contents of the shift register have
been transferred to the Receive buffer, the interrupt request is generated.
For the details of the serial I/O interrupt, refer to “1.13 Serial I/O.”
(6) A-D conversion completion interrupt
As soon as A-D conversion terminates, the interrupt request is generated.
For the details of the A-D conversion completion interrupt, refer to “1.14 A-D Converter.”
(7) BRK instruction interrupt
This is the lowest-priority software interrupt without any corresponding interrupt enable flag, and not
affected by the interrupt disable flag. (Non maskable)
For the details, refer to “SERIES 740 SOFTWARE USER’S MANUAL.”
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HARDWARE
1.11 Interrupts
1.11.2 Operation description
(1) Interrupt operation
After an interrupt is accepted, the contents of the register shown below are automatically pushed to
the stack area in sequence in the order of 1 , 2 and 3 .
1
2
3
Program counter high-order (PCH)
Program counter low-order (PCL)
Processor status register (PS)
After the above register is pushed, a branch is made to the vector address of the accepted interrupt.
When the RTI instruction is executed at the end of the interrupt processing routine, the contents of
the above register which were pushed onto the stack area are popped to the respective registers in
sequence in the order of 3 , 2 and 1 , and the processing precedent to the acceptance of the
interrupt is restarted.
Figure 1.11.2 shows the interrupt operation.
Executing routine
·······
Interrupt occurs
(Accepting interrupt request)
Contents of Program counter (high-order) are pushed onto stack
Contents of Program counter (low-order) are pushed onto stack
Contents of Processor status register are pushed onto stack
Suspended
operation
Resume processing
·······
Interrupt
processing
routine
RTI instruction
Contents of Processor status register are popped from stack
Contents of Program counter (low-order) are popped from stack
Contents of Program counter (high-order) are popped from stack
: Operation commanded by software
: Internal operation to be performed automatically
Fig. 1.11.2 Interrupt operation
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HARDWARE
1.11 Interrupts
(2) Processing upon acceptance of interrupt
When an interrupt is accepted, the following operations are automatically performed.
1
2
The processing being executed is interrupted.
The contents of the Program counter and the Processor status register are pushed to the stack
area.
Figure 1.11.3 shows a change of the contents of the Program counter and the Stack pointer upon
acceptance of the interrupt.
3
4
The vector address (start address of the interrupt processing routine) stored in the vector area
corresponding to the generated interrupt concurrently with pushing is set in the Program counter
and the interrupt processing routine is executed.
After the interrupt processing routine is started, the corresponding interrupt request bit is automatically
cleared to “0.” The interrupt disable flag is set to “1,” thereby disabling a multi-interrupt.
To execute the interrupt processing routine, it is necessary to set a vector address in the vector
area corresponding to each interrupt beforehand.
Program counter
Stack area
PCL
PCH
Program counter (low-order)
Program counter (high-order)
Interrupt disable flag = “0”
Stack pointer
S
(S)
(S)
Interrupt
request is
accepted
Program counter
Stack area
(S) – 3
PCL
PCH
Vector address
Interrupt disable flag = “1”
(from Interrupt vector area)
Processor status register
Program counter (low-order)
Stack pointer
S
(S) Program counter (high-order)
(S) – 3
Fig. 1.11.3 Changes of contents of Program counter and Stack pointer upon acceptance of interrupt
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HARDWARE
1.11 Interrupts
(3) Timing after acceptance of interrupt
The interrupt processing routine starts with the machine cycle after termination of the instruction
being executed.
Figure 1.11.4 shows a processing time up to the execution of the interrupt processing routine and
Figure 1.11.5 shows a timing after acceptance of the interrupt.
Interrupt request occurs
Main routine
Interrupt operation starts
Waiting time for
pipeline post-
processing
Push onto stack
Vector fetch
Interrupt processing routine
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles
(At internal system clock φ = 4 MHz, 1.75 µs to 5.75 µs)
: At the DIV instruction executed.
Fig. 1.11.4 Processing time up to the execution of interrupt processing routine
Waiting time for
pipeline
postprocessing
Interrupt operation starts
Push onto stack
Vector fetch
φ
SYNC
R/W
S, SPS S-1, SPS S-2, SPS
BL
BH
AL, AH
Address bus
Data bus
PC
Not used
PCH
PCL
AL
AH
PS
: CPU operation code fetch cycle
SYNC
(This is an internal signal which cannot be observed from the external unit.)
: Vector address of each interrupt
: Jump destination address of each interrupt
BL, BH
AL, AH
SPS
: “0016” or “0116”
(when the stack page bit is “0,” SPS is 0016,” and when the bit is “1,” SPS is
16”)
“01
Fig. 1.11.5 Timing after acceptance of interrupt
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HARDWARE
1.11 Interrupts
1.11.3 Interrupt control
Regarding interrupts other than the BRK instruction, the acceptance of them can be controlled by the
interrupt request bit, the interrupt enable bit and the interrupt disable flag. This section describes interrupt
control other than the BRK instruction.
Figure 1.11.6 shows a interrupt control diagram.
Interrupt request bit
Interrupt enable bit
Interrupt accepted
Interrupt disable flag
BRK instruction
Reset
Fig. 1.11.6 Interrupt control diagram
The interrupt request bit, the interrupt enable bit and the interrupt disable flag function independently and
do not affect one another. An interrupt is accepted when all the following conditions are satisfied.
● Interrupt request bit ............. “1”
..............
............
● Interrupt enable bit
● Interrupt disable flag
“1”
“0”
The priority is determined by hardware. However, a variety of priority processing can be executed by
software when the above flag and bits are used.
Table 1.11.2 shows a interrupt control bits for individual interrupt sources.
Table 1.11.2 Interrupt control bits for individual interrupt sources
Interrupt request bits
Interrupt enable bits
Interrupt source
Address
00FC16
00FC16
00FC16
00FC16
00FC16
00FC16
00FC16
00FC16
00FD16
00FD16
00FD16
Bits
Bits
Address
00FE16
00FE16
00FE16
00FE16
00FE16
00FE16
00FE16
00FE16
00FF16
00FF16
00FF16
b0
b1
b2
b3
b0
b1
b2
b3
Timer 1
Timer 2
Timer 3
Timer 4
b6 (Note 1)
b5 (Note 2)
b6 (Note 2)
b6 (Note 1)
Serial I/O (7470/7471 group)
Serial I/O receive (7477/7478 group)
Serial I/O transmit (7477/7478 group)
A-D conversion
b5 (Note 2)
b6 (Note 2)
b7
b0
b1
b2
b7
b0
b1
b2
INT0
INT1
CNTR0/CNTR1
Notes 1: This bit is not provided in the 7477/7478 group.
2: This bit is not provided in the 7470/7471 group.
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HARDWARE
1.11 Interrupts
(1) Interrupt request bit
The interrupt request bits are assigned to each bit of the Interrupt request register 1(IR1: Address
00FC16) and the Interrupt request register 2(IR2: Address 00FD16).
If an interrupt request occurs, the corresponding interrupt request bit is set to “1.”
The interrupt request bit is held in the “1” state until the interrupt is accepted. After it is accepted,
this bit is automatically cleared to “0.”
The interrupt request bit can be cleared to “0” by software but cannot be set to “1” by software.
(2) Interrupt enable bit
The interrupt enable bits are assigned to each bit of the Interrupt control register 1 (IE1: Address
00FE16) and the Interrupt control register 2 (IE2: Address 00FF16).
The interrupt enable bit controls the acceptance of the corresponding interrupt. When the interrupt
enable bit is “0,” the acceptance of the corresponding interrupt is disabled. If an interrupt request
occurs when this bit is “0,” the corresponding interrupt request bit is set to “1,” but this interrupt is
not accepted. In this case, the interrupt request bit is cleared to “0” by software or remains in the
“1” state until the interrupt enable bit is set to “1.”
When an interrupt enable bit is “1,” the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1,” this interrupt is accepted. (However, the interrupt disable flag that will be
described later must be “0.”) The interrupt enable bit can be cleared to “0” or set to “1” by software.
(3) Interrupt disable flag
The interrupt disable flag controls the acceptance of the interrupt, and is assigned to bit 2 of the
Processor status register (PS).
When this flag is “1,” the interrupt disable state is provided. When this flag is “0,” the acceptance of
interrupt is enable state.
This flag is set to “1” by the SEI instruction and cleared to “0” by the CLI instruction.
This flag is set to “1” (interrupt disable state) automatically after the interrupt processing routine. To
use a multi-interrupt, set this flag to “0” by using the CLI instruction in the interrupt processing
routine.
2
Interrupt setting
Set an interrupt according to the procedure shown below.
1 The interrupt disable flag is set to “1.”
2 The interrupt enable bit is cleared to “0.”
3 For the INT interrupt or the CNTR interrupt, set the active edge in the Edge polarity selection
register.
Select one of the above interrupts in bit 4 of the Edge polarity selection register because the
CNTR0 interrupt and the CNTR1 interrupt can not be used simultaneously. ( 0: CNTR0, 1:
CNTR1 )
4 The request bit of interrupt used is cleared to “0.” (Refer to “Table 1.11.2.”)
5 The enable bit of interrupt used is set to “1.” (Refer to “Table 1.11.2.”)
6 The interrupt disable flag is cleared to “0.”
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HARDWARE
1.11 Interrupts
1.11.4 Notes on use
(1) When using P30 to P33 as input ports, put the corresponding INT interrupt or the CNTR interrupt into
a disable state.
(2) Set the interrupt request bit and the interrupt enable bit for preparations for an interrupt in the
following order.
1
2
Clear the interrupt request bit to “0.” (No interrupt request)
Set the interrupt enable bit to “1.” (Interrupt enabled)
When using the INT interrupt or the CNTR interrupt, first set the interrupt detection edge and then
set the above items 1 and 2 . (Refer to (4) that will be described later.)
(3) An interrupt request bit can be cleared to “0” by software, but is still remained at the value precedent
to a change immediately after execution of the clear instruction. For this reason, when executing
the BBC or BBS instruction after changing an interrupt request bit, first execute the interrupt request
bit change instruction and then execute the BBC or BBS instruction after one instruction or more.
(4) When the detection edge of the INT interrupt or that of the CNTR interrupt is switched, the corresponding
interrupt request bit may be set to “1.” Accordingly, perform setting referring to the register setting
example shown in Figure 1.11.7.
Clear the corresponding interrupt enable bit to “0”
Set the interrupt active edge
Clear the corresponding interrupt request bit to “0”
Execute one or more instructions (NOP instruction, and so on)
Set the corresponding interrupt enable bit to “1”
Fig. 1.11.7 Example of register setting
(5) Whether an interrupt is caused by the BRK instruction or not can be judged by the contents of the
break flag of the Processor status register pushed on the stack area.
● Break flag = “1” : An interrupt has been caused by the BRK instruction
● Break flag = “0” : In case of the other interrupts
Note: Make this judgment in the interrupt processing routine.
(6) When an INT interrupt request is generated by executing the STP/WIT instruction in one of the
following states, the stop mode/wait mode is released.
● When the active edge of the INT interrupt is a rising edge and the INT pin input level is “H”
● When the active edge of the INT interrupt is a falling edge and the INT pin input level is “L”
Accordingly, when executing the STP/WIT instruction, it is necessary to consider the input level of
the INT pin and the polarity of the INT edge. Examples of countermeasures for it are shown below.
1. An example of a countermeasure for the case where the stop mode/wait mode is released at the
rising edge of the INT pin input level
Point: To release the stop mode/wait mode normally, perform mode release processing in the
INT interrupt processing routine only when the STP/WIT instruction was executed at the
“L” INT pin input level.
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1.11 Interrupts
< Main routine >
In the main routine, set the INT edge polarity according to the INT pin input level just precedent
to execution of the STP/WIT instruction.
1 INT interrupt disable
2 ● Select the falling edge when the INT pin input level is “H.”
● Select the rising edge when the INT pin input level is “L.”
3
Clear the INT interrupt request bit to “0” and enable an INT interrupt after one instruction
or more.
4
5
Clear the interrupt disable flag to “0.”
Execute the STP/WIT instruction
< INT interrupt processing routine >
In the INT interrupt processing routine, change the active edge of the INT interrupt without
performing release processing and proceed to the stop mode/wait mode in the case where the
stop mode/wait mode is released by detecting a falling edge.
● When the INT pin input level is “H” (when a rising edge is detected)
Processing for releasing the stop mode/wait mode
● When the INT pin input level is “L” (when a falling edge is detected)
[1] Select the rising edge
[2] Clear the INT interrupt request bit to “0”
[3] Pop from stack
[4] Perform 4 and 5 processing of the main routine.
2. An example of a countermeasure for the case where the stop mode/wait mode is released at the
rising edge of the INT0 pin input level or the falling edge of the INT1 pin input level after the same
signal is input to the INT0 pin and the INT1 pin.
Point: Select the INT interrupt, by the main routine, that becomes a source of release of the stop
mode/wait mode according to the INT pin input level just precedent to execution of the
STP/WIT instruction.
< Main routine >
1 INT0 and INT1 interrupt disable
2 Select the rising edge for the active edge of the INT0 interrupt.
Select the falling edge for the active edge of the INT1 interrupt.
3 ●When the INT pin input level is “H”
Clear the INT1 interrupt request bit to “0” and enable the INT1 interrupt after one instruction
or more.
●When the INT pin input level is “L”
Clear the INT0 interrupt request bit to “0” and enable the INT0 interrupt after one instruction
or more.
4 Clear the interrupt disable flag to “0.”
5 Execute the STP/WIT instruction.
(7) In ordinary operation, if the pulse width of the INT input signal is 2 internal clocks f ( f(XIN)/2 ) or
more by the built-in noise elimination circuit, it is accepted as an interrupt input. Input the INT input
signal with a pulse width of 100 ns or more in the stop mode and the wait mode.
Reference: As a hardware-level means to prevent incorrect interrupt processing due to noise, a noise
elimination circuit is incorporated in the INT0 and INT1 pins so that no interrupt can be
generated by an “H” pulse (when the rising edge is selected) or an “L” pulse (when a
falling edge is selected) of one machine cycle or less in modes other than the stop mode
and the wait mode. As a software-level means, the levels of the INT0 and INT1 pins are
judged at the beginning of the interrupt processing routine.
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1.11 Interrupts
1.11.5 Related registers
(1) Edge polarity selection register (EG: Address 00D416)
The Edge polarity selection register selects an active edge of each INT interrupt and selects a
source of interrupt.
Figure 1.11.8 shows a structure of Edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416
]
At reset
Name
Function
R
W
B
0
INT
bit
0
1
edge selection
0 : Falling edge
1 : Rising edge
0
0 : Falling edge
1 : Rising edge
1
2
3
4
5
INT
bit
edge selection
0
0
0 : Falling edge
1 : Rising edge
0 : Falling edge
1 : Rising edge
CNTR
selection bit
CNTR edge
selection bit
CNTR /CNTR
interrupt selection bit
0 edge
1
0
0
0 : CNTR
1 : CNTR
0
1
0
1
INT
1
source selection 0 : P3
1 : P0
1
/INT
1
bit (at STP or WIT
0
to P0
7
“L” level input
0
?
instruction execution) (for key-on wake-up)
Nothing is allocated for these bits. These are
write disabled bits and are undefined at reading.
6, 7
?
✕
Fig. 1.11.8 Structure of Edge polarity selection register
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1.11 Interrupts
(2) Interrupt request register 1 (IR1: Address 00FC16)
Interrupt request register 2 (IR2: Address 00FD16)
The Interrupt request register 1 and the Interrupt request register 2 consist of bits that indicate
whether an interrupt request exists or not.
Figure 1.11.9 shows a structure of the Interrupt request register 1 and Figure 1.11.10 shows a
structure of the Interrupt request register 2.
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IR1) [Address 00FC16
]
At reset
B
0
Name
Function
R W
0
0 : No interrupt request
1 : Interrupt requested
Timer 1 interrupt
request bit
✽
1
2
3
4
5
Timer 2 interrupt
request bit
0 : No interrupt request
1 : Interrupt requested
0
0
0
?
✽
✽
Timer 3 interrupt
request bit
Timer 4 interrupt
request bit
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
0 : No interrupt request
1 : Interrupt requested
0 : No interrupt request
1 : Interrupt requested
✽
?
✕
✽
Serial I/O receive interrupt
request bit
0 : No interrupt request
1 : Interrupt requested
0
(7477/7478 group)(Note)
0 : No interrupt request
1 : Interrupt requested
Serial I/O interrupt request
6
bit (7470/7471group)
Serial I/O transmit
interrupt request bit
(7477/7478 group)
0
0
✽
✽
7
A-D conversion completion 0 : No interrupt request
interrupt request bit 1 : Interrupt requested
Note: In the 7470/7471group, nothing is allocated for bit 5. This is write
disabled bit and is undefined at reading.
✽: “0” is set by software, but not “1.”
Fig. 1.11.9 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IR2) [Address 00FD16
]
At reset
B
0
Name
Function
R W
0
0 : No interrupt request
1 : Interrupt requested
INT
bit
INT
bit
0
1
interrupt request
✽
1
2
interrupt request 0 : No interrupt request
1 : Interrupt requested
0 or CNTR1
0
0
?
✽
✽
CNTR
0 : No interrupt request
1 : Interrupt requested
interrupt request bit
Nothing is allocated for these bits. There are write
disabled bits and are undefined at reading.
3
to
7
✕
?
✽: “0” is set by software, but not “1.”
Fig. 1.11.10 Structure of Interrupt request register 2
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1.11 Interrupts
(3) Interrupt control register 1 (IE1: Address 00FE16)
Interrupt control register 2 (IE2: Address 00FF16)
The Interrupt control register 1 and the Interrupt control register 2 control the acceptance of interrupt
by source.
Figure 1.11.11 shows a structure of the Interrupt control register 1 and Figure 1.11.12 shows a
structure of an Interrupt control register 2.
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (IE1) [Address 00FE16
]
At reset
B
0
Name
Function
R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt
enable bit
1
2
3
4
5
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
?
Timer 3 interrupt
enable bit
Timer 4 interrupt
enable bit
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
?
✕
Serial I/O receive interrupt
enable bit (7477/7478
group) (Note)
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Serial I/O interrupt enable
bit (7470/7471 group)
Serial I/O transmit interrupt
enable bit (7477/7478 group)
0 : Interrupt disabled
1 : Interrupt enabled
6
7
A-D conversion completion 0 : Interrupt disabled
interrupt enable bit 1 : Interrupt enabled
0
Note: In the 7470/7471 group, Nothing is allocated for bit 5.
This is write disabled bit and undefined at reading.
Fig. 1.11.11 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (IE2) [Address 00FF16]
At reset
B
0
Name
Function
R W
0
0 : Interrupt disabled
1 : Interrupt enabled
INT0 interrupt enable
bit
1
2
INT1 interrupt enable
bit
CNTR0 or CNTR1
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
?
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is allocated for these bits. There are write
disabled bits and are undefined at reading.
3
to
7
✕
?
Fig. 1.11.12 Structure of Interrupt control register 2
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1.12 Timers
1.12 Timers
The 7470/7471/7477/7478 group has four 8-bit timers (Timer 1, Timer 2, Timer 3 and Timer 4) with an 8-
bit timer latch. The division ratio of the timer is 1/(n+1) when the contents of the timer latch are n (n:0
to 255).
For the timer, the following modes can be selected by software setting.
• Timer mode
• Event counter mode
• Pulse output mode
• External pulse width measurement mode
• PWM mode
Table 1.12.1 shows the modes of each timer and Figure 1.12.1 shows a timer block diagram.
Table 1.12.1 Modes of each timer
Mode
Event
Pulse
External pulse width
Timer mode
PWM mode
Timer
Timer 1
counter mode
output mode
measurement mode
✕
✕
✕
✕
✕
✕
✕
✕
Timer 2
Timer 3
Timer 4
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1.12 Timers
Data bus
X
CIN
1/2
1/8
Timer 1 latch (8)
Timer 1 (8)
X
IN
1/2
T12M
2
CM
7
T12M
0
Timer 1
interrupt request
T12M
1
P3
2
/CNTR
0
EG
2
Port latch
TM2
0
1/2
P12/T
0
T12M
T12M
3
Timer 2 latch (8)
Timer 2 (8)
7
T12M6,
T12M
4
Timer 2
T12M
5
interrupt request
1/4
1/8
TM2
6
T34M
T34M
1
2
1/16
Timer 3 latch (8)
Timer 3 (8)
T34M
0
Timer 3
interrupt request
P3
3
/CNTR
1
EG
3
T34M
4
5
T34M
Timer 4 latch (8)
Timer 4 (8)
Timer 4
interrupt request
EG
4
Port latch
T34M
T34M
6
F/F
T34M
3
P1
3
/T1
1/2
TM2
7
7
EG
EG
EG
EG
3
2
1
0
TM2
1
P3
3
2
/CNTR
/CNTR
1
C
P3
0
1
0
D3 Q3
Q2
D2
D1 Q1
D0 Q0
P3
1
0
/INT
/INT
P3
X
CIN pin.
) described the right side of the register represents
the bit number of the register.
Notes 1: The 7470/7477 group is not provided with the
2: The number (ex. EG
3
Fig. 1.12.1 Timer block diagram
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1.12 Timers
1.12.1 Operation description
In a write operation, the timer latch is specified at the same time when the timer is specified. If the timer
is set to n16, the timer latch is also set to n16 (n: 0016 to FF16). After the timer starts to count,
1 the timer value is counted down as n16 → (n-1)16 → (n-2)16 → ... → 116 → 016 → FF16 at each rise
of the count source.
2 At the next rise of the count source after “FF16,”
● (n-1)16 resulting from decrementing 1 from the timer latch value is set (reloaded) in the timer and
then the timer continues to count.
● When an overflow occurs, the interrupt request bit is set to “1.”
Note: When the interrupt is accepted, the interrupt request bit changes from “1” to “0.” It can be
clearned to “0” but cannot be set to “1” by software.
Figure 1.12.2 shows a timer count timing.
Count start
Count operation stop
Count stop bit
Reload
Writing to timer
Timer count source
(n–1)16
n
16
(n–1)16 (n–2)16 (n–3)16
(n–1)16 (n–2)16 (n–3)16
16
Value of timer
✕✕16
1
16
0
16
FF16
Read value of timer
(n–1)16
n
(✕✕+1)16
1
16
0
16
FF16
Timer interrupt
request bit
Fig. 1.12.2 Timer count timing
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1.12.2 Description of modes
(1) Timer mode
The operations of the timer modes are as explained below.
1
Start of count operation
When the count stop bit is cleared to “0,” a count operation starts. When there is a count source
input, the contents of the timer are decremented by 1.
Note: Because the count stop bit is “0” immediately after reset release, the count operation is
automatically started after reset release.
2
3
Reload operation
When the timer overflows, the value resulting from decrementing 1 from the contents of the timer
latch is transferred (reloaded) to the timer.
Interrupt operation
2 Timer interrupt
When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set
to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer.
4
Stop of count operation
When the counter stop bit is set to “1” by software, the count operation stops. (The count operation
continues until the count stop bit is set to “1.”)
Figure 1.12.3 shows an example of timer mode operation.
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Count period
Count period T(s) = 1 ÷ count source frequency ✕ (the timer initial value + 1)
Timer mode operation example
• OF: Overflow
“1” is written
“0” is written
• RL: Reload
• n: Timer initial value
Timer 1 count stop bit
Timer 1 count source
RL
RL
RL
RL Count stop
(n-1)16
Count restart
Down count
OF
OF
OF
OF
FF16
Time
T
Timer 1 interrupt
request bit
A
A
A
A
Timer 1 interrupt
enable bit
• Clearing by writing “0” to the timer interrupt request bit.
• Clearing by accepting the timer interrupt request when the timer interrupt enable bit is “1.”
A :
Fig. 1.12.3 Example of timer mode operation
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1.12 Timers
[Setting method]
1
Set a value to be used according to the count source setting for timers. The count operation of
the timer is stopped. Refer to “Table 1.12.2 Setting for count stop.”
Table 1.12.2 Setting for count stop
Setting item Timer 12 mode register
(T12M: Address 00F816)
Timer 34 mode register
(T34M: Address 00F916)
Timer
b4
–
1
b0
1
–
b3
b0
Timer 1
–
–
Timer 2
Timer 3
Timer 4
–
1
1
–
–
–
2
Count source selecting
Select a count source according to the count source setting for timers shown in Table 1.12.3 to
Table 1.12.6. Note that selectable count sources are different among timers.
Because the 7470/7477 group is not provided with an XCIN pin, do not select f(XCIN) as a count
source.
Table 1.12.3 Setting for timer 1 count source
Setting item CPU mode register
Timer 12 mode register
(T12M: Address 00F816)
Count source
to be selected
f(XIN)/16
(CM: Address 00FB16)
b7
0
b2
0
b1
(Note)
f(XCIN)
f(XCIN)/16
–
1
1
0
0
External clock input from
CNTR0 pin.
–
–
1
Note: When f(XCIN) is selected as a timer count source, f(XIN) or f(XCIN) can be selected as a system clock.
Table 1.12.4 Setting for timer 2 count source
Setting item
CPU mode register
(CM: Address 00FB16)
b7
Timer 12 mode register
(T12M: Address 00F816)
Count source
to be selected
f(XIN)/16
b7
b6
0
b5
0
0
1
1
0
0
1
1
–
f(XIN)/64
1
0
1
0
1
0
1
–
0
f(XIN)/128
f(XIN)/256
f(XCIN)/16
f(XCIN)/64
f(XCIN)/128
f(XCIN)/256
0
1
1
–
Timer 1 overflow signal
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Table 1.12.5 Setting for Timer 3 count source
Setting item
CPU mode register
Timer mode register 2
Timer 34 mode register
Count source
to be selected
f(XIN)/16
f(XCIN)
f(XCIN)/16
(CM: Address 00FB16)
(TM2: Address 00FA16) (T34M: Address 00F916)
b7
0
b6
–
b2
0
0
b1
0
1
(Note)
–
1
0
0
Timer 1 overflow signal
Timer 2 overflow signal
External clock input from
CNTR1 pin
0
1
–
–
1
1
0
1
–
Note: When f(XCIN) is selected as a timer count source, f(XIN) or f(XCIN) can be selected as a system clock.
Table 1.12.6 Setting for Timer 4 count source
Setting item
CPU mode register
Timer mode register 2
Timer 34 mode register
Count source
to be selected
f(XIN)/16
(CM: Address 00FB16)
(TM2: Address 00FA16) (T34M: Address 00F916)
b7
0
1
b6
–
b6
b5
0
b4
1
f(XCIN)/16
Timer 1 overflow signal
Timer 2 overflow signal
Timer 3 overflow signal
External clock input from
CNTR1 pin
0
1
1
0
0
(Note) (Note)
–
0
0
–
1
1
Note: If the Timer 1 overflow signal is selected as a Timer 2 count source at [b5,b4] = [1,0], the Timer 4
count source becomes the Timer 1 overflow signal regardless of bit 6 of Timer mode register 2.
3
4
Set a count value in the timer.
Refer to “Table 1.12.7 Address allocation
for timer.”
Table 1.12.7 Address allocation of timer
Timer
Address
00F016
00F116
00F216
00F316
Timer 1(T1)
Timer 2(T2)
Timer 3(T3)
Timer 4(T4)
When a value is set according to the count start setting shown in Table 1.12.8, the timer starts
to count.
Table 1.12.8 Count start setting
Setting item
Timer 12 mode register
(T12M: Address 00F816)
Timer 34 mode register
(T34M: Address 00F916)
b4
–
0
b0
0
–
b3
b0
Timer
Timer 1
Timer 2
Timer 3
Timer 4
–
–
–
0
0
–
–
–
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(2) Event counter mode
In the event counter mode, the same operations as those in the timer mode are performed, with the
exception that the signal input from the CNTR pin becomes a count source of Timer 1 and the signal
0
input from the CNTR1 pin becomes a count source of Timer 3 and Timer 4.
The operation in the event counter mode are described below.
1
Start of count operation
After the count stop bit is cleared to “0,” a count operation starts. Each time a count source is
input, the contents of the timer are decremented by 1.
For the active edge of count source, a rise or a fall can be selected by the edge polarity selection
register (address 00D416).
Note: Because the count stop bit is “0” immediately after reset release, the count operation is
automatically started after reset release but the count source is not a CNTR pin input (operates
as the timer mode).
2
3
Reload operation
When the timer overflows, the value resulting from decrementing 1 from the contents of the timer
latch is transferred (reloaded) to the timer.
Interrupt operation
2 Timer interrupt
When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set
to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer.
2 CNTR interrupt
An interrupt request is generated from the edge of the count source input from the CNTR0 pin
or the CNTR1 pin, so that the interrupt request is set to “1.” The acceptance of interrupt is
controlled by the interrupt enable bit of each timer.
The edge polarity selection register selects an active edge of count source and a CNTR0/
CNTR1 interrupt.
4
Stop of count operation
When the counter stop bit is set to “1” by software, the count operation stops. (The count operation
continues until “1” is set in the count stop bit.)
Figure 1.12.4 shows an example of event counter mode operation.
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1.12 Timers
Count period
Count period T(s) = 1 ÷ count source frequency ✕ (the timer initial value + 1)
Event counter mode operation example
“0” is written
• OF: Overflow
“1” is written
• RL: Reload
• n: Timer initial value
Timer 1 count stop bit
Count source
(CNTR0 pin)
to B
Count stop
Count restart
RL
RL
RL
Down count
(n-1)16
FF16
OF
OF
OF
Time
T
CNTR edge
selection bit
In this example, the CNTR interrupt request occurs at rising edge of the count source.
In this example, each CNTR interrupt request does not occur during executing the CNTR interrupt processing routine.
CNTR interrupt
request bit
A
A
A
A
A
A
A
A
A
A
A
A
CNTR interrupt
enable bit
B
Timer 1 interrupt
request bit
A
A
A
Timer 1 interrupt
enable bit
A : • Clearing by writing “0” to the Timer 1 and CNTR interrupt request bits.
• Clearing by accepting the Timer 1 and CNTR interrupt requests when the timer 1 and
CNTR interrupt enable bits are “1.”
Fig. 1.12.4 Example of event counter mode operation
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1.12 Timers
[Setting method]
1
The count operation of a timer to be used is stopped.
Refer to “Table 1.12.2 Setting for count stop.”
2
3
Select a count source according to the event counter mode setting shown in Table1.12.9.
Set a count value in the timer.
Refer to “Table 1.12.7 Address allocation of timer.”
Start a count operation of timer to be used.
4
Refer to “Table 1.12.8 Count start setting.”
Table. 1.12.9 Event counter mode setting
Timer
to be
used
Timer 1
Timer 3
Timer 4
Edge polarity selection register Timer 12 mode register
(EG: Address 00D416) (T12M: Address 00F816)
Timer 34 mode register
(T34M: Address 00F916)
Count
source
b3
–
b2
b1
1
b6
0
b5
b4
–
b2
b1
1
Select (Note)
CNTR0
CNTR1
Select
(Note)
–
1
1
–
–
1
–
Note: 0: The falling edge (An input, when it is inverted, becomes a count source).
1: The rising edge (An input itself becomes a count source).
(3) Pulse output mode
The pulse output mode is a mode resulting from adding a pulse output operation to a timer mode
operation. In this mode, a pulse whose polarity is inverted at each overflow is output from the T0
(Timer 1 overflow signal/2) pin and the T1 (Timer 4 overflow signal/2) pin.
The operations in the pulse output mode are described below.
1
Start of count operation
After the count stop bit is set to “0,” a count operation starts. Each time a count source is input,
the contents of the timer are decremented by 1.
Note: Because the count stop bit is “0” immediately after reset release, the count operation is
automatically started immediately after reset release but no pulse is output.
2
3
Reload operation
When the timer overflows, the value resulting from decrementing 1 from the contents of the timer
latch is transferred (reloaded) to the timer.
Pulse is output
• A pulse whose polarity is inverted at each overflow is output from the T0 pin and the T1 pin.
• “H” or “L” can be selected as a level for a start of pulse output by each division flip-flop.
• A pulse output is started from the moment when the T0 or T1 pin output is selected by the Timer
12 mode register or the Timer 34 mode register.
4
5
Interrupt operation
2 Timer interrupt
When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set.
The acceptance of interrupt is controlled by the interrupt enable bit of each timer.
Stop of count operation
When “1” is set in the counter stop bit by software, the count operation stops. (The count operation
continues until “1” is set in the count stop bit.)
Figure 1.12.5 shows a example of pulse output mode operation.
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Count period
Count period T(s) = 1 ÷ count source frequency ✕ (the timer initial value + 1)
Pulse output mode operation example
• OF: Overflow
• RL: Reload
• n: Timer initial value
Writing “1”
Writing “0”
Timer 1 count stop bit
Timer 1 count
source
Count stop
RL
RL
RL
RL
Down count
(n-1)16
Count restart
OF
OF
OF
OF
FF16
Time
T
T
0
output selected
T0 pin
Setting to
output port
Initial value “0”
Timer FF register
bit 0
Timer 1 interrupt
request bit
A
A
A
A
Timer 1 interrupt
enable bit
A : • Clearing by writing “0” to the Timer 1 interrupt request bit.
• Clearing by accepting the Timer 1 interrupt request when the Timer 1 interrupt enable bit is “1.”
Fig. 1.12.5 Example of pulse output mode operation
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[Setting method]
1
The count operation of a timer to be used is stopped.
Refer to “Table 1.12.2 Setting for count stop.”
2
Set the pulse output mode according to the pulse output mode initial value setting shown in Table
1.12.10. However, set the timer FF register after setting timer mode register 2.
Table 1.12.10 Pulse output mode initial value setting
Setting item
Timer mode register 2
(TM2: Address 00FA16)
Timer FF mode register
(TF: Address 00F716)
b1
–
1
b0
1
–
b1
–
b0
Timer to be used
Select (Note)
–
Timer 1
Timer 4
Select (Note)
Note: 0: The initial value becomes “0.”
1: The initial value becomes “1.”
3
Set the pulse output mode according to the pulse output mode setting shown in Table 1.12.11.
The T0 output port and the T1 output port are used in common with P12 and P13, respectively.
Accordingly, set the bit 2 and bit 3 of the port P1 direction register to the output mode.
Table 1.12.11 Pulse output mode setting
Timer 12 mode register
(T12M: Address 00F816)
b3
Timer 34 mode register
(T34M: Address 00F916)
Timer
Output pin
b7
b6
T0
Timer 1
Timer 4
Timer 1 overflow
signal / 2
1
–
–
T1
Timer 4 overflow
signal / 2
1
0
4
5
Set a count value in Timer 1 (T0 output) and Timer 4 (T1 output).
When a value is set according to the count start setting shown in Table 1.12.8, the timer starts
to count.
Note: When resetting a value in the Timer FF register, be sure to observe the setting methods of
the above items 1 to 5 .
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(4) External pulse width measurement mode
The external pulse width measurement mode is used to measure a pulse width (“H” or “L”) input from
the CNTR0 or CNTR1 pin.
The operations in the external pulse width measuring mode are described below.
1
Start of count operation
After the count stop bit is cleared to “0,” a count operation starts. Each time a count source is
input, the contents of the timer are decremented by 1.
Note: Because the count stop bit is “0” immediately after reset release, the count operation is
automatically started after reset release but the count source is not a CNTR pin input.
At this time, the external pulse width measurement mode is not provided.
2
3
Reload operation
When the timer overflows, the value resulting from decrementing 1 from the contents of the timer
latch is transferred (reloaded) to the timer.
External pulse width measurement mode
● The “H” or “L” level of a pulse can be selected as a pulse measuring period by the Edge polarity
selection register.
● The difference between the initial value of the timer and the counter value at a count stop
becomes a measured pulse width.
● A reload operation by reading the count value is not performed automatically. To perform
measurement continuously, re-set the initial value by software.
4
Interrupt operation
2 Timer interrupt
When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to
“1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer.
2 CNTR interrupt
An interrupt request is generated from the edge of the pulse input from the CNTR0 pin or the
CNTR1 pin, so that the interrupt request bit is set to “1.” Interrupt acceptance is controlled by
the interrupt enable bit.
The pulse active edge and the CNTR0/CNTR1 interrupt are selected by the Edge polarity selection
register.
5
Stop of count operation
The count operation terminates at the falling edge (at “H” level pulse width measurement) or the
falling edge (“L” level pulse width measurement) of the CNTR pin input. This operation is also
terminated by setting "1" in the count stop bit by software.
Figure 1.12.6 shows an example of the operation of the external pulse width measurement mode.
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Pulse width
Pulse width H(s) = 1 ÷ count source frequency ✕ (the timer initial value - count value at count stop)
External pulse width measurement mode operation example
• n: Timer initial value
• m: Count value at count stop
Timer 4 count stop bit
Timer 4 count
source
CNTR0 pin
CNTR
edge selection bit
Setting the initial value
to timer
Setting the initial value
to timer
Count start
Count start
(n-1)16
Count stop
m
16
FF16
Time
H
H
CNTR interrupt
request bit
A
CNTR interrupt
enable bit
Timer 4 interrupt
request bit
Timer 4 interrupt
enable bit
A : • Clearing by writing “0” to the CNTR interrupt request bit.
• Clearing by accepting the CNTR interrupt request when the CNTR interrupt enable bit is “1.”
✽: When the CNTR edge selection bit is “0,” “H” level width of the input pulse is measured.
Fig. 1.12.6 Example of operation of external pulse width measurement mode
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[Setting method]
1
2
3
4
The count operation of Timer 4 is stopped by setting bit 3 of the Timer 34 mode register to “1.”
Refer to “Table 1.12.2 Setting for count stop.”
Set each register according to the external pulse width measuring mode setting shown in Table
1.12.12.
Set a value in the timer.
Refer to “Table 1.12.7 Address allocation of timer.”
Clear bit 3 of the Timer 34 mode register to "0" and start the count of timer 4.
Refer to “Table 1.12.8 Count start setting.”
Table 1.12.12 External pulse width measurement mode setting
Timer 34 mode register
(T34M: Address 00F816)
b5
Edge polarity selection register
(EG: Address 00D416)
Timer to
be used
Measuring
pulse
b6
1
b4
b4
b3
b2
Select
(Note 1)
b5 b4
CNTR0
CNTR1
0
–
0
0
1
1
0 : Timer 3 overflow signal
1 : f (XIN)/16 or f (XCIN)/16
0 : Timer 1 or Timer 2 overflow signal
1 : CNTR1 pin (Note 2)
Timer 4
Select
(Note 1)
–
1
Notes 1: 0: The count source is counted while the external pulse is “H.”
1: The count source is counted while the external pulse is “L.”
2: When the measured pulse is the CNTR1 pin, do not select the CNTR1 as the count source of
Timer 4.
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(5) PWM mode
In the PWM mode, a PWM waveform is output from the T1 pin by using Timer 3 and Timer 4.
The operations in the PWM mode are described below.
1
Start of count operation
After the count stop bit is cleared to “0,” a count operation starts. Each time a count source is
input, the contents of the timer are decremented by 1.
Note: The count stop bit is “0” immediately after reset release. Accordingly, a count operation is
automatically started immediately after reset release but no PWM waveform is output because
the PWM mode is not provided.
2
3
Reload operation
When the timer overflows, the value resulting from decrementing 1 from the contents of the timer
latch is transferred (reloaded) to the timer.
PWM output
In the PWM mode, the following operations are performed.
1
When the PWM mode is started
• The PWM waveform starts with “L.”
• Timer 3: Counts the count sources.
• Timer 4: Stops
2 When Timer 3 overflows
• The PWM waveform goes to “H.”
• Timer 3: Stops.
• Timer 4: Counts the count sources.
3
When Timer 4 overflows
• The PWM waveform goes to “L.”
• Timer 3: Counts the count sources.
• Timer 4: Stops.
The “L” width of the PWM waveform is set in Timer 3 and the “H” width is set in Timer 4.
4
Interrupt operation
2 Timer interrupt
When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to
“1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer.
5
Stop of count operation
When the counter stop bit is set to “1” by software, the count operation stops. (The count operation
continues until the count stop bit is set to “1.”)
Figure 1.12.7 shows an example of the operation of the PWM output mode.
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Count period
Timer 3 count period T3(s) = 1 ÷ timer 3 count source frequency ✕ (the timer 3 initial value + 1)
Timer 4 count period T4(s) = 1 ÷ timer 4 count source frequency ✕ (the timer 4 initial value + 1)
PWM mode operation example
• OF: Overflow
• RL: Reload
• n: Timer 3 initial value
• m: Timer 4 initial value
Timer 3 count
source
'
"
To B
To B
To B
RL
RL
RL
(Note)
(Note)
(n-1)16
FF16
OF
OF
OF
Time
T3
T3
“1” is written
“0” is written
Timer 4 count stop bit
Timer 4 count source
'
To C
To C
Count stop
Count restart
RL
RL
(Note)
(Note)
(m-1)16
OF
OF
FF16
PWM output
mode selected
Time
Setting to
output port
T4
T4
"
"
'
C
'
'
B
B
B
T1 pin
A
A
A
B
B
Timer 3 interrupt
request bit
Timer 3 interrupt
enable bit
A
A
'
C
C
Timer 4 interrupt
request bit
Timer 4 interrupt
enable bit
A : • Clearing by writing “0” to the Timer 3 and Timer 4 interrupt request bits.
• Clearing by accepting the interrupt request when the Timer 3 and Timer 4 interrupt enable bits are “1.”
Note: Timer 3 and Timer 4 do not accept count sources in the period from an overflow of the respective
timer till an overflow of the other timer. Because the timer read value changes at the fall of a count
source, the read value in this period remains “FF16”.
Fig.1.12.7 Example of operation of PWM output mode
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[Setting method]
1
2
3
The count operation of a timer to be used is stopped.
Refer to “Table 1.12.2 Setting for count stop.”
Port P13 is put into the output mode by setting bit 3 of the port P1 direction register (address
00C116) to “1.”
Select a count source of Timer 3 and Timer 4. However, don't select the Timer 3 overflow signal
as a count source of Timer 4.
Refer to “Table 1.12.5 Setting for Timer 3 count source” and “Table 1.12.6 Setting for Timer
4 count source.”
4
5
Set the bit 7 of the Timer 34 mode register to “1.”
Set a value in the timer.
Refer to “Table 1.12.7 Address allocation of timer.”
6
7
Set the bit 7 of the Timer mode register 2 to “1.”
The count operation of a timer to be used is started.
Refer to “Table 1.12.8 Count start setting.”
Note: When the PWM mode is started from another mode, the PWM waveform starts with the “L”
state.
1.12.3 Input latch function
There is a function which latches the levels of the INT0, INT1, CNTR0 and CNTR1 pins to the input latch
register when Timer 4 overflows. Using this function permits knowing the level of each pin accurately the
moment when a Timer 4 overflow occurs. The polarity of each pin is selected by the edge polarity
selection register, the level or the reverse level of each pin are latched to the Input latch register.
Table 1.12.13 shows the Edge polarity selection register setting related to the input latch.
Table 1.12.13 Edge polarity selection register setting
Edge polarity selection register
Input latch register
Latched contents
(EG: Address 00D416)
(ILR: Address 00D616)
b3
–
b2
b1
b0
1
0
INT0 pin level
Reverse level on INT0 pin
INT1 pin level
Reverse level on INT1 pin
CNTR0 pin level
Reverse level on CNTR0 pin
CNTR1 pin level
b0
b1
b2
b3
–
–
1
0
–
–
–
–
–
–
1
0
–
–
1
0
–
Reverse level on CNTR1 pin
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1.12.4 Updating of contents of Timer and Timer latch
After data is written to the Timer, the contents of the Timer and the Timer latch are updated.
2
Timer 1 and Timer 2
When data is written to the Timer, this data is set in the Timer and the Timer latch at the same time.
As a result, after data is written to the Timer which is in count operation, the count period becomes
invalid.
Figure 1.12.8 shows an example of updating of the contents of Timer 1, Time 2 and Timer latch.
Example of updating of Timer 1
• OF: Overflow
• RL: Reload
• n: Timer 1 initial value before updating
• m: Timer 1 initial value after updating
Writing “m16” to timer 1
RL
m16
(m-1)16
RL
RL
(n-1)16
OF
OF
OF
FF16
Time
Incorrect count period
Timer 1 interrupt
request bit
A
A
A
Timer 1 interrupt
enable bit
• Clearing by writing “0” to the Timer 1 interrupt request bit.
A :
• Clearing by accepting the Timer 1 interrupt request when the Timer 1 interrupt enable bit is “1.”
Fig. 1.12.8 Example of updating of Timer 1, Timer 2 and Timer latch
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2 Timer 3 and Timer 4
● At PWM mode
After data is written to the Timer which is in count operation, the written data is set only in the
Timer latch but not in the Timer. After that, when the Timer overflows, a value resulting from
decrementing 1 from the value of the Timer latch is written in the Timer.
When data is written to the Timer being at a stop, the written data is set in both Timer and Timer
latch.
● In modes other than the PWM mode
The same operation as “Timer 1 and Timer 2” described in the previous item is performed.
Figure 1.12.9 shows an example of updating of the contents of Timer 3, Time 4 and Timer latch in
PWM mode.
Example of updating of Timer at PWM mode
• OF: Overflow
• RL: Reload
• n: Timer 3 initial value before updating
• m: Timer 3 initial value after updating
• k: Timer 4 initial value before updating
• h: Timer 4 initial value after updaiting
Writing “m16” to timer 3
RL
m16
(m-1)16
RL
(n-1)16
OF
OF
FF16
Time
Count of timer 3
Count of timer 3 by rewriting timer value
RL
Writing “h16” to timer 4
(h-1)16
(k-1)16
RL
OF
OF
FF16
Time
Count of timer 4 by rewriting timer value
Count of timer 4
Timer 3
Timer 4
interrupt request bit
Timer 4
interrupt
Timer 3
interrupt
Timer 3
interrupt
A
A
A
Timer 3
Timer 4
interrupt enable bit
A :
• Clearing by writing “0” to the Timer 3 or Timer 4 interrupt request bit.
• Clearing by accepting the Timer 3 and the Timer 4 interrupt request when the Timer 3
and the Timer 4 interrupt enable bit is “1.”
Fig. 1.12.9 Example of updating of Timer 3, Timer 4 and Timer latch in PWM mode
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1.12.5 Notes on use
(1) The contents of the Timer 12 mode register (T12M: Address 00F816) and the Timer 34 mode register
(T34M: Address 00F916) become “0016” at reset and each timer performs a count operation.
(2) Figure 1.12.10 shows the relation between Timer value change timing and read value change timing.
The Timer value changes at the rise of the count source, while the read value changes at the fall of
the count source. Accordingly, the read value may be larger than the real timer value by “1.”
Example: Writing “9916” into Timer 1
Timer count source
Timer value
Timer read value
0116
0016
FF16
9816
9716
0216
0116
0016
FF16
9816
9716
Interrupt request bit
Fig. 1.12.10 Relation between timer value change timing and read value change timing
(3) To select the CNTR pin input as Timer count source, the frequency of the CNTR count source should
satisfy the condition shown in Table 1.12.14.
Table 1.12.14 Frequency of CNTR
Frequency of the CNTR count source
Main clock
Upper boundary
1MHz
Lower boundary
There is no
special restriction.
4MHz
8MHz
2MHz
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1.12.6 Related registers
(1) Timer 1, Timer 2, Timer 3, Timer 4 (T1 to T4: Address 00F016 to 00F316)
Each Timer is a register consisting of 8 bits.
Read
The contents (count value) of the Timer are read by reading the timer.
Write
When data is written to the Timer, this data is set in the Timer and the Timer latch at the same
time.
When data is written into the Timer being in count operation in the PWM mode, the written data
is set only in the Timer latch.
Refer to “1.12.4 Updating of contents of Timer and Timer latch.”
✽Timer latch
The Timer latch is a register that holds a value to be automatically transferred (reloaded) to the
Timer as its initial value when the Timer overflows. It is impossible to read the contents of the
Timer latch.
Figure 1.12.11 shows a structure of Timer.
Timers 1 to 4
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1, Timer 2, Timer 3, Timer 4 (T1, T2, T3, T4)
[Address 00F016, 00F116, 00F216, 00F316]
At reset
B
Function
R W
0
to
7
(Note)
•Set “0016 to FF16.”
•The value is decremented by 1 each time a
count source is input.
•Each Timer values are set to the respective
counter.
•The count values are read out by reading the
respective timer.
Note : Timers 1 and 2 are undefined.
Timer 3 is “FF16.”
Timer 4 is “0716.”
Fig. 1.12.11 Structure of Timers 1 to 4
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(2) Timer 12 mode register (T12M: Address 00F816)
The Timer 12 mode register is a register consisting of bits that control a Timer count source and a
count operation.
Figure 1.12.12 shows a structure of Timer 12 mode register.
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register (T12M) [Address 00F816]
B
0
Name
At reset
Function
0 : Count start
1 : Count stop
R
W
Timer 1 count stop
bit
0
0 : Internal clock
1 : P32/CNTR0 external clock
(Note 1)
1
2
Timer 1 count
source selection bit
0
0
Timer 1 internal clock 0 : f(XIN)/16 or f(XCIN)/16
source selection bit
1 : f(XCIN
)
(Note 2)
0 : P12 port output
1 : T0(Timer 1 overflow
divided by 2)
3
P12/T0 port output
selection bit
0
0 : Count start
1 : Count stop
Timer 2 count stop
bit
4
5
0
0
0 : Internal clock (Note 1)
1 : Timer 1 overflow signal
b7 b6
Timer 2 count
source selection bit
Timer 2 internal clock
source selection bits
6, 7
0 0 : f(XIN)/16 or f(XCIN)/16
0 1 : f(XIN)/64 or f(XCIN)/64
1 0 : f(XIN)/128 or f(XCIN)/128
1 1 : f(XIN)/256 or f(XCIN)/256
(Note 3)
0
Notes 1: In the 7470/7477 group, the internal clock is f(XIN)/16.
2: Since the 7470/7477 group is not provided the sub-clock
generating circuit, f(XCIN) cannot be used. Fix this bit to “0.”
3: Since the 7470/7477 group is not provided the sub-clock
generating circuit, f(XCIN) cannot be used.
Fig. 1.12.12 Structure of Timer 12 mode register
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(3) Timer 34 mode register (T34M: Address 00F916)
The Timer 34 mode register is a register consisting of bits that control a timer count source and a
count operation.
Figure 1.12.13 shows a structure of Timer 34 mode register.
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
00F916]
Timer 34 mode register (T34M) [Address
B
0
Name
At reset
Function
R
W
Timer 3 count stop
bit
0 : Count start
1 : Count stop
b2 b1
0
1, 2
Timer 3 count
source selection bits
0 0 : f(XIN)/16 or f(XCIN)/16
0 1 : f(XCIN
)
1 0 : Timer 1 overflow or
Timer 2 overflow
0
1 1 : P3
3
/CNTR
1
external
(Note 2)
clock
3
Timer 4 count stop
bit
0 : Count start
1 : Count stop
0
0
b4 b3
Timer 4 count
source selection bits
4, 5
0 0 : Timer 3 overflow
0 1 : f(XIN)/16 or f(XCIN)/16
1 0 : Timer 1 overflow or
Timer 2 overflow
1 1 : P3
3/CNTR
1
external
clock
(Notes 1, 2)
Timer 4 pulse width
measurement mode
selection bit
6
7
0 : Timer mode
1 : External pulse width
measurement mode
0
0
P13/T1 port output
selection bit
0 : P1
1 : (Timer 4 overflow divided
by 2 or PWM output)
3 port
T
1
Notes 1: When Timer 1 overflow is selected as a Timer 2
count source, the Timer 4 count source is the Timer 1
overflow regardless of the value of bit 6 of the
Timer mode register 2.
2: Since the 7470/7477 group is not provided the sub-clock
generating circuit, f(XCIN) cannot be used.
Fig. 1.12.13 Structure of Timer 34 mode register
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(4) Timer mode register 2 (TM2: Address 00FA16)
The Timer mode register 2 consists of bits that control a mode selection and a count source selection.
Figure 1.12.14 shows a structure of Timer mode register 2.
Timer mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 2 (TM2) [Address 00FA16]
B
0
Name
R
?
W
Function
At reset
Timer 1 overflow FF
set enable bit
Timer 4 overflow FF
set enable bit
0 : Set disable
1 : Set enable
0
0 : Set disable
1 : Set enable
1
0
?
Nothing is allocated for these bits. These are
write disabled bits and are undefined at reading.
2
to
5
✕
Timer 3, timer 4 count
overflow signal selection bit
0 : Timer 1 overflow
1 : Timer 2 overflow
0 : Ordinary mode
1 : PWM mode
6
7
0
0
Timer 3, timer 4
function selection bit
Fig. 1.12.14 Structure of Timer mode register 2
(5) Timer FF register (TF: Address 00F716)
The Timer FF register consists of bits that are used for initialization in the pulse output mode.
Figure 1.12.15 shows a structure of Timer FF register.
Timer FF register
b7 b6 b5 b4 b3 b2 b1 b0
00F716]
Timer FF register (TF) [Address
At reset
B
Name
Timer 1
division flip-flop
Function
R
W
0 : Initial value is “0”
1 : Initial value is “1”
0
0
0 : Initial value is “0”
1 : Initial value is “1”
Timer 4
division flip-flop
1
0
?
2
to
7
Nothing is allocated for these bits. These are
write disabled bits and are undefined at
reading.
? ✕
Fig. 1.12.15 Structure of Timer FF register
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(6) Input latch register (ILR: Address 00D616)
The Input latch register consists of bits that latch the levels of the INT0, INT1, CNTR0 and CNTR1
pins when the Timer 4 overflows.
Figure 1.12.16 shows a structure of Input latch register.
Input latch register
b7 b6 b5 b4 b3 b2 b1b0
Input latch register (ILR) [Address 00D616]
At reset
B
0
Name
Function
R W
When b0 of EG (Note) is “0”:
reverse level on INT0 pin
P30/INT0 latch bit
?
?
✕
When b0 of EG (Note) is “1”:
level on INT0 pin
1
2
3
When b1 of EG (Note) is “0”:
reverse level on INT1 pin
P31/INT1 latch bit
P32/CNTR0 latch bit
P33/CNTR1 latch bit
✕
✕
When b1 of EG (Note) is “1”:
level on INT1 pin
When b2 of EG (Note) is “0”:
reverse level on CNTR0 pin
?
When b2 of EG (Note) is “1”:
level on CNTR0 pin
When b3 of EG (Note) is “0”:
reverse level on CNTR1 pin
?
?
✕
When b3 of EG (Note) is “1”:
level on CNTR1 pin
Nothing is allocated for these bits. These
are write disabled bits and are undefined at
reading.
4
to
7
? ✕
Note: EG is the Edge polarity selection register.
Fig. 1.12.16 Structure of Input latch register
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(7) Edge polarity selection register (EG: Address 00D416)
The Edge polarity selection register consists of bits that control a polarity selection of each of the
INT0, INT1, CNTR0 and CNTR1 pins and an INT1 interrupt or key on wake-up interrupt selection at
stop mode or wait mode.
Figure 1.12.17 shows a structure of Edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416]
At reset
Name
Function
R
W
B
0
INT0 edge selection
bit
0 : Falling edge
1 : Rising edge
0
0 : Falling edge
1 : Rising edge
1
2
3
4
5
INT1 edge selection
bit
0
0
0 : Falling edge
1 : Rising edge
0 : Falling edge
1 : Rising edge
CNTR0 edge
selection bit
CNTR1 edge
selection bit
0
0
0 : CNTR0
1 : CNTR1
CNTR0/CNTR1
interrupt selection bit
INT1 source selection 0 : P31/INT1
bit (at STP or WIT 1 : P0 to P07 “L” level input
0
0
?
instruction execution) (for key-on wake-up)
Nothing is allocated for these bits. These are
write disabled bits and are undefined at reading.
6, 7
?
✕
Fig. 1.12.17 Structure of Edge polarity selection register
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1.13 Serial I/O
1.13 Serial I/O
The 7470/7471/7477/7478 group can transmit or receive 8-bit data in series by Serial I/O.
The Serial I/O transmit/receive method is shown below.
●In the 7470/7471 group, only the clock synchronous is available.
●In the 7477/7478 group, either clock synchronous or clock asynchronous (UART) can be selected.
There are differences in circuit configuration and applicable registers between them.
This section explains each of them as “1.13A 7470/7471 group part” and “1.13B 7477/7478 group part.”
Table 1.13.1 shows defferences between 7470/7471 group and 7477/7478 group.
Table 1.13.1 7470/7471 group vs. 7477/7478 group serial I/O
7470/7471 group
7477/7478 group
Serial I/O transmit/ Clock synchronous
Ț
҂
Ț
Ț
Ț
Ț
Ț
Ț
҂
҂
receive method
SRDY signal output✽
Clock asynchronous
1
1
SARDY signal output✽
2
Byte specification mode✽
✽1 SRDY and SARDY signal : Signal that indicates a Serial I/O transfer ready state
✽2 Byte specification mode : Mode for transmitting or receiving 1-byte data of a specific cycle out of
multiple-byte data to be transmitted or received.
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1.13 Serial I/O
1.13A 7470/7471 group part
1.13A.1 Operation description
The 7470/7471 group incorporates a clock synchronous Serial I/O.
The 8 shift clocks obtained by the clock control circuit are used as synchronous clocks for transmitting
or receiving data. The transmit operation of the transmit side and the receive operation of the receive side
are simultaneously executed in synchronization with these shift clocks.
●The transmit side transmits data bit by bit from the P15/SOUT pin in synchronization with the fall of each
shift clock.
●The receive side receives data bit by bit from the P14/SIN pin in synchronization with the rise of each shift
clock.
Figure 1.13A.1 shows a Serial I/O block diagram.
X
CIN
1/2
Counter
1/4
X
IN
1/2
CM
7
1/2 1/4
1/64
SM
1
0
SARDY
SM
SM
2
SRDY
Synchronous circuit
SM
5
S
RDY
CLK input
(Address 00DE16
)
CLK output
Serial I/O counter (3)
Serial I/O interrupt
request
SM
6
Byte counter (4)
Data bus
(Address 00DE16
)
(Address 00DD16
)
S
IN
Serial I/O register (8)
S
OUT
S
R
Q
✽:
The 7470 group is not provided with the XCIN pin.
Fig. 1.13A.1 Serial I/O block diagram
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1.13 Serial I/O
2
2
Communication format
The half-duplex data communication or the full-duplex data communication are available.
Synchronous clock
The internal clock or the external clock can be selected as a synchronous clock by bit 2 of the Serial
I/O mode register (SM: address 00DC16).
●The synchronous clock for the case where the internal clock is selected is shown below.
• f(XIN)/8
• f(XIN)/16
• f(XIN)/32
When the system clock is f(XIN)
• f(XIN)/512
• f(XCIN)/8
• f(XCIN)/16
• f(XCIN)/32
When the system clock is f(XCIN)
• f(XCIN)/512
Notes 1: In the 7470 group, f(XCIN) is not available.
2: When selecting a divided signal of f(XCIN), set the system clock to the low-speed mode
by bit 7 of the CPU mode register.
●When the external clock is selected, the synchronous clock is an external clock input from the P16/
CLK pin.
Notes on external clock selection
●When writing data into the Serial I/O register, perform a write operation while the synchronous
clock is at “H.”
●The shift operation of the Serial I/O register is continued while the synchronous clock is input to
the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end
of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically.)
●Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL
[s] > 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock
of 2 MHz or less (duty ratio 50 %).
2
2
Shift clock
Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer
selects the internal clock and outputs the 8 shift clock pulses generated by a start of transfer
operation from the P16/CLK pin. The other microcomputer selects the external clock and uses the
clock input from the CLK pin as a synchronous clock.
SRDY signal, SARDY signal
A Serial I/O transfer ready status can be known to the outside by outputting the SRDY signal and the
SARDY signal.
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1.13 Serial I/O
2
Transmit operation of Serial I/O
The transmit operation of the Serial I/O is described below.
●Start of transmit operation
Transmit operation begins by writing transmit data into the Serial I/O register✽2 in the transmit
enable state.✽1 At the time when this data has been written, “7” is set in the Serial I/O counter
(address 00DE16, bit 4 – 6), so that the synchronous clock is forced to go to “H.”
✽1: State in which the register for transmit operation has been initialized. Refer to “[Transmit
setting method]” which will be described later.
✽2: When the external clock is selected, perform a write operation while the synchronous clock is
at “H.”
●Transmit operation
1 The transmit data written in the Serial I/O register is output from the P15/SOUT pin in synchronization
with the fall of the synchronous clock. At this time, the Serial I/O counter is decremented by 1.
2 Transmit data is output starting with the least significant bit of the Serial I/O register. Each time
one bit is output, the contents of the Serial I/O register are shifted by 1 in the direction of the
least significant bit.
3 After the transmit shift operation is completed, an interrupt request occurs at the rise of the last
cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set✽3 to “1.”
✽3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial
I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter
overflows). When the external clock is selected, the contents of the Serial I/O register are
continuously sifted while the synchronous clock is input. Accordingly, stop it externally.
●When using the SRDY output
At the time when transmit data has been written, the level of the SRDY signal changes from “H” to
“L” and the level of the SARDY signal changes from “L” to “H,” by which a receive ready state can
be known externally. The SRDY signal goes to “H” at the first fall of the synchronous clock and the
SARDY signal goes to “L” at the rise of the last cycle of the synchronous clock.
Figure 1.13A.2 shows a transmit operation and Figure 1.13A.3 shows a transmit timing chart.
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1.13 Serial I/O
1
Synchronous clock
Data bus
Address 00DD16
Serial I/O register
Synchronous clock
b0
Write transmit data
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
Serial I/O register
P15/SOUT
2
b0
4 D
D
2
3
D7D6D5D
Transmit shift register
P15/SOUT
Synchronous clock
3
b0
D
7
0
1
Interrupt request
register 1
(Address 00FC16
by rising edge
)
b6
Fig. 1.13A.2 Serial I/O transmit operation
Synchronous clock,
internal clock divided by 8 to 512, or
external clock
S
OUT pin
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Write signal to
serial I/O register
S
RDY signal
SARDY signal
Serial I/O interrupt enable bit
Serial I/O interrupt request bit
A
A :
• Clearing by writing “0” to the Serial I/O interrupt request bit.
• Clearing by accepting the Serial I/O interrupt.
Fig. 1.13A.3 Serial I/O transmit timing chart
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1.13 Serial I/O
[Transmit setting method]
1 Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to “0.”
2 Set the Serial I/O mode register according to “Table 1.13A.1.”
3 When using the Serial I/O interrupt,
[1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to “0.”
[2] Set the Serial I/O interrupt enable bit to “1.”
4 Write transmit data into the Serial I/O register (address 00DD16).
Note: When the external clock is selected, perform a write operation while the synchronous clock is
at “H.”
Table 1.13A.1 shows a Serial I/O transmit setting.
Table 1.13A.1 Serial I/O transmit setting
Serial I/O mode register
(SM: Address 00DC16)
Register to be used
Item
Bit
Setting value
00
f(XIN)/8
f(XCIN)/8
f(XIN)/16
f(XCIN)/16
f(XIN)/32
f(XCIN)/32
f(XIN)/512
01
10
11
Synchronous clock (at internal
b1 • b0
clock selection)
(Note 1)
f(XCIN)/512
External clock
Internal clock
Serial I/O port (SOUT, CLK) (Note 2)
Ordinary port
SRDY signal output
SRDY signal
0
1
1
0
1
0
1
0
1
0
1
Synchronous clock selection
Serial I/O port using
b2
b3
b4
SRDY signal output selection
SRDY signal selection
Serial I/O
b5
b6
b7
SARDY signal
Ordinary mode
Byte specification mode selection Byte specification mode
P15/SOUT, SRDY pin output
CMOS output
N channel open drain output
format
(Note 3)
Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group,
however, f(XCIN) is not available.
●When a divided signal of f(XIN) is selected, the system clock is f(XIN).
●When a divided signal of f(XCIN) is selected, the system clock is f(XCIN).
Select a system clock state by bit 7 of the CPU mode register.
2: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit
may be set to “1.” Clear the Serial I/O interrupt request bit to “0” after one instruction or more
after switching the ordinary port over to the Serial I/O port.
3: When ordinary P17 is selected by bit 4 of the Serial I/O mode register, the CMOS output is
provided regardless of the set value of bit 7.
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1.13 Serial I/O
2
Receive operation of Serial I/O
The receive operation of the Serial I/O is described below.
●Start of receive operation
Receive operation begins by writing the following data into the Serial I/O register (SIO: address
2
✽
1
✽
00DD16) in the receive enable state.
Transmit data in the full-duplex data communication
•
• Arbitrary dummy data in the half-duplex data communication
At the time when this data has been written, “7” is set in the Serial I/O counter (address 00DE16,
bit 4 – 6), so that the synchronous clock is forced to go to “H.”
✽1: State in which the register for receive operation has been initialized. Refer to “[Receive setting
method]” which will be described later.
✽2: When the external clock is selected, perform a write operation while the synchronous clock is
at “H.”
●Receive operation
1 Receive data is input from the P14/SIN pin to the Serial I/O register in synchronization with the
rise of the synchronous clock. At this time, the Serial I/O counter is decremented by 1.
2 Receive data is input starting into the most significant bit of the Serial I/O register. Each time one
bit is input, the contents of the Serial I/O register are shifted by 1 in the direction of the least
significant bit.
3 After the receive shift operation is completed, an interrupt request occurs at the rise of the last
cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set to “1”.✽3
✽3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial
I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter overflows).
When the external clock is selected, the contents of the Serial I/O register are continuously
sifted while the synchronous clock is input. Accordingly, stop it externally.
●When using the SRDY output
At the time when data has been written into the Serial I/O register, the level of the SRDY signal
changes from “H” to “L” and the level of the SARDY signal changes from “L” to “H,” by which a
receive ready state can be known externally. The SRDY signal goes to “H” at the first fall of the
synchronous clock and the SARDY signal goes to “L” at the rise of the last cycle of the synchronous
clock.
Figure 1.13A.4 shows a receive operation and Figure 1.13A.5 shows a receive timing chart.
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1.13 Serial I/O
Synchronous
clock
1
Synchronous clock
3
b0
b0
Serial I/O
register
D0
D7 D6D5 D4 D3D2 D1D0
P14/SIN
Serial I/O register
Synchronous
clock
0
2
Interrupt request
register 1
by rising edge
(Address 00FC16)
1
b6
D3 D2 D1D0
Serial I/O register
P14/SIN
Fig. 1.13A.4 Serial I/O receive operation
Synchronous clock,
internal clock divided by 8 to 512, or
external clock
SIN pin
D0
D1
D2
D3
D4
D5
D6
D7
Writing data to
Serial I/O register
Reading into Serial I/O register
SRDY signal
SARDY signal
Serial I/O interrupt enable bit
Serial I/O interrupt request bit
A
A :
• Clearing by writing “0” to the Serial I/O interrupt request bit.
• Clearing by accepting the Serial I/O interrupt.
Fig. 1.13A.5 Serial I/O receive timing chart
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1.13 Serial I/O
[Receive setting method]
1 Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to “0.”
2 Clear the Port P14 direction register to “0” to set it to the input mode.
3 Clear the Serial I/O mode register according to “Table 1.13A.2.”
4 When using the Serial I/O interrupt,
[1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to “0.”
[2] Set the Serial I/O interrupt enable bit to “1.”
5 Write the following data into the Serial I/O register.
•
•
Transmit data in the full-duplex data communication
Arbitrary dummy data in the half-duplex data communication
Note: When the external clock is selected, write data into the Serial I/O register while the synchronous
clock is at “H.”
Table 1.13A.2 shows a Serial I/O receive setting.
Table 1.13A.2 Serial I/O receive setting
Serial I/O mode register
(SM: Address 00DC16)
Register to be used
Item
Bit
Setting value
00
f(XIN)/8
f(XCIN)/8
f(XIN)/16
f(XCIN)/16
f(XIN)/32
f(XCIN)/32
f(XIN)/512
01
10
11
Synchronous clock (at internal
b1 • b0
clock selection)
(Note 1)
f(XCIN)/512
0
1
0
1
0
1
0
1
0
1
0
1
External clock
Internal clock
b2
b3
b4
b5
b6
b7
Synchronous clock selection
Serial I/O port using
Ordinary port (P15, P16) (Note 2)
Serial I/O port (SOUT, CLK) (Note 3)
Ordinary port
SRDY signal output
SRDY signal
SRDY signal output selection
SRDY signal selection
Serial I/O
SARDY signal
Ordinary mode
Byte specification mode selection Byte specification mode
P15/SOUT, SRDY pin output
CMOS output
N channel open drain output
format
(Note 4, Note 5)
Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group,
however, f(XCIN) is not available.
●When a divided signal of f(XIN) is selected, the system clock is f(XIN).
●When a divided signal of f(XCIN) is selected, the system clock is f(XCIN).
Select a system clock state by bit 7 of the CPU mode register.
2: When the external clock is selected, the P16/CLK pin becomes clock input pin CLK regardless
of the set value of bit 3 of the Serial I/O mode register. For this reason, only P15 is available
as an ordinary port.
3: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit
may be set to “1.” Clear the Serial I/O interrupt request bit to “0” after one instruction or more
after switching the ordinary port over to the Serial I/O port.
4: When ordinary P17 is selected by bit 4 of the Serial I/O mode register, the CMOS output is
provided regardless of the set value of bit 7.
5: When SOUT is selected by bit 3 of the Serial I/O mode register, the data written in the Serial
I/O register is output from the SOUT pin in synchronization with the fall of the synchronous clock.
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1.13 Serial I/O
1.13A.2 Byte specification mode
The Serial I/O of the 7470/7471 group has the byte specification mode.
This mode permits transmitting or receiving specific one-byte data out of multiple-byte data transmitted
or received through the Serial I/O bus.
2
Byte counter (Address 00DE16)
The Byte counter is located at the same address as that of the Serial I/O counter but the Serial
I/O counter is a read-only type. So this counter is not affected by any write operation to the Byte
counter. Because the Byte counter is not provided with a reload function, re-set a value to transmit
or receive data continuously.
2
2
SARDY
When the SARDY signal is selected in the byte specification mode, the N channel open drain is
selected as its output type, and the SRDY pins of multiple microcomputers are connected, the SARDY
signal goes to “H” only when all the microcomputers have become ready for data transfer.
Operations in the byte specification mode
After setting the Serial I/O mode register, specify a byte corresponding to the clock to be used for
a Serial I/O transmit/receive in the Byte counter. Where the value written in the Byte counter is n,
a Serial I/O transmit/receive is performed by the clock of the (n + 1)-th byte.
●Start of transmit/receive operation
A transfer operation is started by writing the data (arbitrary dummy data in the half-duplex data
communication)✽1 to be transmitted to the Serial I/O register.
✽1: When the external clock is selected, write data into the Serial I/O register when the synchronous
clock is at “H.” However, if the Byte counter value is a value other than “0,” writing data is
enabled even if the synchronous clock is at “L.”
●Transmit/receive operation
1
Each time the synchronous clock is input in 8 cycles, the Byte counter value is decremented by 1.
2 With the synchronous clock of the next 8 cycles after the Byte counter value becomes “0,” a
Serial I/O transmit/receive is performed as in the ordinary mode.✽2 After completion of the 8-bit
data output, an interrupt occurs at the rise of the last cycle of the synchronous clock, so that bit
6 of the Interrupt request register (address 00FC16) is set to “1.”
3 When the Byte counter overflows, the Serial I/O transfer stops.
✽2: When the Byte counter value is a value other than 0, the output of the SOUT pin goes to “H”
at the fall of the first synchronous clock. If the N channel open drain is selected as the output
type of the SOUT pin, the output is put into a high-impedance state, so the SOUT pin can be
connected to the SOUT pin of another microcomputer.
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1.13 Serial I/O
Figure 1.13A.6 shows a transmit/receive operation in the byte specification mode.
1
Byte counter
n
16
(n-1)16
0
2
When transmit
When receive
Synchronous
clock
Synchronous
clock
b0
b0
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
D
0
7
P14/SIN
Serial I/O register
P15/SOUT
Serial I/O register
Synchronous clock
8 cycles
Synchronous clock
b0
D7D6D5 D4 D3D2 D1D0
0
Interrupt request
register 1
by rising edge
(Address 00FC16
)
1
b6
3
Byte counter
FF16
Fig. 1.13A.6 Transmit/receive operation in byte specification mode
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1.13 Serial I/O
[Byte specification mode setting]
For a Serial I/O transfer in the byte specification mode, refer to the setting method in the ordinary
mode in “1.13A.1 Operation description,” and also take the following into consideration.
●Select the byte specification mode. (Set bit 6 of the Serial I/O register to “1.”)
●Be sure to select the external clock as the synchronous clock. (Clear bit 2 of the Serial I/O mode
register to “0.”)
[1] When data is received, the ordinary port can be selected by the Serial I/O port selection bit
(bit 3 of the Serial I/O mode register). P16 pin is used as a external clock input pin CLK. Only
P15 is available as an ordinary port.
[2] Write data into the Serial I/O register when the synchronous clock is at “H.” However, if the
Byte counter value is a value other than “0,” writing data is enabled even if the synchronous
clock is at “L.”
●When performing a Serial I/O transmit/receive at the n–th byte, write (n – 1) in the Byte counter.
Note: Because the Byte counter is not provided with a reload function, re-set a value to transmit or
receive data continuously.
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1.13 Serial I/O
1.13A.3 Pins
The 7470/7471 group uses 4 pins for data transmit, data receive, shift clock transmit/receive and receive
ready signal output. All these pins are used in common with P1. A function selection is made by the Serial
I/O port selection bit (bit 3) and the SRDY signal output selection bit (bit 4) of the Serial I/O mode register
(SM : Address 00DC16).
The function of each pin is explained below.
(1) Data transmit pin [SOUT]
Transmit data is output bit by bit. This pin is used in common with P15. When the Serial I/O port
selection bit (bit 3) of the Serial I/O mode register is set to “1,” this pin becomes a Serial I/O data
output pin.
(2) Data receive pin [SIN]
Data is input bit by bit. This pin is used in common with P14. When the port P14 direction register
is put into the input mode, this pin becomes a Serial I/O data input pin.
(3) Shift clock transmit/receive pin [CLK]
This pin inputs (receives from the outside) or outputs (supplies to the outside) the shift clock for data
transmit/receive. This pin is used in common with P16.
The internal clock or the external clock can be selected by bit 2 of the Serial I/O mode register.
(4) Receive enable signal output pins [SRDY], [SARDY]
This pin informs the outside of a receive ready state. This pin is used in common with P17.
●SRDY signal
• SRDY signal output selection bit (bit 4) of Serial I/O mode register is set to “1.”
• SRDY signal selection bit (bit 5) of Serial I/O mode register is cleared to “0.”
When the above 2 conditions are satisfied, the level of the pin changes from “H” to “L” at the timing
at which data is written into the Serial I/O register, informing the outside of a receive ready state.
●SARDY signal
• SRDY signal output selection bit (bit 4) of Serial I/O mode register is set to “1.”
• SRDY signal selection bit (bit 5) of Serial I/O mode register is set to “1.”
When the above 2 conditions are satisfied, the level of the pin changes from “L” to “H” at the timing
at which data is written into the Serial I/O register, informing the outside of a receive ready state.
1.13A.4 Notes on use
When the external clock is selected, take the following points into consideration.
1 When writing data into the Serial I/O register, perform a write operation while the synchronous clock
is at “H.”
2 The shift operation of the Serial I/O register is continued while the synchronous clock is input to the
Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8
cycles. (When the internal clock is selected, the synchronous clock stops automatically at the end of
8 cycles.)
3 Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s]
> 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock of 2
MHz or less (duty ratio 50 %).
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1.13 Serial I/O
1.13A.5 Related registers
(1) Serial I/O register (SIO: Address 00DD16)
The Serial I/O register is written Serial I/O transmit data or is read receive data.
●When transmitting data, write transmit data into this register.
●Receive data can be obtained by reading this register.
Figure 1.13A.7 shows a structure of the Serial I/O register.
Serial I/O register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O register (SIO) [Address 00DD16]
At reset
B
Function
R
W
0
to
7
A value of “0016” to “FF16” can be
set as transmit data.
At the transmit, data is transmitted one
bit at a time starting with the least
significant bit.
At the receive, data is received one bit
at a time starting with the most
significant bit.
At transmit:
At receive:
?
Fig. 1.13A.7 Structure of Serial I/O register
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1.13 Serial I/O
(2) Serial I/O counter, Byte counter (Address 00DE16)
The Serial I/O counter and the Byte counter are located at the same address.
●Serial I/O counter (bit 4 – bit 6)
The Serial I/O counter is set to “7” by writing transmit data into the Serial I/O register and counts
the synchronous clock of the Serial I/O eight times. The Serial I/O counter is a read-only type and
not affected by any write operation to the Byte counter.
●Byte counter (bit 0 – bit 3)
In the Serial I/O byte specification mode, the value written in the Byte counter is counted down at
8 cycles of the synchronous clock. When the value becomes “0,” a Serial I/O transmit/receive is
performed by the synchronous clock of the next 8 cycles. Because a reload function is not available,
re-set a value to transfer data continuously in the byte specification mode.
Figure 1.13A.8 shows a structure of the Serial I/O counter and the Byte counter.
Serial I/O counter and Byte counter (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O counter and Byte counter [Address 00DE16]
At reset
B
Function
R W
0
to
3
Byte counter
When using the byte specification mode, set
a value of “0016” to “0F16.” Supposing that the
value to be written into the byte counter is “n,”
a Serial I/O transmit/receive is performed with
the clock of the “n + 1”-th byte.
?
4
to
6
Serial I/O counter
When the internal clock is selected as a
synchronous clock, this counter generates 8
shift clocks.
When transmit data is written into the Serial
I/O register, “0716” is set in the Serial I/O
counter.
?
?
✕
7
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
? ✕
Fig. 1.13A.8 Structure of Serial I/O counter and Byte counter
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1.13 Serial I/O
(3) Serial I/O mode register (SM: Address 00DC16)
The Serial I/O mode register selects a state of the clock or port to be used for a data transfer.
Figure 1.13A.9 shows a structure of the Serial I/O mode register.
Serial I/O mode register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O mode register (SM) [Address 00DC16]
At reset
R W
B
Name
Function
b1 b0
Internal clock
selection bits
0, 1
0 0 : f(XIN)/8 or f(XCIN)/8
0 1 : f(XIN)/16 or f(XCIN)/16
1 0 : f(XIN)/32 or f(XCIN)/32
1 1 : f(XIN)/512 or f(XCIN)/512
(Note)
0
Synchronous clock 0 : External clock
2
3
0
0
selection bit
1 : Internal clock
0 : Ordinary I/O port
(P15, P16)
Serial I/O port
selection bit
1 : Serial I/O port (SOUT, CLK pin)
0 : Ordinary I/O port(P17)
1 : SRDY signal output pin
SRDY signal output
selection bit
4
5
6
7
0
SRDY signal
selection bit
0 : SRDY signal
1 : SARDY signal
0
0
Serial I/O byte specify
mode selection bit
0 : Ordinary mode
1 : Byte specify mode
P1
5/SOUT, SRDY output 0 : CMOS output
0
structure selection bit
1 : N-channel open-drain
output
Note: Since the 7470 group is not provided with the sub-clock
generating circuit, do not select f(XCIN).
Fig. 1.13A.9 Structure of Serial I/O mode register
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1.13 Serial I/O
1.13B 7477/7478 group part
1.13B.1 Operation description
The 7477/7478 group incorporates a Serial I/O that permits selecting one of the clock synchronous and
the clock asynchronous. This section describes the operation in each of the clock synchronous serial I/
O and the clock asynchronous Serial I/O (UART).
(1) Clock synchronous Serial I/O
In the clock synchronous Serial I/O, the 8 shift clocks obtained by the clock control circuit are used
as synchronous clocks for transmitting or receiving. The transmit operation of the transmit side and
the receive operation of the receive side are simultaneously executed in synchronization with these
shift clocks.
●The transmit side transmits data bit by bit from the P15/TxD pin in synchronization with the fall of
each shift clock.
●The receive side receives data bit by bit from the P14/RxD pin in synchronization with the rise of
each shift clock.
Figure 1.13B.1 shows a clock synchronous Serial I/O block diagram.
Data bus
Address 00E216
Serial I/O control register
P1
6
P1
4
Address 00E016
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
RXD
Receive shift register
Shift clock
Receive
enable bit
(RE)
Clock control circuit
S
CLK
Serial I/O enable bit
(SIOE)
Serial I/O synchronous
clock selection bit (SCS)
Dividing ratio 1/(n+1)
✽
CIN
BRG count source
selection bit (CSS)
X
1/4
Baud rate generator
Address 00E416
1/4
X
IN
S
RDY output
enable bit
(SRDY)
1/4
Falling
detected
Clock control circuit
F/F
Transmit enable
bit (TE)
S
RDY
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit shift register
TXD
Transmit interrupt source
selection bit (TIC)
Transmit buffer register
Transmit buffer empty flag (TBE)
P1
5
P1
7
Address 00E016
Serial I/O status register
Address 00E116
Data bus
✽: The 7477 group is not provided with the XCIN pin.
Fig. 1.13B.1 Clock synchronous Serial I/O block diagram
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1.13 Serial I/O
2
Communication format
The half-duplex data communication or the full-duplex data communication are available for
communication.
2
Synchronous clock
The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register
(SIOCON: address 00E216).
●“0” : Baud rate generator (BRG) output divided by 4
●“1” : External clock input from the SCLK pin
The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit
counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 or f(XCIN)/4 (at “0”),
f(XIN)/16 or f(XCIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register.
Notes on external clock selection
●When setting the transmit enable bit to “1” or writing data into the Transmit buffer register,
perform a write operation while the synchronous clock is at “H.”
●The shift operation of the Transmit shift register or the Receive shift register is continued while
the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop
the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous
clock stops automatically at the end of 8 cycles.)
●Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH,
TWL [s] > 8/(system clock [Hz]). For example, when a system clock is 8 MHz, use a clock of
500 kHz or less (duty ratio 50 %).
2
2
Shift clock
Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer
selects the internal clock and outputs the 8 shift clock pulses generated by a start of transmit
operation from the P16/SCLK pin. The other microcomputer selects the external clock and uses the
clock input from the P16/SCLK pin as a synchronous clock.
Data transfer rate (baud rate)
In the clock synchronous Serial I/O, the expression for calculating a data transfer rate (baud rate),
which is the frequency of the synchronous clock is shown below.
●When the internal clock is selected (using the BRG)
f(XIN)
Baud rate [bps] =
1
2
Division ratio✽ ✕ (BRG set value✽ + 1) ✕ 4
✽1 Division ratio : Select “4” or “16” by the BRG count source selection bit.
✽2 BRG set value : 0 – 255 (0016 – FF16)
●When the external clock is selected
Baud rate [bps] = Input clock frequency to SCLK pin
The BRG is an 8-bit counter dedicated to the Serial I/O, having a reload register, and divides the
count source by (n + 1) by setting the value n. As a count source, f(XIN)/4 or f(XCIN)/4 (at “0”), f(XIN)/
16 or f(XCIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register.
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1.13 Serial I/O
2
2
SRDY signal
The clock synchronous Serial I/O can inform the outside that a serial transfer has become ready,
by outputting the SRDY signal.
Transmit operation of the clock synchronous Serial I/O
The transmit operation of the clock synchronous Serial I/O is described below.
●Start of transmit operation
Transmit data is transmitted by writing it into the Transmit buffer register (TB: address 00E016)✽2
in the transmit enable state.✽1 When the internal clock is selected as a synchronous clock, 8 shift
clocks are generated at the time when this set value has been written.
●Transmit operation
1 After transmit data is written into the Transmit buffer register,✽2 the transmit buffer empty flag
(bit 0) of the Serial I/O status register is cleared to “0.”
2 The transmit data written in the Transmit buffer register is transferred to the Transmit shift
register.✽3
3 When the data transfer from the Transmit buffer register to the Transmit shift register is completed,
the transmit buffer empty flag is set to “1.”✽4
4 The transmit data transferred to the Transmit shift register is output from the P15/TxD pin in
synchronization with the fall of the synchronous clock.
5 When a transmit shift operation is started, the transmit shift completion flag (b2) of the Serial
I/O status register is cleared to “0.”✽5
6 Data is output starting with the least significant bit of the Transmit shift register. Each time one-
bit data is output, the contents of the Transmit shift register are shifted by 1 bit in the direction
of the least significant bit.
7 At the time when the transmit shift operation has been completed, the Transmit shift register
✽5
shift completion flag is set to “1.”✽3
✽1: Status in which the register for transmit operation has been completed. Refer to “[Clock
synchronous Serial I/O setting method]” which will be described later.
✽2: When the external clock is selected, write data into the Transmit buffer register when the
synchronous clock is at “H.”
✽3: A transmit interrupt request occurs immediately after the transfer of 2 when the transmit
interrupt source bit (bit 3) of the Serial I/O control register (SIOCON) is “0,” or at the time of
7
when the said bit is “1.”
✽4: While the transmit buffer empty flag is “1,” the next transmit data can be written into the
Transmit buffer register.
✽5: When the internal clock is used as a synchronous clock, the shift clock supply to the Transmit
shift register is automatically stopped after 8-bit data is transmitted. However, if the next
transmit data is written to the Transmit buffer register while the Transmit shift register shift
completion flag is “0,” the shift clock supply is continued and serial data is continuously
output from the TxD pin.
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1.13 Serial I/O
●When using the SRDY output
At the time when data has been written into the Transmit buffer register, the SRDY pin changes from
“H” to “L,” informing the outside of a receive ready state. The SRDY pin is restored to “H” at the
first fall of the synchronous clock.
●Transmit interrupt operation (valid when the Serial I/O is selected)
Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the
Serial I/O control register (SIOCON).
0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer
register is transferred to the Transmit shift register, an interrupt request is generated.
1: When the shift operation of the Transmit shift register is completed, an interrupt request is
generated.
Figure 1.13B.2 shows a transmit operation of clock synchronous Serial I/O and Figure 1.13B.3
shows a transmit timing chart of clock synchronous Serial I/O.
5
1
1
Data bus
Serial I/O status register
(Address 00E116
)
Transmit data writing
Address 00E016
0
Transmit buffer register
b2
b0
1
Serial I/O status register
(Address 00E116
)
Synchronous clock
6
7
0
b0
D
7
D
6
D
5
D
4
D
3
D
2
D1
2
Transmit buffer register
Transmit data transfer
Transmit shift register
P1
5
/TxD
Transmit shift register
Synchronous clock
b0
D
7
0
Serial I/O status register
(Address 00E116
3
Transmit shift register
P15
/TxD
)
1
✽
b0
When “0” is selected by the bit 3
of the Serial I/O control register
0
1
Serial I/O status register
(Address 00E116
)
0
Interrupt request register 1
(Address 00FC16
)
1
b2
b6
✽
When “1” is selected by the bit 3
of the Serial I/O control register
Synchronous clock
4
b0
0
Interrupt request register 1
(Address 00FC16
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
)
Transmit shift register
P1
5/TxD
1
b6
Fig. 1.13B.2 Transmit operation of clock synchronous Serial I/O
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1.13 Serial I/O
Synchronous clock,
BRG divided by 4, or
external clock
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
TXD pin
Write signal to
transmit buffer register
S
RDY pin
Transmit buffer empty flag
Transmit shift completion flag
B
1
B2
Transmit interrupt enable bit
Transmit interrupt request bit
A
2
B
1
A
1
B2
: • Clearing by writing “0” to the transmit interrupt request bit.
• Clearing by accepting the transmit interrupt.
A
1
A
B
B
2
1
2
: When interrupt request generation is selected, when the Transmit buffer register
becomes empty by clearing the transmit interrupt source selection bit to “0”.
: When interrupt request generation is selected, when the shift operation of the
transmit shift register is completed by setting the transmit interrupt source selection bit to “1”.
Fig. 1.13B.3 Transmit timing chart of clock synchronous Serial I/O
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1.13 Serial I/O
[Clock synchronous Serial I/O transmit setting method]
1 Clear the Serial I/O transmit interrupt enable bit (bit 6 of Interrupt control register 1) to “0.”
2 When selecting the internal clock, set the BRG value.
3 Set the Serial I/O control register according to Table 1.13B.1.
4 When using a Serial I/O transmit interrupt
[1] Clear the Serial I/O transmit interrupt request bit (bit 6 of Interrupt request register 1) to “0.”
Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O transmit
interrupt request bit may be set to “1.” Clear the Serial I/O transmit interrupt request bit
to “0” after one instruction or more after switching the ordinary port over to the Serial I/
O port.
[2] Set the Serial I/O transmit interrupt enable bit to “1.”
5 Write transmit data into the Transmit buffer register (TB: address 00E016).
Note:When the external clock is selected, perform a write operation while the synchronous clock
is at “H.”
Table 1.13B.1 Clock synchronous Serial I/O transmit setting
Serial I/O control register
(SIOCON: Address 00E216)
Register to be used
Item
Setting value
Bit
f(XIN)/4 or f(XCIN)/4
f(XIN)/16 or f(XCIN)/16
0
1
b0
BRG count source selection
BRG output divided by 4
External clock input
Ordinary port
0
1
0
1
b1
b2
Synchronous clock selection
SRDY signal output selection
SRDY signal output
Transmit buffer empty
When the transmit shift operation is completed
Transmit enable
Disable (half-duplex data communication)
Enable (full-duplex data communication)
Clock synchronous
0
1
b3
b4
b5
Transmit interrupt request selection
Transmit enable selection
Receive enable selection
1(Note)
0
1
1
1
Clock synchronous selection
Serial I/O enable selection
b6
b7
P14 to P17 function as serial I/O pins
Note: When the external clock is selected, write “1” in bit 4 (transmit enable bit) while the synchronous
clock is at “H.”
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1.13 Serial I/O
2
Receive operation of clock synchronous Serial I/O
The receive operation of the clock synchronous Serial I/O is described below.
●Start of receive operation
Receive operation begins by writing data into the Transmit buffer register (TB: address 00E016)✽2
in the receive enable state.✽1
• Transmit data in the full-duplex data communication
• Arbitrary dummy data in the half-duplex data communication
●Receive operation
1 Receive data is input bit by bit from the P14/RxD pin to the Receive shift register in synchronization
with the rise of the synchronous clock.
2 Receive data is input starting with the most significant bit of the Receive shift register. Each time
one bit is input, the contents of the Receive shift register are shifted by 1 in the direction of the
least significant bit.
3 After one-byte data is completely input to the Receive shift register, the contents of the Receive
shift register are transferred to the receive buffer register (RB).✽3
4 When receive data has been transferred to the receive buffer register, the receive buffer full flag
(b1) of the Serial I/O status register (SIOSTS) is set to “1,”✽4 so that a receive interrupt request
is generated.
✽1: Status in which the register for receive operation has been completed. Refer to “[Clock
synchronous Serial I/O receive setting method]” which will be described later.
✽2: When the external clock is selected, write data into the Transmit buffer register when the
synchronous clock is at “H.”
✽3: If receive data is further input to the Receive shift register when data remains (when the
receive buffer full flag is “1”) without reading out the contents of the Receive buffer register,
the overrun error flag of the Serial I/O status register is set to “1.” At this time, the data of the
Receive shift register is not transferred to the Receive buffer register and the original data of
the Receive buffer register is held.
✽4: The receive buffer full flag is cleared to “0” by reading out the Receive buffer register.
●When using the SRDY output
At the time when data has been written into the Transmit buffer register, the level of the SRDY
signal changes from “H” to “L” by which a receive ready state can be known externally. The SRDY
signal goes to “H” at the first fall of the synchronous clock of the synchronous clock.
●Receive interrupt operation (Serial I/O select only)
When receive data is transferred from the receive shift register to the Receive buffer register after
one-byte data is all input to the Receive shift register, an interrupt request is generated.
Figure 1.13B.4 shows a receive operation of the clock synchronous Serial I/O and Figure 1.13B.5
shows a receive timing chart of the clock synchronous Serial I/O.
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1.13 Serial I/O
Synchronous clock
1
4
b0
b0
D
0
Serial I/O status
register
0
Receive shift register
P1
4/RxD
(Address 00E116
)
1
Synchronous clock
b1
2
3
D3 D2 D1D0
0
Interrupt request
register 1
(Address 00FC16
Receive shift register
P1
4/RxD
)
1
b5
Synchronous clock
Receive shift
register
D7 D6D5D4 D3D2 D1D0
Receive data transfer
(Address 00E016
)
Receive buffer register
Fig. 1.13B.4 Receive operation of clock synchronous serial I/O
Synchronous clock
D
7
D
0
D
1
D
2
D
4
D
5
D
6
D
3
RxD pin
Reading into receive shift register
Writing data to transmit shift register
S
RDY pin
Receive buffer register
read signal
Receive buffer full flag
Receive enable bit
Receive interrupt request bit
A
A :
• Clearing by writing “0” to the receive interrupt request bit.
• Clearing by accepting the receive interrupt.
Fig. 1.13B.5 Receive timing chart of clock synchronous serial I/O
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1.13 Serial I/O
[Clock synchronous Serial I/O receive setting method]
1 Clear the Serial I/O receive interrupt enable bit (bit 5 of interrupt control register 1) to “0.”
2 When selecting the internal clock, set the BRG value.
3 Set the Serial I/O control register according to Table 1.13B.2.
4 When using a Serial I/O receive interrupt
[1] Clear the Serial I/O receive interrupt request bit (bit 5 of interrupt request register 1) to “0.”
Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O receive
interrupt request bit may be set. Clear the Serial I/O receive interrupt request bit to “0”
after one instruction or more after switching the ordinary port over to the Serial I/O port.
[2] Set the Serial I/O receive interrupt enable bit to “1.”
5 Set the following data into the Transmit buffer register (TB).
• Transmit data in the full-duplex data communication
• Arbitrary dummy data in the half-duplex data communication
Note: When the external clock is selected, perform a write operation while the synchronous
clock is at “H.”
Table 1.13B.2 Clock synchronous Serial I/O receive setting
Serial I/O control register
(SIOCON: Address 00E216)
Register to be used
Item
Bit
Setting value
f(XIN)/4 or f(XCIN)/4
f(XIN)/16 or f(XCIN)/16
0
1
b0
BRG count source selection
BRG output divided by 4
External clock input
Ordinary port
SRDY signal output (Note 1)
Disable (half-duplex data communication)
Enable (full-duplex data communication)
Receive enable
0
1
0
1
b1
b2
b4
Synchronous clock selection
SRDY signal output selection
Transmit enable selection
0
1(Note 2)
b5
b6
b7
1
1
1
Receive enable selection
Clock synchronous selection
Serial I/O enable selection
Clock synchronous
P14 to P17 function as Serial I/O pins
Notes 1: When the receive side performs an SRDY output by using an external clock, set the
receive enable bit, the SRDY output enable bit, and the transmit enable bit to “1”
(transmit enable).
2: When the external clock is selected, write “1” in bit 4 (transmit enable bit) while the
synchronous clock is at “H.”
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1.13 Serial I/O
(2) Clock asynchronous Serial I/O
In case of the clock asynchronous Serial I/O (UART), the transmit operation of the transmit side and
the receive operation of the receive side are simultaneously executed by unifying the baud rate and
the transfer data format between both transmit side and receive side.
Figure 1.13B.6 shows a UART block diagram.
Data bus
Address 00E216
P1
4
Receive enable bit
(RE)
Serial I/O control register
RXD
Address 00E016
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST detected
OE
7 bits
8 bits
Receive shift register
Character length
UART control register
selection bit (CHAS)
SP detected
1/16
PE FE
Address 00E316
Clock control circuit
Serial I/O enable bit(SIOE)
Serial I/O synchronous clock selection bit
(SCS)
S
CLK
BRG count source
selection bit (CSS)
✽
Dividing ratio 1/(n+1)
Baud rate generator
X
X
CIN
IN
1/4
1/4
Address 00E416
1/16
ST/SP/PA occur
Transmit enable bit (TE)
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Transmit shift register
TXD
Character length
selection bit (CHAS)
Transmit interrupt source
selection bit (TIC)
Transmit buffer register
P16 P15
Serial I/O status register
Address 00E016
Address 00E116
Data bus
✽: The 7477 group is not provided with the XCIN pin.
Fig. 1.13B.6 UART block diagram
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1.13 Serial I/O
2
Synchronous clock
The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register
(SIOCON: address 00E216).
●“0” : Baud rate generator (BRG) output divided by 16
●“1” : External clock input from the SCLK pin divided by 16
The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit
counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 or f(XCIN)/4 (at “0”),
f(XIN)/16 or f(XCIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register.
Precaution on internal clock selection
In the UART, when the internal clock is selected as a synchronous clock, the P16/SCLK pin can
be used as port P16.
Notes on external clock selection
●Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH,
TWL [s] > 2/(f(XIN) [Hz]). For example, when f(XIN) = 8 MHz, use a clock of 2 MHz or less (duty
ratio 50 %).
2
Data transfer speed (Baud rate)
In the UART, the expression for calculating a data transfer speed (baud rate), which is the frequency
of the synchronous clock is shown below.
●When the internal clock is selected (using the BRG)
f(XIN) or f(XCIN)
Division ratio✽1 ✕ (BRG set value✽2 + 1) ✕ 16
Baud rate [bps] =
✽1 Division ratio : Select “4” or “16” by the BRG count source selection bit.
✽2 BRG set value : 0 – 255 (0016 – FF16)
●When the external clock is selected
Input clock oscillation frequency to SCLK pin
Baud rate [bps] =
16
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1.13 Serial I/O
The BRG is an 8-bit counter dedicated to the Serial I/O, having a reload register, and divides the
count source by (n + 1) by setting the value n. As a count source, f(XIN)/4 or f(XCIN)/4 (at “0”),
f(XIN)/16 or f(XCIN)/16 (at “1”) can be selected by bit 0 of the Serial I/O control register.
Table 1.13B.3 shows a baud rate reference value.
Table 1.13B.3 Baud rate reference value
At f(XIN) = 7.9872 MHz
At f(XIN) = 3.9936 MHz
Baud rate [bps]
BRG set value
BRG set value
Count source
f(XIN)/16
Count source
f(XIN)/16
300
600
103(6716 )
51(3316 )
25(1916 )
12(0C16)
25(1916 )
12(0C16)
7(0716)
51(3316 )
25(1916 )
12(0C16)
25(1916 )
12(0C16)
f(XIN)/16
f(XIN)/16
f(XIN)/16
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/16
f(XIN)/16
f(XIN)/4
f(XIN)/4
1200
2400
4800
9600
15600
31200
41600
3(0316 )
2(0216 )
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1.13 Serial I/O
2
Transmit/receive data format
A transmit/receive data format can be selected by the bits of the UART control register (UARTCON).
• Start bit (ST)
: 1-bit
• Data bit (DATA) : 7-bit or 8-bit
• Parity bit (PA) : Non or 1-bit
• Stop bit (SP)
: 1-bit or 2-bit
Figure 1.13B.7 shows a transmit/receive data format, Table 1.13B.4 shows a function of each bit of
transmit data, and Figure 1.13B.8 shows all data formats.
● For 1ST-8DATA-1PA-2SP
Next transmit data
(at continuous output)
Transmit data
Data bit (8 bits)
LSB
MSB
PA
ST
D
0
D
1
D
6
D
7
SP SP
ST
D
0
D
1
Fig. 1.13B.7 UART data format
Table 1.13B.4 Each bit function of UART transmit data
Name
Function
Start bit ST
The “L” signal for 1 bit is added by the bit indicating a start of data transmission
immediately before the transmit data.
Data bit DATA
Parity bit PA
This bit indicates the transmit data written in the UART transmit buffer register.
The “0” data is an “L” signal and the “1” data is an “H” signal.
This bit is added immediately after the data bit for improvement of data reliability.
The contents of this bit change according to the contents of the parity selection bit
so that the number of “1”s in the transmit data including the parity bit may always be
even or odd.
Stop bit SP
This bit indicates that data has been transmitted, and is added immediately after the
data bit (immediately after the parity bit when the parity is valid). The “H” signal for
1 bit or 2 bits is output.
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1.13 Serial I/O
ST: Start bit
Di:
Data bit
PA: Parity bit
SP: Stop bit
● For 7-bit UART mode
LSB
MSB
ST
D
0
D
1
D
D
2
2
D
D
3
3
D
D
4
4
D
D
5
5
D
6
SP
SP
PA
LSB
D
MSB
D
ST
0
D
1
6
SP
LSB
D
MSB
D
ST
ST
0
D
D
1
1
D
D
2
2
D
D
3
3
D
D
4
4
D
D
5
5
6
SP
LSB
D
MSB
D
0
6
PA
SP SP
● For 8-bit UART mode
LSB
MSB
ST
ST
D
0
D
D
1
D
D
2
2
D
D
3
3
D
D
4
4
D
D
5
5
D
D
6
6
D
7
SP
LSB
D
MSB
0
1
D
7
SP
SP
PA
PA
LSB
D
MSB
D
ST
ST
0
D
D
1
1
D
D
2
2
D
D
3
3
D
D
4
4
D
D
5
5
D
D
6
6
7
SP
LSB
D
MSB
D
0
7
SP SP
Fig. 1.13B.8 Transmit/receive format of UART
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1.13 Serial I/O
2 Transmit operation of UART
The Transmit operation of the UART is described below.
●Start of Transmit operation
Transmit data is transmitted by writing it into the Transmit buffer register (TB: address 00E016) in
1
the Transmit enable state.✽
●Transmit operation
1
After transmit data is written into the Transmit buffer register, the transmit buffer empty flag (bit
0) of the Serial I/O status register is cleared to “0.”
2
The transmit data written in the Transmit buffer register is transferred to the Transmit shift
register. When the data transfer from the Transmit buffer register to the Transmit shift register
2
is completed, the transmit buffer empty flag is set to “1.”✽
When the transmit interrupt source bit (bit 3) of the Serial I/O control register (SIOCON) is “0,”
the interrupt request bit is set to “1,” then a transmit interrupt request occurs.
The transmit data transferred to the transmit shift register is output from the P15/TxD pin in
synchronization with the fall of the synchronous clock starting with the start bit. The start bit,
the parity bit and the stop bit are automatically generated and output according to the contents
of setting of the UART control register.
3
4
5
When a transmit shift operation is started, the transmit shift completion flag (b2) of the Serial
I/O status register is cleared to “0.”
Data is output starting with the least significant bit of the Transmit shift register. Each time one-
bit data is output, the contents of the Transmit shift register are shifted by 1 bit in the direction
of the least significant bit.
3
6
After one-half a cycle of the synchronous clock✽ after a start of stop bit transmission, the
transmit shift completion flag is set to “1.”
When the bit 3 of the Serial I/O control register is “1” (transmit shift operation is completed),
at the time the interrupt request bit is set to “1” and the Transmit interrupt request occurs.
✽1: Status in which the register for transmit operation has been completed. Refer to the “[UART
transmit setting method]” which will be described later.
✽2: While the transmit buffer empty flag is “1,” the next transmit data can be written into the
Transmit buffer register.
✽3: In case of two stop bits, the stop bit output period is that of the 2nd bit.
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1.13 Serial I/O
●Transmit interrupt operation (valid when the Serial I/O is selected)
Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the
Serial I/O control register (SIOCON).
0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer
register is transferred to the Transmit shift register, an interrupt request is generated.
1: When the shift operation of the Transmit shift register is completed, an interrupt request is
generated.
*
In case of the UART, an interrupt operation is performed in the same way as when the synchronous
clock is selected.
Figure 1.13B.9 shows a transmit operation of UART and Figure 1.13B.10 shows a transmit timing
of UART.
1
2
Data bus
4
Write transmit data
Address 00E016
1
Transmit buffer register
b0
1
Serial I/O status register
(Address 00E116
)
0
b2
Serial I/O status register
(Address 00E116
)
0
5
6
Synchronous clock
b0
Transmit buffer register
Transfer transmit data
Transmit shift register
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
P1
5/TxD
Transmit shift register
0
SP
Synchronous clock
Serial I/O status register
(Address 00E116
)
P1
5/TxD
1
b0
0
When “0” is selected by the bit 3
of the Serial I/O control register
Serial I/O status register
(Address 00E116
)
1
b2
0
Interrupt request register 1
(Address 00FC16
)
When “1” is selected by the bit 3
of the Serial I/O control register
1
b6
Synchronous clock
3
0
Interrupt request
register 1
b0
ST
D7 D6 D5D4 D3
D2
D1D0
(Address 00FC16
)
1
b6
P1
5
/TxD
Transmit shift register
Fig. 1.13B.9 Transmit operation of UART
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1.13 Serial I/O
Synchronous clock,
BRG output divided by 16, or
external clock divided by 16
ST
D
0
D
1
D
2
D
6
SP
T
X
D pin
D
7
Serial I/O not used
Write signal to
Transmit buffer register
Transmit buffer empty flag
Transmit shift completion flag
Transmit interrupt enable bit
Transmit interrupt request bit
A
1
A2
B1
B2
A1
A2
: • Clearing by writing “0” to the transmit interrupt request bit.
• Clearing by accepting the transmit interrupt.
: When interrupt request generation is selected, when the Transmit buffer register
becomes empty by clearing the transmit interrupt source selection bit to “0”.
B
1
2
: When interrupt request generation is selected, when the shift operation of the
B
Transmit shift register is completed by setting the transmit interrupt source selection bit to “1”.
Fig. 1.13B.10 Transmit timing chart of UART
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1.13 Serial I/O
[UART transmit setting method]
1
2
3
4
5
Clear the Serial I/O transmit interrupt enable bit (bit 6 of Interrupt control register 1) to “0.”
When selecting the internal clock, set the BRG value.
Set the Serial I/O control register according to Table 1.13B.5.
Set the data format according to Table 1.13B.6.
When using a Serial I/O transmit interrupt
[1] Clear the Serial I/O transmit interrupt request bit (bit 6 of Interrupt request register 1) to “0.”
Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O transmit
interrupt request may be set to “1.” Clear the Serial I/O transmit interrupt request bit
to “0” after one instruction or more after switching the ordinary port over to the Serial
I/O port.
[2] Set the Serial I/O transmit interrupt enable bit to “1.”
6
Write transmit data into the Transmit buffer register.
Table 1.13B.5 UART transmit setting
Serial I/O control register
Register to be used
(SIOCON: Address 00E216
)
Item
bit
setting value
f (XIN)/4 or f(XCIN)/4
f (XIN)/16 or f(XCIN)/16
0
1
b0
BRG count source selection
BRG output divided by 16
External clock input divided by 16
0
1
b1
b2
b3
b4
b5
Synchronous clock selection
SRDY signal output selection
Transmit interrupt request selection
Transmit enable selection
Receive enable selection
(Note 1)
Transmit buffer empty
When the transmit shift operation is completed
Transmit enable
Disable (Half-duplex data communication)
Enable (Full-duplex data communication)
Clock asynchronization
0
1
1
0
1
0
1
b6
b7
Clock asynchronous selection
Serial I/O enable selection
P14 to P17 function as Serial I/O pins (Note 2)
Notes 1: When the UART is selected, this bit does not function.
2: When the internal clock is selected, the P16/SCLK pin can be used as port P16.
Table 1.13B.6 Set value of UART control register
UART control register (UARTCON: Address 00E316)
Serial I/O data transfer format
1ST-8DATA-1SP
1ST-7DATA-1SP
1ST-8DATA-1PA-1SP
1ST-7DATA-1PA-1SP
1ST-8DATA-2SP
b3
0
0
b2
b1
0
0
b0
0
1
–
0
0
Selection
(Note)
1
1
0
1
1
1
0
0
0
1
_
1ST-7DATA-2SP
1ST-8DATA-1PA-2SP
1ST-7DATA-1PA-2SP
Note: 0: Even parity
1: Odd parity
1
1
Selection
(Note)
1
1
0
1
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1.13 Serial I/O
2 Receive operation of UART
The receive operation of UART is described below.
●Start of receive operation
Set the receive enable bit (bit 5) of the Serial I/O control register (SIOCON) to the enable state
1
(“1”) in the receive enable state.✽ With this operation, the start bit is detected and serial data is
received.
●Receive operation
1
After a fall of the P14/RxD pin is detected, the level of the P14 /RxD pin is checked after one-
half a cycle of the synchronous clock. If its level is “L,” the bit is judged as a start bit. When
its level is “H,” it is judged that noise is generated, so that the the receive operation is stopped
and the UART waits for the start bit.
2
3
Receive data is input bit by bit from the P14/RxD pin to the Receive shift register in synchronization
with the rise of the synchronous clock.
Data, immediately after the start bit, is input starting with the most significant bit of the Receive
shift register. Each time one bit is received, the contents of the Receive shift register are shifted
by 1 bit in the direction of the least significant bit.
4
5
When the specified number of bits are all input in the Receive shift register, the contents of the
2, 3
✽
Receive shift register are transferred to the Receive buffer register (RB). ✽
After 1/2 cycle of the shift clock after a start of stop bit reception, the receive buffer full flag
4
(bit 1) of the Serial I/O status register (SIOSTS) is set to “1”✽ and a receive interrupt request
is generated.
6
Error flag detection is started concurrently with the occurrence of the receive interrupt request.
✽1:Status in which the register for receive operation has been completed. Refer to the “[UART
receive setting method]” which will be described later.
✽2:When the data bit length is 7 bits, the contents of the Receive buffer register consist of receive
data of bits 0 to 6 and “0” of bit 7 (MSB).
✽3:If receive data is further input to the Receive shift register when data remains (when the
receive buffer full flag is “1”) without reading out the contents of the Receive buffer register, the
overrun error flag of the Serial I/O status register is set to “1.” At this time, the data of the
Receive shift register is not transferred to the Receive buffer register and the original data of
the Receive buffer register is held.
✽4:The receive buffer full flag is cleared to “0” by reading out the Receive buffer register.
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1.13 Serial I/O
●Receive interrupt operation (valid when the Serial I/O is selected)
When receive data is transferred from the Receive shift register to the Receive buffer register after
one-byte data is all input to the Receive shift register, an interrupt request is generated.
*
In case of the UART, an interrupt operation is performed in the same way as when the synchronous
clock is selected.
Figure 1.13B.11 shows a receive operation of UART and Figure 1.13B.12 shows a receive timing
of UART.
1
5
Synchronous clock
RxD (SP)
Synchronous clock
RxD (noise)
“H” level detected
→ judge as noise
0
Serial I/O status register
“L” level detected
→ judge as start bit
RxD (ST)
(Address 00E116
)
1
b1
2
3
Synchronous clock
0
b0
Interrupt request register 1
D
0
(Address 00FC16
)
1
b5
P1
P1
4
/RxD
Receive shift register
Synchronous clock
6
0 0 0 0
b0
Serial I/O status register
D3 D2 D1 D0
(Address 00E116
)
1 1 1 1
4/RxD
Receive shift register
b6 b5b4 b3
b3(OE)=“1” when the overrun error occurs.
b4(PE)=“1” when the parity error occurs.
b5(FE)=“1” when the framing error occurs.
b6(SE)=“1” when OE U PE U FE=1.
Synchronous clock
4
Receive shift register
D7D6 D5D4D3
D
2 D1D0
Receive data transfer
Receive buffer register
(Address 00E016
)
Fig. 1.13B.11 Receive operation of UART
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1.13 Serial I/O
Synchronous clock
Receive started
by falling of ST
Test that level of ST
is “L”
RXD pin
ST
D1
D2
D0
PAR
D6
SP
Read into Receive shift register
Receive buffer register
read out signal
Receive buffer full flag
Receive interrupt request bit
A
Receive enable bit
: • Clearing by writing “0” to the receive interrupt request bit.
• Clearing by accepting the receive interrupt.
A
Fig. 1.13B.12 Receive timing chart of UART
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1.13 Serial I/O
[UART receive setting method]
1
2
3
4
5
Clear the Serial I/O receive interrupt enable bit (bit 5 of Interrupt control register 1) to “0.”
When selecting the internal clock, set the BRG value.
Set the Serial I/O control register according to Table 1.13B.7.
Set the data format according to Table 1.13B.6.
When using a Serial I/O receive interrupt
[1] Clear the Serial I/O receive interrupt request bit (bit 5 of Interrupt request register 1) to “0.”
Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O receive
interrupt request may be set to “1.” Clear the Serial I/O receive interrupt request bit
to “0” after one instruction or more after switching the ordinary port over to the Serial
I/O port.
[2] Set the Serial I/O receive interrupt enable bit to “1.”
6
In the full-duplex data communication, set transmit data in the Transmit buffer register (TB).
Table 1.13B.7 UART receive setting
Serial I/O control register
Register to be used
(SIOCON: Address 00E216
)
Item
bit
setting value
f (XIN)/4 or f(XCIN)/4
f (XIN)/16 or f(XCIN)/16
0
1
b0
BRG count source selection
BRG output divided by 16
External clock input divided by 16
0
1
b1
b2
b3
Synchronous clock selection
SRDY signal output selection
Transmit interrupt request selection
(Note 1)
Transmit buffer empty
0
1
0
1
1
0
1
When the transmit shift operation is completed
Disable (Half-duplex data communication)
Enable (Full-duplex data communication)
Receive enable
Clock asynchronous
P14 to P17 function as serial I/O pins (Note 2)
b4
Transmit enable selection
b5
b6
b7
Receive enable selection
Clock asynchronous selection
Serial I/O enable selection
Notes 1: When the UART is selected, this bit does not function.
2: When the internal clock is selected, the P16/SCLK pin can be used as port P16.
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1.13 Serial I/O
1.13B.2 Pins
The 7477/7478 group uses 4 pins for data transmit, data receive, shift clock transmit/receive and serial
I/O transfer ready signal output. All these pins are used in common with P1. A function selection is made
by the serial I/O enable bit (bit 7) and the SRDY output enable bit (bit 2) of the Serial I/O control register.
The function of each pin is explained below.
(1) Data transmit pin[TxD]
Transmit data is output bit by bit. This pin is used in common with P15. When the transfer enable
bit and the serial I/O enable bit of the Serial I/O control register is set to “1,” this pin becomes a serial
I/O data output pin.
(2) Data receive pin [RxD]
Data is input bit by bit. This pin is used in common with P14. When the receive enable bit and the
serial I/O enable bit of serial I/O control register are set to “1,” this pin becomes a serial I/O data
input pin.
(3) Shift clock transmit/receive pin [SCLK]
2
Clock synchronous
This pin inputs (receives from the outside) or outputs (supplies to the outside) the synchronous
clock for data transmit/receive.
When the serial I/O synchronous clock selection bit (bit 1) of the Serial I/O control register is
cleared to “0” (use of internal clock), the synchronous clock is output.
When the same bit is set to “1” (use of internal clock), the synchronous clock is input from the
outside.
2
Clock asynchronous (UART)
When the serial I/O synchronous clock selection bit (bit 1) of the Serial I/O control register is set
to “1” (use of external clock), the synchronous clock is supplied from the outside.
When the same bit is cleared to “0” (use of internal clock), this pin does not function.
Note: When the internal clock is selected, SCLK pin can be used as port P16.
(4) Serial transfer enable signal output pin [SRDY]
This pin informs the outside of a receive enable state in the clock synchronous serial I/O.
In case of the UART, this pin does not function.
● SRDY signal output enable bit (bit 2) of Serial I/O control register is set to “1.”
● Transmit enable bit (bit 4) of Serial I/O control register is set to “1.”
When the above 2 conditions are satisfied, the level of the pin changes from “H” to “L” at the timing
at which data was written into the Transmit buffer register, informing the outside of a serial I/O transfer
enable state.
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1.13 Serial I/O
1.13B.3 Notes on use
(1) Notes on external clock selection
In the 7477/7478 group, either the internal clock or external clock can be selected as the synchronous
clock. When the external clock is selected as the synchronous clock, take the following points into
consideration.
2
Clock synchronous serial I/O
1
During data transmission, when setting the transmit enable bit to “1” or writing data into the
Transmit buffer register, perform a write operation while the synchronous clock is at “H.”
The transmission or the shift operation of the Receive shift register is continued while the
synchronous clock is input to the serial I/O circuit. When the external clock is selected, stop the
synchronous clock at the end of 8 cycles. When the internal clock is selected, the synchronous
clock stops automatically at the end of 8 cycles.
2
3
When the external clock is selected, set the “H” and “L” widths (TWH, TWL) of the pulse used
as the external clock source to TWH, TWL [s] Q 8/(f(XIN) [Hz]). For example, when f(XIN) is 8
MHz, use a clock of 500 kHz or less (duty ratio 50 %).
2
UART
Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH,
TWL [s] Q 2/(f(XIN) [Hz]). For example, when f(XIN) is 8 MHz, use a clock of 2 MHz or
less (duty ratio 50 %).
(2) When the SRDY output is performed in the clock synchronous serial I/O
When the receive side using the external clock performs an SRDY output, set the receive enable bit,
the SRDY output enable and the transmit enable bit to “1” (transmit enable).
(3) When a serial I/O transmit interrupt or a serial I/O receive interrupt is caused
2
When using a serial I/O transmit interrupt
1
Clear the serial I/O transmit interrupt request bit (bit 6 of IR1) to “0” after one instruction or
more after setting a value in the Serial I/O control register.
2
After setting in 1 , set the serial I/O transmit interrupt enable bit (bit 6 of IE1) to “1.”
2
When using a serial I/O receive interrupt
1
2
Clear the serial I/O receive interrupt request bit (bit 5 of IR1) to “0” after one instruction or more
after setting a value in the Serial I/O control register.
After setting in 1 , set the serial I/O receive interrupt enable bit (bit 5 of IE1) to “1.”
(4) Transmit interrupt request in the transmit enable state
After the transmit enable bit is set to “1,” the transmit buffer empty flag and the transmit shift
completion flag are set to “1.” Accordingly, even if a transmit buffer empty state is selected or a
termination of shift operation of the Transmit shift register is selected as a transmit interrupt source,
an interrupt request is generated and the transmit interrupt request bit is set to “1.”
For this reason, when using a transmit interrupt, set the transmit enable bit to “1,” clear the transmit
interrupt request bit to “0,” and then set the transmit interrupt enable bit to “1” (enable state).
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1.13 Serial I/O
(5) Disabling transmission after transmission of 1-byte data
In the 7477/7478 group, it is possible to make reference to the transmit shift register completion flag
(TSC flag) to know that data has been transmitted.
The TSC flag is “0” during data transmission, and becomes “1” after data has been transmitted.
Accordingly, if data transmission is disabled at the time of confirmation of a change of the TSC flag
from “0” to “1,” data transmission can be terminated after 1-byte data is transmitted. However, the
TSC flag is also set to “1” when the serial I/O is enabled and does not become “0” until a synchronous
clock is generated and transmitted. For this reason, if data transmission is disabled by making
reference to the TSC flag at this time, data is not transmitted. Make reference to the TSC flag after
a start of data transmission.
The change of the TSC flag from “1” to “0” has a delay of 0.5 to 1.5 cycles of the synchronous clock.
(6) Re-setting the Serial I/O control register (SIOCON)
Re-set the Serial I/O control register after setting both transmit enable bit and receive enable bit to
“0” to re-set the transmit circuit and the receive circuit.
1
2
3
Clear both transmit enable bit (TE) and receive enable bit (RE) to “0.”
Set the bit 0 to bit 3 and bit 6 of the Serial I/O control register.
Set both transmit enable bit (TE) and receive enable bit (RE) to “1.”
(It is possible to set 2 and 3 simultaneously with the LDM instruction.)
(7) Stopping data transmit/receive
2
In the following cases, clear the transmit enable bit to “0” (transmit disable).
●To stop the transmit operation when data is transmitted in the clock synchronous serial I/O
●To stop the transmit operation when UART data is transmitted
●To stop only the transmit operation when UART data is transferred
2
2
2
In the following cases, clear receive enable bit (receive disable) or serial I/O enable bit to “0”
(serial I/O disable).
●To stop the receive operation when data is received in the clock synchronous serial I/O
In the following cases, clear the receive enable bit to “0.”
●To stop the receive operation when UART data is received.
●To stop only the receive operation when UART data is transferred.
In the following cases, clear both transmit enable bit and receive enable bit to “0” (transfer
disable) simultaneously.
●To stop the transmit operation and the receive operation when data is transferred in the clock
synchronous serial I/O
Note: When data is transferred in the clock synchronous serial I/O, it is impossible to stop only
the transmit operation or the receive operation.
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1.13 Serial I/O
(8) Processing upon occurrence of errors
2
When a parity error, a framing error or a summing error occurs
When a parity error, a framing error or a summing error occurs, the flag corresponding to each
error in the Serial I/O status register is set to “1.” These flags are not cleared to “0” automatically.
Clear them to “0” by software.
The parity error flag, the framing error flag and the summing error flag can be cleared to “0” by
one of the following two methods.
●Clear the receive enable bit to “0.”
●Write arbitrary dummy data into the Serial I/O status register.
2
Processing upon occurrence of overrun error
An overrun error occurs when data has all been input to the Receive shift register while data is
stored in the Receive buffer register.
When an overrun error occurs, the data of the Receive shift register is not transferred to the
Receive buffer register and the data of the Receive buffer register is held. At this time, even if
the data of the Receive buffer register is read out, the data of the Receive shift register is not
transferred. Accordingly, the data of the Receive buffer register can be read out but the data of
the Receive shift register cannot be read out and becomes invalid.
When an overrun error occurs, clear the overrun error flag of the Serial I/O status register to “0”
and then make preparations for receiving data again.
The overrun error flag can be cleared by one of the following methods.
●Clear the serial I/O enable bit to “0.”
●Clear the receive enable bit to “0.”
●Write arbitrary dummy data into the Serial I/O status register.
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1.13 Serial I/O
1.13B.4 Related registers
(1) Transmit/receive buffer register (TB/RB: Address 00E016)
The Transmit/receive buffer register is written serial I/O (used in common with the clock synchronous
serial I/O and the UART) transmit data and is read out serial I/O receive data.
●To transmit data, write this transmit data into this register.
●Receive data can be obtained by reading this register.
Figure 1.13B.13 shows a structure of the Transmit/receive buffer register.
Transmit/receive buffer register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/receive buffer register (TB/RB) [Address 00E016]
At reset
B
Function
R
W
A value of “0016” to “FF16” can be
set as transmit data.
At transmit:
At receive:
0
to
7
The transmit data is transferred
automatically by writing the transmit
data into the Transmit shift register.
When all receive data has been input
into the Receive shift register, the
receive data is automatically trans-
ferred to the receive buffer register.
?
Fig. 1.13B.13 Structure of Transmit/receive buffer register
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1.13 Serial I/O
(2) Serial I/O status register (SIOSTS: Address 00E116)
The Serial I/O status register consists of flags for representing the buffer/register state to be used
for data transfer, and error flags.
●This register is a read-only type.
●Bit 7 is unused and “1” at a read operation.
Figure 1.13B.14 shows a structure of the Serial I/O status register.
Serial I/O status register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1
Serial I/O status register (SIOSTS) [Address 00E116]
At reset
R
B
0
Name
W
Function
0 : Buffer full
1 : Buffer empty
Transmit buffer
empty flag (TBE)
0
0
0
0
0
0
0
1
✕
Receive buffer full
flag (RBF)
0 : Buffer empty
1 : Buffer full
1
2
3
4
5
6
7
✕
✕
✕
✕
✕
✕
Transmit shift
completion flag (TSC)
Overrun error flag
(OE)
0 : Transmit shift in progress
1 : Transmit shift completed
0 : No error
1 : Overrun error
Parity error flag
(PE)
0 : No error
1 : Parity error
Framing error flag
(FE)
0 : No error
1 : Framing error
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
Summing error
flag (SE)
Nothing is allocated for this bit. This is a write
disabled bit. When this bit is read out, the value
is “1.”
1 ✕
Fig. 1.13B.14 Structure of Serial I/O status register
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1.13 Serial I/O
Each bit of the Serial I/O status register is described below.
2 Transmit buffer empty flag (TBE, bit 0)
This flag indicates the state of the Transmit buffer register.
This bit is set to “1” after the data written in the Transmit buffer register is transferred to the
Transmit shift register, and cleared to “0” after data is written into the Transmit buffer register.
This flag is valid in both clock synchronous serial I/O and UART.
2 Receive buffer full flag (RBF, bit 1)
This flag indicates the state of the Receive buffer register.
When 1-byte data has been all input to the Receive shift register and then the receive data has
been transferred from the Receive shift register to the Receive buffer register, this flag is automatically
set to “1.” When the transferred data has been read out from the Receive buffer register, the flag
is automatically cleared to “0.”
If receive data is further input to the Receive shift register when the receive buffer full flag is “1”
(without reading out the contents of the Receive buffer register), the overrun error flag is set to
“1.”
The receive buffer full flag is valid in both clock synchronous serial I/O and UART.
2 Transmit shift completion flag (TSC, bit 2)
This flag indicates the state of the transmit shift operation.
When transmit data has been transferred to the Transmit shift register and then a shift operation
has been started with the synchronous clock (transmission of the 1st bit of the transmit data), this
flag is cleared to “0.” When the shift operation has been completed (completion of transmission
the last bit of the transmit data), the flag is set to “1.”
This flag is valid in both clock synchronous serial I/O and UART.
2 Overrun error flag (OE, bit 3)
This flag indicates the receive data read state.
If receive data is further input to the Receive shift register when the receive buffer full flag is “1”
(without reading out the contents of the Receive buffer register), the overrun error flag is set to
“1.”
This flag is cleared to “0” by any operation shown in Table 1.13B.8.
This flag is valid in both clock synchronous Serial I/O and UART.
2 Parity error flag (PE, bit 4)
This flag indicates a hardware check result on the even parity or odd parity in the UART.
If there is a difference between the parity of received data and the set parity, the flag is set to
“1.”
This flag is cleared to “0” by any operation shown in Table 1.13B.8.
This flag is valid in the parity enable state in UART.
2
Framing error flag (FE, bit 5)
This flag judges a frame synchronization error in UART.
When the stop bit of receive data cannot be received at the set timing, the flag is set to “1.”
At stop bit detection, only the 1st stop bit is detected but the 2nd stop bit is not checked.
This flag is cleared by any operation shown in Table 1.13B.8.
This flag is valid in UART only.
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1.13 Serial I/O
2
Summing error flag (SE, bit 6)
This flag judges a serial I/O error.
If one of an overrun error, a parity error and a framing error occurs, the flag is set to “1.”
This flag is cleared by any operation shown in Table 1.13B.8.
This flag is valid in both clock synchronous serial I/O and UART.
[Error flag clear method]
The error flags (bit 3 to bit 6) in the Serial I/O status register can be cleared to “0” by the error
flag clear methods shown in Table 1.13B.8.
Table 1.13B.8 Error flag clear method
Clear the serial I/O inter- Clear the receive enable bit Write dummy data into the
Error flag
rupt enable bit to “0.”
to “0.”
SIOSTS.
Overrun error flag
Parity error flag
Framing error flag
Summing error flag
,
,
,
,
,
,
,
,
,
×
×
×
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1.13 Serial I/O
(3) Serial I/O control register (SIOCON: Address 00E216)
The Serial I/O control register exerts various types of control over the serial I/O, for example, transfer
mode, clocks and pin function selection. All the bits of this register can be read and written by
software.
Figure 1.13B.15 shows a structure of the Serial I/O control register.
Serial I/O control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address 00E216]
At reset
B
0
Function
Name
BRG count source
selection bit (CSS)
R W
0 : f(XIN)/4 or f(XCIN)/4
1 : f(XIN)/16 or f(XCIN)/16
0
1
Serial I/O
synchronous clock
selection bit (SCS)
•In clock synchronous mode
0 : BRG output divided by 4
1 : External clock input
•In UART mode
0
0 : BRG output divided by 16
1 : External clock input
divided by 16
2
3
SRDY output enable
bit (SRDY)
✽In the UART mode,
0 : P17/SRDY pin operates
as ordinary I/O pin
1 : P17/SRDY pin operates
as SRDY output pin
0
0
this bit is invalid.
Transmit interrupt
source selection
bit (TIC)
0 : When transmit buffer
has emptied
1 : When transmit shift
operation is completed
0 : Transmit disabled
1 : Transmit enabled
4
5
6
Transmit enable bit (TE)
Receive enable bit (RE)
0
0
0 : Receive disabled
1 : Receive enabled
Serial I/O mode
selection bit (SIOM)
0 : Clock asynchronous
serial I/O (UART)
0
1 : Clock synchronous
7
Serial I/O enable
bit (SIOE)
0 : Serial I/O disabled
(pins operates as ordinary
0
I/O pins P14–P17)
1 : Serial I/O enabled
(pins operates as serial
I/O pins RXD - SRDY)
(Note)
Note: Port P14–P17 are operates as the serial I/O pin only when
the serial I/O enable bit is “1” (enable state).
At this time, Port P17 is also used as an ordinary I/O port.
In the UART mode, port P1 6 is used as an ordinary I/O port
when the internal clock is selected.
Fig. 1.13B.15 Structure of Serial I/O control register
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1.13 Serial I/O
Each bit of the Serial I/O control register is described below.
2
2
BRG count source selection bit (CSS, bit 0)
This bit selects a count source to be input to the BRG.
• “0”: f(XIN)/4
• “1”: f(XIN)/16
Serial I/O synchronous clock selection bit (SCS, bit 1)
This bit selects a synchronous clock to be used for the serial I/O.
● In the clock synchronous serial I/O
• “0”: The BRG output divided by 4 becomes a shift clock.
• “1”: The external clock (P16/SCLK pin input) becomes a synchronous clock.
● In the UART
• “0”: The BRG output divided by 16 becomes a shift clock.
• “1”: The external clock (P16/SCLK pin input) divided by 16 becomes a synchronous clock.
2
SRDY output enable bit (SRDY, bit 2)
This bit selects whether the P17/SRDY pin is used as P17 or as serial I/O pin SRDY or SRDY output
disable.
● In the clock synchronous serial I/O
• “0”: SRDY pin output disable (used as port P17)
• “1”: SRDY pin output enable (used as serial I/O pin SRDY)
● In the UART
The P17/SRDY pin is used as P17 regardless of the value of this bit.
2
2
Transmit interrupt request selection bit (TIC, bit 3)
This bit determines a source for generating a transmit interrupt request.
• “0”: When the contents of the Transmit buffer register are transferred to the Transmit shift
register, a transmit interrupt request is generated.
• “1”: When the shift operation of the Transmit shift register terminates, a transmit interrupt
request is generated.
Transmit enable bit (TE, bit 4)
This bit controls a transmit operation.
● When the serial I/O enable bit (bit 7) is “0” (serial I/O disable)
The transmit enable bit is invalid.
● When the serial I/O enable bit (bit 7) is “1” (serial I/O disable)
The control shown in Table 1.13B.9 is exerted.
Table 1.13B.9 Transmit enable bit function
Transmit buffer
empty flag
Cleared to “0”
Flag function is valid.
Transmit shift
completion flag
Cleared to “0”
Transmit enable bit
P15/TXD pin function
1
2
0
1
Port P15
Serial I/O data transmit pin TXD
Flag function is valid.
1: Bit 0 of Serial I/O status register
2: Bit 2 of Serial I/O status register
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1.13 Serial I/O
2
Receive enable bit (bit 5)
This bit controls the receive operation.
● When the serial I/O enable bit (bit 7) is “1” (serial I/O enable), the control shown in Table
1.13B.10 is exerted.
● When the serial I/O enable bit (bit 7) is “0” (serial I/O disable), this bit is invalid.
Table 1.13B.10 Receive enable bit function
1
2
Receive enable bit
P14/RXD pin function
Receive buffer full flag
Each error flag
Cleared to “0”
0
1
Port P14
Serial I/O data transmit pin R
Cleared to “0”
Flag function is valid.
XD
Flag function is valid.
1: Bit 1 of Serial I/O status register
2: Bit 3,4,5 and 6 of Serial I/O status register
2
Serial I/O mode selection bit (bit 6)
This bit selects the clock synchronous serial I/O or the UART.
• “0”: UART
• “1”: Clock synchronous serial I/O
2
Serial I/O enable bit (bit 7)
This bit selects whether each of the P14/RxD, P15/TxD, P16/SCLK and P17/SRDY pins is used as
a port or a serial I/O pin.
When using the serial I/O, set this bit to “1.”
• “0”: The respective pins become P14 to P17.
• “1”: The respective pins become serial I/O pins, RXD, TxD, SCLK, SRDY.
Note: In the UART, when the internal clock is selected, the P16/SCLK pin can be used as port P16.
However, for the P17/SRDY pin, take the following points into consideration.
2
2
In the clock asynchronous serial I/O
When using the P17/SRDY pin as serial I/O pin SRDY, set the SRDY output enable bit (bit 2) to “1.”
In the UART
The P17/SRDY pin is used as P17 regardless of the value of the serial I/O enable bit.
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1.13 Serial I/O
(4) UART control register (UARTCON: Address 00E316)
The UART control register controls the UART transfer data format and the P15/TxD pin output type.
Figure 1.13B.16 shows a structure of UART control register.
UART control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1
UART control register (UARTCON) [Address 00E316]
At reset
B
0
Name
Function
R W
0: 8 bits
1: 7 bits
Character length
selection bit (CHAS)
0
0
0
0
0: Parity checking disabled
1: Parity checking enabled
1
2
3
Parity enable bit
(PARE)
Parity selection bit
(PARS)
0: Even parity
1: Odd parity
Stop bit length
0: 1 stop bit
selection bit (STPS) 1: 2 stop bits
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
4
to
7
1
1 ✕
Fig. 1.13B.16 Structure of UART control register
Each bit of the UART control register is described below.
2
2
2
2
Character length selection bit (CHAS, bit 0)
This bit selects a data bit length of the UART transfer data format.
• “0”: 8-bit length
• “1”: 7-bit length
Parity enable bit (PARE, bit 1)
This bit selects whether a parity check is made.
• “0”: No parity check (Parity error flag is invalid.)
• “1”: Parity check (Parity error flag is valid.)
Parity selection bit (PARS, bit 2)
This bit selects a parity type of the UART transfer data format.
• “0”: Even
• “1”: Odd
Stop bit length selection bit (STPS, bit 3)
This bit selects a stop bit length of the UART transfer data format.
• “0”: 1-stop bit
• “1”: 2-stop bit
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1.14 A-D converter
1.14 A-D converter
In the 7470/7471/7477/7478 group, the following A-D converter is incorporated.
……
● Analog input pins
7470/7477 group: 4 channels (in common with Port P2)
7471/7478 group: 8 channels (in common with Port P2)
● Conversion method Successive approximation comparison
…
In the 7470/7471 group, when the A-D converter is not used, power dissipation can be suppressed by the
VREF switch. (The 7477/7478 group is not provided with this function.)
Figure 1.14.1 shows a block diagram of the A-D converter.
Data bus
b4
b0
(Note 2)
A-D control register
(Address 00D916
)
A-D conversion
interrupt request
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
/IN
/IN
/IN
/IN
/IN
/IN
/IN
/IN
0
1
2
3
4
5
6
7
A-D control circuit
Comparator
A-D conversion register
(Address 00DA16
)
Switch tree
Resistor ladder
(Note 1)
V
REF switch (Note 2)
V
SS
VREF
Notes 1. The 7470/7477 group is not provided with the P2
4
/IN4–P27/IN7 pins.
2. The 7477/7478 group is not provided with the VREF switch and the VREF connection selection bit
(bit 4) of the A-D control register.
Fig. 1.14.1 A-D converter block diagram
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1.14 A-D converter
1.14.1 A-D conversion method
The A-D conversion method is of successive approximation comparison.
The reference voltage Vref generated internally is compared with the analog input voltage VIN which is
input from the analog input pin (P20/IN0–P27/IN7), and its result is stored into each bit of the A-D conversion
register (address 00DA16) successively to obtain a digital value.
[Internal operation]
After A-D conversion is started, the following operations are automatically performed.
1
2
3
The contents of the A-D conversion register is set to “0016.”
The most significant bit (bit 7) of the A-D conversion register is set to “1.”
The reference voltage Vref is input to the comparator. The reference voltage Vref is specified by
the contents n of the A-D conversion register and the reference voltage VREF input from the VREF
pin.
An expression for the reference voltage Vref is shown below.
Relational expression between Vref and VREF
When n = 0
Vref = 0
When n = 1 to 255
Vref = VREF/256 × (n – 0.5)
n: The values of A-D conversion register (decimal notation)
4
The reference voltage Vref and the analog input voltage VIN are compared with 8 times. Upon
completion of each comparison, the comparison result is stored into the A-D conversion register.
As the A-D conversion register changes, the reference voltage Vref changes.
[1] Determination of the most significant bit (bit 7) of the A-D conversion register (in the 1st
comparison)
The reference voltage Vref and the analog input voltage VIN are compared. Bit 7 is determined
according to its result as follows.
If Vref < VIN , then bit 7 = “1.”
If Vref > VIN , then bit 7 = “0.”
[2] Determination of the bit 0 - 6 of the A-D conversion register (after the 2nd comparison).
First, bit 6 of the A-D conversion register is set to “1.” Next, the reference voltage Vref is
compared with the analog input voltage VIN. Bit 6 is determined according to its result as
follows.
If Vref < VIN , then bit 6 = “1.”
If Vref > VIN , then bit 6 = “0.”
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1.14 A-D converter
Likewise, bit 5 to bit 0 are determined according to comparison results of the 3rd to 8th
comparisons.
A digital value (contents of the A-D conversion register) corresponding to the analog input
voltage VIN is determined bit by bit by these operations.
Figure 1.14.2 shows the changes of the contents of the A-D conversion register and the reference
voltage during A-D conversion.
5
After completion of A-D conversion, bit 3 of the A-D control register is set to “1” and an interrupt
request is generated concurrently with the completion of A-D conversion.
Notes 1: An A-D conversion result can be obtained by reading the A-D conversion register after
bit 3 of the A-D control register is set to “1.”
2: The A-D conversion result is held in the A-D conversion register until bit 3 of the A-D
control register is set to “1” again after completion of the next A-D conversion.
Reference voltage (Vref) [V]
Contents of A-D conversion register
A-D conversion start
0 0 0 0 0 0 0 0
0
VREF
VREF
512
VREF
4
VREF
4
1
–
±
±
0 0 0 0 0 0 0
1st comparison start
2nd comparison start
2
VREF
2
VREF
2
VREF
512
VREF
8
1 1
0 0 0 0 0 0
–
±
VREF
512
3rd comparison start
8th comparison start
1 2 1 0 0 0 0 0
–
VREF
2
VREF
4
VREF
8
VREF
256
.....
±
±
±
±
–
1 2 3 4 5 6 7 1
VREF
512
.......
A-D conversion completion
(8th comparison completion)
1 2
4 5 6 7 8
3
Digital value corresponding
to analog input voltage
m
m
: Value determined by m th (m=1 to 8) result
Fig 1.14.2 Contents of A-D conversion register and reference voltage during A-D conversion
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1.14 A-D converter
2
Conversion time
● After a start of A-D conversion, this A-D conversion terminates after 50 cycles (12.5 µs at f(XIN)
= 8 MHz).
● Main clock input oscillation frequency f(XIN)/2 is used as an operating clock for the A-D converter,
so the A-D conversion time can be basically obtained by the following expression.
2
A-D conversion time =
× conversion cycle (50: cycles)
f(XIN)
Note: Because the comparator is configurated by capacity coupling, use the A-D converter in the
following condition.
f(XIN) > 1 MHz
Accordingly, use the A-D converter in the condition that bit 7 of the CPU mode register
(address 00FB16) is “0” (ordinary mode).
[Setting method]
In the 7470/7471 group
1
Clear the bit of the Port P2 direction register corresponding to the used analog input pin to “0”
(input mode).
2
3
Clear the port pull-up control bit corresponding to the used analog input pin to “0” (no pull-up).
Clear the A-D conversion interrupt request bit of the Interrupt request register 1 to “0.”
Note: After A-D conversion is started, the A-D conversion interrupt request bit is not cleared to “0”
automatically.
4
5
When using an A-D conversion interrupt, set the A-D conversion interrupt enable bit to “1” to
provide an interrupt enable state.
Set the A-D control register as follows.
● Select an analog input pin by the analog input pin selection bit.
● Set the VREF connection selection bit to “1” and connect VREF to a ladder resistor.
Wait for 1.0 µs or more as VREF stabilizing time.
6
7 Clear the A-D conversion end bit of the A-D control register to “0.” (With this setting, A-D conversion
is started.)
In the 7477/7478 group
1
Clear the A-D conversion interrupt request bit of the Interrupt request register 1 to “0.”
Note: After A-D conversion is started, the A-D conversion interrupt request bit is not cleared to “0”
automatically.
2
3
When using an A-D conversion interrupt, set the A-D conversion interrupt enable bit to “1” to
provide an interrupt enable state.
Set the A-D control register as follows.
● Select an analog input pin by the analog input pin selection bit.
● Clear the A-D conversion end bit to “0.” (With this setting, A-D conversion is started.)
Don't read the contents of the A-D conversion register during A-D conversion.
For register setting, refer to “Table 1.14.1 Setting at A-D Conversion.”
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1.14 A-D converter
Processing after conversion
1
A termination of conversion can be verified by any of the following operations.
● State of A-D conversion end bit.
● State of A-D conversion interrupt request bit.
● Branch to A-D conversion interrupt routine.
Read the A-D conversion register to obtain a conversion result.
2
Notes 1: Be sure to connect VREF to a ladder resistor during A-D conversion (7470/7471 group).
2: A-D conversion is restarted at the time when the A-D conversion end bit (bit 3) of the
A-D control register is cleared to “0” during A-D conversion.
Table 1.14.1 Setting at A-D conversion
Register
1 Port P2 direction register(P2D: Address 00C516)
(7470/7471 group)
Bit
b0
Value
Clear the bit corresponding to the used ana-
log input pin (one of pins P20/IN0 to P27/
IN7) to “0” (input mode).
Note: In the 7470 group, only pins P20/IN0
to P23/IN3 are available.
0: P20 to P23 are not pulled up.
Note: When one of pins P20/IN0 to P23/IN3
is used as an analog input pin
0: P24 to P27 are not pulled up.
Note: When one of pins P24/IN4 to P27/IN7
is used as an analog input pin
(7471 group)
b7
b2
b3
2
Port P1-P4 pull-up control register (7470 group)
Port P1-P5 pull-up control register (7471 group)
(Address 00D116)
3
4
5
Interrupt request register 1 (IR1: Address 00FC16)
Interrupt control register 1 (IE1: Address 00FE16)
A-D conversion control register
b7
b7
0: A-D conversion interrupt disabled
1: A-D conversion interrupt enabled
b2, b1, b0 • 000: P20/IN0
• 001: P21/IN1
(ADCON: Address 00D916)
• 010: P22/IN2
• 011: P23/IN3
• 100: P24/IN4
• 101: P25/IN5
• 110: P26/IN6
• 111: P27/IN7
Set the value corresponding to the used ana-
log input pin.
Note: In the 7470/7477 group, only pins P20/
IN0 to P23/IN3 are available.
0: During conversion (A-D conversion is started.)
1: VREF connection (7470/7471 group)
Fix this bit to “0.”
b3
b4
b7
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1.14 A-D converter
1.14.2 Pins
The pins used in the A-D converter are described below.
(1) Analog input pin (P20/IN0 to P27/IN7) (P20/IN0 to P23/IN3 in the 7470/7477 group)
● The analog input pin is an input pin for analog voltage.
● Apply a voltage of VSS (AVSS) - VREF to this pin.
● This pin is used in common with P20 to P27 (P20 to P23 in the 7470/7477 group).
When using the A-D converter, select a pin to be used as an analog input pin by bit 2 to bit 0 of
the A-D control register (ADCON: address 00D916).
Use the A-D converter in the following condition in the 7470/7471 group.
• When the bit of the Port P2 direction register, which corresponds to the used analog input pin,
is “0” (input mode)
• When the bit of the Pull-up control register, which corresponds to the used analog input pin, is
“0” (no pull-up)
(2) Reference voltage input pin (VREF)
● The reference voltage input pin is an input pin for reference voltage.
● In the 7470/7471 group: Input a voltage of VCC/2 (> 2) - VCC [V].
In the 7477/7478 group: Input a voltage of 2 - VCC [V].
(3) Analog power source input pin (AVSS)
● Analog power source input pin is an input pin for GND.
● Apply the same potential as the VSS pin to this pin.
● This pin is dedicated to the 56P6N-A package product of the 7471/7478 group.
1.14.3 Notes on use
When using the A-D converter, take the following points into consideration.
2 The comparator is configured by capacity coupling, so the charge is lost if the clock input oscillation
frequency is low.
● Set f(XIN) at 1 MHz or more during A-D conversion.
● Don’t execute the STP instruction during A-D conversion.
2
Apply a voltage of VCC/2 (> 2) - VCC [V] to the reference voltage input pin VREF.
Note that if the reference voltage is lowered below the above valve, the A-D conversion precision will
be degraded.
2 Apply the same potential as that of the VSS pin to the analog power supply voltage input pin AVSS.
The AVSS pin is dedicated to the 56P6N-A package product of the 7471/7478 group.
2 In the 7470/7471 group, clear the bit of the Port P2 direction register which corresponds to the used
analog input pin to “0” (input mode).
2
In the 7470/7471 group, clear the bit of the Pull-up control register which corresponds to the used
analog input pin to “0” (no pull-up).
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1.14.4 References
2 Definition of A-D conversion precision
The definition of A-D conversion precision is described.
Refer to the definition of A-D conversion precision shown in Figure 1.14.3.
(1) Relative precision
● Zero transition error (VOT)
Deviation of the input voltage, at which A-D conversion output data changes from “0” to “1,” from
the ideal A-D conversion characteristics between 0 and VREF
1
2
VREF
256
VOT = (VO –
×
)/1LSB [LSB]
● Full-scale transition error (VFST)
Deviation of the ideal A-D conversion characteristics between 0 and VREF of the input voltage
when the A-D conversion output data changes from “255” to “254”.
3
2
VREF
256
VFST = {(VREF –
×
) – V254}/1LSB [LSB]
● Non-linearity error
Deviation of the real A-D conversion characteristics from the ideal characteristics between V0 and V254
Non-linearity error = {Vn – (1LSB × n + VO)}/1LSB [LSB]
● Differential non-linearity error
Deviation of the input voltage required to change output data by “1” from the ideal characteristics
between V0 and V254
Differential non-linearity error = {(Vn+1 – Vn) – 1LSB}/1LSB [LSB]
(2) Absolute precision
● Absolute precision
Deviation of the real A-D conversion characteristic from the ideal characteristics between 0 and
VREF.
1
2
Absolute precision = {Vn – 1LSB × (n +
)}/1LSB [LSB]
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Output data
Full-scale transition error
(VFST
)
255
254
3
2
LSB
Differential non-linearity error
1LSB at relative accuracy
n+1
n
Ideal A-D conversion characteristics
between 0 and VREF
Actual A-D conversion characteristics
Non-linearity error
Absolute accuracy
1LSB at absolute
accuracy
Ideal A-D conversion
characteristics between
and V254
V
0
1
2
LSB
Zero transition error (VOT
)
1
0
V
0
V
1
V
n
Vn+1
V
254
VREF
Analog voltage
Fig. 1.14.3 Definition of A-D conversion precision
Vn: Analog input voltage when output data changes from “n” to “n + 1” (n = 0 – 254).
V254 – VO
• 1LSB =
(V) → 1LSB at relative precision
254
VREF
256
• 1LSB =
(V) → 1LSB at absolute precision
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1.14.5 Related registers
(1) A-D conversion register (AD: Address 00DA16)
The A-D conversion register stores A-D conversion results. This register is a read-only type.
Figure 1.14.4 shows a structure of the A-D conversion register.
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address 00DA16]
At reset
R
B
Function
W
0
to
7
This is a read-only register to store A-D
conversion results.
?
✕
Fig. 1.14.4 Structure of A-D conversion register
(2) A-D control register (ADCON: Address 00D916)
The A-D control register consists of bits that exerts various types of control over the A-D converter.
Figure 1.14.5 shows a structure of the A-D control register.
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A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
0
A-D control register (ADCON) [Address 00D916]
At reset
R
W
B
0
Name
Function
b2 b1 b0
A-D input selection
bits
0 0 0 : P20/IN0
0 0 1 : P21/IN1
0 1 0 : P22/IN2
0 1 1 : P23/IN3
1 0 0 : P24/IN4
1 0 1 : P25/IN5
1 1 0 : P26/IN6
1 1 1 : P27/IN7
0
1
2
0
(Note 1)
0
1
3
4
0 : Under conversion
1 : End conversion
A-D conversion end
bit
(Note 2)
VREF connection
0 : The VREF pin is
separated from the
comparison voltage
The 7477/7478 group is not
selection bit
0
✽
generator.
1 : The VREF pin is
connected to
provided with this bit.
This bit is undefined at
reset.
comparison voltage
generator.
Nothing is allocated for these bits.
These are write disabled bits and are
undefined at reading.
5, 6
7
?
0
? ✕
Fix this bit to “0.”
0 0
Notes 1: Since the 7470/7477 group is not provided with pins
P24–P27, do not set.
2: •A-D conversion is started by setting bit 3 to “0.”
•Writing “0” into bit 3 is valid. Even if “1” is written into
bit 3, this bit is not set to “1.” Accordingly, when writing a
value into the A-D control register without affecting bit 3,
set bit 3 to “1.”
Fig. 1.14.5 Structure of A-D control register
Each bit of the A-D control register is described below.
2
2
Analog input pin selection bit (Bit 2 to 0)
These bits select an analog input pin.
Pins that are not used as analog input pins of P2 function as programmable I/O ports (input ports
in the 7477/7478 group).
A-D conversion end bit (Bit 3)
This bit indicates the operation state of the A-D converter.
This bit is cleared to “0” during A-D conversion and set to “1” upon termination of A-D conversion.
A-D conversion is started by clearing this bit to “0.” (At the time when the bit is cleared to “0” during
A-D conversion, A-D conversion is restarted.)
2
VREF connect selection bit (Bit 4) (The 7477/7478 group is not provided with this bit.)
This bit connects the VREF pin to a ladder resistor.
When using the A-D converter, be sure to set this bit to “1.”
When the A-D converter is not used, power consumption can be reduced by clearing this bit to “0.”
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1.15 Reset
1.15 Reset
The microcomputer is reset by applying the “L” level to the RESET pin for 2 µs or more when the power
source voltage is within the standard value range. After that, when the “H” level is applied to the RESET
pin, the reset state of the microcomputer is released, so that the program is run starting with the reset
vector address.
1.15.1 Operation description
Figure 1.15.1 shows an internal processing sequence after reset release.
V
CC
X
IN
Internal clock φ
2 µs or more
RESET
32768 counts of XIN pin input signal
Internal reset
Address bus
Data bus
FFFE16 FFFF16
AL,AH
A
L
A
H
SYNC
Internal clock φ
:
:
CPU reference clock frequency
after reset release)
f(XIN)/2 (ordinary mode immediately
=
AH, AL
Content of reset vector address
CPU operation code fetch cycle
SYNC :
(This is a internal signal, so that it cannot be observed from the external unit.)
Undefined
:
Fig. 1.15.1 Internal processing sequence after reset release
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1.15 Reset
When the “H” level is applied to the RESET pin at the reset state, the contents of timer 3 and timer 4 and
the count source are automatically set as shown in Table 1.15.1, so that the internal reset state is
released by an overflow of timer 4.
Table 1.15.1 Timer 3 and 4 at reset
Item
Setting value
Timer 3
FF16
Timer 4
0716
overflow of
timer 3
count source
f(XIN)/16
After the “H” level is applied to the RESET pin, only the main clock oscillates regardless of the oscillation
state precedent to the reset state, so that the microcomputer starts to operate in the ordinary mode. The
XCIN pin and the XCOUT pin become P50 and P51, respectively.
After the reset state is released, the microcomputer runs the program starting with the high-order address
corresponding to the contents of address FFFF16 and the low-order address corresponding to the contents
of address FFFE16.
Note: The 7470/7477 group is not provided with the XCIN and XCOUT pins.
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1.15.2 Internal status immediately after reset release
Figure 1.15.2 shows an internal register status immediately after reset release.
Address
(C116)•••
(C316)•••
0016
0016
0016
(1) Port P0 direction register (P0D)
(2) Port P1 direction register (P1D)
(3) Port P2 direction register (P2D)
(The 7477/7478 group is not provided.)
(4) Port P4 direction register (P4D)
(C516)•••
(C916)•••
0 0 0 0
(D016)•••
(D116)•••
(D416)•••
(D916)•••
(5) Port P0 pull-up control register
0016
(6) Port P1–P5 pull-up control register
(In the 7470/7477 group, port P1–P4 pull-up control register)
(7) Edge polarity selection register (EG)
0
0 0 0 0 0
0 0 0 0 0 0
0 1 0 0 0
0016
(8) A-D control register (ADCON)
0
(9) Serial I/O mode register (SM)
(The 7477/7478 group is not provided.)
(10) Serial I/O status register (SIOSTS)
(The 7470/7471 group is not provided.)
(11) Serial I/O control register (SIOCON)
(The 7470/7471 group is not provided.)
(12) UART control register (UARTCON)
(The 7470/7471 group is not provided.)
(13) Timer 3 (T3)
(DC16)•••
(E116)•••
(E216)•••
1 0
0 0 0 0 0 0
0016
1 1 0 0 0 0
FF16
(E316)•••
(F216)•••
1
1
(14) Timer 4 (T4)
0716
(F316)•••
(F716)•••
0 0
(13) Timer FF register (TF)
(14) Timer 12 mode register (T12M)
(15) Timer 34 mode register (T34M)
(F816)•••
0016
0016
(F916)•••
(FA16)•••
(16) Timer mode register 2 (TM2)
(17) CPU mode register (CPUM)
(18) Interrupt request register 1 (IR1)
0 0
0 0
(FB16)•••
0 0 0 0
0 0 0
0 0 0
0 0 0 0
0 0 0
(FC16)•••
(FD16)•••
(19) Interrupt request register 2 (IR2)
(20) Interrupt control register 1 (IE1)
(21) Interrupt control register 2 (IE2)
(FE16)•••
(FF16)•••
0 0 0
0 0 0 0
0 0 0
(22) Program counter (PCH)
Contents of address FFFF16
Contents of address FFFE 16
1
(PCL)
(23) Processor status register (PS)
: The contents are undefined at reset release.
Note : The contents of all other registers and RAM are undefined at reset, so set their initial valves.
The bits are different depending on the product. Refer to the structure of each register.
Fig. 1.15.2 Internal status immediately after reset release
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1.15.3 Notes on use
1. The timer continues to perform a count operation after reset release.
2. After the reset state is released, the microcomputer runs the program starting with the high-order
address corresponding to the contents of address FFFF16 and the low-order address corresponding to
the contents of address FFFE16.
3. After the “H” level is applied to the RESET pin, only the main clock oscillates regardless of the
oscillation state precedent to the reset state, so that the microcomputer starts to operate in the
ordinary mode. The XCIN pin and the XCOUT pin become P50 and P51, respectively.
(The 7470/7477 group is not provided with the XCIN and XCOUT pins.)
4. When the STP instruction is executed in the ordinary mode, I/O ports are held in the state just
precedent to a stop of system clock oscillation. After that, the I/O ports are put into the input mode
after a reset operation of the microcomputer is performed, so that they go to the high-impedance state.
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1.16 Oscillation circuit
1.16 Oscillation circuit
The 7470/7471/7477/7478 group has the following circuits to obtain clocks required for operations.
• 7470/7477 group: Main clock oscillation circuit
• 7471/7478 group: Main clock oscillation circuit and sub-clock oscillation circuit
1.16.1 Oscillation circuit
(1) Clock generating circuit
The clock generating circuit controls the oscillation of the oscillation circuit and a generated clock
(internal clock φ) is supplied to the CPU and peripheral units.
Figure 1.16.1 shows a clock generating circuit block diagram.
Interrupt disable flag I
Interrupt request
Reset
Internal system clock selection bit (CM
Main clock (XIN–XOUT) stop bit (CM
7
6
)
)
Q
S
R
STP instruction
XIN
XCIN
XOUT
Q
Q
S
R
1/2
1/8
WIT instruction
Internal system clock
selection bit (CM
XCOUT
7)
1/2
Reset
Internal clock φ
S
R
Timer 3 count
source
selection bits
CNTR1
STP
instruction
T34M
T34M
1
2
Timer 1 or timer 2
overflow signal
Timer 3 count stop bit
(T34M
0
)
Timer 3
Timer 4 count source selection bits
T34M
T34M
4
5
Timer 4 count stop bit
(T34M
3)
.
Timer 4
Note : The 7470/7477 group is not provided with pins XCIN and XCOUT.
Fig. 1.16.1 Clock generating circuit block diagram
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1.16 Oscillation circuit
This oscillation circuit can stop and start oscillation.
• XIN-XOUT oscillation circuit ......................... Main clock f(XIN)
• XCIN-XCOUT oscillation circuit .................... Sub-clock f(XCIN)
There are two oscillation circuits (the main clock only in the 7470/7477 group) as shown above. The
clock obtained by dividing a signal input to the clock input pin XIN or XCIN becomes an internal clock
+
φ
which is used as a reference for operations.
+ : The internal clock φ varies with the operation modes of the microcomputer.
• Ordinary mode ................ Signal input to the XIN pin divided by 2
• Low-speed mode ............ Signal input to the XCIN pin divided by 2
(2) Oscillation circuit using a ceramic resonator or a crystal oscillator
An oscillation circuit can be formed by connecting a ceramic resonator or a crystal oscillator between
the XIN pin and the XOUT pin and between the XCIN pin and the XCOUT pin.
For a circuit example, refer to “Chapter 2 Application, 2.7 Oscillation Circuit.”
Please ask the oscillator maker for information on circuit constants and then set the value recommended
by the maker.
(3) External clock input circuit
It is also possible to supply a clock to the oscillation circuit from the outside.
As an external clock to be input to the XIN and XCIN pins, use a pulse signal with a duty ratio of 50 %.
At this time, make the XOUT and XCOUT pins open.
For a circuit example, refer to “Chapter 2 Application, 2.7 Oscillation Circuit.”
Note: Because the 7470/7477 group is not provided with the XCIN and XCOUT pins, the sub-clock f(XCIN)
is not available.
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1.16 Oscillation circuit
1.16.2 Sub-clock oscillation circuit
In the 7471/7478 group, the sub-clock f(XCIN) is available when the P50/XCIN pin and the P51/XCOUT pin
are used as the XCIN pin and the XCOUT pin.
The power supplied to the sub-clock oscillation circuit is given through a voltage reduction regulator to
reduce power dissipation in the sub-clock mode. That is, power is reduced by reducing the voltage applied
to the VCC pin by the voltage reduction regulator. The supply voltage to this oscillation circuit can be set
to one of the 2 stages of high power mode and low power mode in bit 5 of the CPU mode register.
Notes 1: When using the sub-clock, set f(XCIN) < 50 kHz < f(XIN)/3.
2: When using the sub-clock f(XCIN) in the 7471/7478 group, set the P50-P53 pull-up control bit (bit
6) of the P1-P5 pull-up control register to “0” and disconnect the pull-up transistor of the P50/XCIN
pin and P51/XCOUT pin.
3: When using the sub-clock as the internal clock φ, use it in one of the following states.
● Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection
bit of the CPU mode register to “1”).
● When fixing the XCOUT drive capacity to the Low power mode (set the XCOUT drive capacity
+
selection bit of the CPU mode register to “0”), lower the value of the resistor Rd in the sub-
clock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop.
+ “Resistor Rd”: Refer to the circuit example in “Chapter 2 Application, 2.7 Oscillation circuit.”
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1.16.3 Oscillation operation
(1) Oscillation operation
The microcomputer is put into the ordinary mode at reset release. At this time, only the main clock
oscillates and the P50/XCIN pin and the P51/XCOUT pin function as input ports P50 and P51.
Notes 1: The 7470/7477 group is not provided with XCIN and XCOUT pins.
2: When using the sub-clock f(XCIN) in the 7471/7478 group, set the P50-P53 pull-up control bit
(bit 6) of the P1-P5 pull-up control register to “0” and disconnect the pull-up transistor of the
P50/XCIN pin and P51/XCOUT pin.
2
Ordinary mode
The clock resulting from dividing a signal input to the XIN pin by 2 becomes internal clock φ.
Changing the mode to the low-speed mode (7471/7478 group)
Execute the following procedure.
1 Set the P50, P51/XCIN, XCOUT selection bit (bit 4) of the CPU mode register to “1” (XCIN, XCOUT).
2
3
4
Set the XCOUT drive capacity selection bit (bit 5) of the CPU mode register to “1” (High power).
Generate oscillation stabilizing wait time of f(XCIN) by software.
Set the system clock selection bit (bit 7) of the CPU mode register to “1” f(XCIN). At that time,
set the XCOUT drive capacity selection bit to “0” (low power) as required.
2
Low-speed mode (7471/7478 group)
The clock resulting from dividing a signal input to the XCIN pin by 2 becomes internal clock φ.
In the low-speed mode, a low power dissipation operation can be attained by setting the main clock
(XIN-XOUT) stop bit (bit 6) of the CPU mode register to “1.”
Changing the mode to the ordinary mode
Execute the following procedure.
1
2
3
Clear the main clock (XIN-XOUT) stop bit (bit 6) of the CPU mode register to “0” (oscillate).
Generate oscillation stabilizing wait time of f(XIN) by software.
Clear the system clock selection bit (bit 7) of the CPU mode register to “0” f(XIN).
Notes 1: Switch between the ordinary mode and the low-speed mode after the oscillation of the main clock
and the sub-clock becomes stable. For the oscillation stablizing time, ask the oscillator maker for
information.
2: Use the low-speed mode in one of the following states.
● Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection
bit of the CPU mode register to “1”).
● When fixing the XCOUT drive capacity to the Low power mode (clear the XCOUT drive capacity
+
selection bit of the CPU mode register to “0”), lower the value of the resistor Rd in the sub-
clock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop.
+ Resister Rd: Refer to a example of circuit in “chapter 2 application, 2.7 Oscillation circuit.”
3: When using the sub-clock especially, it takes a long time until the oscillation becomes stable.
When the ordinary mode is changed to the stop mode while the sub-clock is in the oscillation
state and then the ordinary mode is restored from the stop mode, the oscillation of the sub-clock
is not stabilized even if the main clock becomes stable and the CPU is restored.
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(2) Oscillation operation in the stop mode
After the stop mode is provided by execution the STP instruction, all oscillation stops. After that,
when the previous mode is restored from the stop mode by inputting the reset signal or generating
a restoration interrupt request, the oscillation starts.
For the details of the stop mode, refer to “1.17.1 Stop mode.”
(3) Oscillation operation in the wait mode
When the wait mode is provided by execution the WIT instruction, the internal clock φ supplied to the
CPU stops.
When the previous mode is restored from the wait mode by inputting the reset signal or generating
an interrupt request, the supply of internal clock φ to the CPU starts.
For the details of the wait mode, refer to “1.17.2 Wait mode.”
(4) State transitions of internal clock
Refer to “1.18 State transitions.”
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1.16.4 Oscillation stabilizing time
In the oscillation circuit using a ceramic resonator or a crystal oscillator, the oscillation becomes unstable
for a certain period at a start of oscillation of the oscillator. The time required for stabilization of oscillation
is called oscillation stabilizing time.
A proper oscillation stabilizing wait time fit for the used oscillation circuit is required. For the oscillation
stabilizing time, ask the oscillator maker for information.
(1) Oscillation stabilizing wait time at power on
In the 7470/7471/7477/7478 group, the oscillation stabilizing wait time for 32768 counts of the XIN
pin input signal is automatically generated in the period from power on to reset release.
Figure 1.16.2 shows a oscillation stabilizing wait time after power on.
✽
2.7V
V
CC
2 µs or more
RESET
X
IN
Oscillation stabilizing wait time
32768 counts of XIN pin input signal
Internal reset
Release internal reset state
✽: At f(XIN) = (2.2 VCC – 2) MHz
Fig. 1.16.2 Oscillation stabilizing wait time after power on
(2) Oscillation stabilizing wait time at recovery from stop mode
In the stop mode, oscillation stops. When the previous mode is restored from the stop mode by
inputting a reset signal or generating an interrupt, the oscillation stabilizing wait time for 32768
counts of the XIN pin input signal or the XCIN pin input signal is automatically generated in the same
way as the power on time.
● At recovery by reset, f(XIN) becomes a count source that generates oscillation stabilizing wait time.
● At recovery by interrupt, the count source of timer 3 set immediately before execution of the STP
instruction becomes a count source that generates oscillation stabilizing wait time. Note that when
f(XIN) is the system clock, the oscillation of the f(XCIN) side may not be stabilized after the lapse
of this oscillation stabilizing wait time.
For the details of the stop mode, refer to “1.17.1 Stop mode.”
Note: In the 7470/7477 group, f(XCIN) is not available.
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1.16.5 Notes on use
1. When inputting the external clock to the XIN pin or the XCIN pin, use a pulse signal with a duty ratio
of 50 % as an input signal. At this time, make the XOUT pin and the XCOUT pin open.
Refer to a example of circuit in “Chapter 2 application, 2.7 Oscillation circuit.”
2. When using the sub-clock f(XCIN) in the 7471/7478 group, set f(XCIN) < 50 kHz < f(XIN)/3.
3. In the 7471/7478 group, switch between the ordinary mode and the low-speed mode after the oscillation
of the main clock and the sub-clock becomes stable. For the oscillation stabilizing time, ask the
oscillator maker for information.
4. Use the low-speed mode in one of the following states.
• Fix the XCOUT drive capacity to the high power mode (Set the XCOUT drive capacity selection bit
of the CPU mode register to “1”).
• When fixing the XCOUT drive capacity to the Low-power mode (clear the XCOUT drive capacity
+
selection bit of the CPU mode register to “0”), lower the value of the resistor Rd in the sub-clock
oscillation circuit to a level at which the oscillation of f(XCIN) does not stop.
+ Resister Rd: Refer to a example of circuit in “Chapter 2 application, 2.7 Oscillation circuit.”
5. When using the sub-clock f(XCIN) in the 7471/7478 group, it takes a long time until the oscillation
becomes stable.
When the ordinary mode is changed to the stop mode while the sub-clock is in the oscillation state and
then the ordinary mode is recovered from the stop mode, the oscillation of the sub-clock is not stabilized
even if the main clock becomes stable and the CPU is restored.
Note: In the 7470/7477 group, the sub-clock f(XCIN) is not available because neither XCIN pin nor XCOUT
pin is provided.
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1.17 Low-power dissipation function
1.17 Low-power dissipation function
The 7470/7471/7477/7478 group is provided with a function to put the CPU into a wait state with low-power
dissipation by stopping the CPU operation by softoware.
The low-power dissipation function has the following 2 modes.
● Stop mode by a STP instruction
● Wait mode by a WIT instruction
Figure 1.17.1 shows the operation states of the microcomputer at low-power dissipation and Figure 1.17.2
shows a state transition.
WIT mode
Oscillation stops Oscillation is operating
STP mode
Stop
Stop
CPU
Peripheral device
Timer
A-D converter
Serial I/O
Operating
Stop
Note : When using an
external clock,
timer and serial
I/O are operating.
External interrupt
Operating
Operating
Fig. 1.17.1 Operation states of the microcomputer at low-power dissipation
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1.17 Low-power dissipation function
STP mode
WIT mode
Interrupt
Interrupt
Reset
Reset
Registers except timers
3, 4 and RAM are held.
Only RAM is held and the
other registers are reset.
Registers and RAM are
held.
Oscillation stabilizing wait time:
32768 counts of the specified
count source are counted
Oscillation stabilizing wait time :
f(XIN)/16 is counted
No oscillation stabilizing wait time
Reset release
(Program execution
from reset vector)
Interrupt processing
Proceed to the next
address of the STP or
WIT instruction
(Program is continued)
Fig. 1.17.2 State transition at low-power dissipation
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1.17 Low-power dissipation function
1.17.1 Stop mode
To switch to the stop mode, execute the STP instruction. In the stop mode, the oscillation of both f(XIN)
and f(XCIN) stops and the internal clock φ stops.
Accordingly, the CPU stops and the peripheral units also stop. This leads to a reduction of power dissipation.
Note: In the 7470/7477 group, the f(XCIN) is not available.
(1) State of stop mode
Table 1.17.1 shows a state of stop mode.
Note: When the STP instruction is executed, “FF16” and “0716” are automatically set in timer 3 and
timer 4, respectively.
Table 1.17.1 State of stop mode
Item
Oscillation
State of stop mode
Stop
CPU
Stop
State at execution STP
instruction is held.
When internal count source selected : Stop
When external count source selected : Operate
Internal clock mode: Stop
External clock mode: Operate
Held
I/O port P0 to P5
Timer
Serial I/O
RAM
SFR
CPU register
Held (except timer3, timer4)
Held
+
+ CPU register :
The following 6 registers are incorporated in the
CPU.
• Accumulator
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register
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1.17 Low-power dissipation function
(2) Releasion of stop mode
The stop mode is released by inputting a reset signal or generating an interrupt request. There is a
difference in restore processing from the stop mode between the use of reset input and the use of
interrupt.
2
Recovery by reset input
The microcomputer is reset by applying the "L" level to the RESET pin for 2 m s or more in the stop
mode, thereby releasing the stop mode.
After the stop mode is released, oscillator starts. (At this time, the inside is in the reset state.)
The reset state is released after 32768 counts of the XIN pin input after the “H” level is applied to
the RESET pin.
At a start of oscillation of the oscillator, the oscillation is unstable. It takes time before stabilization
of oscillation (oscillation stabilizing time). The oscillation stabilizing wait time is secured by the time
for holding this internal reset state.
For the details of the reset, Refer to “1.15 Reset.”
Note: When the stop mode is released, the contents of the RAM before reset are held. However,
the contents of the CPU register and the SFR cannot be held but are reset.
Figure 1.17.3 shows the oscillation stabilizing wait time at recovery from stop mode by reset input.
Stop mode
V
CC
2 µs or more
Oscillation stabilizing wait time : 32768 counts of XIN pin input signal
RESET
X
IN
Undefined
X
X
IN: in high-impedance state
OUT: “H”
(Note)
Execute STP instruction
Recovered by reset input
Note: No waveform may be input to XIN (in low-speed mode).
Fig. 1.17.3 oscillation stabilizing wait time at recovery from stop mode by reset input
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1.17 Low-power dissipation function
2
Recovery by interrupt
When an interrupt request is generated in the stop mode, this stop mode is released and oscillation
is started. The interrupt sources that are available for recovery are shown below.
● INT0, INT1
● CNTR0, CNTR1
● Serial I/O at using external clock
● Timer (timer 1, timer 2) at using external clock
● Key input (key on wake up)
However, when the above interrupt sources are used for recovery from the stop mode, perform the
following setting and then execute the STP instruction to permit an interrupt to be used.
[Register setting]
1
2
3
Clear the interrupt enable bit of timer 3 and timer 4 to “0.” (Disabled)
Set the count stop bit of timer 3 and timer 4 to “1.” (Stop)
Select a count source of timer 3 in consideration of the oscillation stabilizing time of the
oscillator.
Note: Re-set the previous count source at recovery.
4
5
6
7
Clear the interrupt request bit of the interrupt source to be used for recovery to “0.”
Set the interrupt enable bit of the interrupt source to be used for recovery to “1.”(Enabled)
Clear the count stop bit of timer 3 and timer 4 to “0.” (Count starts)
When using the sub-clock, set the XCOUT drive capacity to high power. (Refer to “1.16.2 Sub-
clock oscillation circuit.”)
8
Clear the interrupt disable flag I to “0.” (Enabled)
Note: In the stop mode, A-D conversion operation stops. Accordingly, execute the STP instruction
after termination of the A-D conversion.
For the details of the Interrupt, refer to “1.11 Interrupts.”
At a start of oscillation of the oscillator, the oscillation is unstable. It takes time before stabilization
of oscillation (oscillation stabilizing time). At recovery by interrupt, the waiting time for the supply
+ 1
+ 2
of internal clock φ to the CPU by timer 3 and timer 4 is automatically generated . The oscillation
stabilizing time of the system clock side is secured by this waiting time.
Figure 1.17.4 shows an example of restoration sequence from the stop mode by the INT0 interrupt.
+1: When the STP instruction is executed, “FF16” and “0716” are automatically set in the counter
and latch of timer 3 and the counter and latch of timer 4, respectively.
+2: The count source is supplied to timer 3 immediately after a start of oscillation, thereby starting
a count operation. The supply of internal clock φ to the CPU is started when timer 4 overflows.
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1.17 Low-power dissipation function
●When recovering from stop mode by using INT0 interrupt (rising edge selected)
Oscillation stabilizing wait time
2048 counts of timer 3
count source (Note)
Stop mode
X
IN or XCIN
Undefined
XIN, XCIN ; in high-impedance stat
XOUT ; “H”
INT
0 pin
Count down
“FF16”
“0716”
Timer 3
Timer 4
interrupt
INT
0
request bit
Operating
Operating
Stop
Operating
Peripheral device
CPU
Stop
Operating
•INT
0
interrupt
signal input
(INT interrupt
•Timer 4 overflow
•Start supplying internal
clock φ to CPU
•STP instruction
execution
0
request occurs)
•Oscillation start
•Timer 3 count start
•Accept INT
request
0 interrupt
Note: The count source is a count source of timer 3 before execution of the STP instruction.
Fig. 1.17.4 Example of recovery sequence from stop mode by INT0 interrupt
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1.17 Low-power dissipation function
1.17.2 Wait mode
To switch to the wait mode, execute the WIT instruction. In the wait mode, oscillation is continued but the
internal clock φ stops. Accordingly, the CPU stops but the peripheral units operate since oscillation is
continued.
(1) State of wait mode
Table 1.17.2 shows a state of wait mode.
Table 1.17.2 State of wait mode
Item
Oscillation
State of wait mode
Operate
CPU
Stop
State at execution WIT instruc-
I/O port P0 to P5
tion is held.
Operate
Operate
Held
Timer
Serial I/O
RAM
SFR
CPU register
Held
Held
+
+ CPU register :
The following 6 registers are incorporated in the
CPU.
• Accumulator
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register
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1.17 Low-power dissipation function
(2) Releasion of wait mode
The wait mode is released by inputting a reset signal or generating an interrupt request. There is a
difference in restore processing from the wait mode between the use of reset input and the use of
interrupt.
2
Recovery by reset input
The microcomputer is reset by applying the “L” level to the RESET pin for 2 ms or more in the wait
mode, thereby releasing the wait mode.
After the wait mode is released by inputting the reset signal, the supply of internal clock φ to the
CPU is started.
The reset state is released after 32768 counts of the XIN pin input signal after the “H” level is
applied to the RESET pin.
For the details of the reset, refer to “1.15 Reset.”
Note: When the wait mode is released, the contents of the RAM before reset are held. However,
the contents of the CPU register and the SFR cannot be held but are reset.
Figure 1.17.5 shows the reset input time.
Wait mode
V
CC
Oscillation stabilizing wait time : 32768 counts of XIN pin input signal
2 µs or more
RESET
X
IN
(Note)
Execute WIT instruction
Recovered by reset input
Note: No waveform may be input to XIN (in low-speed mode).
Fig. 1.17.5 Reset input time
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1.17 Low-power dissipation function
2
Recovery by interrupt
In the wait mode, oscillation is continued. Accordingly, as soon as the wait mode is released, an
instruction is executed.
When an interrupt request is generated in the wait mode, this wait mode is released and the supply
of internal clock φ to the CPU is started. At the same time, the interrupt request used for recovery
is accepted, so that the interrupt processing routine is executed.
The interrupt sources that are available for recovery are shown below.
● INT0, INT1
● CNTR0, CNTR1
● Serial I/O
● A-D conversion
● Timer 1 to timer 4
● Key input (key on wake up)
However, when the above interrupt sources are used for recovery from the wait mode, perform the
following setting and then execute the WIT instruction to permit an interrupt to be used.
[Register setting]
1
2
3
Clear the interrupt request bit of the interrupt source to be used for recovery to “0.”(No request)
Set the interrupt enable bit of the interrupt source to be used for recovery to “1.”(Enabled)
Clear the interrupt disable flag I to “0.” (Enabled)
For the details of the Interrupt, refer to “1.11 Interrupts.”
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1.17 Low-power dissipation function
1.17.3 Notes on use
[Notes on use of the stop mode]
2
Clock after recovery
After recovery from the stop mode by interrupt, the contents of the CPU mode register before
execution of the STP instruction are held. Accordingly, if both f(XIN) and f(XCIN) were oscillating
before execution of the STP instruction, the oscillation of both f(XIN) and f(XCIN) is restarted after
recovery by interrupt.
In the above case, if f(XIN) is set as the system clock, the oscillation stabilizing wait time for 32768
counts of the XIN pin input signal is secured at recovery from the stop mode.
Note that the f(XCIN) clock may not be stabilized even after the lapse of the f(XIN) oscillation
stabilizing wait time.
Note: In the 7470/7477 group, the f(XCIN) is not available.
2
Interrupt processing after recovery
After recovery from the stop mode, the interrupt request bit of timer 3 and timer 4 is “1.” Clear
it to “0” if necessary. The interrupt request bit of timer 1 and timer 2 may also be set to “1.” Clear
it to “0” as required.
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1.17 Low-power dissipation function
1.17.4 Related register
(1) CPU mode register (Address 00FB16)
+ 1
+ 2
The CPU mode register consists of a stack page selection bit
and system clock control bits
.
+ 1: In series having a RAM capacity of 192 bytes or less, this bit is not used because no RAM is
located on page 1. (Be sure to set this bit to “0.”)
+ 2: In the 7470/7477 group, which is not provided with a sub-clock generating circuit, this bit is not
used. (Be sure to set this bit to “0.”)
Figure 1.17.6 shows a structure of CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
CPU mode register (CPUM) [Address 00FB16
]
B
Name
Function
At reset R W
0
Fix these bits to “0.”
0, 1
0: In page 0 area
1: In page 1 area
Stack page selection
bit
2
0
(Note 1)
3
4
Nothing is allocated for this bit. This is write
enabled bit and is undefined at reading.
?
0
? ✕
P5
0, P51/XCIN,XCOUT
0: P50, P51
selection bit
1: XCIN, XCOUT (Note 2)
0: Low
1: High
X
COUT drive capacity
0
0
5
6
(Note 2)
(Note 2)
selection bit
Main clock (XIN–XOUT
stop bit
)
0: Oscillates
1: Stops
Internal system clock
selection bit
0: XIN–XOUT selected
(Ordinary mode)
1: XCIN–XCOUT selected
(Low speed mode)
(Note 2)
7
0
Notes 1:
2:
In the products having a RAM capacity of 192 bytes or
less, set this bit to “0.”
Since the 7470/7477 group is not provided with the
sub-clock generating circuit, f(XCIN) cannot be used.
Fix these bits to “0.”
Fig. 1.17.6 Structure of CPU mode register
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1.18 State transitions
1.18 State transitions
The operation modes of the 7470/7471/7477/7478 group are classified as follows.
● Reset
● Oridinary mode
● Low-speed mode (7471/7478 group)
● Sub-clock mode (7471/7478 group)
● Stop mode
● Wait mode
Figure 1.18.1 shows a state transitions.
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1.18 State transitions
Reset
Wait mode
State E
Stop mode
State F
Ordinary mode
WIT
instruction
STP
instruction
State A
b7 b6 b5 b4
CPUM 0
0
0 0
I
nternal clock
φ: Stopped
Internal clock φ: Stopped
f(XIN): Oscillating
f(XCIN): Stopped
f(XIN): Stopped
f(XCIN): Stopped
Internal clock φ: f(XIN)/2
f(XIN): Oscillating
f(XCIN): Stopped
Interrupt
Interrupt (Note 1)
Ordinary mode
WIT
instruction
State B
STP
instruction
b7 b6 b5 b4
—
0
CPUM 0
1
Internal clock φ: Stopped
Internal clock
φ: Stopped
f(XIN): Oscillating
f(XCIN): Oscillating
f(XIN): Stopped
f(XCIN): Stopped
Internal clock φ: f(XIN)/2
f(XIN): Oscillating
f(XCIN): Oscillating
Interrupt
Interrupt (Note 1)
(Note 2)
(Note 3)
State C
Low-speed mode
STP
WIT
(Note 4)
instruction
instruction
b7 b6 b5 b4
I
nternal clock
φ
: Stopped
I
nternal clock φ: Stopped
f(XIN): Oscillating
f(XCIN): Oscillating
—
1
1
CPUM
0
f(XIN): Stopped
f(XCIN): Stopped
Internal clock φ: f(XCIN)/2
Interrupt (Note 1)
Interrupt
f(XIN): Oscillating
f(XCIN): Oscillating
(Note 3)
Low-speed mode
STP
instruction
Sub-clock mode
State G
nternal clock φ: Stopped
WIT
instruction
(Note 4)
State D
b7 b6 b5 b4
—
I
nternal clock
φ: Stopped
1 1
1
CPUM
I
f(XIN): Stopped
f(XCIN): Stopped
f(XIN): Stopped
f(XCIN): Oscillating
Internal clock φ: f(XCIN)/2
f(XIN): Stopped
f(XCIN): Oscillating
Interrupt (Note 1)
Interrupt
Fig. 1.18.1 State transitions
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1.18 State transitions
Notes 1: When changing from the stop mode to another mode, oscillation stabilizing wait time is generated
automatically by connecting timer 3 and timer 4.
2: In the 7471/7478 group, where oscillating the stopped clock and switching the system clock, it
is necessary to wait at software until oscillation is stabilized. At this time, set the bit 5 of the CPU
mode register to “1” and set the XCOUT drive capacity to the high power mode. After the oscil-
lation of sub-clock f(XCIN) becomes stable, clear the bit to “0” (low power mode) as required.
3: In the 7471/7478 group, when returning from the low-speed mode to the ordinary mode, use the
main clock f(XIN) as a count source of the internal clock φ (state B). After that, clear bit 4 of the
CPU mode register to “0” to stop the oscillation of f(XCIN) if necessary.
4: When using the low-speed mode in the 7471/7478 group, use it in one of the following states.
● Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection bit
of the CPU register to “1.”)
● When fixing the XCOUT drive capacity to the low power mode (clear the XCOUT drive capacity
+
selection bit of the CPU mode register to “0”), lower the value of the resistor Rd in the sub-
clock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop.
+ “Resistor Rd”: Refer to the circuit example in “Chapter 2 Application, 2.7 Oscillation circuit.”
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1.18 State transitions
2
Reset → Ordinary mode (State A)
Immediately after reset, the main clock divided by 2 (f(XIN)/2) is selected as an internal clock φ and
the I/O pins XCIN and XCOUT of the sub-clock f(XCIN) become ordinary ports. “FF16” and “0716” are
set in timer 3 and timer 4 respectively, and also the main clock divided by 16 (f(XIN)/16) is selected
as a count source of timer 3 and the overflow signal of timer 3 is selected as a count source of
timer 4. Then a down-count is started.
When timer 4 overflows, the internal reset is released and the program starts from the address
specified by reset vector.
2
2
Low-speed mode (Stae C and state D)
To the low-speed mode (state C and state D) using the sub-clock divided by 2 (f(XCIN)/2) as an
internal clock φ, a transition is made by way of the ordinary mode (state A) → state B ( → state
C).
In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not
provided.
Wait mode (State E)
In this mode, all the states of registers, I/O ports and internal RAMs are held. The internal clock
φ stops at “H” but the oscillator does not stop.
From any of state A, state B, state C and state D, a return is made to the wait mode by executing
the WIT instruction. When a return is made from the state D to the wait mode, the sub-clock mode
in which only the timer function operates is provided. (In the 7470/7477 group, which is not
provided with a sub-clock oscillation circuit, the sub-clock mode is not provided.)
Refer to “1.17.2 Wait mode.”
2
2
Stop mode (State F)
In this mode, all the states of registers, I/O ports and internal RAMs except timer 3 and timer 4
are held and the oscillation of both main sub-clock is stopped. From any of state A, B, C and D,
a return is made to the stop mode by executing the STP instruction.
Refer to “1.17.1 Stop mode.”
Sub-clock mode (State G)
Only the clock-function is made to operate by sub-clock mode at low-power dissipation.
The sub-clock mode (state G) is provided by executing the WIT instruction in the low-speed mode
(state D), and restoration from this state to the low-speed mode is attached by each interrupt.
In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not
provided.
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1.19 Built-in PROM version
1.19 Built-in PROM version
In contrast with the mask ROM version, a microcomputer incorporating a programmable ROM is called
built-in PROM version.
There are two types of built-in PROM version as shown below.
●One Time PROM version
Writing to the built-in PROM can be performed only once. Neither erase nor rewrite operations are
enabled.
●Built-in EPROM version
The built-in EPROM version is a programmable microcomputer with window and can perform write,
erase, and rewrite operations.
The built-in PROM version has the EPROM mode for writing to the built-in PROM in addition to the same
functions as those of the mask ROM version.
For an outline of performance, a pin configuration and a functional block diagram of the built-in PROM
version, refer to “1.3 Performance overview”, “1.4 Pin configuration”, and “1.6 Functional block
diagram”, respectively.
The 7470/7471/7477/7478 group supports the built-in PROM versions shown in Table 1.19.1.
Table 1.19.1 7470/7471/7477/7478 group built-in PROM version supporting products
(P)ROM size RAM size
Product name
I/O Ports
Package
Remarks
(bytes)
(bytes)
I/O ports: 22
M37470E4-XXXSP
8192
192
(Including 4 analog
input pins.)
Input ports: 4
One Time PROM version
32P4B
M37470E8-XXXSP
16384
8192
384
192
M37471E4-XXXSP
M37471E4-XXXFP
M37471E8-XXXSP
M37471E8-XXXFP
M37471E8SS
M37477E8-XXXSP
M37477E8-XXXFP
M37477E8TXXXSP
M37477E8TXXXFP
M37478E8-XXXSP
M37478E8-XXXFP
M37478E8TXXXSP
M37478E8TXXXFP
M37478E8SS
42P4B
56P6N-A
42P4B
I/O ports: 28
(Including 8 analog
input pins.)
One Time PROM version
16384
16384
384
384
56P6N-A
Input ports: 8
42S1B-A EPROM version
32P4B
I/O ports: 18
Input ports: 8
(Including 4 analog
input pins.)
One Time PROM version
32P2W-A
32P4B
32P2W-A
42P4B
56P6N-A
42P4B
One Time PROM version*
One Time PROM version
One Time PROM version*
I/O ports: 20
Input ports: 16
(Including 8 analog
input pins.)
16384
384
56P6N-A
42S1B-A
EPROM version
*: Extended operating temperature version.
(As of July, 1996)
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1.19 Built-in PROM version
1.19.1 EPROM mode
The built-in PROM version has the EPROM mode in addition to the same operation modes as those of
the mask ROM version. The EPROM mode permits writing to the built-in PROM and reading from the built-
in PROM. To the built-in PROM, writing, reading and erasing can be performed by the same operations
as those of the M5M27C256K.
Table 1.19.2 shows a pin function in EPROM mode and Figure 1.19.1 to 1.19.6 show a connections in
EPROM mode.
Table 1.19.2 Pin functions in EPROM mode
Built-in PROM version
M5M27C256K
VCC
P33
VCC
VPP
VSS
VSS
P11 to P17, P20 to P23,
P30, P31, P40, P41
P00 to P07
Pin name
A0 to A14
D0 to D7
CE
VREF
P32
OE
(TOP VIEW)
A10
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D7
D6
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
P07
P06
P05
P04
P03
P02
P01
P00
3
A8
A7
D5
4
D4
5
A6
A5
A4
D3
6
D2
7
D1
8
D0
P10
A3
A2
A1
A0
9
A14
A13
VPP
OE
A12
A11
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
P40
10
11
12
13
14
15
16
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
CE
XIN
XOUT
VSS
VSS
VCC
VSS
Outline 32P4B
: Same functions as M5M27C256K
Fig. 1.19.1 Pin connection in EPROM mode of 7470 group
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1.19 Built-in PROM version
(TOP VIEW)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
P53
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
P52
P07
P06
P05
P04
P03
P02
P01
P00
P43
P42
P41
A10
A9
A8
A7
A6
A5
A4
D7
D6
D5
D4
D3
D2
D1
D0
3
4
5
6
7
8
9
P10
10
11
12
13
14
15
16
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
A14
A13
VPP
P40
A3
A2
A1
A0
CE
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
P51/XCOUT
P50/XCIN
VCC
OE
A12
A11
17
18
19
20
21
XIN
XOUT
VSS
VSS
VCC
VSS
Outline 42P4B (Note)
42S1B-A (M37471E8SS)
: Same functions as M5M27C256K
Note: The only difference between the 42P4B package product and the 56P6N-A package product
are package shape, absolute maximum ratings and the fact that the 56P6N-A package
product has an AVSS pin.
Fig. 1.19.2 Pin connection in EPROM mode of 7471 group (1)
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HARDWARE
1.19 Built-in PROM version
(TOP VIEW)
45
28
27
26
25
24
23
22
21
20
19
18
17
NC
RESET
NC
46
D
D
D
5
6
7
P0
P0
P0
P5
5
6
7
2
VSS
47
48
49
50
51
52
53
54
55
56
P5
1
/XCOUT
/XCIN
P50
NC
M37471E4-XXXFP
M37471E8-XXXFP
V
V
CC
SS
NC
V
V
CC
VSS
V
SS
SS
P53
AVSS
NC
A10
P1
P1
P1
7
/SRDY
A
A
9
8
6
/CLK
/SOUT
NC
X
X
OUT
IN
5
NC
Outline 56P6N-A (Note)
NC: No connection
: Same functions as M5M27C256K
Note: The only difference between the 42P4B package product and the 56P6N-A package product
are package shape, absolute maximum ratings and the fact that the 56P6N-A package
product has an AVSS pin.
Fig. 1.19.3 Pin connection in EPROM mode of 7471 group (2)
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HARDWARE
1.19 Built-in PROM version
(TOP VIEW)
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
A9
D7
D6
D5
D4
D3
D2
D1
D0
A14
A13
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P07
P06
P05
P04
P03
P02
P01
P00
3
A8
A7
4
5
A6
A5
A4
6
7
8
P10
9
A3
A2
A1
A0
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
P40
10
11
12
13
14
15
16
VPP
OE
A12
A11
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
CE
XIN
XOUT
VSS
VSS
VCC
VSS
Outline 32P4B (Note)
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
A9
D7
D6
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P07
P06
P05
P04
P03
P02
P01
P00
3
A8
A7
D5
4
D4
5
A6
A5
A4
D3
6
D2
7
D1
8
D0
P10
9
A3
A2
A1
A0
A14
A13
VPP
OE
A12
A11
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
P40
10
11
12
13
14
15
16
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
CE
XIN
XOUT
VSS
VCC
VSS
VSS
Outline 32P2W-A (Note)
: Same functions as M5M27C256K
Note: The only difference between the 32P2W-A package product and the 32P4B package
product are package shape, absolute maximum ratings.
Fig. 1.19.4 Pin connection in EPROM mode of 7477 group
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HARDWARE
1.19 Built-in PROM version
(TOP VIEW)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
P53
P52
P07
P06
P05
P04
P03
P02
P01
P00
P43
P42
P41
A10
D7
D6
D5
D4
D3
D2
D1
D0
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
A9
A8
A7
A6
A5
A4
3
4
5
6
7
8
9
P10
10
11
12
13
14
15
16
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
A14
A13
VPP
P40
A3
A2
A1
A0
CE
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
P51/XCOUT
P50/XCIN
VCC
OE
A12
A11
17
18
19
20
21
XIN
XOUT
VSS
VSS
VSS
VCC
Outline 42P4B (Note)
42S1B-A (M37478E8SS)
NC: No connection
: Same functions as M5M27C256K
Note: The only difference between the 42P4B package product and the 56P6N-A package product
are package shape, absolute maximum ratings and the fact that the 56P6N-A package
product has an AVSS pin.
Fig. 1.19.5 Pin connection in EPROM mode of 7478 group (1)
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HARDWARE
1.19 Built-in PROM version
(TOP VIEW)
45
46
47
48
49
50
51
52
53
54
55
56
28
NC
RESET
NC
27
D
D
D
5
6
7
P0
P0
P0
P5
5
6
7
2
V
SS
26
25
24
23
22
21
20
19
18
17
P5
P5
1
/XCOUT
/XCIN
0
NC
V
V
CC
SS
NC
V
V
CC
M37478E8-XXXFP
M37478E8TXXXFP
V
SS
V
SS
SS
P53
AVSS
NC
A
10
P1
P1
P1
7
/SRDY
/SCLK
A
A
9
8
X
X
OUT
6
IN
5
/T
X
D
NC
NC
Outline 56P6N-A (Note)
NC: No connection
: Same functions as M5M27C256K
Note: The only difference between the 42P4B package product and the 56P6N-A package product
are package shape, absolute maximum ratings and the fact that the 56P6N-A package
product has an AVSS pin.
Fig. 1.19.6 Pin connection in EPROM mode of 7478 group (2)
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HARDWARE
1.19 Built-in PROM version
1.19.2 Pin description
Table 1.19.3 to Table 1.19.5 show the description of pin functions in the ordinary mode and the EPROM
mode.
Table 1.19.3 Pin description (1)
Input/
Output
Pin
Name
Functions
Mode
VCC, VSS
Power source
• Apply the following voltage to the VCC pin:
2.7 V to 4.5 V (at f(XIN) = (2.2 VCC–2) MHz) or
4.5 V to 5.5 V (at f(XIN) = 8 MHz).
• Apply 0 V to the VSS pin.
Ordinary
/EPROM
AVSS
VREF
Analog power
source
• Ground level input pin for the A-D converter.
• Apply the same voltage as the VSS pin to the
AVSS pin.
Note:This pin is dedicated to 56P6N-A package
products among the 7471/7478 group.
• Reference voltage input pin for the A-D con-
verter.
Ordinary
/EPROM
Reference
voltage input
Input
Ordinary
• When using the A-D converter, apply VCC/2 (Q2)
to VCC [V].
• When not using the A-D converter, connect to
VCC.
Mode input
Reset input
Input
Input
• VREF works as CE input.
• Reset input pin
EPROM
Ordinary
RESET
• The microcomputer is put into a reset state by
keeping the RESET pin at “L” for 2 ms or more,
and the reset state is released by returning the
RESET pin to “H.”
Reset input
Clock input
Input
Input
• Connect to the VSS pin.
• An input pin and an output pin for the main
clock generating circuit.
EPROM
Ordinary
/EPROM
XIN
• Connect a ceramic resonator or a quartz-crys-
tal oscillator between pins XIN and XOUT.
• A feedback resistor is incorporated between the
XIN and the XOUT pins.
• To use an external clock input, connect the
clock oscillation source to the XIN pin and leave
the XOUT pin open.
XOUT
P00–P07
Clock output
I/O port P0
Output
Ordinary
/EPROM
Input/
output
• Port P0 is an 8-bit I/O port.
Ordinary
EPROM
• The output structure is CMOS output.
• In input mode, a pull-up transistor is connect-
able in units of one bit.
• In input mode, a key-on wake up function is
provided.
Data I/O D0–D7
Input/
• Port P0 works as data I/O (D0 – D7)
output
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HARDWARE
1.19 Built-in PROM version
Table 1.19.4 Pin description (2)
Input/
Output
Input/
output
Pin
Name
Functions
Mode
P10–P17
I/O port P1
• Port P1 is an 8-bit I/O port.
Ordinary
• The output structure is CMOS output.
• In input mode, pull-up transistor can be con-
nected in units of 4-bit.
• Pins P12 and P13 are in common with timer
output pins T0, T1 respectively.
• In the case of the 7470/7471 group, P14 – P17
are in common with serial I/O pins SIN, SOUT,
CLK, SRDY respectively.
• In the case of the 7470/7471 group, the out-
puts of pins SOUT and the SRDY can be N-channel
open drain outputs.
• In the case of the 7477/7478 group, pins
P14 – P17 are in common with serial I/O pins
RXD, TXD, SCLK, SRDY, respectively.
• The P11–P17 pins are address (A4 – A10) input
pins. Put P10 into the open state.
• Port P2 is an 8-bit I/O port.
• The output structure is CMOS output.
• In input mode, pull-up transistor can be con-
nected in units of 4-bit.
Address input
A4–A10
I/O port P2
(7470/7471
group)
Input
EPROM
Ordinary
P20–P27
Input/
output
• Pins P20–P27 are in common with analog input
pins IN0–IN7 respectively.
Note: The 7470 group has only the 4 pins
P20–P23 (IN0–IN3).
Input port P2
(7477/7478
group)
Input
Input
• Port P2 is an 8-bit input port.
• It is impossible to connect a pull-up transistor.
• Pins P20–P27 are in common with analog input
pins IN0–IN7 respectively.
Note: The 7477 group has only the 4 pins
P20–P23 (IN0–IN3) are available.
Address input
A0–A3
• The P20 to P23 pins are address (A0–A3) input
pins.
EPROM
• In the case of the 7471/7478 group, put the
P24–P27 pins into the open state.
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HARDWARE
1.19 Built-in PROM version
Table 1.19.5 Pin description (3)
Input/
Output
Input
Pin
Name
Functions
Mode
P30–P33
Input port P3
• Port P3 is a 4-bit input port.
Ordinary
• Pins P30, P31 are in common with external in-
terrupt input pins INT0, INT1 respectively.
• Pins P32, P33 are in common with timer input
pins CNTR0, CNTR1 respectively.
• The P30 and P31 pins are the address (A11,
A12) input pins.
• The P32 pin becomes an OE input pin.
• The P33 pin is a VPP input pin and VPP is applied
to it when the VPP is input and the program is
verified.
Address input
A11, A12
Mode input
VPP input
Input
EPROM
Ordinary
P40–P43
I/O port P4
Input/
• Port P4 is a 4-bit I/O port.
output
• The output structure is CMOS output.
• In input mode, pull-up transistor can be con-
nected in units of 4-bit.
Note: The 7470/7477 group has only 2 pins P40
and P41.
Address input
A13, A14
Input
Input
• The P40 to P41 pins are the address (A13, A14)
input pins.
• In the case of the 7471/7478 group, put the
P42 and P43 pins into the open state.
• Port P5 is a 4-bit input port.
EPROM
Ordinary
P50–P53
Input port P5
• Pull-up transistor can be connected in units of
4-bit.
• Pins P50, P51 are in common with input/output
pins for sub-clock generating circuit XCIN, XCOUT
respectively.
• When using pins P50 and P51 as pins XCIN
and XCOUT, connect a quartz-crystal oscillator
between pins XCIN and XCOUT.
• When using pins P50 and P51 as pins XCIN
and XCOUT, a feedback resistor is connected
between pins XCIN and XCOUT.
• To use an external clock input, connect the
clock oscillation source to the XCIN pin and leave
the XCOUT pin open.
Note: Only the 7471/7478 group has pins P50
to P53.
Input port P5
Input
• Put this port into the open state.
EPROM
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HARDWARE
1.19 Built-in PROM version
1.19.3 Writing, reading, and erasing to built-in PROM
The built-in PROM version is put into the EPROM mode by applying the “L” level to the RESET pin. Write,
read and erase operations to the built-in PROM in the EPROM mode are described below.
Table 1.19.6 shows input signals in each mode.
(1) Reading
● Apply 0 V to the RESET pin and 5 V to the VCC pin.
● When an address signal (A0-A14) is input and the CE pin and the OE pin are caused to go “L”, the
contents of the PROM appear to data I/O pins (D0-D7).
● The data I/O pins (D0-D7) are put into a floating when either the CE pin or the OE pin is in the “H”
state.
(2) Writing
● Apply 0 V to the RESET pin and 5 V to the VCC pin.
● When the OE pin is caused to go to “H” and VPP is applied to the VPP pin, the program mode is
provided.
● Set an address to the address input pins (A0-A14) and give write data to the data I/O pins (D0-D7)
in parallel.
● In the above condition, a write operation is performed by causing the CE pin to go to “L”.
When using a PROM programmer, specify an address into the following area.
● Address 600016 to address 7FFF16 (for the M3747xE4)
● Address 400016 to address 7FFF16 (for the M3747xE8)
(3) Erasing
● An erase operation is enabled only in the built-in EPROM version with window (M37471E8SS/
M37478E8SS).
● Data can be erased by irradiating ultraviolet rays having a wave length of 2537Å.
2
● The minimum amount of irradiation required for an erase operation is 15 W•s/cm .
Table 1.19.6 Input/Output signal on each mode
Pin
CE
OE
VPP
VCC
VCC
RESET
0 V
D0 to D7
Mode
Reading
Output disable
Writing
Writing verify
Writing disable
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIL
VIH
VCC
VCC
VPP
VPP
VPP
Output
Floating
Input
Output
Floating
Note: VIL denotes an “L” input voltage and VIH denotes an “H” input voltage.
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HARDWARE
1.19 Built-in PROM version
1.19.4 Notes on use
The notes on using the built-in PROM version are shown below.
(1) All built-in PROM version products
■ Precautions at write operation
● Be careful not to apply an overvoltage to pins because a high voltage is used for a write
operation. Exercise special care when turning on the power supply.
● For writing the contents of the PROM, use a dedicated programming adapter. This permits using
a general-purpose PROM programmer for writing data. For details of dedicated programming
adapters, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data
book.
■ Precautions at read operation
● When reading the contents of the PROM, use a dedicated programming adapter, so that reading
can be performed by a general-purpose PROM programmer. For details of dedicated programming
adapters, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data
book.
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HARDWARE
1.19 Built-in PROM version
(2) One Time PROM version
■ Precautions before use
● The PROM of the One Time PROM version is
not tested or screened in the assembly process
and following processes. To ensure proper
operation after programming, the procedure
shown in Figure 1.19.7 is recommended to
verify programming.
Programming with PROM programmer
Screening (Caution)
(Leave at 150°C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher
than the storage temperature. Never expose to
150°C exceeding 100 Hours.
Fig. 1.19.7 Programming and testing of One
Time PROM version
(3) Built-in EPROM version
■ Precautions on erasing
● Sunlight and fluorescent light include light that may erase the information written in the built-in
PROM. When using the built-in EPROM version in the read mode, be sure to cover the transparent
glass portion with a seal.
● This seal to cover the transparent glass portion is prepared on our side. Be careful not to bring
the seal into contact with the microcomputer lead wires when covering the portion with the seal
because this seal is made of metal (aluminum).
● Before erasing data, clean the transparent glass. If any finger stain or seal adhesive is stuck to
the transparent glass, this prevents ultraviolet rays from passing, thereby affecting the erase
characteristic adversely.
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HARDWARE
1.20 Emulator MCU
1.20 Emulator MCU
The M37471RSS and the M37478RSS are emulator MCUs for the 7470/7471/7477/7478 group software
development. When an emulator is connected to the socket on the top surface, user program debugging
can be performed efficiently by using a real-time trace function, etc.
It is possible to monitor every internal bus information through the emulator because 16 address bus
signals, two-way data bus signals and SYNC, RD, WR and f signals are output from the socket on the top
surface.
In the debug system using the M37471RSS and the M37478RSS, the MCU pins for emulator are directly
connected to the user system. This permits debugging in a condition similar to a real mounting condition.
For details of development support systems for the M37471RSS and the M37478RSS, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTER” data book.
Figure 1.20.1 shows a pin connection diagram of the M37471RSS and M37478RSS.
PIN CONFIGURATION (TOP VIEW)
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P53
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
P52
P07
P06
P05
P04
P03
P02
P01
P00
P43
P42
P41
2
3
(Note 1)
4
5
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CNVSS2
A12
VCC2
A14
A13
A8
6
7
3
A7
8
4
A6
5
9
A5
A9
P10
10
11
12
13
14
15
16
17
18
19
20
21
6
A4
A11
φ
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
7
A3
8
A2
A10
S
9
A1
P40
(Note 2)
10
11
12
13
14
A0
D7
D6
D5
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
P51/XCOUT
P50/XCIN
VCC
D0/RD
D1/WR
D2/SYNC D4/A15
VSS2 D3/A14
XIN
M37471RSS(Note 3)
M37478RSS
XOUT
VSS
Outline 42S1M
Notes 1: In the case of the M37478RSS, the pins CLK, SOUT, SIN shown in this
figure function as the pins SCLK , TxD, RxD respectively.
2: In the case of the M37478RSS, the pins P20/IN0–P27/IN7 shown in this
figure function as the input pins.
3: The power source voltage of the M37471RSS and the M37478RSS is 5 V±5 %.
Fig. 1.20.1 Pin configuration of M37471RSS and M37478RSS
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HARDWARE
1.21 Electrical characteristics
1.21 Electrical characteristics
1.21.1 Electrical characteristics
(1) 7470 group electrical characteristics
Table 1.21.1 shows the absolute maximum ratings of the 7470 group. Table 1.21.2 shows the
recommended operating conditions. Table 1.21.3 shows the electrical characteristics.
Table 1.21.4 shows the A-D converter characteristics.
Table 1.21.1 Absolute maximum ratings (7470 group)
Symbol
VCC
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage
Conditions
Ratings
Unit
V
V
–0.3 to +7
All voltages are based on VSS.
Output transistors are cut-off.
Ta = 25 °C
–0.3 to VCC+0.3
–0.3 to VCC+0.3
1000
–20 to +85
–40 to +150
Output voltage
V
Power dissipation
Operating temperature
Storage temperature
mW
°C
°C
Table 1.21.2 Recommended operating conditions (7470 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
Parameter
Unit
Min.
4.5
2.7
Max.
5.5
4.5
f(XIN) = 8.0 MHz
f(XIN) = (2.2VCC–2.0 )MHz
V
V
V
VCC
Power source voltage
Power source voltage
VSS
0
VIH
VIH
VIH
“H” input voltage P00 to P07, P10 to P17, P30 to P33
“H” input voltage P20 to P23, P40, P41
“H” input voltage XIN, RESET
0.8VCC
0.7VCC
0.8VCC
VCC
VCC
VCC
V
V
V
VIL
VIL
VIL
VIL
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
“L” input voltage P00 to P07, P10 to P17, P30 to P33
“L” input voltage P20 to P23, P40, P41
“L” input voltage XIN
0
0
0
0
0.2VCC
0.25VCC
0.16VCC
0.12VCC
–30
–30
60
60
V
V
V
V
mA
mA
mA
mA
“L” input voltage RESET
“H” sum output current of P00 to P07 and P40 and P41
“H” sum output current of P10 to P17 and P20 to P23
“L” sum output current of P00 to P07, P40 and P41
“L” sum output current of P10 to P17 and P20 to P23
“H” peak output current
P00 to P07, P10 to P17, P20 to P23, P40, P41
“L” peak output current
P00 to P07, P10 to P17, P20 to P23, P40, P41
“H” average output current
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
–10
20
mA
mA
mA
mA
–5
P00 to P07, P10 to P17, P20 to P23, P40, P41 (Note 1)
“L” average output current
P00 to P07, P10 to P17, P20 to P23, P40, P41 (Note 1)
10
Timer input frequency
f(XIN) = 8 MHz
MHz
MHz
2
1
f(CNTR)
CNTR0 (P32),
f(XIN) = 4 MHz
CNTR1 (P33) (Note 2)
f(XIN) = 8 MHz
f(XIN) = 4 MHz
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
MHz
MHz
MHz
MHz
Serial I/O clock input frequency
CLK (P16) (Note 2)
Clock input oscillation frequency
(Note 2)
2
1
8
f(CLK)
f(XIN)
2.2VCC–2.0
Notes 1: The average output current IOH (avg) or IOL (avg) are the average value during a 100 ms.
2: The oscillation frequency is at 50 % duty cycle.
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1.21 Electrical characteristics
Table 1.21.3 Electrical characteristics (7470 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
3.0
Max.
“H” output voltage
P00 to P07, P10 to P17
P20 to P23, P40, P41
“L” output voltage
P00 to P07, P10 to P17
P20 to P23, P40, P41
Hysteresis P00 to P07
P30 to P33
VCC = 5 V, IOH = –5 mA
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
V
V
V
V
VOH
2.0
2.0
1.0
VOL
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
0.5
0.3
0.5
0.3
0.5
0.3
V
V
V
V
V
VT+ – VT–
VT+ – VT– Hysteresis RESET
Hysteresis P14/SIN
VT+ – VT–
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
Use as SIN or CLK
P16/CLK
V
VI = 0 V
–5
–3
–1.0
–0.35
–5
–3
–5
–3
µA
µA
mA
mA
µA
µA
µA
µA
mA
mA
µA
µA
“L” input current
P00 to P07, P10 to P17
P30 to P32, P40, P41
Not use pull-up transistor
VI = 0 V
Use pull-up transistor
IIL
IIL
IIL
–0.25
–0.08
–0.5
–0.18
“L” input current P33
VI = 0 V
VI
= 0 V, not use pull-up tran- VCC = 5 V
sistor, not use as analog input VCC = 3 V
= 0 V, use pull-up transistor, VCC = 5 V
not use as analog input
VI = 0 V
“L” input current
P20 to P23
VI
–0.25
–0.08
–0.5
–0.18
–1.0
–0.35
–5
VCC = 3 V
VCC = 5 V
VCC = 3 V
“L” input current
XIN, RESET
IIL
XIN is at stop mode
–3
“H” input current
P00 to P07, P10 to P17
P30 to P32, P40, P41
µA
µA
VCC = 5 V
VCC = 3 V
5
3
VI = VCC
Not use pull-up transistor
IIH
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
VCC = 5 V
VCC = 3 V
= VCC, not use pull-up tran- VCC = 5 V
5
3
5
3
5
3
14
7
3.6
15
8
4
4
2
1
1
10
5.5
IIH
IIH
IIH
“H” input current P33
VI = VCC
“H” input current
P20 to P23
“H” input current
XIN, RESET
VI
sistor, not use as analog input VCC = 3 V
VI = VCC
XIN is at stop mode
At system op-
eration,
A-D conversion
is not executed
VCC = 5 V
VCC = 3 V
f(XIN) = 8 MHz
7
3.5
1.8
7.5
4
2
2
1
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
f(XIN) = 4 MHz
At system op- f(XIN) = 8 MHz
eration,
A-D conversion
f(XIN) = 4 MHz
is executed
ICC
Power source current
RAM retention voltage
f(XIN) = 8 MHz
At wait mode
f(XIN) = 4 MHz
VCC = 3 V
Ta = 25 °C
Ta = 85 °C
0.5
0.1
1
At stop mode VCC = 5 V
Stop all oscillation
VRAM
2.0
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1.21 Electrical characteristics
Table 1.21.4 A-D converter characteristics (7470 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20
°C to +85
°C, f(XIN) = 4 MHz, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Resolution
Non-linearity error
Differential non-linearity error
Test conditions
Min.
Typ.
Max.
8
bits
LSB
LSB
LSB
LSB
LSB
LSB
µs
—
—
—
±2
±0.9
2
3
4
7
12.5
25
V
V
V
CC = VREF = 5.12 V, IOL(sum) = 0 mA
CC = VREF = 3.072 V, IOL(sum) = 0 mA
CC = VREF = 5.12 V
Zero transition error
Full scale transition error
Conversion time
VOT
VFST
VCC = VREF = 3.072 V
f(XIN) = 8 MHz
f(XIN) = 4 MHz
TCONV
VREF
µs
0.5VCC
(Note)
Reference input voltage
VCC
V
Ladder resistance value
Analog supply voltage
2
0
5
10
VREF
kΩ
V
RLADDER
VIA
Note: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect
it to VCC.
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1.21 Electrical characteristics
(2) 7471 group electrical characteristics
Table 1.21.5 shows the absolute maximum ratings of the 7471 group. Table 1.21.6 shows the
recommended operating conditions. Table 1.21.7 shows the electrical characteristics.
Table 1.21.8 shows the A-D converter characteristics.
Table 1.21.5 Absolute maximum ratings (7471 group)
Symbol
VCC
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage
Conditions
All voltages are based on VSS.
Output transistors are cut-off.
Ta = 25 °C
Ratings
Unit
V
V
–0.3 to +7
–0.3 to VCC+0.3
–0.3 to VCC+0.3
1000 (Note)
Output voltage
V
Power dissipation
Operating temperature
Storage temperature
mW
°C
°C
–20 to +85
–40 to +150
Note: The rating is 500 mW for the 56P6N-A package product.
Table 1.21.6 Recommended operating conditions (7471 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
Parameter
f(XIN) = 8.0 MHz
f(XIN) = (2.2VCC–2.0) MHz
Unit
Min.
4.5
2.7
Max.
5.5
4.5
V
V
VCC
Power source voltage
VSS
AVSS
VIH
VIH
VIH
Power source voltage
Analog supply voltage
“H” input voltage P00 to P07, P10 to P17, P30 to P33
“H” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1)
“H” input voltage XIN, RESET
0
0
V
V
V
V
0.8VCC
0.7VCC
0.8VCC
VCC
VCC
VCC
V
VIL
VIL
VIL
VIL
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
“L” input voltage P00 to P07, P10 to P17, P30 to P33
“L” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1)
“L” input voltage XIN
0
0
0
0
0.2VCC
0.25VCC
0.16VCC
0.12VCC
–30
–30
60
60
V
V
V
V
mA
mA
mA
mA
“L” input voltage RESET
“H” sum output current of P00 to P07 and P40 to P43
“H” sum output current of P10 to P17 and P20 to P27
“L” sum output current of P00 to P07 and P40 to P43
“L” sum output current of P10 to P17 and P20 to P27
“H” peak output current
P00 to P07, P10 to P17, P20 to P27, P40 to P43
“L” peak output current
P00 to P07, P10 to P17, P20 to P27, P40 to P43
“H” average output current
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
–10
20
mA
mA
mA
mA
–5
P00 to P07, P10 to P17, P20 to P27, P40 to P43 (Note 2)
“L” average output current
P00 to P07, P10 to P17, P20 to P27, P40 to P43 (Note 2)
10
Timer input frequency
CNTR0 (P32)
CNTR1 (P33) (Note 3)
Serial I/O clock input frequency f(XIN) = 8 MHz
CLK (P16) (Note 3) f(XIN) = 4 MHz
Clock input oscillation frequency VCC = 4.5 V to 5.5 V
(Note 3) VCC = 2.7 V to 4.5 V
Sub-clock input oscillation frequency (Note 3, 4)
f(XIN) = 8 MHz
2
1
MHz
MHz
f(CNTR)
f(CLK)
f(XIN) = 4 MHz
2
1
MHz
MHz
MHz
MHz
kHz
8
2.2VCC–2.0
50
f(XIN)
f(XCIN)
32
Notes 1: Except when P50 is used as XCIN.
2: The average output current IOH(avg) or IOL(avg) are the average value during a 100 ms.
3: The oscillation frequency is at 50 % duty cycle.
4: Set f(XCIN) < f(XIN)/3 when the sub-clock is used.
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1.21 Electrical characteristics
Table 1.21.7 Electrical characteristics (7471 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20 °C to +85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
3.0
Max.
“H” output voltage
VCC = 5 V, IOH = –5 mA
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
V
V
V
V
VOH
P00 to P07, P10 to P17
P20 to P27, P40 to P43
“L” output voltage
P00 to P07, P10 to P17
P20 to P27, P40 to P43
Hysteresis P00 to P07
P30 to P33
2.0
2.0
1.0
VOL
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
0.5
0.3
0.5
0.3
0.5
0.3
V
V
V
V
V
VT+ – VT–
VT+ – VT– Hysteresis RESET
Hysteresis P14/SIN
VT+ – VT–
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
When used as SIN or CLK
P16/CLK
“L” input current
P00 to P07, P10 to P17
P30 to P32, P40 to P43
V
VI = 0 V
–5
–3
–1.0
–0.35
–5
–3
–5
–3
µA
µA
mA
mA
µA
µA
µA
µA
mA
mA
µA
µA
Not use pull-up transistor
VI = 0 V
Use pull-up transistor
IIL
–0.25
–0.08
–0.5
–0.18
P50 to P53
IIL
IIL
IIL
IIH
“L” input current P33
VI = 0V
V
I
= 0 V, not use pull-up tran- VCC = 5 V
sistor, not use as analog input VCC = 3 V
= 0 V, use pull-up transis- VCC = 5 V
tor, not use as analog input VCC = 3 V
“L” input current
P20 to P27
V
I
–0.25
–0.08
–0.5
–0.18
–1.0
–0.35
–5
“L” input current
XIN, RESET
“H” input current
P00 to P07, P10 to P17
P30 to P32, P40 to P43
P50 to P53
VI = 0 V
VCC = 5 V
VCC = 3 V
XIN is at stop mode
–3
VCC = 5 V
VCC = 3 V
5
3
µA
µA
VI = VCC
Not use pull-up transistor
VCC = 5 V
VCC = 3 V
= VCC, not use pull-up tran- VCC = 5 V
5
3
5
3
5
3
14
7
3.6
15
8
µA
µA
µA
µA
µA
IIH
IIH
IIH
“H” input current P33
VI = VCC
“H” input current
P20 to P27
“H” input current
XIN, RESET
V
I
sistor, not use as analog input VCC = 3 V
VI = VCC
XIN is at stop mode
At system op-
eration,
A-D conversion
is not executed
VCC = 5 V
VCC = 3 V
µA
f(XIN) = 8 MHz
7
mA
mA
mA
mA
mA
mA
VCC = 5 V
VCC = 3 V
VCC = 5 V
3.5
1.8
7.5
4
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
At system op-
eration,
A-D conversion
is executed
VCC = 3 V
VCC = 5 V
2
4
In low-speed mode, Ta = 25°C, low-power mode
f(XCIN) = 32 kHz
At A-D conversion is not executed
f(XIN) = 8 MHz
30
15
80
40
µA
µA
VCC = 3 V
VCC = 5 V
ICC
Power source current
2
1
0.5
4
2
1
mA
mA
mA
At wait mode
f(XIN) = 4 MHz
VCC = 3 V
VCC = 5 V
At wait mode, Ta = 25°C,
low-power mode, f(XCIN) =
32 kHz
µA
3
2
12
8
µA
VCC = 3 V
µA
µA
V
Ta = 25 °C
Ta = 85 °C
0.1
1
1
10
5.5
At stop mode, VCC = 5 V
Stop all oscillation
VRAM
RAM retention voltage
2.0
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1.21 Electrical characteristics
Table 1.21.8 A-D converter characteristics (7471 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20
°C to +85
°C, f(XIN) = 4 MHz, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Resolution
Non-linearity error
Differential non-linearity error
Test conditions
Min.
Typ.
Max.
8
bits
LSB
LSB
LSB
LSB
LSB
LSB
µs
—
—
—
±2
±0.9
2
3
4
7
12.5
25
V
V
CC = VREF = 5.12 V, IOL(sum) = 0 mA
CC = VREF = 3.072 V, IOL(sum) = 0 mA
V = VREF = 5.12 V
Zero transition error
Full scale transition error
Conversion time
VOT
VFST
VCC = VREF = 3.072 V
f(XIN) = 8 MHz
f(XIN) = 4 MHz
TCONV
VREF
µs
0.5VCC
(Note)
Reference input voltage
VCC
V
Ladder resistance value
Analog input voltage
2
0
5
10
VREF
kΩ
V
RLADDER
VIA
Note: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect
it to VCC.
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1.21 Electrical characteristics
(3) 7477 group electrical characteristics
Table 1.21.9 shows the absolute maximum ratings of the 7477 group. Table 1.21.10 shows the
recommended operating conditions. Table 1.21.11 shows the electrical characteristics.
Table 1.21.12 shows the A-D converter characteristics.
Table 1.21.9 Absolute maximum ratings (7477group)
Symbol
VCC
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage
Conditions
All voltages are based on VSS.
Output transistors are cut-off.
Ta = 25 °C
Ratings
Unit
V
V
–0.3 to +7
–0.3 to VCC+0.3
–0.3 to VCC+0.3
1000 (Note 1)
–20 to +85 (Note 2)
–40 to +150 (Note 3)
Output voltage
V
Power dissipation
Operating temperature
Storage temperature
mW
°C
°C
Notes 1: The rating is 500 mW for the 32P2W-A package product.
2: –40 °C to +85 °C for extended operating temperature version.
3: –65 °C to +150 °C for extended operating temperature version.
Table 1.21.10 Recommended operating conditions (7477 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20
°C to +85
°C(Note 1), unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
4.5
2.7
Typ.
5.0
Max.
5.5
f(XIN) = 8.0 MHz
f(XIN) = (2.2VCC–2.0) MHz
V
V
VCC
Power source voltage
Power source voltage
4.5
VSS
0
V
VIH
VIH
VIH
“H” input voltage P00 to P07, P10 to P17, P30 to P33
“H” input voltage P20 to P23, P40, P41
“H” input voltage XIN, RESET
0.8VCC
0.7VCC
0.8VCC
VCC
VCC
VCC
V
V
V
VIL
VIL
VIL
VIL
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
“L” input voltage P00 to P07, P10 to P17, P30 to P33
“L” input voltage P20 to P23, P40, P41
“L” input voltage XIN
0
0
0
0
0.2VCC
0.25VCC
0.16VCC
0.12VCC
–30
–30
60
60
V
V
V
V
mA
mA
mA
mA
“L” input voltage RESET
“H” sum output current P00 to P07, P40 and P41
“H” sum output current P10 to P17
“L” sum output current P00 to P07, P40 and P41
“L” sum output current P10 to P17
“H” peak output current
P00 to P07, P10 to P17, P40, P41
“L” peak output current
P00 to P07, P10 to P17, P40, P41
“H” average output current
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
f(CNTR)
–10
20
mA
mA
mA
mA
–5
P00 to P07, P10 to P17, P40, P41 (Note 2)
“L” average output current
P00 to P07, P10 to P17, P40, P41 (Note 2)
10
Timer input frequency
CNTR (P3 ), CNTR (P3
f(XIN) = 8 MHz
) (Note 3) f(XIN) = 4 MHz
2
1
500
250
2
1
8
MHz
MHz
kHz
0
2
1
3
Use as clock synchro- f(XIN) = 8 MHz
Serial I/O clock input frequency nous serial I/O mode f(XIN) = 4 MHz
kHz
f(SCLK)
SCLK (P16) (Note 3)
Use as UART f(XIN) = 8 MHz
mode f(XIN) = 4 MHz
MHz
MHz
MHz
MHz
Clock input oscillation frequency
(Note 3)
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
f(XIN)
2.2VCC–2.0
Notes 1: –40 °C to +85 °C for extended operating temperature version.
2: The average output current IOH (avg) or IOL (avg) are the average value during a 100 ms.
3: The oscillation frequency is at 50 % duty cycle.
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HARDWARE
1.21 Electrical characteristics
Table 1.21.11 Electrical characteristics (7477 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20
°C to +85
°C(Note), unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
“H” output voltage
P00 to P07, P10 to P17
P40, P41
“L” output voltage
P00 to P07, P10 to P17
P40, P41
VCC = 5 V, IOH = –5 mA
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
3.0
2.0
V
V
V
V
VOH
2.0
1.0
VOL
Hysteresis P00 to P07
P30 to P33
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
0.5
0.3
0.5
0.3
0.5
0.3
V
V
V
V
V
VT+ – VT–
VT+ – VT– Hysteresis RESET
Hysteresis P14/RxD
VT+ – VT–
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
When used as RxD or SCLK
P16/SCLK
V
VI = 0 V
Not use pull-up transistor
VI = 0 V
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
µA
µA
mA
mA
µA
µA
µA
µA
µA
µA
“L” input current
P00 to P07, P10 to P17
P30 to P32, P40, P41
IIL
–0.25
–0.08
–0.5
–0.18
Use pull-up transistor
IIL
IIL
IIL
“L” input current P33
VI = 0V
“L” input current
P20 to P23
“L” input current
XIN, RESET
VI = 0 V,
Not use as analog input
VI = 0 V
XIN is at stop mode
–3
“H” input current
P00 to P07, P10 to P17
P30 to P32, P40, P41
µA
µA
VCC = 5 V
VCC = 3 V
5
3
VI = VCC
Not use pull-up transistor
IIH
µA
µA
µA
µA
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
5
3
5
3
5
3
14
7
3.6
15
8
4
4
2
1
1
10
5.5
IIH
IIH
IIH
“H” input current P33
VI = VCC
“H” input current
P20 to P23
“H” input current
XIN, RESET
VI = VCC
Not use as analog input
VI = VCC
XIN is at stop mode
At system op-
eration,
A-D conversion
is not executed
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
f(XIN) = 8 MHz
7
3.5
1.8
7.5
4
2
2
1
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
f(XIN) = 4 MHz
At system op-
f(XIN) = 8 MHz
eration,
A-D conversion
is executed
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
ICC
Power source current
RAM retention voltage
At wait mode
VCC = 3 V
Ta = 25 °C
Ta = 85 °C
0.5
0.1
1
At stop mode, VCC = 5 V
Stop all oscillation
VRAM
2.0
Note: –40 °C to +85 °C for extended operating temperature version.
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Table 1.21.12 A-D converter characteristics (7477 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = –20 °C to +85 °C(Note 1), unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Resolution
Test conditions
Unit
Min.
Max.
8
±3
12.5
25
bits
LSB
µs
—
—
Absolute accuracy
V
V
CC = 4.5 V to 5.5 V, f(XIN) = 8 MHz
CC = 2.7 V to 5.5 V, f(XIN) = 4 MHz
Conversion time
TCONV
µs
0.5VCC
(Note 2)
Reference input voltage
VCC
V
VREF
5
Ladder resistance value
Analog input voltage
2
0
10
VREF
kΩ
V
RLADDER
VIA
Notes 1: –40 °C to +85 °C for extended operating temperature version.
2: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect
it to VCC.
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1.21 Electrical characteristics
(4) 7478 group electrical characteristics
Table 1.21.13 shows the absolute maximum ratings of the 7478 group. Table 1.21.14 shows the
recommended operating conditions. Table 1.21.15 shows the electrical characteristics.
Table 1.21.16 shows the A-D converter characteristics.
Table 1.21.13 Absolute maximum ratings (7478 group)
Symbol
VCC
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage
Conditions
All voltages are based on VSS.
Output transistors are cut-off.
Ta = 25 °C
Ratings
Unit
V
V
–0.3 to +7
–0.3 to VCC+0.3
–0.3 to VCC+0.3
1000 (Note 1)
–20 to +85 (Note 2)
–40 to +150 (Note 3)
Output voltage
V
Power dissipation
Operating temperature
Storage temperature
mW
°C
°C
Notes 1: The rating is 500 mW for the 56P6N-A package product.
2: –40 °C to +85 °C for extended operating temperature version.
3: –65 °C to +150 °C for extended operating temperature version.
Table 1.21.14 Recommended operating conditions (7478 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20
°C to +85
°C(Note 1), unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
4.5
2.7
Typ.
5.0
Max.
5.5
f(XIN) = 8.0 MHz
f(XIN) =(2.2VCC–2.0) MHz
V
V
VCC
Power source voltage
4.5
VSS
AVSS
VIH
VIH
VIH
Power source voltage
Analog supply voltage
“H” input voltage P00 to P07, P10 to P17, P30 to P33
“H” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 2)
“H” input voltage XIN, RESET
0
0
V
V
V
V
0.8VCC
0.7VCC
0.8VCC
VCC
VCC
VCC
V
VIL
VIL
VIL
VIL
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
“L” input voltage P00 to P07, P10 to P17, P30 to P33
“L” input voltage P20 to P27, P40 to P43, P50 to P53 (Note 2)
“L” input voltage XIN
0
0
0
0
0.2VCC
0.25VCC
0.16VCC
0.12VCC
–30
–30
60
60
V
V
V
V
mA
mA
mA
mA
“L” input voltage RESET
“H” sum output current of P00 to P07 and P40 to P43
“H” sum output current of P10 to P17
“L” sum output current of P00 to P07 and P40 toP43
“L” sum output current of P10 to P17
“H” peak output current
P00 to P07, P10 to P17, P40 to P43
“L” peak output current
P00 to P07, P10 to P17, P40 to P43
“H” average output current
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
f(CNTR)
–10
20
mA
mA
mA
mA
–5
P00 to P07, P10 to P17, P40 to P43 (Note 3)
“L” average output current
P00 to P07, P10 to P17, P40 to P43 (Note 3)
10
Timer input frequency
CNTR (P3 ), CNTR (P3
f(XIN) = 8 MHz
) (Note 4) f(XIN) = 4 MHz
2
1
500
250
2
1
MHz
MHz
kHz
0
2
1
3
Use as clock synchro- f(XIN) = 8 MHz
Serial I/O clock input frequency nous serial I/O mode f(XIN) = 4 MHz
SCLK (P16) (Note 4) Use as UART f(XIN) = 8 MHz
mode f(XIN) = 4 MHz
Clock input oscillation frequency VCC = 4.5 V to 5.5 V
(Note 4) VCC = 2.7 V to 4.5 V
Sub-clock input oscillation frequency (Notes 4, 5)
kHz
f(SCLK)
MHz
MHz
MHz
MHz
kHz
8
2.2VCC–2.0
50
f(XIN)
f(XCIN)
32
Notes 1: –40 °C to +85 °C for extended operating temperature version.
2: Except when P50 is used as XCIN.
3: The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms.
4: The oscillation frequency is at 50 % duty cycle.
5: Set f(XCIN) < f(XIN)/3 when the sub-clock is used.
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1.21 Electrical characteristics
Table 1.21.15 Electrical characteristics (7478 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20
°C to +85
°
C(Note), unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
“H” output voltage
P00 to P07, P10 to P17
P40 to P43
“L” output voltage
P00 to P07, P10 to P17
P40 to P43
VCC = 5 V, IOH = –5 mA
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
3.0
2.0
V
V
V
V
VOH
2.0
1.0
VOL
Hysteresis P00 to P07
P30 to P33
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
0.5
0.3
0.5
0.3
0.5
0.3
V
V
V
V
V
V
µA
µA
VT+ – VT–
VT+ – VT– Hysteresis RESET
Hysteresis P14/RxD
VT+ – VT–
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
When used as RxD or SCLK
P16/SCLK
“L” input current
P00 to P07, P10 to P17
P30 to P32, P40 to P43
P50 to P53
VI = 0 V
Not use pull-up transistor
VI = 0 V
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
IIL
–0.25
–0.08
–0.5
–0.18
mA
mA
µA
µA
µA
µA
µA
µA
Use pull-up transistor
IIL
IIL
IIL
“L” input current P33
VI = 0V
“L” input current
P20 to P27
“L” input current
XIN, RESET
VI = 0 V
Not use as analog input
VI = 0 V
XIN is at stop mode
–3
“H” input current
P00 to P07, P10 to P17
P30 to P32, P40 to P43
P50 to P53
VCC = 5 V
VCC = 3 V
5
3
µA
µA
VI = VCC,
Not use pull-up transistor
IIH
5
3
5
3
5
3
14
7
3.6
15
8
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
IIH
IIH
IIH
“H” input current P33
VI = VCC
“H” input current
P20 to P27
“H” input current
XIN, RESET
VI = VCC
Not use as analog input
VI = VCC
XIN is at stop mode
At system op-
f(XIN) = 8 MHz
eration,
7
VCC = 5 V
VCC = 3 V
VCC = 5 V
A-D conversion
is not executed f(XIN) = 4 MHz
3.5
1.8
7.5
4
At system op- f(XIN) = 8 MHz
eration,
A-D conversion
f(XIN) = 4 MHz
is executed
VCC = 3 V
VCC = 5 V
2
4
At low-speed mode,
power mode, (XCIN
T
a
=
25°C, low-
30
15
80
40
µA
µA
f
)
=
32 kHz, A-D
VCC = 3 V
VCC = 5 V
ICC
Power source current
conversion is not executed
f(XIN) = 8 MHz
2
1
0.5
4
2
1
mA
mA
mA
At wait mode
f(XIN) = 4 MHz
VCC = 3 V
VCC = 5 V
At wait mode, Ta = 25°C, low-
power mode, f (XCIN) = 32
kHz
µA
µA
3
2
12
8
VCC = 3 V
µA
µA
V
Ta = 25 °C
Ta = 85 °C
0.1
1
1
10
5.5
At stop mode, VCC = 5 V
Stop all oscillation
VRAM
RAM retention voltage
2.0
Note: –40 °C to +85 °C for extended operating temperature version.
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Table 1.21.16 A-D converter characteristics (7478 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20
°C to +85
°C(Note 1), unless otherwise noted)
Limits
Unit
Symbol
Parameter
Resolution
Test conditions
Min.
Typ.
Max.
8
bits
LSB
µs
—
—
Absolute accuracy
±3
12.5
25
VCC = 4.5 V to 5.5 V, f(XIN) = 8 MHz
VCC = 2.7 V to 5.5 V, f(XIN) = 4 MHz
Conversion time
TCONV
µs
0.5VCC
(Note 2)
Reference input voltage
VCC
V
VREF
Ladder resistance value
Analog input voltage
2
0
10
VREF
kΩ
V
RLADDER
VIA
5
Notes 1: –40 °C to +85 °C for extended operating temperature version.
2: Set the VREF voltage to 0.5 V or more and 2 V or more. When using no A-D converter, connect
it to VCC.
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1.21 Electrical characteristics
1.21.2 Timing requirements, switching characteristics
(1) 7470/7471 group timing requirements, switching characteristics
Table 1.21.17 shows the timing requirements and switching characteristics of the 7470/7471 group.
Figure 1.21.1 shows the timing chart.
Table 1.21.17 Timing requirements and switching characteristics (7470/7471 group)
(VCC = 4.0 V to 5.5 V, VSS = 0V, Ta = –20
°C to +85
°C, f(XIN) = 4 MHz)
Limits
Typ.
Symbol
tc(CLK)
tWH(CLK)
tWL(CLK)
tsu(SIN–CLK)
th(CLK-SIN)
td(CLK-SOUT)
Parameter
Unit
Min.
1000
400
400
200
200
Max.
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input set up time
ns
ns
ns
ns
ns
Serial I/O input hold time
Serial I/O output delay time
150
ns
tc(CLK)
tWL(CLK)
tWH(CLK)
0.8VCC
0.8VCC
0.8VCC
CLK
0.2VCC
0.2VCC
su(SIN-CLK)
t
th(CLK-SIN)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
SIN
td(CLK-SOUT)
S
OUT
Fig. 1.21.1 Timing chart (7470/7471 group)
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1.21 Electrical characteristics
(2) 7477/7478 group timing requirements, switching characteristics
Table 1.21.18 shows the timing requirements and switching characteristics of the 7477/7478 group.
Figure 1.21.2 shows the timing chart.
Table 1.21.18 Timing requirements and switching characteristics (7477/7478 group)
(VCC = 4.5 V to 5.5 V, VSS = 0V, Ta = –20 °C to +85°C(Note), f(XIN) = 8 MHz)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2000
880
880
160
80
Max.
100
tc(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RXD–SCLK)
th(SCLK-RXD)
td(SCLK-TXD)
tc(SCLK)
tWH(SCLK)
tWL(SCLK)
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input set up time
Serial I/O input hold time
Serial I/O output delay time
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
500
220
220
Note: –40 °C to +85 °C for extended operating temperature version.
tc(SCLK)
tWL(SCLK)
t
WH(SCLK)
0.8VCC
0.8VCC
0.8VCC
S
CLK
0.2VCC
0.2VCC
D-SCLK
t
su(RX
)
th(SCLK-RXD)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
R
X
D
D
td
(SCLK-T
X
D)
TX
Fig. 1.21.2 Timing chart (7477/7478 group)
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1.21 Electrical characteristics
1.21.3 Power source current standard characteristics
The power source current standard characteristics described in this section are mentioned as an characteristic
example of the 7470/7471/7477/7478 group but not guaranteed by us. For standard values, refer to
“1.21.1 Electrical characteristics.”
Figure 1.21.3 shows the power source current standard characteristics measuring circuit.
1
In ordinary mode (f(XIN) = 8 MHz, 4 MHz)
2 In low-speed mode (f(XCIN) = 32 kHz, 7471/7478 group)
M3747x
M3747x
ICC
ICC
VCC
VCC
VSS
VSS
A
A
XIN XOUT
XCIN XCOUT
0 V to 5.5 V
0 V to 5.5 V
Fig. 1.21.3 Power source current standard characteristics measuring circuit
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1.21 Electrical characteristics
(1) 7470/7471 group power source current standard characteristics
Figure 1.21.4 to Figure 1.21.6 show the ICC - VCC characteristics of the 7470/7471 group.
[Measuring condition : 25 °C, f(X IN) = 8 MHz]
9.0
8.0
In ordinary mode
7.0
6.0
5.0
4.0
3.0
2.0
In wait mode
1.0
In stop mode
6.0
0.0
2.0
3.0
4.0
5.0
7.0
Power source voltage VCC [V]
Fig. 1.21.4 ICC – VCC characteristics (f(XIN) = 8 MHz, 7470/7471 group)
[Measuring condition : 25 °C, f(XIN) = 4 MHz]
5.0
In ordinary mode
4.0
3.0
2.0
1.0
0.0
In wait mode
In stop mode
6.0
2.0
3.0
4.0
5.0
7.0
Power source voltage VCC [V]
Fig. 1.21.5 ICC – VCC characteristics (f(XIN) = 4 MHz, 7470/7471 group)
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[Measuring condition : 25 °C, f(XCIN) = 32 kHz]
40.0
In low-speed mode
µ
30.0
20.0
10.0
0.0
In wait mode
In stop mode
2.0
3.0
4.0
5.0
6.0
7.0
CC
Power source voltage V [V]
Fig. 1.21.6 ICC – VCC characteristics (f(XCIN) = 32 kHz, 7471 group)
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1.21 Electrical characteristics
(2) 7477/7478 group power source current standard characteristics
Figure 1.21.7 to Figure 1.21.9 show the ICC - VCC characteristics of the 7477/7478 group.
[Measuring condition : 25 °C, f(XIN) = 8 MHz]
8.0
In ordinary mode
7.0
6.0
5.0
4.0
3.0
2.0
In wait mode
1.0
In stop mode
6.0
0.0
2.0
3.0
4.0
5.0
7.0
Power source voltage VCC [V]
Fig. 1.21.7 ICC – VCC characteristics (f(XIN) = 8 MHz, 7477/7478 group)
[Measuring condition : 25 °C, f(XIN) = 4 kHz]
5.0
In ordinary mode
4.0
3.0
2.0
1.0
0.0
In wait mode
In stop mode
6.0
2.0
3.0
4.0
5.0
7.0
Power source voltage VCC [V]
Fig. 1.21.8 ICC – VCC characteristics (f(XIN) = 4 MHz, 7477/7478 group)
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[Measuring condition : 25 °C, f(XCIN) = 32 kHz]
30.0
In low-speed mode
µ
20.0
10.0
0.0
In wait mode
In stop mode
2.0
3.0
4.0
5.0
6.0
7.0
CC
Power source voltage V [V]
Fig. 1.21.9 ICC – VCC characteristics (f(XCIN) = 32 kHz, 7478 group)
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1.21 Electrical characteristics
1.21.4 Port standard characteristic
The port standard characteristics described in this section are mentioned as a characteristic example of
the 7470/7471/7477/7478 group but not guaranteed by us. For standard values, refer to “1.21.1 Electrical
characteristics.”
Figure 1.21.10 shows the port standard characteristic measuring circuits.
1
IOH–VOH characteristic
measuring circuit
2
IOL–VOL characteristic
measuring circuit
3
IIL–VIL characteristic
measuring circuit
M3747x
M3747x
M3747x
VCC
VCC
VCC
0 V to 5.5 V
0 V to 5.5 V
A
A
IOL
P00
P00
P00
IOH
IIL
A
0 V to 5.5 V
VSS
VSS
VSS
Fig. 1.21.10 Port standard characteristic measuring circuits
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1.21 Electrical characteristics
(1) 7470/7471 group port standard characteristic
Figure 1.21.11 to Figure 1.21.13 show the port standard characteristics of the 7470/7471 group.
[Measuring condition : Port P0
–60.0
0, 25 °C]
–50.0
–40.0
V
CC = 5 V
–30.0
–20.0
–10.0
0.0
V
CC = 3 V
–5.0
–4.0
–3.0
–2.0
–1.0
0.0
OH
“H” output voltage V –VCC [V]
Fig. 1.21.11 IOH – VOH characteristics of programmable I/O port (CMOS output)
P-channel side (7470/7471 group)
[Measuring condition : Port P0
60.0
0, 25 °C]
V
CC = 5 V
50.0
40.0
30.0
20.0
10.0
V
CC = 3 V
1.0
2.0
3.0
4.0
5.0
0.0
“L” output voltage VOL [V]
Fig. 1.21.12 IOL – VOL characteristics of programmable I/O port (CMOS output)
N-channel side (7470/7471 group)
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1.21 Electrical characteristics
[Measuring condition : Port P0
–0.7
0, 25 °C]
V
CC = 5 V
V
CC = 3 V
0.0
–5.0
–4.0
–3.0
–2.0
–1.0
0.0
Supply voltage VIL–VCC [V]
Fig. 1.21.13 IIL – VIL characteristics of programmable I/O port (CMOS output)
pull-up transistor (7470/7471 group)
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1.21 Electrical characteristics
(2) 7477/7478 group port standard characteristic
Figure 1.21.14 to Figure 1.21.16 show the port standard characteristics of the 7477/7478 group.
[Measuring condition : Port P0
–60.0
0, 25 °C]
–50.0
–40.0
–30.0
–20.0
–10.0
V
CC = 5 V
V
CC = 3 V
0.0
–5.0
–4.0
–3.0
–2.0
–1.0
0.0
OH
“H” output voltage V –VCC [V]
Fig. 1.21.14 IOH – VOH characteristics of programmable I/O port (CMOS output)
P-channel side (7477/7478 group)
[Measuring condition : Port P0
60.0
0, 25 °C]
V
CC = 5 V
50.0
40.0
30.0
20.0
10.0
V
CC = 3 V
0.0
1.0
2.0
3.0
4.0
5.0
“L” output voltage VOL [V]
Fig. 1.21.15 IOL – VOL characteristics of programmable I/O port (CMOS)
N-channel side (7477/7478 group)
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[Measuring condition : Port P0
–0.6
0, 25 °C]
V
CC = 5 V
V
CC = 3 V
0.0
–5.0
–4.0
–3.0
–2.0
–1.0
0.0
Supply voltage VIL–VCC [V]
Fig. 1.21.16 IIL – VIL characteristics of programmable I/O port (CMOS output)
pull-up transistor (7477/7478 group)
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1.21.5 A-D conversion standard characteristic
(1) Relative precision (7470/7471 group)
Figure 1.21.17 to Figure 1.21.18 show the A-D conversion standard characteristics on the relative
precision of the 7470/7471 group.
In the graph, the lower line indicates a deviation from the ideal value at the point where the output
code changes, namely, relative precision error (ERROR). For example, in Figure 1.21.17, the change
of “3F16 to 4016” of the output code occurs ideally at the point of IN0 = 757.32 mV. However, since
the relative precision error is -3.567 mV, “757.32 - 3.567 = 753.753 mV” represents a measuring
change point.
In the graph, the upper line indicates an input voltage width (1 LSB WIDTH) in which the output code
is the same. For example, in Figure 1.21.17, since the measured value of input voltage width, when
the output code is “3F16”, is 10.701 mV, the differential nonlinear error on the relative precision
represents “10.701 -11.89 = -1.189 mV (-0.1 LSB)”.
Fig. 1.21.17 A-D conversion standard characteristics, relative precision error (1)
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HARDWARE
1.21 Electrical characteristics
Fig. 1.21.18 A-D conversion standard characteristics, relative precision error (2)
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HARDWARE
1.21 Electrical characteristics
(2) Absolute precision
Figure 1.21.19 to Figure 1.21.23 show the A-D conversion standard characteristics on the absolute
precision of the 7470/7471/7477/7478 group.
In the graph, the lower line indicates a deviation from the ideal value at the point where the output
code changes, namely, absolute precision error (ERROR). For example, in Figure 1.21.17, the change
of “3F16 to 4016” of the output code occurs ideally at the point of IN0 = 762 mV. However, since the
absolute precision error is -8.4 mV, “762 - 8.4 = 753.6 mV” represents the measuring change point.
In the graph, the upper line indicates an input voltage with (1 LSB WIDTH) in which the output code
is the same. For example, since the measured value of input voltage width, when the output code
is “3F16”, is 10.8 mV, the differential nonlinear error represents “10.8 - 12 = -1.2 mV (-0.1 LSB)”.
Fig. 1.21.19 A-D conversion standard characteristics, absolute precision error (1)
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HARDWARE
1.21 Electrical characteristics
Fig. 1.21.20 A-D conversion standared characteristics, absolute precision error (2)
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HARDWARE
1.21 Electrical characteristics
Fig. 1.21.21 A-D conversion standard characteristics, absolute precision error (3)
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HARDWARE
1.21 Electrical characteristics
Fig. 1.21.22 A-D conversion standard characteristics, absolute precision error (4)
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HARDWARE
1.21 Electrical characteristics
Fig. 1.21.23 A-D conversion standard characteristics, absolute precision error (5)
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CHAPTER 2
APPLICATION
2.1 I/O pins
2.2 Interrupts
2.3 Timers
2.4 Serial I/O
2.5 A-D converter
2.6 Reset
2.7 Oscillation circuit
2.8 Low-power
dissipation function
2.9 Countermeasures
against noise
2.10 Notes on programming
2.11 Differences between
7470/7471 group and
7477/7478 group
2.12 Example of application
circuit
APPLICATION
2.1 I/O pins
7470 7471 7477 7478
2.1 I/O pins
2.1.1 I/O port
(1) Port register
Table 2.1.1 shows a memory allocation of port register corresponding to each port.
Table 2.1.1 Port register memory allocation
Address of port register
Port
7470 group 7471 group 7477 group 7478 group
00C016 00C016 00C016 00C016
00C216 00C216 00C216 00C216
00C416 00C416 00C416 00C416
00C616 00C616 00C616 00C616
00C816 00C816 00C816 00C816
P0
P1
P2
P3
P4
P5
–
00CA16
–
00CA16
Note: In the 7470/7477 group, P2 is 4 bits of b0
- b3 and P4 is 2 bits of b0 and b1.
In the 7471/7478 group, P5 is 4 bits of b0 -
b3.
In Chapter 2, each page describes the corresponding products by using the following table.
M37470Mx/Ex-XXXSP
M37471Mx/Ex-XXXSP/FP
M37477Mx/E8-XXXSP/FP, M37477Mx/E8TXXXSP/FP
M37478Mx/E8-XXXSP/FP, M37478Mx/E8TXXXSP/FP
7470 7471 7477 7478
✕ ✕
Non-corresponding products
Corresponding products
7470/7471/7477/7478 GROUP USER’S MANUAL
2-2
APPLICATION
2.1 I/O pins
(2) Port Pi direction register (i = 0 to 5)
7470 7471 7477 7478
Switching between input and output for programmable I/O ports is performed by the port direction
register corresponding to each port. Table 2.1.2 shows a memory allocation of the port direction
register corresponding to each port and Figure 2.1.1 shows an example of port direction register
setting.
Table 2.1.2 Port direction register memory
allocation
Address of port direction register
7470 group 7471 group 7477 group 7478 group
Port
P0
P1
P2
P3
P4
P5
00C116 00C116 00C116 00C116
00C316 00C316 00C316 00C316
00C516 00C516
–
–
–
–
–
–
00C916 00C916 00C916 00C916
–
–
–
–
Note: In the 7470 group, P2 is 4 bits of b0 - b3
and P4 is 2 bits of b0 and b1.
In the 7477 group, P4 is 2 bits of b0 and
b1.
b7
b0
0 1 1 0 1 0 1 0
When “6A16” (
) is set in the Port P0 direction register
Port P0 I/O direction
P07
P06
P05
P04
P03
P02
P01
P00
Input Output Output Input Output Input Output Input
Fig. 2.1.1 Example of port direction register setting
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2-3
APPLICATION
2.1 I/O pins
(3) Pull-up control register
7470 7471 7477 7478
The ports shown in Table 2.1.3 can be pulled up by software. A pull-up operation can be performed
by the P0 pull-up control register (address 00D016) and P1-P5 pull-up control register (address
00D116).
Table 2.1.3 I/O ports that permit pull-up by software
Register
Device
7470 group
Port P0 pull-up control register
Port P1-P5 pull-up control register*
Control by 4-bit unit
P1, P2, P4
Control by 1-bit unit
P0
P0
P0
P0
7471 group
7477 group
7478 group
P1, P2, P4, P5
P1, P4
P1, P4, P5
* : In the 7470/7477 group, the P1-P4 pull-up control register is arranged.
Note: In the 7470 group, P2 is 4 bits of b0 - b3 and P4 is 2 bits of b0 and b4.
In the 7477 group, P4 is 2 bits of b0 and b1.
In the 7471/7478 group, P5 is 4 bits of b0 - b3.
7470/7471/7477/7478 GROUP USER’S MANUAL
2-4
APPLICATION
2.1 I/O pins
2.1.2 Notes on use
7470 7471 7477 7478
When using I/O pins, take the following points into consideration.
(1) Double function ports
Table 2.1.4 shows double function ports. For setting, refer to a structure of each register.
Table 2.1.4 Double function port and control register
Double function port
7470/7471 group 7477/7478 group
Control register
Pin
7470/7471 group
7477/7478 group
T0
T1
Timer 12 mode register (T12M: Address 00F816)
Timer 34 mode register (T34M: Address 00F916)
P12
P13
Serial I/O mode register
Serial I/O control register
SIN
RXD
P14
(SM: Address 00DC16)
Serial I/O mode register
Serial I/O mode register
Serial I/O mode register
(SIOSTS: Address 00E216)
Serial I/O control register
Serial I/O control register
Serial I/O control register
SOUT
CLK
TXD
SCLK
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P50
P51
SRDY
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
INT0
INT1
CNTR0
CNTR1
XCIN
A-D control register (ADCON: Address 00D916)
A-D control register
A-D control register
A-D control register
A-D control register
A-D control register
A-D control register
A-D control register
Edge polarity selection register (EG: Address 00D416)
Edge polarity selection register
Edge polarity selection register, Timer 12 mode register
Edge polarity selection register, Timer 34 mode register
CPU mode register (CPUM: Address 00FB16)
CPU mode register
XCOUT
Note: In the 7470/7477 group, P2 is 4 bits of b0 to b3. The 7470/7477 group is not provided with P5.
7470/7471/7477/7478 GROUP USER’S MANUAL
2-5
APPLICATION
2.1 I/O pins
(2)Description of Pull-up control
7470 7471 7477 7478
, , , ,
When pulling up a port by software, take the following points into consideration.
● When P1 is used in the serial I/O mode, the pull-up settings corresponding to P14 to P17 are
invalidated. (Pull-up is impossible.)
● Pull-up control is exerted in the following bit units.
P0
: 1-bit unit
P1 to P5 : 4-bit unit
When using an external pull-up resistor and software pull-up control for the same port in combined
form, use P0, which can be controlled in bit units.
(3)Notes on external circuit design for I/O ports
1
When designing an external circuit for I/O ports, be sure to set the following items within the
standard value range.
● Sum output current
● Peak output current
● Average output current
Figure 2.1.2 shows the example of external circuit design for I/O port.
V
CC=5 V
M3747x
Maximum standard value
“L” sum output current
OL2=36 mA
I
OL0
+
I
OL1
+
I
< 60 mA
P0
0
I
OL0=12 mA
✽
✽
✽
R0=250 Ω
“L” peak output current
OL2=12 mA
I
OL0
=
I
OL1
=
I
<
20 mA
P0
1
I
I
OL1=12 mA
R
R
1
=250 Ω
=250 Ω
“L” average output current (within 100 ms)
P0
2
12 mA✕10 ms✕5
OL2=12 mA
= 6 mA < 10 mA
2
100 ms
10 ms
Ports P00 – P02
Timing of LED on
(duty ratio: 50 %)
✽: LED (VF= 2 V) used
10 ms
Fig. 2.1.2 Example of external circuit design for I/O port
2 When performing multiple key-in operations by forming a key matrix, design in consideration of
the port input current for multiple key-in operations.
For other notes, refer to “1.10 I/O Pins.”
7470/7471/7477/7478 GROUP USER’S MANUAL
2-6
APPLICATION
2.2 Interrupts
7470 7471 7477 7478
2.2 Interrupts
2.2.1 Memory allocation
Figure 2.2.1 shows a memory map of interrupt related registers.
Address
Edge polarity selection register (EG)
00D416
Interrupt request register 1 (IR1)
Interrupt request register 2 (IR2)
Interrupt control register 1 (IE1)
Interrupt control register 2 (IE2)
00FC16
00FD16
00FE16
00FF16
Fig. 2.2.1 Memory map of interrupt related registers
7470/7471/7477/7478 GROUP USER’S MANUAL
2-7
APPLICATION
2.2 Interrupts
2.2.2. Processor status register (PS)
7470 7471 7477 7478
The Processor status register consists of 8 bits.
Figure 2.2.2 shows the structure of the Processor status register. Bit 2 related to interrupts is described
below.
2 Interrupt disable flag: b2
The interrupt disable flag controls the acceptance of interrupt requests other than the BRK instruction.
When this flag is “1,” the acceptance of interrupt requests is disabled. When the flag is “0,” the
acceptance of interrupt requests is enabled. The instruction to set this flag to “1” is the SEI instruction
and the instruction to set this flag to “0” is the CLI instruction.
At a branch to an interrupt processing routine, this flag is automatically set to “1,” thereby multiple
interrupts are disabled. To use multiple interrupt, set this flag to “0” by using the CLI instruction in
the interrupt processing routine.
Processor status register
b7
b2
b0
Unde-
fined
1
Processor status register (PS)
Undefined
b
0
1
2
3
4
5
6
7
Flag name
: Carry flag
C
Z : Zero flag
I : Interrupt disable flag
: Decimal mode flag
: Break flag
D
B
T
V
: Index X mode flag
: Overflow flag
N: Negative flag
b7
b0
denotes the initial value immediately after reset release.
The value in
Fig. 2.2.2 Structure of Processor status register
7470/7471/7477/7478 GROUP USER’S MANUAL
2-8
APPLICATION
2.2 Interrupts
2.2.3 Application example
7470 7471 7477 7478
(1)External event detection by CNTR
To detect a rising edge or a falling edge of the level of an input pin by using a pin other than the
INT0 pin and the INT1 pin, it is possible to use the CNTR pin. Examples of use are shown below.
● When the CNTR0 pin is used
+1
<Interrupt source>
<Setting>
CNTR interrupt
1
Set the edge polarity selection register.
• Select a CNTR0 edge polarity.
• Select CNTR0 as an interrupt source.
Clear the CNTR interrupt request bit to “0.”
Execute the NOP instruction.
2
3
4
Set the CNTR interrupt enable bit to “1.”
● When the CNTR1 pin is used
+1,+2
<Interrupt source>
<Setting>
Timer 3 interrupt
1
2
3
4
5
6
7
Stop the count operation of timer 3.
Select CNTR1 as a count source of timer 3.
Select a CNTR1 edge polarity by the Edge polarity selection register.
Set timer 3 to “0.”
Clear the timer 3 interrupt request bit to “0.”
Set the timer 3 interrupt enable bit to “1.”
Start the count operation of timer 3.
+1: It is possible to use the CNTR0 pin for a timer interrupt and the CNTR1 pin for a CNTR interrupt.
+2: It is possible to use timer 4 as an interrupt source.
2.2.4 Notes on use
For notes on use, refer to “1.11 Interrupts.”
7470/7471/7477/7478 GROUP USER’S MANUAL
2-9
APPLICATION
2.3 Timers
7470 7471 7477 7478
2.3 Timers
,
,
,
,
2.3.1 Memory allocation
Figure 2.3.1 shows a memory map of timer related registers.
Address
00D416 Edge polarity selection register (EG)
00D516
Input latch register (ILR)
00D616
00F016
00F116
00F216
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
00F316 Timer 4 (T4)
00F716
00F816
00F916
Timer FF register (TF)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Timer mode register 2 (TM2)
CPU mode register (CPUM)
Interrupt request register 1 (IR1)
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
Interrupt request register 2 (IR2)
Interrupt control register 1 (IE1)
Interrupt control register 2 (IE2)
Fig. 2.3.1 Memory map of timer related registers
7470/7471/7477/7478 GROUP USER’S MANUAL
2-10
APPLICATION
2.3 Timers
2.3.2 Application example
(1) Each mode of timer
7470 7471 7477 7478
,
,
,
,
For timers 1, 2, 3 and 4, the following 5 operation modes are available. For each timer mode and
the details of it, refer to “1.12 Timers.”
1
2
3
4
5
Timer mode
Event counter mode
Pulse output mode
External pulse width measurement mode
PWM mode
Each timer mode has relation to the T0, T1, CNTR0 and CNTR1 pins as shown in Table 2.3.1. There
are some modes that cannot be used for some combinations of timer and pin. Consider this when
designing timers.
Table 2.3.1 Relation between timer-used pins and modes
Pin
T0
T1
×
CNTR0
CNTR1
Timer
Timer 1
Pulse output
mode
Event counter mode
×
×
×
×
×
×
×
Timer 2
Timer 3
Event counter mode
Event counter mode
PWM
mode
Pulse output
mode
External pulse width
measurement mode External pulse width
measurement mode
×
Timer 4
7470/7471/7477/7478 GROUP USER’S MANUAL
2-11
APPLICATION
2.3 Timers
(2) Example of use of each mode
7470 7471 7477 7478
×
,
×
,
An example of use of each mode is shown below.
1
Timer mode: One-second measurement (timer function)
Outline: Divide the clock by the timer. Count one second by a timer 1 interrupt that is generated
at an internal of 0.4 ms. Cause the timer to count up at each second.
Specifications: Divide f(XCIN) = 32 kHz by timer 1 to generate an interrupt. Check the value of
the counter that counts with an timer 1 interrupt by the main routine. If one
second has elapsed, execute timer count-up processing.
Figure 2.3.2 shows an example of control procedure.
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2-12
APPLICATION
2.3 Timers
7470 7471 7477 7478
×
,
×
,
RESET
Initialization
Set the interrupt disable flag (each interrupt disabled)
Clear the timer 1 interrupt enable bit
(timer 1 interrupt disabled)
Set the timer 12 mode register
0
✕ ✕ ✕ ✕ ✕ 1
1
T12M (Address 00F816
Timer 1 count stop
)
Timer 1 count source
Timer 1 internal clock count source
← f(XCIN
← Internal clock
)
Set the CPU mode register
0
CPUM (Address 00FB16)
✕ ✕ 1 1 ✕ ✕
0
Fixed to “0”
Select XCIN, XCOUT
X
COUT drive capacity ← High power
● For concrete time, ask the oscillator manufacture for information.
Wait the f(XCIN) oscillation stabilizing time
7F16
Set the Timer 1 to “7F16
”
● 1 second = 1/32 kHz ✕ (127+1) ✕ 250
Dividing ratio
Count by interrupt processing
Set the Timer 12 mode register
0
✕ ✕ ✕ ✕ ✕ 1
0
T12M (Address 00F816
Timer 1 count start
)
Clear the timer 1 interrupt request bit
Set the timer 1 interrupt enable bit
(Timer 1 interrupt enabled)
Interrupt at every 0.4 ms
Timer 1 interrupt
Clear the interrupt disable flag (each interrupt enabled)
1 second counter + 1
Y
Clock stop ?
RTI
N
N
1 second has elapsed ?
(1 second counter = 250 ?)
Y
Clear 1 second counter
Clock count up (second–year)
✽
Processing for timer
set is completed ?
N
Y
● When re-starting the clock from zero second
after completing to set the clock, set timers again.
Set the Timer 1 to “7F16
”
Clear the Timer 1 interrupt request bit
Clear 1 second counter
✽
●
Set the timer so that every processing within the loop marked may
be executed in a period of 1 second or less.
Fig. 2.3.2 Example of control procedure [Clock function]
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2-13
APPLICATION
2.3 Timers
2
Event counter mode: Frequency measurement
7470 7471 7477 7478
,
,
,
,
Outline: The frequency of the pulse input to the CNTR0 pin (“H” active) is measured by the
number of events in a certain period.
Specifications: A count operation is started specifying the count source of timer 1 as CNTR0.
Timer 2 (count source: f(XIN)/64) detects 1 ms and the frequency of the pulse
input to CNTR0 is calculated from the number of events counted within 1 ms.
Note: The number of events of an input pulse is specified as 255 or less within 1 ms.
Figure 2.3.3 shows an example of measurement method of frequency and Figure 2.3.4 shows an
example of control procedure.
Timer 2 interrupt request bit
1 ms has elapsed
Count stop
Count start
CNTR
0
Count start
Count stop
X times
X times
● Pulse frequency of CNTR0 input =
kHz
1 ms
Fig. 2.3.3 Example of measurement method of frequency
7470/7471/7477/7478 GROUP USER’S MANUAL
2-14
APPLICATION
2.3 Timers
7470 7471 7477 7478
,
,
,
,
Frequency measurement routine
Clear the timer 2 interrupt enable bit
(Timer 2 interrupt disabled)
Set the Timer 12 mode register
✕
T12M (Address 00F816
Timer 1 count stop
Timer 2 count stop
)
✕ ✕ ✕ 1 ✕ ✕
1
Set the Edge polarity selection register
✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
EG (Address 00D416
)
CNTR rising edge selected
0
Set the Timer 12 mode register
✕ 1 1 T12M (Address 00F816
)
0 1 0 1 ✕
Timer 1 count source ← CNTR
0
Timer 2 count source
← Internal clock
Timer 2 internal clock count source
←f(XIN)/64
Set the Timer 1 to “FF16
”
”
Set the Timer 2 to “7C16
According to required accuracy, the event count
value within 1 ms is detected repeatedly, and its
results are averaged.
✽
Clear the timer 2 interrupt request bit
Set the timer 2 interrupt enable bit
(Timer 2 interrupt enabled)
Set the Timer 12 mode register
Timer 2 interrupt
✕ 1 0
0 1 0 0 ✕
T12M (Address 00F816)
Timer 1 count start
Timer 2 count start
Set the Timer 12 mode register
0 1 0 1 ✕ ✕ 1 1
T12M (Address 00F816
Timer 1 count stop
Timer 2 count stop
)
Read timer 1
(Timer 1 set value FF16) – (Timer 1 read value)
← Event count value within 1 ms
RTS
RTI
Fig. 2.3.4 Example of control procedure [Frequency measurement]
7470/7471/7477/7478 GROUP USER’S MANUAL
2-15
APPLICATION
2.3 Timers
3
Pulse output mode: Piezoelectric buzzer output
7470 7471 7477 7478
,
,
,
,
Outline: The pulse output function of the timer is applied for a piezoelectric buzzer output.
Specifications: A square wave obtained by dividing the clock f(XIN) = 8 MHz into about 2 kHz is
output from the T0 pin. While the buzzer output stops, the level of the T0 pin is
fixed at “H.”
Figure 2.3.5 shows an example of a peripheral circuit. Figure 2.3.6 shows a connection of the timer
and setting of the division ratio. Figure 2.3.7 shows an example of control procedure.
While the piezoelectric buzzer output stops, the “H” level is output.
M3747x
T
0
250 µs
250 µs
Set the division ratio so that the underflow period of
timer 1 may be equal to this value.
Fig. 2.3.5 Example of a peripheral circuit [Pulse output mode]
Fix
Timer 1
f(XIN)
8MHz
1/2
1/16
1/125
T0
Fig. 2.3.6 Connection of timer and setting of division ratio
7470/7471/7477/7478 GROUP USER’S MANUAL
2-16
APPLICATION
2.3 Timers
7470 7471 7477 7478
,
,
,
,
RESET
Initialization
Set the interrupt disable flag (each interrupt disabled)
Clear the timer 1 interrupt enable bit
(Timer 1 interrupt disabled)
Set the Timer 12 mode register
✻ A piezoelectric buzzer output stops.
0 0 1
✕ ✕ ✕ ✕ 1
T12M (Address 00F816
Timer 1 count stop
)
Timer 1 count source
← Internal clock
Timer 1 internal clock count source
← f(XIN)/16
T0 output selected
Set the Timer mode register 2
✕ ✕ ✕ ✕ ✕ ✕ ✕ 1
TM2 (Address 00FA16
)
Timer 1 division flip flop set enabled
Set the Timer FF register
✕ ✕ ✕ ✕ ✕ ✕ ✕ 0
TF (Address 00F716
)
Timer 1 division flip flop initial value 0
Set the port P1
Port P1
2
as an output
2
← “H”
8 MHz
Set the Timer 1 to “7C16
”
✻ 2 kHz =
16 ✕ (124+1) ✕ 2
Timer 1 overflow divided by 2
Fixed dividion ratio
Set the Timer 1 interrupt enable bit
(Timer 1 interrupt enabled)
7C16
Count by interrupt processing
Clear the interrupt disable flag (each interrupt enabled)
A piezoelectric buzzer request generated in the
main processing is processed in the output unit.
✻
Main processing
Output unit
Y (= 0 Request)
A piezoeletric buzzer is requested ?
N
N (= No request)
Set the Timer 12 mode register
✻ Buzzer output stop
Immediately after no request?
✻ Buzzer output start
Y
0
✕ ✕ ✕ ✕ 1 0
1
T12M (Address 00F816
Timer 1 count stop
)
Set the Timer 1 to “7C16
”
Set the Timer 12 mode register
Port P12 ← “H”
✕ ✕ ✕ ✕ 1 0 0 0
T12M (Address 00F816
Timer 1 count start
)
Fig. 2.3.7 Example of control procedure [Piezoelectric buzzer output]
7470/7471/7477/7478 GROUP USER’S MANUAL
2-17
APPLICATION
2.3 Timers
4
Pulse width measurement mode: Feedback control of phase control
signal
7470 7471 7477 7478
,
,
,
,
Outline: The phase control signal is adjusted by using the pulse width measurement mode.
Specifications: The M3747x controls a load by phase control. At this time, the width of the pulse
output from the load as a feedback signal is measured. With this result, the control
over the load is compensated.
Figure 2.3.8 shows an example of peripheral circuit and Figure 2.3.9 shows an example of control
procedure.
M3747x
CNTR
0
Load
Port
V
AC
Fig. 2.3.8 Example of peripheral circuit [Pulse width measurement mode]
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2-18
APPLICATION
2.3 Timers
7470 7471 7477 7478
,
,
,
,
Pulse width measurement routine
Set the Timer 34 mode register
✕
T34M (Address 00F916
Timer 4 count stop
)
✕ ✕ ✕ ✕ 1 ✕
✕
Set the Edge polarity selection register
0 ✕ ✕
✕ ✕ ✕ 0 ✕
EG (Address 00D416)
Select the measurement of CNTR0 “H” width
Interrupt ← CNTR0 selected
Set the Timer 34 mode register
✕ ✕ ✕
✕ 1 ✕ ✕ 1
T34M (Address 00F916
Timer 4 count source
)
←
select according to an input pulse
External pulse width
measurement mode selected
Set the Timer 4 to “FF16
”
Clear the CNTR interrupt request bit
Set the Timer 34 mode register
✕ ✕ ✕
✕ 1 ✕ ✕ 0
T34M (Address 00F916
Timer 4 count start
)
N
CNTR interrupt request ?
Y
✻ Measurement completed
Set the Timer 34 mode register
✕ ✕ ✕
✕ 1 ✕ ✕ 1
T34M (Address 00F916
Timer 4 count stop
)
Read Timer 4
(Timer 4 set value FF16) – (Timer 4 read value)
← Input pulse “H” width measurement value
RTS
Fig. 2.3.9 Example of control procedure [Pulse width measurement mode]
7470/7471/7477/7478 GROUP USER’S MANUAL
2-19
APPLICATION
2.3 Timers
5
PWM mode: Analog output
7470 7471 7477 7478
,
,
,
,
Outline: An analog output is performed by using the PWM function of the timer.
Specifications: A count source of Timer 3 and Timer 4 is selected and a PWM waveform is output
from the T1 pin. The PWM waveform is converted into an analog voltage by the
external circuit of the T1 pin, and then this voltage is output.
Note: The analog voltage to be output varies depending on the duty of the PWM waveform.
Figure 2.3.10 shows an example of peripheral circuit and Figure 2.3.11 shows an example of
control procedure.
M3747x
3 : 2
5 V
T1
0
Fig. 2.3.10 Example of peripheral circuit [PWM mode]
7470/7471/7477/7478 GROUP USER’S MANUAL
2-20
APPLICATION
2.3 Timers
7470 7471 7477 7478
,
,
,
,
Analog output routine
Set the Timer 34 mode register
✕
✕ ✕ ✕ ✕ 1 ✕
1
T34M (Address 00F916)
Timer 3 count stop
Timer 4 count stop
Set port P13 as an output
Set the Timer 34 mode register
1 ✕ ✕ ✕ 1 ✕ ✕ 1 T34M (Address 00F916)
Select timer 3 count source
Select timer 4 count source
Select T1 output
Set the Timer 3
Set the Timer 4
Set the Timer mode register 2
✕ ✕ ✕ TM2 (Address 00FA16)
1 ✕ ✕ ✕ ✕
Select PWM mode
Set the Timer 34 mode register
✕
1 ✕ ✕ ✕ 0 ✕ 0 T34M (Address 00F916)
Timer 3 count start
Timer 4 count start
RTS
Fig. 2.3.11 Example of control procedure [PWM mode]
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2-21
APPLICATION
2.3 Timers
2.3.3 Notes on use
7470 7471 7477 7478
,
,
,
,
2
When using a 16-bit counter by using two timers, take the following points into consideration
according to “1.12.5 Notes on use (2).”
●The timing at which the timer value and the read value change, when two 8-bit timers are
connected in series, is shown in Figure 2.3.12, taking the case where timer 1 and timer 2 are
connected as an example (When Timer 1 and Timer 2 are connected and the set value of the
Timer 1 is 216 and the set value of the Timer 2 is 116).
The count source of timer 2 is the overflow signal of timer 1. In this case, the read value of timer
2 changes at the fall of the count source. When Timer 1 and Timer 2 are read continuously as
a 16-bit counter, the count source of timer 2 changes at the falling edge of the count source of
timer 1, so the A section can not be distinguished from the B section. Likewise, the C section
cannot be distinguished from the D section.
Timer 1 count source
Timer 1 value
1
0
FF
1
0
FF
1
0
FF
1
0
2
1
0
FF
1
0
FF
1
0
FF
1
0
Timer 1 read value
Writing to timer 1
Timer 1 interrupt request
Timer 2 count source
Timer 2 value
0
FF
0
FF
A
B
C
D
1
0
FF
0
Timer 2 read value
Writing to timer 2
Timer 2 interrupt request
Fig. 2.3.12 Timing at which timer value and read value change in the case where two timers are
connected in series
2
For other notes on use, refer to “1.12 timers.”
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2-22
APPLICATION
2.4 Serial I/O
7470 7471 7477 7478
2.4 Serial I/O
×
×
2.4.1 7470/7471 group memory allocation
Figure 2.4.1 shows a memory map of serial I/O related registers in the 7470/7471 group.
Address
Serial I/O mode register (SM)
Serial I/O register (SIO)
)
00DC16
00DD16
00DE16
Serial I/O counter
Byte counter
00FC16
00FD16
Interrupt request register 1 (IR1)
00FE16 Interrupt control register 1 (IE1)
00FF16
Fig. 2.4.1 Memory map of serial I/O related registers in 7470/7471 group
7470/7471/7477/7478 GROUP USER’S MANUAL
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APPLICATION
2.4 Serial I/O
2.4.2 Application example
7470 7471 7477 7478
×
×
(1) Clock synchronous serial I/O mode
Outline: Clock synchronous communication is performed among the 7470/7471 group.
……
Specifications: M3747x 1
Transmit side in half-duplex communication
• Synchronous clock: f(XIN)/16
• Port P17 is used as an SRDY signal input pin.
……
M3747x 2
Receive side in half-duplex communication
• Synchronous clock: External clock
• SRDY signal output
Figure 2.4.2 shows an example of connections and Figure 2.4.3 shows an example of control
procedure.
Use
→
→
Full-duplex communication
Half-duplex communication
No use
2
M3747x
1
M3747x
P17
CLK
SRDY
CLK
SIN
SOUT
SIN
SOUT
Fig. 2.4.2 Example of connections [Clock synchronous serial I/O mode, 7470/7471 group]
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APPLICATION
2.4 Serial I/O
7470 7471 7477 7478
×
×
M3747x 1
M3747x 2
Clear the serial I/O interrupt enable bit
(Serial I/O interrupt disabled)
Clear the serial I/O interrupt enable bit
(Serial I/O interrupt disabled)
Set port P1
7 to input
Set port P1
4 to input
Set the Serial I/O mode register
Set the Serial I/O mode register
0
0 0 ✕ 0 1 1
1
SM (Address 00DC16
Internal clock ← f(XIN)/16
)
SM (Address 00DC16
–
)
0 ✕ ✕
0 0 0 1 1
Synchronous clock
← Internal clock
Synchronous clock
←
External clock
Select SOUT, CLK
Select SOUT, CLK
RDY signal output
Select SRDY signal
Select port P1
–
7
S
Mode ← Ordinary mode
CMOS output
Mode ← Ordinary mode
CMOS output
Clear the serial I/O interrupt request bit
Clear the serial I/O interrupt request bit
Set the serial I/O interrupt enable bit
(Serial I/O interrupt enabled)
Set the serial I/O interrupt enable bit
(Serial I/O interrupt enabled)
Write the transmit data into the Serial I/O register
(Write the dummy data in the half-duplex communication)
N
Port P1
7
= “L” ?
Y
Write the transmit data into the Serial I/O register
Serial I/O interrupt
Serial I/O interrupt
Fig. 2.4.3 Example of control procedure [Clock synchronous serial I/O mode, 7470/7471 group]
7470/7471/7477/7478 GROUP USER’S MANUAL
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APPLICATION
2.4 Serial I/O
(2)Byte specification mode
7470 7471 7477 7478
×
×
Outline: Among the 7470/7471 group, transfer is performed for two or more microcomputers by
using the clock synchronous byte specification mode.
Specifications: Transmit side M3747x 1
• Synchronous clock: f(XIN)/32
• Port P17 is used as an SRDY signal input pin.
• Port P10 is used as an transmit preparation command signal output pin.
Receive side M3747x 2 , M3747x 3 , M3747x 4
• Synchronous clock: External clock
• SARDY signal output
• Port P10 is used as an transmit preparation command signal output pin.
Figure 2.4.4 shows an example of connections and Figure 2.4.5 and 2.4.6 show an example of
control procedure.
Transmit side (M3747x 1 )
Serial I/O mode register
0
0
0
0
1
1
1
0
• Set port P1
• Connect a pull-up transistor to port P1
• Set port P1 as an output
(Port P1 : Transmit preparation
command signal)
7 as an input
7
0
0
P1
7
CLK
S
OUT P1
0
SARDY
CLK
Serial data
Transmit/receive preparation command signal
S
RDY(SARDY)
S
RDY(SARDY
)
S
IN
S
IN
P10
P1
0
CLK
S
RDY(SARDY) CLK
S
IN
P10
CLK
• Set port P1
0
as an input
• Set port P1
(Port P1
0
as an input
• Set port P1 as an input
0
(Port P1
command signal)
• Set port P1 as an input
0
: Transmit/receive preparation
0
: Transmit/receive preparation
command signal)
• Set port P1 as an input
(Port P1 : Transmit/receive preparation
command signal)
• Set port P1 as an input
0
4
4
4
Serial I/O mode register
Serial I/O mode register
Serial I/O mode register
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
Byte counter (Initial value) = 0
Byte counter (Initial value) = 1
Byte counter (Initial value) = 2
Receive side 1 (M3747x 2 )
Receive side 2 (M3747x 3 )
Receive side 3 (M3747x 4 )
Fig. 2.4.4 Example of connections [Byte specification mode, 7470/7471 group]
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APPLICATION
2.4 Serial I/O
7470 7471 7477 7478
×
×
Transmit side (M3747x 1 )
Clear the serial I/O interrupt enable bit
Receive side 1 (M3747x 2 )
Clear the serial I/O interrupt enable bit
(Serial I/O interrupt disabled)
(Serial I/O interrupt disabled)
Set port P1
Set port P1
4
0
as an input
as an input
Set port P1 as an input
7
Connect a pull-up transistor to port P17
Set port P1 as an output
Set the Serial I/O mode register
0
0 0 0
1 1 1 1 1
SM (Address 00DC16
)
–
Set the serial I/O mode register
1 1 0
Synchronous clock
Select SOUT, CLK
Select SRDY signal output pin.
Select SARDY signal
Mode ← Byte specify mode
N-channel open-drain output
← External clock
0 0 0 0 1
SM (Address 00DC16
)
Internal clock ← f(XIN)/32
Synchronous clock
Select SOUT, CLK
← Internal clock
Select port P1
–
7
Mode ← Ordinary mode
CMOS output
Clear the serial I/O interrupt request bit
Set the serial I/O interrupt enable bit
(Serial I/O interrupt enabled)
Clear the serial I/O interrupt request bit
Set the serial I/O interrupt enable bit
(Serial I/O interrupt enabled)
Transmit preparation
signal port P1
0 ← “L” ?
N
0
Transmit preparation signal port P1 ← “L”
Y
Set the initial value of “0” of the receive side 1 in the byte counter
N
Port P1
7
= “H” ?
Y
Write the dummy data into the Serial I/O register
0
Transmit preparation signal port P1 ← “H”
Write the transmit data to receive side 1
into the Serial I/O register
Serial I/O interrupt
Serial I/O interrupt
Write the transmit data to receive side 2
into the Serial I/O register
Serial I/O interrupt
Write the transmit data to receive side 3
into the Serial I/O register
Serial I/O interrupt
Fig. 2.4.5 Example of control procedure (1) [Byte specification mode, 7470/7471 group]
7470/7471/7477/7478 GROUP USER’S MANUAL
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APPLICATION
2.4 Serial I/O
7470 7471 7477 7478
×
×
Receive side 3 (M3747x 4 )
Clear the serial I/O interrupt enable bit
Receive side 2 (M3747x 3 )
Clear the serial I/O interrupt enable bit
(Serial I/O interrupt disabled)
(Serial I/O interrupt disabled)
Set port P1
Set port P1
4
0
as an input
as an input
Set port P1
Set port P1
4
0
as an input
as an input
Set the Serial I/O mode register
Set the Serial I/O mode register
0 0 0
0 0 0
1 1 1 1 1
1 1 1 1 1
SM (Address 00DC16
–
)
SM (Address 00DC16
–
)
Synchronous clock
←
External clock
Synchronous clock
← External clock
Select SOUT, CLK
Select SOUT, CLK
Select SRDY signal output pin.
Select SARDY signal
Select SRDY signal output pin
Select SARDY signal
Mode ← Byte specify mode
N-channel open-drain output
Mode ← Byte specify mode
N-channel open-drain output
Clear the serial I/O interrupt request bit
Clear the serial I/O interrupt request bit
Set the serial I/O interrupt enable bit
(Serial I/O interrupt enabled)
Set the serial I/O interrupt enable bit
(Serial I/O interrupt enabled)
N
Transmit preparation
signal port P10 ← “L” ?
Transmit preparation
signal port P10 ← “L” ?
N
Y
Y
Set the initial value of “1” of the receive side 2 in the Byte counter
Set the initial value of “2” of the receive side 3 in the Byte counter
Write the dummy data into the Serial I/O register
Write the dummy data into the Serial I/O register
Serial I/O interrupt
Serial I/O interrupt
Fig. 2.4.6 Example of control procedure (2) [Byte specification mode, 7470/7471 group]
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APPLICATION
2.4 Serial I/O
2.4.3 7477/7478 group memory allocation
7470 7471 7477 7478
×
×
Figure 2.4.7 shows a memory map of serial I/O related registers in the 7477/7478 group.
Address
00E016 Transmit/receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
00E116
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
00E216
00E316
00E416
00FC16
00FD16
00FE16
00FF16
Interrupt request register 1 (IR1)
Interrupt control register 1 (IE1)
Fig. 2.4.7 Memory map of serial I/O related registers in 7477/7478 group
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APPLICATION
2.4 Serial I/O
2.4.4 Application examples
7470 7471 7477 7478
×
×
(1) Clock synchronous serial I/O mode
Outline: Clock synchronous communication is performed among the 7477/7478 group.
……
Specifications: M3747x 1
Transmit side in half-duplex communication.
• Synchronous clock: BRG output (f(XIN)/4 or f(XIN)/16)/4.
• Port P17 is used as an SRDY signal input pin.
……
M3747x 2
Receive side in half-duplex communication
• Synchronous clock: External clock
• SRDY signal output
Figure 2.4.8 shows an example of connections and Figure 2.4.9 shows an example of control
procedure.
Use → Full-duplex communication
No use → Half-duplex communication
M3747x 1
M3747x 2
P17
SRDY
SCLK
TxD
RxD
SCLK
RxD
TxD
Fig. 2.4.8 Example of connections [Clock synchronous serial I/O mode, 7477/7478 group]
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APPLICATION
2.4 Serial I/O
7470 7471 7477 7478
×
×
M3747x 2
M3747x 1
Clear the serial I/O transmit interrupt enable bit
(Serial I/O transmit interrupt disable)
Clear the serial I/O transmit interrupt enable bit
(Serial I/O transmit interrupt disabled)
Clear the serial I/O receive interrupt enable bit
(Serial I/O receive interrupt disable)
Clear the serial I/O receive interrupt enable bit
(Serial I/O receive interrupt disabled)
Set the Serial I/O control register
Set baud rate generator
SIOCON (Address 00E216
)
1 1 ✕
1 1 1 1 ✕
Set port P1
7 as an input
Select BRG count source
Synchronous clock
← External clock
S
RDY output enabled
Set the Serial I/O control register
Select transmit interrupt source
Transmit enabled
Receive enabled
Clock synchronous serial I/O selected
Serial I/O enabled
0
SIOCON (Address 00E216
Select BRG count source
)
1 1 1 1 ✕ 0
✕
Synchronous clock
← BRG output divided by 4
S
RDY output disabled
Select transmit interrupt source
Transmit enabled
Receive enabled
Clock synchronous serial I/O selected
Serial I/O enabled
NOP
Clear the serial I/O transmit interrupt request bit
Clear the serial I/O receive interrupt request bit
NOP
Set the serial I/O transmit interrupt enable bit
(Serial I/O transmit interrupt enabled)
Set the serial I/O receive interrupt enable bit
(Serial I/O receive interrupt enabled)
Clear the serial I/O transmit interrupt request bit
Clear the serial I/O receive interrupt request bit
Set the serial I/O transmit interrupt enable bit
(Serial I/O transmit interrupt enable)
Set the serial I/O receive interrupt enable bit
Write the transmit data into the Transmit buffer register
(Write the dummy data in the half-duplex communication)
(Serial I/O receive interrupt enable)
N
Port P1
7
= “L” ?
Y
Serial I/O transmit interrupt
Serial I/O receive interrupt
Write the transmit data into the Transmit buffer register
Serial I/O transmit interrupt
Serial I/O receive interrupt
Fig. 2.4.9 Example of control procedure [Clock synchronous serial I/O mode, 7477/7478 group]
7470/7471/7477/7478 GROUP USER’S MANUAL
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APPLICATION
2.4 Serial I/O
(2)Clock asynchronous serial I/O mode
7470 7471 7477 7478
×
×
Outline: Clock asynchronous communication is performed among the 7477/7478 groups.
……
Specifications: M3747x 1
Transmit side in half-duplex communication
f(XIN)
4 × (XX16 + 1) × 16
Receive side in half-duplex communication
• Baud rate:
bps
……
M3747x 2
f(XIN)
bps
• Baud rate:
4 × (XX16 + 1) × 16
“XX16” is a set value of the baud rate generator.
Figure 2.4.10 shows an example of connections and Figure 2.4.11 shows an example of control
procedure.
Use → Full-duplex communication
No use → Half-duplex communication
M3747x 1
M3747x 2
TxD
RxD
RxD
TxD
Fig. 2.4.10 Example of connections [Clock asynchronous serial I/O mode, 7477/7478 group]
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APPLICATION
2.4 Serial I/O
7470 7471 7477 7478
×
×
M3747x 1
M3747x 2
Clear the serial I/O transmit interrupt enable bit
Clear the serial I/O transmit interrupt enable bit
(Serial I/O transmit interrupt disabled)
Clear the serial I/O receive interrupt enable bit
(Serial I/O receive interrupt disabled)
(Serial I/O transmit interrupt disabled)
Clear the serial I/O receive interrupt enable bit
(Serial I/O receive interrupt disabled)
Set baud rate generator
Set baud rate generator
(Set “✕✕16” to BRG)
(Set “✕✕16” to BRG)
Set the Serial I/O control register
Set the Serial I/O control register
SIOCON (Address 00E216
)
1 0 1 1 ✕ ✕ 0 0
SIOCON (Address 00E216
)
0
1 0 1 1 ✕ ✕
0
BRG count source ← f(XIN)/4
BRG count source ← f(XIN)/4
Synchronous clock
–
← BRG output divided by 16
Synchronous clock
–
← BRG output divided by 16
Select transmit interrupt source
Transmit enabled
Receive enabled
Clock asynchronous serial I/O selected
Serial I/O enabled
Select transmit interrupt source
Transmit enabled
Receive enabled
Clock asynchronous serial I/O selected
Serial I/O enabled
NOP
NOP
Clear the serial I/O transmit interrupt request bit
Clear the serial I/O receive interrupt request bit
Clear the serial I/O transmit interrupt request bit
Clear the serial I/O receive interrupt request bit
Set the serial I/O transmit interrupt enable bit
(Serial I/O transmit interrupt enabled)
Set the serial I/O receive interrupt enable bit
(Serial I/O receive interrupt enabled)
Set the serial I/O transmit interrupt enable bit
(Serial I/O transmit interrupt enabled)
Set the serial I/O receive interrupt enable bit
(Serial I/O receive interrupt enabled)
Write the transmit data into the Transmit buffer register
Write the transmit data to the Transmit buffer register
in the full-duplex communication
Serial I/O transmit interrupt
Serial I/O receive interrupt
Serial I/O transmit interrupt
Serial I/O receive interrupt
Fig. 2.4.11 Example of control procedure [Clock asynchronous serial I/O mode, 7477/7478 group]
7470/7471/7477/7478 GROUP USER’S MANUAL
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APPLICATION
2.4 Serial I/O
2.4.5 Notes on use
7470 7471 7477 7478
For notes on use, refer to “1.13 Serial I/O.”
7470/7471/7477/7478 GROUP USER’S MANUAL
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APPLICATION
2.5 A-D converter
7470 7471 7477 7478
2.5 A-D converter
2.5.1 Memory allocation
Figure 2.5.1 shows a memory map of A-D conversion related registers.
Address
A-D control register (ADCON)
A-D conversion register (AD)
00D916
00DA16
Interrupt request register 1 (IR1)
Interrupt control register 1 (IE1)
00FC16
00FD16
00FE16
00FF16
Fig. 2.5.1 Memory map of A-D conversion related registers
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APPLICATION
2.5 A-D converter
2.5.2 Application examples
7470 7471 7477 7478
(1) A-D conversion value determination methods
For improvement of the accuracy of A-D conversion results, we recommend you perform sampling
several times to determine a value.
The following A-D conversion value sampling methods are available (m, n: Arbitrary values based on
the specification).
n
Example: 1 Sampling 2 times
n
2 Moving sampling 2 times
n
3 Sampling (2 + 2) times
For value determination, the following methods are available.
Example: [1] The sum of sampling result is divided by sampling times.
n
[2] After execution of sampling (2 + 2) times, the minimum value and the maximum
n
value are excluded and then the remaining values are added and then divided by 2
times.
[3] When updating the average value calculated by [1]or [2], this average value is not
updated if the difference from the previous value is ± m or more.
In “2.5.2 Application examples, (2) Example of A-D conversion setting,” an example of using the
sampling methods 2 + 3 and the determination method [3] is shown.
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APPLICATION
2.5 A-D converter
(2) Example of A-D conversion setting
7470 7471 7477 7478
An example of A-D conversion setting using the sampling methods 2 + 3 and the determination
method [3] described on the previous page is shown below.
Specifications: After execution of 6-time moving sampling the maximum value and the minimum
value are excluded and then the remaining values are added. This result is
divided by 4 (times). If the difference from the previous value is less than ±5, the
value is updated. If the same difference is ±5 or more, it is not updated.
Figure 2.5.2 shows an example of control procedure.
Maximum
Minimum
value
value
Sampling point
A-D conversion result
A616
A816
A916
A716
A816
AB16
A-D conversion routine
✻
Set the port P20 as an input
Clear the A-D conversion interrupt
request bit
N
A-D conversion completed ?
(Note 3)
Set the A-D control register
Y
0
0 ✕ ✕ 1 1 0
0
ADCON (Address 00D916)
AD input pin ← P20/IN0
End conversion
The contents of A-D conversion register is read
and stored into RAM.
(ADRAM) ← AB16
VREF is connected (Note 1)
Fixed to “0”
After execution of 6-time samplings to this time, the
minimum value and the maximum value are excluded and
then the remaining values are added.
Wait the VREF stabilizing time
(1.0 µs or more) (Note 2)
A816+A916+A716+A816=2A016
Set the A-D control register
Total of 4-time sampling
4
2A016
4
=A816
0 0 0
0 ✕ ✕ 1 0
ADCON (Address 00D916)
Clear the A-D conversion
completion bit
±5 or more
Compare with the previous fixed
value
✻
less than ±5
Notes 1: The 7477/7478 group is not provided with this bit.
2: Performs this operation only in the 7470/7471
group.
Renewal of fixed value
3:
A termination of A-D conversion is verified by the
state of the A-D conversion completion bit, the
state of the A-D conversion completion interrupt
request bit and a branch to the A-D conversion
completion interrupt processing routine.
RTS
Fig. 2.5.2 Example of A-D conversion control procedure
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APPLICATION
2.5 A-D converter
2.5.3 Notes on use
7470 7471 7477 7478
The analog input internal equivalent circuit is shown in Figure 2.5.3. For correct A-D conversion,
it is necessary that the internal capacitor should be completely charged within the specified time.
The maximum value of output impedance of the analog input source required to terminate capacitor
charging within this time is shown below.
• At f(XIN) = 4 MHz, Approximately 10 kΩ
• At f(XIN) = 8 MHz, Approximately 2 kΩ
If the maximum value of output impedance exceeds the above value, take a proper measure, for
example, insert a capacitor (0.1 µF to 1 µF) between analog input pin and VSS.
VCC
C1
=10 pF
±50%
R=4 kΩ ±60%
SW1(Note 2)
C2=6 pF ±30%
Port P2i/INi
(i=0 to 7)
SW2
V
SS
VSS
Amplifier
(Note 1)
Reference voltage
generation circuit
Switch tree
Resistor ladder
VREF switch (Note 3)
V
SS
VREF
Notes 1: This is a parasitic diode of the output transistor.
2: SW1 is turned on only when the analog input pin is selected.
3: The VREF switch is not provided in the 7477/7478 group.
Fig. 2.5.3 Analog input internal equivalent circuit
For other notes on use, refer to “1.14 A-D converter.”
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APPLICATION
2.6 Reset
7470 7471 7477 7478
2.6 Reset
2.6.1 Reset circuit
Figure 2.6.1 shows an example of reset circuit.
M3747x
M3747x
Supply voltage
detection circuit
RESET
RESET
V
CC
VCC
RESET, VCC pin number
32P
18
56P
42P
25
RESET
CC
28
23
V
17
22
Fig. 2.6.1 Example of reset circuit
2.6.2 Notes on use
For notes on use, refer to “1.15 Reset.”
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APPLICATION
2.7 Oscillation circuit
7470 7471 7477 7478
2.7 Oscillation circuit
(1) Oscillation circuit using a ceramic resonator
An oscillation circuit can be formed by connecting a ceramic resonator or a crystal oscillator between
the XIN pin and the XOUT pin and between the XCIN pin and the XCOUT pin.
Figure 2.7.1 shows an example of oscillation circuit using a ceramic resonator.
Regarding such circuit constants as Rd, CIN and COUT, ask the oscillator maker for information and
then set the recommended value.
7471/7478 group
7470/7477 group
X
IN
X
OUT
X
CIN
X
COUT
24
X
IN
XOUT
15
14
19
(18)
20
(19)
23
(25)
(26)
R
d
R
d
Rd'
C
IN
C
OUT
C
CIN
CCOUT
C
IN
COUT
Note: The number in parentheses denotes the case of a flat package.
Fig. 2.7.1 Example of Oscillation circuit using ceramic resonator
(2) External clock input
To the main clock and timer clock oscillation circuits, clocks can also be supplied from the outside.
Figure 2.7.2 shows an example of circuits in this case. At this time, make the XOUT (XCOUT) pin open.
As an external clock to be input to the XIN (XCIN) pin, use a pulse signal with a duty ratio of 50 %.
7471/7478 group
7470/7477 group
XIN
14
XOUT
XCIN
XIN
19
(18)
XOUT
XCOUT
24
(26)
Open
15
20
(19)
23
(25)
Open
Rd
External oscillation circuit
External oscillation circuit
VCC
VCC
CIN
COUT
VSS
Duty ratio 50%
VSS
Duty ratio 50%
Note: The number in parentheses denotes the case of a flat package.
Fig. 2.7.2 Example of external clock input circuit
Note: The XCIN and the XCOUT pin are not provided in the 7470/7477 group.
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APPLICATION
2.8 Low-power dissipation function
7470 7471 7477 7478
2.8 Low-power dissipation function
2.8.1 CPU mode register
+ 1
The CPU mode register consists of a stack page selection bit
and internal system clock control
+ 2
bits
.
+1: In the products having a RAM capacity of 192 bytes or less, a RAM is not arranged on page 1,
so this bit is not available. (Be sure to set this bit to “0.”)
+2: In the 7470/7477 group, which is not provided with a sub-clock (f(XCIN)) generating circuit, f(XCIN)
is not used. (Be sure to set this bit to “0.”)
Figure 2.8.1 shows a structure of CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
CPU mode register (CPUM) [Address 00FB16
]
B
Name
Function
At reset R W
0
Fix these bits to “0.”
0, 1
0: In page 0 area
1: In page 1 area
Stack page selection
bit
2
0
(Note 1)
3
4
Nothing is allocated for this bit. This is write
enabled bit and is undefined at reading.
?
0
? ✕
P5
0, P51/XCIN,XCOUT
0: P50, P51
selection bit
1: XCIN, XCOUT (Note 2)
0: Low
1: High
X
COUT drive capacity
0
0
5
6
(Note 2)
(Note 2)
selection bit
Main clock (XIN–XOUT
stop bit
)
0: Oscillates
1: Stops
Internal system clock
selection bit
0: XIN–XOUT selected
(Ordinary mode)
1: XCIN–XCOUT selected
(Low speed mode)
(Note 2)
7
0
Notes 1:
2:
In the products having a RAM capacity of 192 bytes or
less, set this bit to “0.”
Since the 7470/7477 group is not provided with the
sub-clock generating circuit, f(XCIN) cannot be used.
Fix these bits to “0.”
Fig. 2.8.1 Structure of CPU mode register
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APPLICATION
2.8 Low-power dissipation function
2.8.2 Application examples
7470 7471 7477 7478
As examples of application, examples of setting between modes are shown below.
(1) Ordinary mode → Stop mode → Ordinary mode
(2) Ordinary mode → Wait mode → Ordinary mode
(3) Ordinary mode → Low speed mode
(4) Low speed mode → Ordinary mode
Note: In the 7470/7477 group, which is not provided with a sub-clock generating circuit, the low-
speed mode is not available.
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APPLICATION
2.8 Low-power dissipation function
(1) Ordinary mode → Stop mode → Ordinary mode
7470 7471 7477 7478
,
,
,
,
Specifications: The stop mode is executed by the STP instruction.
Restoration to the ordinary mode is attained by INT0 interrupt.
Figure 2.8.2 shows an example of control procedure.
Clear the timer 3 interrupt enable bit (timer 3 interrupt disabled)
Clear the timer 4 interrupt enable bit (timer 4 interrupt disabled)
Stop the timer 3 and timer 4 and select the timer 3 count
source
(Set the Timer 34 mode register)
✕
✕ ✕ ✕ ✕ 1 ✕
1
T34M (Address 00F916
)
Select the timer 3 count source
Set the return interrupt source
Clear the INT interrupt request bit
Execute the NOP instruction
Set the INT interrupt enable bit
(INT interrupt enabled)
0
0
0
Set the timer 3 and 4 count state
(Set the Timer 34 mode register)
✕ ✕ ✕ ✕ 0 ✕ ✕ 0
T34M (Address 00F916
Timer 3 count
)
Timer 4 count
Clear the interrupt disable flag (each interrupt enabled)
Execute the STP instruction
INT0 interrupt
RTI
Set the interrupt disable flag (each interrupt disabled)
Re-set the timer 3 and 4
Timer 34 mode register
Timer 3 register
Timer 4 register
Clear the interrupt disable flag (each interrupt enabled)
Fig. 2.8.2 Example of control procedure [Ordinary mode → Stop mode → Ordinary mode]
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APPLICATION
2.8 Low-power dissipation function
(2) Ordinary mode → Wait mode → Ordinary mode
7470 7471 7477 7478
Specifications: The wait mode is executed by the WIT instruction.
Restoration to the ordinary mode is attained by INT0 interrupt.
Figure 2.8.3 shows an example of control procedure.
Set the return interrupt source
Clear the INT interrupt request bit
Execute the NOP instruction
Set the INT interrupt enable bit
(INT interrupt enable)
0
0
0
Clear the interrupt disable flag (each interrupt enable)
Execute the WIT instruction
INT0 interrupt
RTI
The next address of the WIT instruction
Fig. 2.8.3 Example of control procedure [Ordinary mode → Wait mode → Ordinary mode]
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APPLICATION
2.8 Low-power dissipation function
(3) Ordinary mode → Low speed mode
7470 7471 7477 7478
×
×
Specifications: The system clock is switched from the main clock (f(XIN) = 8 MHz) to the sub-
clock (f(XCIN) = 32 kHz). The main clock is stopped.
Figure 2.8.4 shows an example of control procedure.
Set the CPU mode register
✕ 0 0
0 0 1 1 ✕
CPUM (Address 00FB16)
Fixed to “0”
XCIN, XCOUT selected
XCOUT drive capacity High power selected
Main clock oscillation
System clock Ordinary mode selected
Wait f(XCIN) oscillation stabilizing time
✻ For certain time, ask the oscillator manufacturer for
information.
Set the CPU mode register
0
1 1 1 1 ✕ ✕
0
CPUM (Address 00FB16)
Fixed to “0”
XCIN, XCOUT selected
XCOUT drive capacity High power selected
Main clock stop
System clock Low speed mode selected
Fig. 2.8.4 Example of control procedure [Ordinary mode → Low speed mode]
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APPLICATION
2.8 Low-power dissipation function
(4) Low speed mode → Ordinary mode
7470 7471 7477 7478
×
×
Specifications: The system clock is switched from the sub-clock (f(XCIN) = 32 kHz) to the main
clock (f(XIN) = 8 MHz). The sub-clock is stopped.
Figure 2.8.5 shows an example of control procedure.
Set the CPU mode register
✕ 0 0
1 0 1 1 ✕
CPUM (Address 00FB16)
Fixed to “0”
XCIN, XCOUT selected
XCOUT drive capacity High power selected
Main clock oscillation
System clock Low-speed mode selected
Wait f(XIN) oscillation stabilizing time
✻ For certain time, ask the oscillator manufacturer.
Set the CPU mode register
0
0 0 ✕ 0 ✕ ✕
0
CPUM (Address 00FB16)
Fixed to “0”
P50, P51 selected
Main clock oscillation
System clock Ordinary mode selected
Fig. 2.8.5 Example of control procedure [Low speed mode → Ordinary mode]
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APPLICATION
2.8 Low-power dissipation function
2.8.3 Notes on use
7470 7471 7477 7478
2
For notes on use, refer to “1.17 Low-power dissipation function.”
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APPLICATION
2.9 Countermeasures against noise
7470 7471 7477 7478
2.9 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual
use.
2.9.1 Shortest wiring length
The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for the RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
Reason
The reset works to initialize a microcomputer.
The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If
noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released
before the internal state of the microcomputer is completely initialized. This may cause a program
runaway.
Noise
Reset
circuit
Reset
circuit
RESET
VSS
RESET
VSS
VSS
VSS
7470/7471/
7477/7478
group
7470/7471/
7477/7478
group
N.G.
O.K.
Fig. 2.9.1 Wiring for the RESET pin
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APPLICATION
2.9 Countermeasures against noise
7470 7471 7477 7478
(2) Wiring for clock input/output pins
● Make the length of wiring which is connected to clock I/O pins as short as possible.
● Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected
to an oscillator and the VSS pin of a microcomputer as short as possible.
● Separate the VSS pattern only for oscillation from other VSS patterns.
Reason
A microcomputer’s operation synchronizes with a clock generated by the oscillator (circuit). If noise
enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program
runaway.
Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and
the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
An example of VSS patterns on the
underside of a printed circuit board
Noise
Oscillator wiring
pattern example
X
X
V
IN
OUT
SS
X
X
V
IN
X
X
V
IN
OUT
SS
OUT
SS
Separate the VSS line for oscillation from other VSS lines
N.G.
O.K.
Fig. 2.9.2 Wiring for clock I/O pins
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APPLICATION
2.9 Countermeasures against noise
(3) Wiring for the VPP pin of the One Time PROM version and the
EPROM version
7470 7471 7477 7478
● Make the length of wiring which is connected to the
VPP pin as short as possible.
● Connect an approximately 5 kΩ resistor to the VPP
pin in serial.
● The P33 pin is also used as the VPP pin.
7470/7471/7477/7478 group
Approximately
Reason
5kΩ
The VPP pin of the One Time PROM and the EPROM
version is the power source input pin for the built-in
PROM. When programming in the built-in PROM, the
impedance of the VPP pin is low to allow the electric
current for wiring flow into the PROM. Because of
this, noise can enter easily. If noise enters the VPP
pin, abnormal instruction codes or data are read from
the built-in PROM, which may cause a program runaway.
P33/VPP
Fig. 2.9.3 Wiring for the VPP pin of the One
Time PROM and the EPROM
version
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APPLICATION
2.9 Countermeasures against noise
2.9.2 Connection of a bypass capacitor across the Vss line and
7470 7471 7477 7478
the Vcc line
Connect an approximately 0.1 µF bypass capacitor across
the VSS line and the VCC line as follows:
● Connect a bypass capacitor across the VSS pin and
the VCC pin at equal length.
● Connect a bypass capacitor across the VSS pin and
the VCC pin with the shortest possible wiring.
● Use lines with a larger diameter than other signal lines
for VSS line and VCC line.
V
CC
Chip
Chip
VCC
V
SS
V
CC
VSS
VSS
2.9.3 Wiring to analog input pins
● Connect an approximately 100 Ω to 1 kΩ resistor to an
analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the
microcomputer as close as possible.
● Connect an approximately 1000 pF capacitor across
the VSS pin and the analog input pin. Besides, connect
the capacitor to the VSS pin as close as possible. Also,
connect the capacitor across the analog input pin and
the VSS pin at equal length.
Fig. 2.9.4 Bypass capacitor across the VSS
line and the VCC line
Noise
Reason
Signals which is input in an analog input pin (such as an
A-D converter input pin) are usually output signals from
sensor. The sensor which detects a change of event is
installed far from the printed circuit board with a
microcomputer, the wiring to an analog input pin is longer
necessarily.
(Note)
Microcomputer
Analog
input pin
Thermistor
This long wiring functions as an antenna which feeds
noise into the microcomputer, which causes noise to an
analog input pin.
N.G.
O.K.
VSS
If a capacitor between an analog input pin and the VSS
pin is grounded at a position far away from the VSS pin,
noise on the GND line may enter a microcomputer through
the capacitor.
Note : The resistor is for dividing resistance
with a thermister.
Fig. 2.9.5 Analog signal line and a resistor
and a capacitor
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APPLICATION
2.9 Countermeasures against noise
2.9.4 Consideration for oscillator
7470 7471 7477 7478
Take care to prevent an oscillator that generates clocks
for a microcomputer operation from being affected by other
signals.
(1) Keeping an oscillator away from large current signal
lines
Microcomputer
Mutual inductance
M
Install a microcomputer (and especially an oscillator)
as far as possible from signal lines where a current
larger than the tolerance of current value flows.
X
X
IN
Large
current
OUT
V
SS
<Reason>
GND
In the system using a microcomputer, there are signal
lines for controlling motors, LEDs, and thermal heads
or others. When a large current flows through those
signal lines, strong noise occurs because of mutual
inductance.
Fig. 2.9.6 Wiring for a large current signal
line
(2) Keeping an oscillator away from signal lines where
potential levels change frequently
Install an oscillator and a connecting pattern of an
osillator away from signal lines where potential levels
change frequently.
Also, do not cross such signal lines over the clock
lines or the signal lines which are sensitive to noise.
CNTR
Do not cross
XIN
XOUT
VSS
<Reason>
Signal lines where potential levels change frequently
(such as the CNTR pin line) may affect other lines at
signal rising or falling edge. If such lines cross over
a clock line, clock waveforms may be deformed, which
causes a microcomputer failure or a program runaway.
Fig. 2.9.7 Wiring to a signal line where
p o t e n t i a l levels change
frequently
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APPLICATION
2.9 Countermeasures against noise
2.9.5 Setup for I/O ports
7470 7471 7477 7478
Setup I/O ports using hardware and software as follows:
<Hardware>
● Connect a resistor of 100 Ω or more to an I/O port
in series.
Noise
<Software>
O.K.
● As for an input port, read data several times by a
program for checking whether input levels are equal
or not.
● As for an output port, since the output data may
reverse because of noise, rewrite data to its port
latch at fixed periods.
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
● Rewrite data to direction registers and pull-up control
registers (only the product having it) at fixed periods.
When a direction register is set for input port again
at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable,
connect a capacitor to this port to remove the
noise pulse.
Fig. 2.9.8 Setup for I/O ports
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APPLICATION
2.9 Countermeasures against noise
2.9.6 Providing of watchdog timer function by software
7470 7471 7477 7478
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors
of the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine
processing.
<The main routine>
● Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N + 1 Q (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the
initial value N should have a margin.
● Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing count after the initial value N has been set.
● Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following cases:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
● Decrements the SWDT contents by 1 at each interrupt processing.
● Determins that the main routine operates normally when the SWDT contents are reset to the initial
value N at almost fixed periods (at the fixed interrupt processing count).
● Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
When the contents of the SWDT reach 0 or less by continuative decrement without initializing to
the initial value N.
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APPLICATION
2.9 Countermeasures against noise
7470 7471 7477 7478
Interrupt processing routine
Main routine
(SWDT) ← (SWDT)—1
(SWDT) ← N
CLI
Interrupt processing
Main processing
> 0
(SWDT)
≤ 0 ?
RTI
≠ N
≤ 0
(SWDT)
= N ?
Return
= N
Main routine
errors
Interrupt processing
routine errors
Fig. 2.9.9 Watchdog timer by software
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APPLICATION
2.10 Notes on programming
7470 7471 7477 7478
2.10 Notes on programming
2.10.1 Processor status register
(1) Initialization of processor status register
After a reset, the contents of the processor
status register (PS) are undefined except for
the I flag which is “1.” Therefore, flags which
affect program execution must be initialized
after a reset.
Reset
Flags initializing
Main program
In particular, it is essential to initialize the T
and D flags because they have an important
effect on calculations.
(2) How to reference the processor status
register
To reference the contents of the processor
status register (PS), execute the PHP instruction
once then read the contents of (S + 1). If
necessary, execute the PLP instruction to return
the PS to its original status. A NOP instruction
should be executed after every PLP instruction.
Fig. 2.10.1 Initialization of flags in PS
(S)
Saved PS
(S) + 1
Fig. 2.10.2 Stack memory contents after PHP
instruction execution
PLP instruction
NOP instruction
Fig. 2.10.3 Note to execute by PLP instruction
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APPLICATION
2.10 Notes on programming
2.10.2 Decimal calculations
7470 7471 7477 7478
(1) Execution of decimal calculations
The ADC and SBC are the only instructions
which will yield proper decimal results in decimal
mode. To calculate in decimal notation, set
the decimal mode flag (D) to “1” with the SED
instruction. After executing the ADC or SBC
instruction, execute another instruction before
executing the SEC, CLC, or CLD instruction.
Set D Flag to “1”
ADC or SBC instruction
NOP instruction
(2) Note on flags in decimal mode
When decimal mode is selected, the values of
three of the flags in the status register (the N,
V, and Z flags) are invalid after a ADC or SBC
instruction is executed.
SEC, CLC, or CLD instruction
The Carry flag (C) is set to “1” if a carry is
generated as a result of the calculation, or is
cleared to “0” if a borrow is generated. To
determine whether a calculation has generated
a carry, the C flag must be initialized to “0”
before each calculation. To check for a bor-
row, the C flag must be initialized before each
calculation.
Fig. 2.10.4 Note for decimal operation
2
For other notes, refer to the notes described in
each section.
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APPLICATION
2.12 Example of application circuit
7470 7471 7477 7478
2.12 Example of application circuit
×
×
×
Figures 2.12.1 and 2.12.2 show examples of application circuit using the 7470 group, the 7478 group respectively.
M37470M2
Fig. 2.12.1 Application circuit example (cleaner)
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APPLICATION
2.12 Example of application circuit
7470 7471 7477 7478
×
×
×
M37478M4T
Fig. 2.12.2 Application circuit example (Semi-auto air conditioner)
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CHAPTER 3
APPENDIX
3.1 Control registers
3.2 Mask ROM ordering
method
3.3 ROM programming
ordering method
3.4 Mark specification form
3.5 Package outline
3.6 SFR memory map
3.7 Pin configuration
APPENDIX
3.1 Control registers
3.1 Control registers
Port Pi direction register
b7 b6 b5 b4 b3b2 b1 b0
Port Pi direction register (PiD) (i = 0,1,2,4)
[Address 00C116, 00C316, 00C516, 00C916]
At reset
R W
B
0
Name
Function
0 : Port Pi0 input mode
1 : Port Pi0 output mode
Port Pi direction
register
0
0 : Port Pi1 input mode
1 : Port Pi1 output mode
1
2
3
4
0
0
0
0
0
0
0
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
5
6
0 : Port Pi6 input mode
1 : Port Pi6 output mode
7
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Notes 1: The 7477/7478 group is not provided with the port P2
direction register (input only).
2: The Port P4 is provided as below:
•7470/7477 group has 2 bits of P4 0 and P41
•7471/7478 group has 4 bits of P4 0 to P43.
Fig. 3.1.1 Structure of Port Pi direction register (i=0, 1, 2, 4)
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register
[Address 00D016]
Function
At reset
B
0
Name
R W
Port P00 pull-up
control bit
0 : No pull-up
1 : Pull-up
0
Port P01 pull-up
control bit
0 : No pull-up
1 : Pull-up
1
2
3
4
0
0
0
0
0
0
0
Port P02 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P03 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P04 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P05 pull-up
control bit
0 : No pull-up
1 : Pull-up
5
6
Port P06 pull-up
control bit
0 : No pull-up
1 : Pull-up
Port P07 pull-up
control bit
0 : No pull-up
1 : Pull-up
7
Fig. 3.1.2 Structure of Port P0 pull-up control register
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APPENDIX
3.1 Control registers
Ports P1 to P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Ports P1 to P5 pull-up control register [Address 00D116]
At reset
b
0
Function
0 : No pull-up
1 : Pull-up
Name
R W
Ports P10 to P13
pull-up control bit
Ports P14 to P17
pull-up control bit
0
0
0
0
0
?
0 : No pull-up
1 : Pull-up
1
Ports P2
0
to P2
3
pull-up
(Note 2)
0 : No pull-up
1 : Pull-up
2
3
control bit
0 : No pull-up
1 : Pull-up
Ports P2
control bit
Ports P4
control bit
4
to P2
7
pull-up
(Notes 2, 3)
0 : No pull-up
1 : Pull-up
0
to P4
3
pull-up
(Note 4)
4
5
6
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
✕
✕
?
?
Ports P5
0
to P5
3
pull-up
(Note 3)
0 : No pull-up
1 : Pull-up
0
?
control bit
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
7
Notes
1 : In the 7470/7477 group, the P1 to P4 Pull-up control register
is provided.
2 : In the 7477/7478 group, nothing is allocated to these bits.
They are undefined at reading.
3 : In the 7470/7477 group, nothing is allocated to these bits.
They are undefined at reading.
4 : The 7470/7477 group is provided with only P40 and P41.
Fig. 3.1.3 Structure of Ports P1 to P5 pull-up control register
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416]
At reset
Name
Function
R
W
B
0
INT0 edge selection
bit
0 : Falling edge
1 : Rising edge
0
0 : Falling edge
1 : Rising edge
1
2
3
4
5
INT1 edge selection
bit
0
0
0 : Falling edge
1 : Rising edge
0 : Falling edge
1 : Rising edge
CNTR0 edge
selection bit
CNTR1 edge
selection bit
0
0
0 : CNTR0
1 : CNTR1
CNTR0/CNTR1
interrupt selection bit
INT1 source selection 0 : P31/INT1
bit (at STP or WIT 1 : P0 to P07 “L” level input
0
0
?
instruction execution) (for key-on wake-up)
Nothing is allocated for these bits. These are
write disabled bits and are undefined at reading.
6, 7
?
✕
Fig. 3.1.4 Structure of Edge polarity selection register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-3
APPENDIX
3.1 Control registers
Input latch register
b7 b6 b5 b4 b3 b2 b1b0
Input latch register (ILR) [Address 00D616
]
At reset
B
0
Name
Function
When b0 of EG (Note) is “0”:
reverse level on INT pin
R W
P30
/INT
0
latch bit
0
?
✕
When b0 of EG (Note) is “1”:
level on INT pin
0
1
2
3
When b1 of EG (Note) is “0”:
reverse level on INT pin
P31
P32
P33
/INT
1
latch bit
1
?
?
✕
When b1 of EG (Note) is “1”:
level on INT pin
1
When b2 of EG (Note) is “0”:
reverse level on CNTR0 pin
/CNTR
/CNTR
0
1
latch bit
latch bit
✕
✕
When b2 of EG (Note) is “1”:
level on CNTR pin
0
When b3 of EG (Note) is “0”:
reverse level on CNTR pin
1
?
?
When b3 of EG (Note) is “1”:
level on CNTR pin
1
Nothing is allocated for these bits. These
are write disabled bits and are undefined at
reading.
4
to
7
?
✕
Note: EG is the Edge polarity selection register.
Fig. 3.1.5 Structure of Input latch register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
0
A-D control register (ADCON) [Address 00D916
]
At reset
B
0
Name
R
Function
W
b2 b1 b0
A-D input selection
bits
0 0 0 : P2
0 0 1 : P2
0 1 0 : P2
0 1 1 : P2
1 0 0 : P2
1 0 1 : P2
1 1 0 : P2
1 1 1 : P2
0
1
2
3
4
5
6
7
/IN
/IN
/IN
/IN
/IN
/IN
/IN
/IN
0
1
2
3
4
5
6
7
0
1
2
0
(Note 1)
0
1
A-D conversion end
3
4
0 : Under conversion
1 : End conversion
bit
(Note 2)
V
REF connection
selection bit
The 7477/7478 group is not
provided with this bit.
This bit is undefined at
reset.
0 : The VREF pin is
separated from the
comparison voltage
generator.
1 : The VREF pin is
connected to
0
✽
comparison voltage
generator.
Nothing is allocated for these bits.
These are write disabled bits and are
undefined at reading.
5, 6
7
?
0
? ✕
Fix this bit to “0.”
0
0
Notes 1: Since the 7470/7477 group is not provided with pins
P2 –P2 , do not set.
2: •A-D conversion is started by setting bit 3 to “0.”
4
7
•Writing “0” into bit 3 is valid. Even if “1” is written into
bit 3, this bit is not set to “1.” Accordingly, when writing a
value into the A-D control register without affecting bit 3,
set bit 3 to “1.”
Fig. 3.1.6 Structure of A-D control register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-4
APPENDIX
3.1 Control registers
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address 00DA16]
At reset
R
B
Function
W
0
to
7
This is a read-only register to store A-D
conversion results.
?
✕
Fig. 3.1.7 Structure of A-D conversion register
Serial I/O mode register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O mode register (SM) [Address 00DC16]
At reset
R W
B
Name
Function
b1 b0
Internal clock
selection bits
0, 1
0 0 : f(XIN)/8 or f(XCIN)/8
0 1 : f(XIN)/16 or f(XCIN)/16
1 0 : f(XIN)/32 or f(XCIN)/32
1 1 : f(XIN)/512 or f(XCIN)/512
(Note)
0
Synchronous clock 0 : External clock
2
3
0
0
selection bit
1 : Internal clock
0 : Ordinary I/O port
(P15, P16)
Serial I/O port
selection bit
1 : Serial I/O port (SOUT, CLK pin)
0 : Ordinary I/O port(P17)
1 : SRDY signal output pin
SRDY signal output
selection bit
4
5
6
7
0
SRDY signal
selection bit
0 : SRDY signal
1 : SARDY signal
0
0
Serial I/O byte specify
mode selection bit
0 : Ordinary mode
1 : Byte specify mode
P1
5/SOUT, SRDY output 0 : CMOS output
0
structure selection bit
1 : N-channel open-drain
output
Note: Since the 7470 group is not provided with the sub-clock
generating circuit, do not select f(XCIN).
Fig. 3.1.8 Structure of Serial I/O mode register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-5
APPENDIX
3.1 Control registers
Serial I/O register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O register (SIO) [Address 00DD16]
At reset
B
Function
R
W
0
to
7
A value of “0016” to “FF16” can be
set as transmit data.
At the transmit, data is transmitted one
bit at a time starting with the least
significant bit.
At the receive, data is received one bit
at a time starting with the most
significant bit.
At transmit:
At receive:
?
Fig. 3.1.9 Structure of Serial I/O register
Serial I/O counter and Byte counter (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O counter and Byte counter [Address 00DE16]
At reset
B
Function
R W
0
to
3
Byte counter
When using the byte specification mode, set
a value of “0016” to “0F16.” Supposing that the
value to be written into the byte counter is “n,”
a Serial transmit/receive is performed with the
clock of the “n + 1”-th byte.
?
4
to
6
Serial I/O counter
When the internal clock is selected as a
synchronous clock, this counter generates 8
shift clocks.
When transmit data is written into the Serial
I/O register, “0716” is set in the Serial I/O
counter.
?
?
✕
7
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
? ✕
Fig. 3.1.10 Structure of Serial I/O counter and Byte counter
7470/7471/7477/7478 GROUP USER’S MANUAL
3-6
APPENDIX
3.1 Control registers
Transmit/receive buffer register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/receive buffer register (TB/RB) [Address 00E016]
At reset
B
Function
R
W
A value of “0016” to “FF16” can be
set as transmit data.
At transmit:
At receive:
0
to
7
The transmit data is transferred
automatically by writing the transmit
data into the Transmit shift register.
When all receive data has been input
into the Receive shift register, the
receive data is automatically trans-
ferred to the receive buffer register.
?
Fig. 3.1.11 Structure of Transmit/receive buffer register
Serial I/O status register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1
Serial I/O status register (SIOSTS) [Address 00E116]
At reset
R
W
B
0
Name
Function
0 : Buffer full
1 : Buffer empty
Transmit buffer
empty flag (TBE)
0
✕
✕
✕
✕
✕
✕
✕
Receive buffer full
flag (RBF)
0 : Buffer empty
1 : Buffer full
1
2
3
4
5
6
7
0
0
0
0
0
0
1
Transmit shift
completion flag (TSC)
Overrun error flag
(OE)
0 : Transmit shift in progress
1 : Transmit shift completed
0 : No error
1 : Overrun error
Parity error flag
(PE)
0 : No error
1 : Parity error
Framing error flag
(FE)
0 : No error
1 : Framing error
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
Summing error
flag (SE)
Nothing is allocated for this bit. This is a write
disabled bit. When this bit is read out, the value
is “1.”
1 ✕
Fig. 3.1.12 Structure of Serial I/O status register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-7
APPENDIX
3.1 Control registers
Serial I/O control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address 00E216
]
At reset
B
0
Function
Name
BRG count source
selection bit (CSS)
R W
0 : f(XIN)/4 or f(XCIN)/4
1 : f(XIN)/16 or f(XCIN)/16
0
1
Serial I/O
synchronous clock
selection bit (SCS)
•In clock synchronous mode
0 : BRG output divided by 4
1 : External clock input
•In UART mode
0
0 : BRG output divided by 16
1 : External clock input
divided by 16
2
3
S
RDY output enable
0 : P1
as ordinary I/O pin
1 : P1 /SRDY pin operates
7/SRDY pin operates
bit (SRDY)
✽In the UART mode,
0
0
7
this bit is invalid.
as SRDY output pin
Transmit interrupt
source selection
bit (TIC)
0 : When transmit buffer
has emptied
1 : When transmit shift
operation is completed
0 : Transmit disabled
1 : Transmit enabled
4
5
6
Transmit enable bit (TE)
Receive enable bit (RE)
0
0
0 : Receive disabled
1 : Receive enabled
Serial I/O mode
selection bit (SIOM)
0 : Clock asynchronous
serial I/O (UART)
0
1 : Clock synchronous
7
Serial I/O enable
bit (SIOE)
0 : Serial I/O disabled
(pins operates as ordinary
0
I/O pins P14–P17)
1 : Serial I/O enabled
(pins operates as serial
I/O pins RXD - SRDY
)
(Note)
Note: Port P1
the serial I/O enable bit is “1” (enable state).
At this time, Port P1 is also used as an ordinary I/O port.
In the UART mode, port P1 is used as an ordinary I/O port
when the internal clock is selected.
4–P17 are operates as the serial I/O pin only when
7
6
Fig. 3.1.13 Structure of Serial I/O control register
UART control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1
1
UART control register (UARTCON) [Address 00E316
]
At reset
B
0
Name
Function
R W
0: 8 bits
1: 7 bits
Character length
selection bit (CHAS)
0
0
0
0
0: Parity checking disabled
1: Parity checking enabled
1
2
3
Parity enable bit
(PARE)
Parity selection bit
(PARS)
0: Even parity
1: Odd parity
Stop bit length
0: 1 stop bit
selection bit (STPS) 1: 2 stop bits
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
4
to
7
1
1 ✕
Fig. 3.1.14 Structure of UART control register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-8
APPENDIX
3.1 Control registers
Timers 1 to 4
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1, Timer 2, Timer 3, Timer 4 (T1, T2, T3, T4)
[Address 00F016, 00F116, 00F216, 00F316]
At reset
B
Function
R W
0
to
7
(Note)
•Set “0016 to FF16.”
•The value is decremented by 1 each time a
count source is input.
•Each Timer values are set to the respective
counter.
•The count values are read out by reading the
respective timer.
Note : Timers 1 and 2 are undefined.
Timer 3 is “FF16.”
Timer 4 is “0716.”
Fig. 3.1.15 Structure of Timers 1 to 4
Timer FF register
b7 b6 b5 b4 b3 b2 b1 b0
00F716]
Timer FF register (TF) [Address
Name
At reset
B
0
Function
R
W
Timer 1
division flip-flop
0 : Initial value is “0”
1 : Initial value is “1”
0 : Initial value is “0”
1 : Initial value is “1”
0
0
?
Timer 4
division flip-flop
1
2
to
7
Nothing is allocated for these bits. These are
write disabled bits and are undefined at
reading.
? ✕
Fig. 3.1.16 Structure of Timer FF register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-9
APPENDIX
3.1 Control registers
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register (T12M) [Address 00F816
]
B
0
Name
At reset
0
Function
0 : Count start
1 : Count stop
R
W
Timer 1 count stop
bit
0 : Internal clock
1 : P32/CNTR0 external clock
(Note 1)
1
2
Timer 1 count
source selection bit
0
0
Timer 1 internal clock 0 : f(XIN)/16 or f(XCIN)/16
source selection bit 1 : f(XCIN (Note 2)
)
0 : P1
2 port output
3
P1 /T port output
selection bit
2
0
1 : T (Timer 1 overflow
0
0
divided by 2)
0 : Count start
1 : Count stop
Timer 2 count stop
bit
4
5
0
0
0 : Internal clock (Note 1)
1 : Timer 1 overflow signal
b7 b6
Timer 2 count
source selection bit
Timer 2 internal clock
source selection bits
6, 7
0
0
1
1
0
1
0
1
:
:
:
:
f(XIN)/16 or f(XCIN)/16
f(XIN)/64 or f(XCIN)/64
f(XIN)/128 or f(XCIN)/128
f(XIN)/256 or f(XCIN)/256
(Note 3)
0
Notes 1: In the 7470/7477 group, the internal clock is f(XIN)/16.
2: Since the 7470/7477 group is not provided the sub-clock
generating circuit, f(XCIN) cannot be used. Fix this bit to “0.”
3: Since the 7470/7477 group is not provided the sub-clock
generating circuit, f(XCIN) cannot be used.
Fig. 3.1.17 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
00F916
]
Timer 34 mode register (T34M) [Address
B
Name
At reset
0
Function
R
W
0
Timer 3 count stop
bit
0 : Count start
1 : Count stop
b2 b1
1, 2
Timer 3 count
source selection bits
0 0 : f(XIN)/16 or f(XCIN)/16
0 1 : f(XCIN
)
1 0 : Timer 1 overflow or
Timer 2 overflow
0
1 1 : P3
3
/CNTR
1
external
(Note 2)
clock
3
Timer 4 count stop
bit
0 : Count start
1 : Count stop
0
0
b4 b3
Timer 4 count
source selection bits
4, 5
0 0 : Timer 3 overflow
0 1 : f(XIN)/16 or f(XCIN)/16
1 0 : Timer 1 overflow or
Timer 2 overflow
1 1 : P3
3/CNTR
1
external
clock
(Notes 1, 2)
Timer 4 pulse width
measurement mode
selection bit
6
7
0 : Timer mode
1 : External pulse width
measurement mode
0
0
P1
3/T1 port output
0 : P1
1 : (Timer 4 overflow divided
by 2 or PWM output)
3 port
selection bit
T
1
Notes 1: When Timer 1 overflow is selected as a Timer 2
count source, the Timer 4 count source is the Timer 1
overflow regardless of the value of bit 6 of the
Timer mode register 2.
2: Since the 7470/7477 group is not provided the sub-clock
generating circuit, f(XCIN) cannot be used.
Fig. 3.1.18 Structure of Timer 34 mode register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-10
APPENDIX
3.1 Control registers
Timer mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 2 (TM2) [Address 00FA16]
B
Name
R
?
W
Function
At reset
Timer 1 overflow FF
set enable bit
Timer 4 overflow FF
set enable bit
0 : Set disable
1 : Set enable
0
0
0 : Set disable
1 : Set enable
1
0
?
Nothing is allocated for these bits. These are
write disabled bits and are undefined at reading.
2
to
5
✕
Timer 3, timer 4 count
overflow signal selection bit
0 : Timer 1 overflow
1 : Timer 2 overflow
0 : Ordinary mode
1 : PWM mode
6
7
0
0
Timer 3, timer 4
function selection bit
Fig. 3.1.19 Structure of Timer mode register 2
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
CPU mode register (CPUM) [Address 00FB16]
B
Name
Function
At reset R W
0
Fix these bits to “0.”
0, 1
0: In page 0 area
1: In page 1 area
Stack page selection
bit
2
0
(Note 1)
3
4
Nothing is allocated for this bit. This is write
enabled bit and is undefined at reading.
?
0
? ✕
P50, P51/XCIN,XCOUT
selection bit
0: P50, P51
1: XCIN, XCOUT (Note 2)
0: Low
1: High
XCOUT drive capacity
selection bit
0
0
5
6
(Note 2)
Main clock (XIN–XOUT)
stop bit
0: Oscillates
1: Stops
(Note 2)
Internal system clock
selection bit
0: XIN–XOUT selected
(Ordinary mode)
1: XCIN–XCOUT selected
(Low speed mode)
(Note 2)
7
0
Notes 1:
2:
In the products having a RAM capacity of 192 bytes or
less, set this bit to “0.”
Since the 7470/7477 group is not provided with the
sub-clock generating circuit, f(XCIN) cannot be used.
Fix these bits to “0.”
Fig. 3.1.20 Structure of CPU mode register
7470/7471/7477/7478 GROUP USER’S MANUAL
3-11
APPENDIX
3.1 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IR1) [Address 00FC16]
At reset
B
0
Name
Function
R W
0
0 : No interrupt request
1 : Interrupt requested
Timer 1 interrupt
request bit
✽
1
2
3
4
5
Timer 2 interrupt
request bit
0 : No interrupt request
1 : Interrupt requested
0
0
0
?
✽
✽
Timer 3 interrupt
request bit
Timer 4 interrupt
request bit
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
0 : No interrupt request
1 : Interrupt requested
0 : No interrupt request
1 : Interrupt requested
✽
?
✕
✽
Serial I/O receive interrupt
request bit
0 : No interrupt request
1 : Interrupt requested
0
(7477/7478 group)(Note)
0 : No interrupt request
1 : Interrupt requested
Serial I/O interrupt request
6
bit (7470/7471group)
Serial I/O transmit
interrupt request bit
(7477/7478 group)
0
0
✽
✽
7
A-D conversion completion 0 : No interrupt request
interrupt request bit 1 : Interrupt requested
Note: In the 7470/7471group, nothing is allocated for bit 5. This is write
disabled bit and is undefined at reading.
✽: “0” is set by software, but not “1.”
Fig. 3.1.21 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IR2) [Address 00FD16]
At reset
B
0
Name
Function
R W
0
0 : No interrupt request
1 : Interrupt requested
INT0 interrupt request
bit
✽
1
2
INT1 interrupt request 0 : No interrupt request
0
0
?
✽
✽
bit
1 : Interrupt requested
CNTR0 or CNTR1
interrupt request bit
0 : No interrupt request
1 : Interrupt requested
Nothing is allocated for these bits. There are write
disabled bits and are undefined at reading.
3
to
7
✕
?
✽: “0” is set by software, but not “1.”
Fig. 3.1.22 Structure of Interrupt request register 2
7470/7471/7477/7478 GROUP USER’S MANUAL
3-12
APPENDIX
3.1 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (IE1) [Address 00FE16]
At reset
B
0
Name
Function
R W
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt
enable bit
Timer 2 interrupt
enable bit
1
2
3
4
5
0 : Interrupt disabled
1 : Interrupt enabled
Timer 3 interrupt
enable bit
Timer 4 interrupt
enable bit
Nothing is allocated for this bit. This is write
disabled bit and is undefined at reading.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
?
0
?
✕
Serial I/O receive interrupt
enable bit (7477/7478
group) (Note)
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O interrupt enable
bit (7470/7471 group)
Serial I/O transmit interrupt
enable bit (7477/7478 group)
0 : Interrupt disabled
1 : Interrupt enabled
6
7
0
0
A-D conversion completion 0 : Interrupt disabled
interrupt enable bit 1 : Interrupt enabled
Note: In the 7470/7471 group, Nothing is allocated for bit 5.
This is write disabled bit and undefined at reading.
Fig. 3.1.23 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (IE2) [Address 00FF16]
At reset
B
0
Name
Function
R W
0
0 : Interrupt disabled
1 : Interrupt enabled
INT0 interrupt enable
bit
1
2
INT1 interrupt enable
bit
CNTR0 or CNTR1
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
?
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is allocated for these bits. There are write
disabled bits and are undefined at reading.
3
to
7
✕
?
Fig. 3.1.24 Structure of Interrupt control register 2
7470/7471/7477/7478 GROUP USER’S MANUAL
3-13
APPENDIX
3.2 Mask ROM ordering method
3.2 Mask ROM ordering method
GZZ-SH02-91B<9YA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37470M2-XXXSP
MITSUBISHI ELECTRIC
Section head Supervisor
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Note : Please fill in all items marked ❈.
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)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from
this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
EPROM address
EPROM address
000016
000016
000016
Area for ASCII
codes of the name
of the product
‘M37470M2–’
Area for ASCII
codes of the name
of the product
‘M37470M2–’
Area for ASCII
codes of the name
of the product
‘M37470M2–’
000F16
001016
000F16
001016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
ROM (4K)
ROM (4K)
ROM (4K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37470M2–’ to addresses 000016 to 000F16.
ASCII codes ‘M37470M2–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘0’ = 3016
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-14
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-92B<9YA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37470M4-XXXSP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from
this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM
EPROM type (indicate the type used)
(hexadecimal notation)
27128
27256
27512
EPROM address
EPROM address
EPROM address
000016
000016
000016
Area for ASCII
codes of the name
of the product
‘M37470M4–’
Area for ASCII
codes of the name
of the product
‘M37470M4–’
Area for ASCII
codes of the name
of the product
‘M37470M4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37470M4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37470M4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘0’ = 3016
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-16
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-93B<9YA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37470M8-XXXSP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from
this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM
EPROM type (indicate the type used)
(hexadecimal notation)
27256
27512
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
‘M37470M8–’
Area for ASCII
codes of the name
of the product
‘M37470M8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37470M8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37470M8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘0’ = 3016
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘8’ = 3816
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-18
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-94B<9YB0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37471M2-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from
this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Microcomputer name :
M37471M2-XXXSP
M37471M2-XXXFP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37471M2–’
Area for ASCII
codes of the name
of the product
‘M37471M2–’
‘M37471M2–’
000F16
001016
000F16
001016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
ROM (4K)
ROM (4K)
ROM (4K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37471M2–’ to addresses 000016 to 000F16.
ASCII codes ‘M37471M2–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘1’ = 3116
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-20
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-95B<9YB0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37471M4-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from
this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Microcomputer name :
M37471M4-XXXSP
M37471M4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37471M4–’
Area for ASCII
codes of the name
of the product
‘M37471M4–’
‘M37471M4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37471M4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37471M4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘1’ = 3116
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘4’ = 3416
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-22
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-96B<9YB0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37471M8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from
this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
M37471M8-XXXSP
M37471M8-XXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37471M8–’
‘M37471M8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37471M8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37471M8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘1’ = 3116
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-24
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH08-22B<3ZA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37477M2TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37477M2TXXXSP
M37477M2TXXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Product name
Product name
ASCII code :
‘M37477M2T’
Product name
ASCII code :
‘M37477M2T’
ASCII code :
‘M37477M2T’
000F16
001016
000F16
001016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
data
data
data
ROM 4096 bytes
ROM 4096 bytes
ROM 4096 bytes
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘7’ = 3716
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
(2) The ASCII codes of the product name “M37477M2T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-26
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-67B<2XA1>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37477M4-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37477M4-XXXSP
M37477M4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Product name
Product name
ASCII code :
‘M37477M4–’
Product name
ASCII code :
‘M37477M4–’
ASCII code :
‘M37477M4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
data
data
data
ROM 8192 bytes
ROM 8192 bytes
ROM 8192 bytes
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘7’ = 3716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
(2) The ASCII codes of the product name “M37477M4–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘4’ = 3416
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-28
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-73B<2XA1>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37477M4TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37477M4TXXXSP
M37477M4TXXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Product name
Product name
ASCII code :
‘M37477M4T’
Product name
ASCII code :
‘M37477M4T’
ASCII code :
‘M37477M4T’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
data
data
data
ROM 8192 bytes
ROM 8192 bytes
ROM 8192 bytes
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘7’ = 3716
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
(2) The ASCII codes of the product name “M37477M4T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-30
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-68B<2XA1>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37477M8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37477M8-XXXSP
M37477M8-XXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37477M8–’
ASCII code :
‘M37477M8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘7’ = 3716
‘M’ = 4D16
‘8’ = 3816
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M37477M8–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-32
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-74B<2XA1>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37477M8TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37477M8TXXXSP
M37477M8TXXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37477M8T’
ASCII code :
‘M37477M8T’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘7’ = 3716
‘ T ’ = 5416
FF16
(2) The ASCII codes of the product name “M37477M8T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘8’ = 3816
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-34
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH08-23B<2XA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37478M2TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37478M2TXXXSP
M37478M2TXXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Product name
Product name
ASCII code :
‘M37478M2T’
Product name
ASCII code :
‘M37478M2T’
ASCII code :
‘M37478M2T’
000F16
001016
000F16
001016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
data
data
data
ROM 4096 bytes
ROM 4096 bytes
ROM 4096 bytes
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘8’ = 3816
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
(2) The ASCII codes of the product name “M37478M2T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-36
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-70B<2XA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37478M4-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37478M4-XXXSP
M37478M4-XXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Product name
Product name
ASCII code :
‘M37478M4–’
Product name
ASCII code :
‘M37478M4–’
ASCII code :
‘M37478M4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
data
data
data
ROM 8192 bytes
ROM 8192 bytes
ROM 8192 bytes
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘8’ = 3816
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
(2) The ASCII codes of the product name “M37478M4–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-38
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-76B<2XA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37478M4TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37478M4TXXXSP
M37478M4TXXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Product name
Product name
ASCII code :
‘M37478M4T’
Product name
ASCII code :
‘M37478M4T’
ASCII code :
‘M37478M4T’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
data
data
data
ROM 8192 bytes
ROM 8192 bytes
ROM 8192 bytes
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘8’ = 3816
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
(2) The ASCII codes of the product name “M37478M4T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-40
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-71B<2XA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37478M8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37478M8-XXXSP
M37478M8-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37478M8–’
ASCII code :
‘M37478M8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘8’ = 3816
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M37478M8–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘8’ = 3816
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-42
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-77B<2XA0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37478M8TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37478M8TXXXSP
M37478M8TXXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37478M8T’
ASCII code :
‘M37478M8T’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘8’ = 3816
‘ T ’ = 5416
FF16
(2) The ASCII codes of the product name “M37478M8T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘8’ = 3816
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-44
APPENDIX
3.3 ROM programming ordering method
3.3 ROM programming ordering method
GZZ-SH03-60B<06A0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37470E4-XXXSP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this
data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
EPROM address
EPROM address
000016
000016
000016
Area for ASCII
codes of the name
of the product
‘M37470E4–’
Area for ASCII
codes of the name
of the product
‘M37470E4–’
Area for ASCII
codes of the name
of the product
‘M37470E4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37470E4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37470E4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘0’ = 3016
‘E’ = 4516
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-46
APPENDIX
3.3 ROM programming ordering method
GZZ-SH02-97B<9YA0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37470E8-XXXSP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this
data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM
EPROM type (indicate the type used)
(hexadecimal notation)
27256
27512
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
‘M37470E8–’
Area for ASCII
codes of the name
of the product
‘M37470E8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37470E8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37470E8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘0’ = 3016
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
‘E’ = 4516
‘8’ = 3816
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-48
APPENDIX
3.3 ROM programming ordering method
GZZ-SH03-59B<06B0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37471E4-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this
data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Microcomputer name :
M37471E4-XXXSP
M37471E4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
EPROM address
EPROM address
000016
000016
000016
Area for ASCII
codes of the name
of the product
‘M37471E4–’
Area for ASCII
codes of the name
of the product
‘M37471E4–’
Area for ASCII
codes of the name
of the product
‘M37471E4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37471E4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37471E4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘1’ = 3116
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
‘E’ = 4516
‘4’ = 3416
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-50
APPENDIX
3.3 ROM programming ordering method
GZZ-SH02-98B<9YB0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37471E8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this
data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
M37471E8-XXXSP
M37471E8-XXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
‘M37471E8–’
Area for ASCII
codes of the name
of the product
‘M37471E8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37471E8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37471E8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘1’ = 3116
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-52
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-79B<2XA1>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37477E8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37477E8-XXXSP
M37477E8-XXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37477E8–’
ASCII code :
‘M37477E8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘7’ = 3716
‘E’ = 4516
‘8’ = 3816
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M37477E8–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-54
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-83B<2XA1>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37477E8TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M37477E8TXXXSP
M37477E8TXXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37477E8T’
ASCII code :
‘M37477E8T’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘7’ = 3716
‘E’ = 4516
‘8’ = 3816
‘ T ’ = 5416
FF16
(2) The ASCII codes of the product name “M37477E8T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-56
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-81B<2XA0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37478E8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from
this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37478E8-XXXSP
M37478E8-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37478E8–’
ASCII code :
‘M37478E8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘8’ = 3816
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M37478E8–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘E’ = 4516
‘8’ = 3816
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-58
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-85B<2XA0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37478E8TXXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from
this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37478E8TXXXSP
M37478E8TXXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M37478E8T’
ASCII code :
‘M37478E8T’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
data
data
ROM 16384 bytes
ROM 16384 bytes
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘8’ = 3816
‘ T ’ = 5416
FF16
(2) The ASCII codes of the product name “M37478E8T”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘E’ = 4516
‘8’ = 3816
(1/2)
7470/7471/7477/7478 GROUP USER’S MANUAL
3-60
APPENDIX
3.4 Mark specification form
3.4 Mark specification form
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
#
!
Mitsubishi lot number
(6-digit or 7-digit)
Mitsubishi IC catalog name
q
!
!
B. Customer’s Parts Number + Mitsubishi catalog name
#
Customer’s Parts Number
Note : The fonts and size of characters
are standard Mitsubishi type.
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
q
!
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,
,
,
(periods), and (commas) are usable.
.
4 : If the Mitsubishi logo
is not required, check the box on the right.
Mitsubishi logo is not required
C. Special Mark Required
#
!
q
!
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as
close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the Special Mark, check the
Special logo required
box on the right. Please submit a clean original of the logo. For the new special
character fonts a clean font original (ideally logo drawing) must be submitted.
3 : The standard Mitsubishi font is used for all characters except for a logo.
7470/7471/7477/7478 GROUP USER’S MANUAL
3-62
APPENDIX
3.4 Mark specification form
32P2W-A (32-PIN SOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
#
!
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
q
!
B. Customer’s Parts Number + Mitsubishi catalog name
Customer’s Parts Number
#
!
Note : The fonts and size of characters are standard Mitsubishi
type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi
type.
Mitsubishi lot number
(6-digit or 7-digit)
3 : Customer’s Parts Number can be up to 13 characters :
,
Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,
mas) are usable.
,
(periods), (com-
.
4 : If the Mitsubishi logo
below.
is not required, check the box
q
!
Mitsubishi logo is not required
C. Special Mark Required
#
!
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
q
!
Special logo required
3 : The standard Mitsubishi font is used for all characters
except for a logo.
7470/7471/7477/7478 GROUP USER’S MANUAL
3-63
APPENDIX
3.4 Mark specification form
42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
$
@
Mitsubishi lot number
(6-digit or 7-digit)
Mitsubishi IC catalog name
q
@
@
B. Customer’s Parts Number + Mitsubishi catalog name
$
Customer’s Parts Number
Note : The fonts and size of characters
are standard Mitsubishi type.
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
q
@
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
,
3 : Customer’s Parts Number can be up to 15 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,
,
(periods), and (commas) are usable.
.
4 : If the Mitsubishi logo
is not required, check the box on the right.
Mitsubishi logo is not required
C. Special Mark Required
$
@
q
@
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as
close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the Special Mark, check the
Special logo required
box on the right. Please submit a clean original of the logo. For the new special
character fonts a clean font original (ideally logo drawing) must be submitted.
3 : The standard Mitsubishi font is used for all characters except for a logo.
7470/7471/7477/7478 GROUP USER’S MANUAL
3-64
APPENDIX
3.4 Mark specification form
56P6N-A (56-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
$
@
$
@
Mitsubishi lot number
(6-digit or 7-digit)
Mitsubishi IC catalog name
%
!
q
!
B. Customer’s Parts Number + Mitsubishi IC catalog name
$ @
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi
$
@
type.
Mitsubishi IC catalog name and Mitsubishi lot number
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi
type.
3 : Customer’s Parts Number can be up to 11 characters :
,
Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,
(comma) are usable.
, (period), and
.
4 : If the Mitsubishi logo
below.
is not required, check the box
%
!
q
!
Mitsubishi logo is not required
5 : Arrangement of Mitsubishi IC catalog name and
Mitsubishi lot number is dependent on number of
Mitsubishi IC catalog name and that Mitsubishi logo is
required or not.
C. Special Mark Required
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
$
$
@
@
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
%
q
!
!
Special logo required
3 : The standard Mitsubishi font is used for all characters
except for a logo.
7470/7471/7477/7478 GROUP USER’S MANUAL
3-65
APPENDIX
3.4 Mark specification form
SHRINK DIP MARK SPECIFICATION FORM
for One Time PROM version microcomputers
Enter the catalog number of the microcomputer for which this mark specification is intended. (If you do not know the ROM code number,
enter XXX in its place.)
The catalog number of the microcomputer
M
A. Standard Mitsubishi Mark
Customer specified part number will be printed together with the ROM code number on the top line.
Enter the desired part number left aligned in the box below. (up to 10 characters)
Note2 :
RXXX
Mitsubishi catalog name
(blank model number before writing)
Mitsubishi lot number
(6-digit or 7-digit)
Note1 : The following characters can be used in the part number :
Uppercase alphabet, numbers, ampersand, hyphen, period, comma, +, /, (, ),
x
will be printed at 1.5 character width)
(
2 : XXX is the ROM code number.
B. Special Mark Required
If you desire anything other than the standard Mitsubishi mark, it will be treated as a special mark.
Special marks will take longer to produce and should be avoided if possible.
If a special mark is to be printed, indicate the desired layout of the mark in the figure below. The layout will be duplicated as closely as
possible.
Note1 : If the customer’s trademark logo must be used in the Special Mark, please submit a clean original logo.
Note that special marks require extra cost and time to produce.
7470/7471/7477/7478 GROUP USER’S MANUAL
3-66
APPENDIX
3.5 Package outline
3.5 Package outline
7470/7471/7477/7478 GROUP USER’S MANUAL
3-67
APPENDIX
3.5 Package outline
7470/7471/7477/7478 GROUP USER’S MANUAL
3-68
APPENDIX
3.6 SFR memory map
3.6 SFR memory map
Figure 3.6.1 shows the special function register (SFR) memory map.
Port P0
Transmit/receive buffer register
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
Port P0 direction register
Port P1
Serial I/O status register
Serial I/O control register
UART control register
Baud rate generator
(Note 5)
Port P1 direction register
Port P2
Port P2 direction register (Note 1)
Port P3
00C816 Port P4
Port P4 direction register
00C916
00CA16 Port P5 (Note 2)
00CB16
00CC16
00CD16
00CE16
00CF16
Port P0 pull-up control register
Port P1-P5 pull-up control register (Note 3)
Timer 1
Timer 2
Timer 3
Timer 4
00D016
00D116
00D216
00D316
00D416 Edge polarity selection register
00D516
Input latch register
00D616
00D716
00D816
00D916
00F716 Timer FF register
Timer 12 mode register
Timer 34 mode register
00F816
00F916
A-D control register
00DA16 A-D conversion register
00DB16
00FA16 Timer mode register 2
CPU mode register
00FB16
00FC16
Serial I/O mode register
Interrupt request register 1
00DC16
(Note 4)
00DD16 Serial I/O register
00FD16 Interrupt request register 2
Interrupt control register 1
00FF16 Interrupt control register 2
00DE16
00DF16
00FE16
Serial I/O counter Byte counter
Notes 1: In the 7477/7478 group, this register is not located.
2: In the 7470/7477 group, this register is not located.
3: This address is allocated P1-P4 pull-up control register for the 7470/7477 group.
4: In the 7477/7478 group, this register is not located.
5: In the 7470/7471 group, this register is not located.
Fig. 3.6.1 SFR memory map
7470/7471/7477/7478 GROUP USER’S MANUAL
3-69
APPENDIX
3.7 Pin configuration
3.7 Pin configuration
Figures 3.7.1 to 3.7.4 show the pin configuration of 7470/7471/7477/7478 group.
1
2
32
31
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
P07
P06
P05
P04
P03
P02
P01
P00
3
4
30
29
5
6
28
27
26
25
24
23
22
21
20
7
8
P10
9
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
P40
10
11
12
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
13
14
15
16
19
18
17
XIN
XOUT
VSS
Outline 32P4B (Note)
Note: The M37470M2-XXXSP and M37470M4/E4-XXXSP are included in the 32P4B package. All of
these products are pin-compatible.
Fig. 3.7.1 Pin configuration of 7470 group
7470/7471/7477/7478 GROUP USER’S MANUAL
3-70
APPENDIX
3.7 Pin configuration
42
41
1
2
3
P53
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
P52
P07
P06
P05
P04
P03
P02
P01
P00
P43
P42
P41
40
39
38
37
4
5
6
7
36
35
34
33
32
31
30
29
28
27
8
9
P10
10
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
11
12
13
14
P40
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
15
16
17
26
18
19
20
21
25
24
23
22
XIN
XOUT
VSS
P51/XCOUT
P50/XCIN
VCC
Outline 42P4B (Note 1)
42S1B-A (M37471E8SS)
45
28
27
26
RESET
NC
P51/XCOUT
P50/XCIN
NC
VCC
VSS
AVSS
NC
XOUT
XIN
NC
P05
P06
P07
P52
NC
VSS
P53
46
47
48
49
25
24
50
M37471M8-XXXFP
M37471E8-XXXFP
23
22
51
52
21
20
53
54
55
56
P17/SRDY
P16/CLK
P15/SOUT
NC
19
18
17
NC
NC: No connection
Outline 56P6N-A (Note 2)
Notes 1 :The M37471M2-XXXSP and M37471M4/E4-XXXSP are included in the 42P4B package. All of these
products are pin-compatible.
2 :The M37471M2-XXXFP and M37471M4/E4-XXXFP are included in the 56P6N-A package. All of
these products are pin-compatible.
3 :The only differences between the 42P4B package product and the 56P6N-A package product are
package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
Fig. 3.7.2 Pin configuration of 7471 group
7470/7471/7477/7478 GROUP USER’S MANUAL
3-71
APPENDIX
3.7 Pin configuration
1
2
32
31
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P07
P06
P05
P04
P03
P02
P01
P00
3
4
30
29
5
28
27
6
7
26
25
8
P10
9
24
23
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
P40
10
11
12
13
14
15
16
22
21
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
20
19
XIN
XOUT
VSS
18
17
Outline 32P4B (Note 1)
1
2
32
31
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P07
P06
P05
P04
P03
P02
P01
P00
3
30
29
4
5
28
27
6
7
26
25
8
P10
9
24
23
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
P40
10
11
12
13
14
15
16
22
21
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
20
19
XIN
XOUT
VSS
18
17
Outline 32P2W-A (Note 2)
Notes 1 : The M37477M2TXXXSP, M37477M4-XXXSP and M37477M4TXXXSP are included in the 32P4B package.
These products are pin-compatible.
2 : The M37477M2TXXXFP, M37477M4-XXXFP and M37477M4TXXXFP are included in the 32P2W-A package.
These products are pin-compatible.
3 : The only differences between the 32P4B package product and the 32P2W-A package product are
package shape and absolute maximum ratings.
Fig. 3.7.3 Pin configuration of 7477 group
7470/7471/7477/7478 GROUP USER’S MANUAL
3-72
APPENDIX
3.7 Pin configuration
1
2
42
41
40
P53
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P52
P07
P06
P05
P04
P03
P02
P01
P00
P43
P42
P41
3
4
5
39
38
37
6
7
36
35
34
33
8
9
P10
10
11
12
13
14
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
32
31
30
P40
29
28
27
26
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
15
16
17
25
24
23
22
18
19
20
21
XIN
XOUT
VSS
P51/XCOUT
P50/XCIN
VCC
Outline 42P4B (Note 1)
42S1B-A (M37478E8SS)
45
28
RESET
NC
P51/XCOUT
P50/XCIN
NC
VCC
VSS
AVSS
NC
XOUT
XIN
NC
P05
P06
P07
P52
NC
VSS
P53
46
47
27
26
48
49
25
24
23
22
21
20
19
M37478M8-XXXFP
M37478E8-XXXFP
M37478M8TXXXFP
M37478E8TXXXFP
50
51
52
53
54
P17/SRDY
P16/SCLK
P15/TXD
NC
55
56
18
17
NC
Outline 56P6N-A (Note 2)
NC: No connection
Notes1 : The M37478M2TXXXSP, M37478M4-XXXSP and M37478M4TXXXSP are included in the 42P4B package.
These products are pin-compatible
2 : The M37478M2TXXXFP, M37478M4-XXXFP and M37478M4TXXXFP are included in the 56P6N-A package.
These products are pin-compatible
3 : The only differences between the 42P4B package product and the 56P6N-A package product are package
shape, absolute maximum ratings and the fact that the 56P6N-A package product has an
AVSS pin.
Fig. 3.7.4 Pin configuration of 7478 group
7470/7471/7477/7478 GROUP USER’S MANUAL
3-73
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
7470/7471/7477/7478 Group
November First Edition 1996
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1996 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
7470/7471/7477/7478 Group
Printed in Japan (ROD)
© 1996 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective November, 1996.
Specifications subject to change without notice.
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