74ABT16245CMTDX [ETC]
Dual 8-bit Bus Transceiver ; 双8位总线收发器\n
| 型号： | 74ABT16245CMTDX |
| 厂家： | 
ETC |
| 描述： | Dual 8-bit Bus Transceiver
|
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1992
Revised November 1999
74ABT16245
16-Bit Transceiver with 3-STATE Outputs
General Description
Features
■ Bidirectional non-inverting buffers
■ Separate control logic for each byte
■ 16-bit version of the ABT245
The ABT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. Each
byte has separate control inputs which can be shorted
together for full 16-bit operation. The T/R inputs determine
the direction of data flow through the device. The OE inputs
disable both the A and B ports by placing them in a high
impedance state.
■ A and B output sink capability of 64 mA, source
capability of 32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and
250 pF loads
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
Ordering Code:
Order Number
74ABT16245CSSC
74ABT16245CMTD
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD48
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs/Outputs
T/Rn
A0–A15
B0–B15
Side B Inputs/Outputs
© 1999 Fairchild Semiconductor Corporation
DS010986
www.fairchildsemi.com
Truth Tables
Logic Diagrams
Inputs
Outputs
OE1
T/R1
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH-Z State on A0–A7, B0–B 7
H
Inputs
Outputs
OE2
T/R2
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A 15
Bus A8–A15 Data to Bus B8–B 15
HIGH-Z State on A8–A15, B8–B 15
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Functional Description
The ABT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
V
CC Pin Potential to Ground Pin
Minimum Input Edge Rate (∆V/∆t)
Data Input
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
−0.5V to +7.0V
50 mV/ns
20 mV/ns
−30 mA to +5.0 mA
Enable Input
Power-Off State
−0.5V to 5.5V
−0.5V to VCC
in the HIGH State
Current Applied to Output
in LOW State (Max)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
twice the rated IOL (mA)
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500 mA
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
10V
DC Electrical Characteristics
VCC
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
VIH
VIL
2.0
V
V
Recognized HIGH Signal
Recognized LOW Signal
Input LOW Voltage
0.8
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
V
Min
I
I
I
I
IN = −18 mA (OEn, T/Rn)
OH = −3 mA (An, Bn)
OH = −32 mA (An, Bn)
OL = 64 mA (An, Bn)
2.5
2.0
V
V
V
Min
Min
Min
VOL
Output LOW Voltage
Input HIGH Current
0.55
IIH
1
1
V
V
IN = 2.7V (OEn, T/Rn) (Note 3)
IN = VCC (OEn, T/Rn)
µA
Max
IBVI
IBVIT
IIL
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (I/O)
Input LOW Current
7
µA
µA
Max
Max
V
V
IN = 7.0V (OEn, T/Rn)
IN = 5.5V (An, Bn)
100
−1
V
V
IN = 0.5V (OEn, T/Rn) (Note 3)
IN = 0.0V (OEn, T/Rn)
µA
Max
0.0
−1
VID
Input Leakage Test
4.75
V
I
ID = 1.9 µA (OEn, T/Rn)
All Other Pins Grounded
I
I
IH + I OZH Output Leakage Current
IL + I OZL Output Leakage Current
10
µA
µA
0 − 5.5V
0 − 5.5V
V
OUT = 2.7V (An, Bn); OE = 2.0V
−10
V
V
V
V
OUT = 0.5V (An, Bn); OE = 2.0V
OUT = 0.0V (An, Bn)
IOS
ICEX
IZZ
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
−100
−275
50
mA
µA
µA
Max
Max
0.0
OUT = VCC (An, Bn)
100
OUT = 5.50V (An, Bn);
All Others GND
All Outputs HIGH
All Outputs LOW
ICCH
ICCL
ICCZ
Power Supply Current
Power Supply Current
100
60
µA
Max
Max
mA
Power Supply Current
100
µA
Max
OEn = VCC, T/Rn = GND or VCC
All others at VCC or GND
VI = VCC − 2.1V
ICCT
Additional ICC/Input
Outputs Enabled
2.5
2.5
mA
mA
Outputs 3-STATE
Outputs 3-STATE
Max
OEn, T/ Rn VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All others at VCC or GND
Outputs OPEN
50
µA
ICCD
Dynamic ICC
(Note 3)
No Load
mA/
Max
0.1
MHz
OEn = GND, T/Rn = GND or VCC
One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed, but not tested.
3
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DC Extended Electrical Characteristics
Conditions
VCC
Symbol
Parameter
Min
Typ
Max
Units
C
L = 50 pF; RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
0.5
−1.0
3.0
0.9
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
TA = 25°C (Note 4)
TA = 25°C (Note 4)
TA = 25°C (Note 5)
TA = 25°C (Note 5)
TA = 25°C (Note 6)
VOLV
VOHV
VIHD
VILD
Quiet Output Minimum Dynamic VOL
−1.4
2.5
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
2.0
1.4
1.2
0.8
Note 4: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 6: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
T
A = +25°C
T
A = −55°C to +125°C
CC = 4.5V – 5.5V
L = 50 pF
Max
T
A = −40°C to +85°C
CC = 4.5V – 5.5V
L = 50 pF
Max
V
CC = +5V
V
V
Symbol
Parameter
Units
C
L = 50 pF
C
C
Min
1.0
1.0
1.5
1.5
1.3
1.3
Typ
2.4
2.8
3.6
3.7
4.6
3.7
Max
3.9
3.9
6.3
6.3
6.9
6.9
Min
Min
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation
0.5
0.5
0.8
0.9
1.3
1.0
4.5
5.2
6.4
6.9
6.9
6.9
1.0
1.0
1.5
1.5
1.3
1.3
3.9
3.9
6.3
6.3
6.9
6.9
ns
Delay Data to Outputs
Output Enable
Time
ns
ns
Output Disable
Time
Extended AC Electrical Characteristics
T
A =−40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
V
V
V
C
C
C
Symbol
Parameter
Units
16 Outputs Switching
(Note 7)
1 Output Switching
(Note 8)
16 Outputs Switching
(Note 9)
Min
Typ
Max
Min
Max
Min
Max
fTOGGLE Maximum Toggle Frequency
100
MHz
ns
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
Data to Outputs
Output Enable
Time
1.5
1.5
1.5
1.5
1.0
1.0
5.0
5.3
6.5
6.5
6.9
6.9
1.5
1.5
2.5
2.5
6.0
6.0
8.2
8.2
2.5
2.5
2.5
2.5
8.0
8.0
10.0
9.0
ns
ns
Output Disable
Time
(Note 10)
(Note 10)
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10: 3-STATE delay are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet.
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4
Skew
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 50 pF
T
A = −40°C to +85°C
CC = 4.5V–5.5V
L = 250 pF
V
V
C
C
Symbol
Parameter
Units
16 Outputs Switching
(Note 11)
16 Outputs Switching
(Note 12)
Max
Max
tOSHL
Pin to Pin Skew
1.3
1.3
1.5
1.7
2.0
1.5
1.5
2.0
2.5
3.0
ns
ns
ns
ns
ns
(Note 13)
tOSLH
HL Transitions
Pin to Pin Skew
LH Transitions
(Note 13)
tPS
Duty Cycle
(Note 14)
tOST
LH–HL Skew
Pin to Pin Skew
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
(Note 13)
tPV
(Note 15)
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-
LOW (tOST). The specification is guaranteed but not tested.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Conditions
Symbol
Parameter
Typ
Units
T
A = 25°C
CIN
I/O (Note 16)
Input Capacitance
Output Capacitance
5
V
V
CC = 0.0V (OEn, T/Rn)
CC = 5.0V (An, Bn)
pF
pF
C
11
Note 16: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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AC Loading
*Includes jig and probe capacitance
FIGURE 2. Input Pulse Requirements
FIGURE 1. Standard AC Test Load
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 4. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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6
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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