74ACT374SCX [ETC]
Octal D-Type Flip-Flop ; 八D型触发器\n
| 型号： | 74ACT374SCX |
| 厂家： | 
ETC |
| 描述： | Octal D-Type Flip-Flop
|
| 文件： | 总10页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised November 1999
74AC374 • 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
■ ICC and IOZ reduced by 50%
■ Buffered positive edge-triggered clock
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
■ See 273 for reset version
■ See 377 for clock enable version
■ See 373 for transparent latch version
■ See 574 for broadside pinout version
■ See 564 for broadside pinout version with inverted
outputs
■ ACT374 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC374SC
74AC374SJ
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC374MTC
74AC374PC
74ACT374SC
74ACT374SJ
74ACT374MSA
74ACT374MTC
74ACT374PC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20B
M20D
MSA20
MTC20
N20A
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
Description
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009959
www.fairchildsemi.com
Logic Symbols
Functional Description
The AC/ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
IEEE/IEC
Truth Table
Inputs
Outputs
Dn
H
L
CP
OE
L
On
H
L
L
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
− 0.5V to + 7.0V
DC Input Diode Current (IIK
VI = − 0.5V
)
Supply Voltage (VCC
)
− 20 mA
+ 20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
− 0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = − 0.5V
− 20 mA
+ 20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
− 0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
± 50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
± 50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
(PDIP)
)
− 65°C to + 150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = − 50 µA
5.4
5.4
V
IN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = − 12 mA
V
V
OH = − 24 mA
OH = − 24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
3.0
4.5
5.5
5.5
0.36
0.36
0.36
±0.1
0.44
0.44
0.44
±1.0
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current
µA
µA
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, GND
IOZ
Maximum 3-STATE Current
5.5
±0.25
±2.5
V
V
V
V
O = VCC, GND
IOLD
IOHD
Minimum Dynamic
5.5
5.5
5.5
75
mA
mA
µA
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 3)
−75
40.0
ICC (Note 4) Maximum Quiescent Supply Current
4.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
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DC Electrical Characteristics for ACT
VCC
T
A = + 25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = − 50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = − 24 mA
OH − 24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum
5.5
5.5
5.5
±0.1
±1.0
±2.5
1.5
µA
µA
VI = VCC, GND
VI = VIL, VIH
IOZ
±0.25
3-STATE Current
Maximum
VO = VCC, GND
ICCT
0.6
mA
VI = VCC − 2.1V
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
− 75
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°
CCL = 50 pF
C
L = 50 pF
Symbol
fMAX
tPLH
Parameter
(V)
(Note 7)
3.3
Units
Min
60
Typ
110
155
11.0
8.0
Max
Min
60
Max
Maximum Clock
MHz
ns
Frequency
5.0
100
3.0
2.5
2.5
2.0
3.0
2.0
2.5
2.0
3.0
2.0
2.0
1.5
100
1.5
1.5
2.0
1.5
1.5
1.0
1.5
1.0
2.0
2.0
1.0
1.0
Propagation Delay
CP to On
3.3
13.5
9.5
15.5
10.5
14.0
10.0
13.0
9.5
5.0
tPHL
Propagation Delay
CP to On
3.3
10.0
7.0
12.5
9.0
ns
5.0
tPZH
Output Enable Time
3.3
9.5
11.5
8.5
ns
5.0
7.0
tPZL
Output Enable Time
Output Disable Time
Output Disable Time
3.3
9.0
11.5
8.5
13.0
9.5
ns
5.0
6.5
tPHZ
3.3
10.5
8.0
12.5
11.0
11.5
8.5
14.5
12.5
12.5
10.0
ns
5.0
tPLZ
3.3
8.0
ns
5.0
6.5
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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4
AC Operating Requirements
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
tS
Setup Time, HIGH or LOW
Dn to CP
2.0
1.0
−1.0
0
5.5
6.0
4.5
1.0
1.5
6.0
4.5
ns
ns
ns
5.0
4.0
1.0
1.5
5.5
4.0
tH
Hold Time, HIGH or LOW
3.3
Dn to CP
5.0
tW
CP Pulse Width,
HIGH or LOW
3.3
4.0
2.5
5.0
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics
VCC
(V)
T
A = +25°C
T
A = −40°C to +85°C
C
L = 50 pF
CL = 50 pF
Symbol
Parameter
Units
(Note 9)
Min
Typ
Max
Min Max
fMAX
Maximum Clock
5.0
100
160
8.5
8.0
90
2.0
1.5
MHz
ns
Frequency
tPLH
Propagation Delay
CP to On
5.0
5.0
2.0
2.0
10.0
9.5
11.5
11.0
tPHL
Propagation Delay
CP to On
ns
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
1.5
1.5
1.5
8.0
8.0
8.5
7.0
9.5
9.0
1.5
1.5
1.0
1.0
10.5
10.5
12.5
10.0
ns
ns
ns
ns
11.5
8.5
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
VCC
(V)
T
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
C
Symbol
Parameter
Units
(Note 10)
Typ
tS
Setup Time, HIGH or LOW
5.0
1.0
5.5
5.5
1.5
5.0
ns
ns
ns
Dn to CP
tH
Hold Time, HIGH or LOW
Dn to CP
5.0
5.0
0
1.5
5.0
tW
CP Pulse Width,
HIGH or LOW
2.5
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Typ
4.5
Units
Conditions
CIN
pF
VCC = OPEN
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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