74FR244SCX [ETC]
Dual 4-Bit Non-Inverting Buffer/Driver ; 双4位非反相缓冲器/驱动器\n
| 型号： | 74FR244SCX |
| 厂家： | 
ETC |
| 描述： | Dual 4-Bit Non-Inverting Buffer/Driver
|
| 文件： | 总6页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1990
Revised May 2001
74FR244
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR244 is a non-inverting octal buffer and line driver
designed to be employed as memory and address driver,
clock driver and bus-oriented transmitter/receiver.
Features
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs sink 64 mA and source 15 mA
■ Guaranteed pin-to-pin skew
Ordering Code:
Order Number Package Number
Package Description
74FR244SC
74FR244SJ
74FR244PC
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OE1,–OE2
I0–I7
Output Enable Input (Active-LOW)
Inputs
O0–O7
Outputs
Truth Tables
Inputs
Outputs
OE1
In
(Pins 12, 14, 16, 18)
L
L
L
H
X
L
H
Z
H
Inputs
Outputs
OE2
In
(Pins 3, 5, 7, 9)
L
L
L
H
X
L
H
Z
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
© 2001 Fairchild Semiconductor Corporation
DS010900
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
−65°C to +150°C
Storage Temperature
Ambient Temperature Under Bias
Junction Temperature Under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
4000V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
V
Conditions
Recognized HIGH Signal
Recognized LOW Signal
2.0
VIL
Input LOW Voltage
0.8
V
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
V
Min
Min
Min
Min
Max
Max
Max
0.0
I
I
I
I
IN = −18 mA
OH = −3 mA
OH = −15 mA
OL = 64 mA
2.4
2.0
V
V
VOL
IIH
Output LOW Voltage
0.55
5
V
Input HIGH Current
µA
µA
µA
V
V
V
V
IN = 2.7V
IN = 7.0V
IN = 0.5V
IBVI
IIL
Input HIGH Current Breakdown Test
Input LOW Current
7
−150
VID
Input Leakage Test
4.75
I
ID = 1.9 µA,
All Other Pins Grounded
IOD = 150 mV,
All Other Pins Grounded
IOD
Output Circuit Leakage Current
3.75
µA
0.0
V
IOZH
IOZL
IOS
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
20
−20
−225
50
µA
µA
mA
µA
µA
mA
mA
mA
pF
Max
Max
Max
Max
0.0
V
V
V
V
V
OUT = 2.7V
OUT = 0.5V
OUT = 0.0V
OUT = VCC
OUT = 5.25V
−100
ICEX
IZZ
100
50
ICCH
ICCL
ICCZ
CIN
Power Supply Current
Power Supply Current
Power Supply Current
Input Capacitance
30
55
35
8.0
Max
Max
Max
5.0
All Outputs HIGH
All Outputs LOW
Outputs 3-STATED
75
50
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2
AC Electrical Characteristics
T
A = +25°C
T
A = 0°C to +70°C
CC = +5.0V
L = 50 pF
Max
V
CC = +5.0V
V
Symbol
Parameter
Units
C
L = 50 pF
C
Min
1.0
1.0
2.5
2.5
1.6
1.6
Typ
2.6
1.8
4.8
3.9
3.7
3.6
Max
3.9
3.9
6.6
6.6
6.4
6.4
Min
1.0
1.0
2.5
2.5
1.6
1.6
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
Output Enable Time
Output Disable Time
3.9
3.9
6.6
6.6
6.4
6.4
ns
ns
ns
Extended AC Characteristics
T
A = 0°C to +70°C
CC = +5.0V
L = 50 pF
T
A = 0°C to +70°C
CC = +5.0V
V
V
C
CL = 250 pF
Symbol
Parameter
Units
Eight Outputs Switching
(Note 3)
(Note 4)
Min
1.0
1.0
2.5
2.5
1.6
1.6
Max
5.0
5.0
7.7
7.7
6.5
6.5
Min
Max
tPLH
tPHL
tPZH
tPZL
Propagation Delay
Output Enable Time
Output Disable Time
2.3
2.3
7.3
7.3
ns
ns
ns
ns
ns
ns
tPHZ
tPLZ
tOSHL
Pin-to-Pin Skew
1.6
1.0
3.5
for HL Transitions (Note 5)
Pin-to-Pin Skew
tOSLH
for LH Transitions (Note 5)
Pin-to-Pin Skew
tOST
for HL/LH Transitions (Note 5)
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to any outputs switching HIGH-to-LOW, (tOSHL), LOW-to-HIGH, (tOSLH), or HIGH-to-LOW and/or LOW-to-HIGH, (tOST). Specification guaran-
teed with all outputs switching in phase.
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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