74LCXZ163245MTDX [ETC]
Dual 8-bit Bus Transceiver ; 双8位总线收发器\n
| 型号： | 74LCXZ163245MTDX |
| 厂家： | 
ETC |
| 描述： | Dual 8-bit Bus Transceiver
|
| 文件： | 总7页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
May 2001
Revised May 2001
74LCXZ163245
16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs (Preliminary)
so that the control pins (T/Rn, OEn) are powered by VCCB
,
General Description
so that VCCA may be removed when the I/Os are disabled.
The 74LCXZ163245 is a dual supply, 16-bit, translating
transceiver that is designed for two-way asynchronous
communication between busses at different supply volt-
ages. This device is suited for PCMCIA and other real-time
configurable I/O applications that utilize mixed power sup-
plies.
The 74LCXZ163245 is suitable for mixed voltage applica-
tions such as notebook computers using a 3.3V CPU and
5.0V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
The 74LCXZ163245 is designed to Power-Up and Power-
Down into a High Impedance state (outputs disabled). The
feature eliminates the need to power-up in a specific
sequence to avoid drawing excessive current.
Features
■ Bidirectional interface between 3V busses and
5V busses
The A Port interfaces with the higher voltage bus (3.0V to
5.5V), and the B Port interfaces with the lower voltage bus
(2.3V to 3.6V). This dual supply design allows for transla-
tion from low voltage busses (2.3V to 3.6V) to busses at a
higher potential, up to 5.5V. The 74LCXZ163245 is
intended to be used in applications where the A Port is con-
nected to the PCMCIA card slots, and the B Port is con-
nected to the 3.0V host system.
■ Supports live insertion and withdrawal (Note 1)
■ Outputs source/sink up to 24 mA
■ Uses patented Quiet Series noise/EMI reduction
circuitry
■ Functionally compatible with the 74 series 16245
■ Port A I/O may be disabled by use of OEn or removal of
A Port VCC
Furthermore, when both OE’s are HIGH, the A Port I/O pins
are disabled, and both A Port I/O connections and A Port
VCC are allowed to float. This feature permits PCMCIA
■ Port A VCC may be removed when OEn is used to
disable I/O’s
■ Port A VCC removal may occur coincident with rising
edge of OEn
cards to be inserted and removed during normal operation.
The Transmit/Receive (T/R) input determines the direction
of data flow. Transmit (active-HIGH) enables data from A
Ports to B Ports; Receive (active-LOW) enables data from
B Ports to A Ports. The Output Enable (OE1, OE2) inputs,
■ Configurable as one 16-bit or two 8-bit transceivers
■ Unrestricted power-up sequencing
Note 1: To ensure the high impedance state during power up or down OE
when HIGH, disable their associated ports by placing the
I/Os in HIGH-Z condition. The 74LCXZ163245 is designed
should be tied to VCC through a pull-up resistor; the minimum value of the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Package
Order Number
Package Description
Number
74LCXZ163245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS500364
www.fairchildsemi.com
Preliminary
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
T/Rn
Transmit/Receive Input
A0–A15
B0–B15
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Connection Diagram
Truth Tables
Inputs
Outputs
OE1
T/R1
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
H
Inputs
Outputs
OE2
T/R2
L
L
L
H
X
Bus B8–B15 Data to Bus A8–A15
Bus A8–A15 Data to Bus B8–B15
HIGH-Z State on A8–A15, B8–B15
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
LCXZ163245 Translator Power Up Note
The LCXZ163245 Translator is designed with two separate
in a high impedance (Z) state prevents intermittent low
V
CC power rails. VCCA is the higher potential rail, operating
impedance loading or glitching in bus oriented applications.
at 3.0 to 5.5 volts, and VCCB is the lower potential rail, oper-
To ensure the high impedance state during power up
beyond a VCC of 1.5V and also during power down, the
ating at 2.3 to 3.6 volts. The control pins of the device
(OEn, T/Rn) are supplied by the VCCB rail.
OEn pin should be tied to VCCB through a pull up resistor.
The minimum value of this resistor is determined by the
current-sourcing capability of the device driving the OEn
The LCXZ163245 will remain in high impedance mode
(outputs are disabled) when VCCA and/or VCCB is between
pin.
0 volts and 1.5 volts during power up. Placing the outputs
Logic Diagrams
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Preliminary
Absolute Maximum Ratings(Note 2)
Symbol
Parameter
Value
Conditions
Units
V
CCA, VCCB Supply Voltage
−0.5 to +7.0
V
VI
DC Input Voltage
−0.5 to +7.0
−0.5 to +7.0
OE, T/R Control Pins
Outputs 3-STATE
V
VI/O
DC Output Voltage
−0.5 to VCCA +0.5 A Outputs in HIGH or LOW State (Note 3)
−0.5 to VCCB +0.5 B Outputs in HIGH or LOW State (Note 3)
V
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND (OE, T/R)
mA
mA
IOK
V
V
O < GND
O > VCC
±50
IO
DC Output Source or Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 4)
Symbol
Parameter
Min
2.3
3.0
Max
3.6
Units
VCC
Supply Voltage
VCCB
VCCA
V
5.5
VI
Input Voltage @ OE, T/R
Output Voltage
0
0
5.5
VCCA
VCCB
5.5
V
V
VI/O
An HIGH or LOW State
Bn HIGH or LOW State
3-STATE
0
0
TA
Free Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V - 2.0V, VCCB = 2.3V - 3.6V, VCCA = 4.5V - 5.5V
10
ns/V
Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs or I/O’s must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCCB
VCCA
TA = −40°C to +85°C
Symbol
VIHA
Parameter
Units
Conditions
(V)
2.3
3.0
3.6
2.3
3.0
3.6
2.7
3.0
3.6
2.7
3.0
3.6
(V)
3.0
3.6
5.5
3.0
3.6
5.5
3.0
3.6
5.5
3.0
3.6
5.5
Min
2.0
2.0
2.0
1.7
2.0
2.0
Max
Minimum HIGH
An
Level Input
Voltage
V
VIHB
VILA
VILB
Bn
OE
T/R
An
Maximum LOW
Level Input
Voltage
0.8
0.8
0.8
0.7
0.8
0.8
V
Bn
OE
T/R
3
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Preliminary
DC Electrical Characteristics (Continued)
VCCB
VCCA
TA = −40°C to +85°C
Symbol
VOHA
Parameter
Units
Conditions
(V)
2.3
2.3
2.3
2.7
2.7
2.3
2.3
2.3
3.0
2.3
2.3
2.3
3.6
3.0
2.3
3.0
3.6
3.6
(V)
3.0
3.0
3.0
3.0
4.5
3.0
3.0
4.5
4.5
3.0
3.0
3.0
4.5
3.0
3.0
4.5
3.6
5.5
Min
Max
Minimum HIGH Level
Output Voltage
VCCA−0.2
2.4
I
I
I
I
I
I
I
I
I
I
I
OUT = −100 µA
OH = −4 mA
OH = −24 mA
OH = −4 mA
OH = −24 mA
OUT = −100 µA
OH = −4 mA
OH = −24 mA
OH = −24 mA
OUT = 100 µA
OL = 24 mA
2.0
2.4
3.7
V
VOHB
VCCB−0.2
1.8
2.2
2.2
VOLA
Maximum LOW Level
Output Voltage
0.2
0.8
0.6
0.7
0.2
0.6
0.8
IOL
=
4 mA
OL = 24 mA
OUT = 100 µA
4 mA
OL = 24 mA
V
I
I
VOLB
IOL
=
I
IIN
Maximum Input
Leakage Current @
OE, T/R
±5.0
µA
µA
µA
VI = VCCB or GND
IOZA
Maximum 3-STATE
Output Leakage
@ An
3.6
3.6
3.6
5.5
±5.0
±5.0
VI = VIL, VIH
OE = VCCB
,
V
O = VCCA, GND
IOZB
Maximum 3-STATE
Output Leakage
@ Bn
3.6
3.6
3.6
5.5
±5.0
±5.0
VI = VIL, VIH
OE = VCCB
,
V
O = VCCB, GND
∆ICC
Maximum
Bn, OE, T/R
An
3.6
3.6
5.5
5.5
500
2.0
µA
VI = VCCB–0.6V
VI = VCCA–2.1V
I
CC/Input
mA
ICCA1
Quiescent VCCA
Supply Current
as A Port Floats
Quiescent VCCA
Supply Current
A
B
n = VCCA or GND
3.6
Open
50
µA
µA
n = Open, OE = VCCB,
T/R = VCCB, VCCA = Open
ICCA2
3.6
3.6
3.6
5.5
50
80
A
B
n = VCCA or GND,
n = VCCB or GND,
OE = GND, T/R = GND
ICCB
Quiescent VCCB
Supply Current
3.6
3.6
3.6
5.5
50
50
A
B
n = VCCA or GND,
n = VCCB or GND,
µA
µA
OE = GND, T/R = VCCB
O = 5V to VCC
VI = GND or VCC
IPU/PD
Power Up 3-STATE Output Current
0-1.5
0-1.5
±5.0
V
Dynamic Switching Characteristics
VCCB
VCCA
T
A = +25°C
Symbol
VOLPB
Parameter
Conditions
Units
(V)
2.5
3.3
2.5
3.3
2.5
3.3
2.5
3.3
(V)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Typical
0.4
Quiet Output Dynamic
C
C
C
C
L = 30 pF, VIH = VCC, VIL = 0V
V
V
V
V
Peak VOL, A to B
0.4
VOLPA
VOLVB
VOLVA
Quiet Output Dynamic
Peak VOL, B to A
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
0.4
0.8
Quiet Output Dynamic
Valley VOL, A to B
Quiet Output Dynamic
Valley VOL, B to A
−0.4
−0.4
−0.4
−0.8
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4
Preliminary
AC Electrical Characteristics
T
A = −40°C to +85°C
T
A = −40°C to +85°C
L = 30 pF
CL = 50 pF
C
Symbol
Parameter
V
CCB = 3.3V ± 0.3V
CCA = 5.0V ± 0.5V
V
CCB = 2.5V ± 0.2V
Units
V
VCCA = 5.0V ± 0.5V
Min
1.0
Max
Min
Max
tPHL
Propagation Delay
A to B
6.5
1.0
6.0
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPHZ
tPLZ
tPHZ
tPLZ
tOSHL
tOSLH
Propagation Delay
B to A
1.0
1.0
1.0
1.0
1.0
6.5
9.0
9.0
9.5
9.5
1.0
1.0
1.0
1.0
1.0
1.0
6.0
10.5
10.0
10.0
10.5
1.0
Output Enable Time
OE to B
Output Enable Time
OE to A
Output Disable Time
OE to B
Output Disable Time
OE to A
Output to Output Skew (Note 5)
Data to Output
Note 5: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Note: Typical values at VCCA = 3.3V, VCCB = 5.0V @ 25°C.
Note: Typical values at VCCA = 3.3V, VCCB = 3.3V @ 25°C.
Capacitance
Symbol
CIN
CI/O
Parameter
Typ
4.5
10
Units
pF
Conditions
Input Capacitance
V
V
V
V
V
CC = Open
CCA = 5.0V
Input/Output Capacitance
pF
CCB = 2.5V, 3.3V
CCB = 2.5V, 3.3V
CCA = 5.0V
CPD
Power Dissipation
A→B
B→A
40
65
pF
pF
Capacitance (Note 6)
Note 6: CPD is measured at 10 MHz.
5
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Preliminary
I/O Application for PCMCIA Cards
Block Diagram
The LCXZ163245 is a 48-pin dual supply device well suited
for PCMCIA I/O applications. Ideal for low power notebook
designs, the LCXZ163245 consumes less than 1 mW of
quiescent power in all modes of operation. The
LCXZ163245 meets all PCMCIA I/O voltage requirements
at 5V and 3.3V operation. By tying VCCB of the
The VCCB pin on the LCXZ163245 must always be tied to a
3V power supply. This voltage connection provides internal
references needed to account for variations in VCCA. When
connected as in the figure above, the LCXZ163245 meets
all the voltage and current requirements of the ISA bus
standard (IEEE P996).
LCXZ163245 to the card voltage supply, the PCMCIA card
will always experience rail to rail output swings, maximizing
the reliability of the interface.
Please reference Application Note AN-5001 for more
detailed information on using Fairchild’s LVX Low Voltage
Dual Supply CMOS Translating Transceivers.
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6
Preliminary
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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