74LVQ86SJX [ETC]
Quad 2-input Exclusive OR (XOR) Gate ; 四2输入异或（ XOR ）门\n
| 型号： | 74LVQ86SJX |
| 厂家： | 
ETC |
| 描述： | Quad 2-input Exclusive OR (XOR) Gate
|
| 文件： | 总5页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1992
Revised June 2001
74LVQ86
Low Voltage Quad 2-Input Exclusive-OR Gate
General Description
The LVQ86 contains four 2-input exclusive-OR gates.
Features
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number Package Number
Package Description
74LVQ86SC
74LVQ86SJ
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A0–A3
Description
Inputs
B0–B3
Inputs
O0–O3
Outputs
© 2001 Fairchild Semiconductor Corporation
DS011348
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
LVQ
2.0V to 3.6V
0V to VCC
0V to VCC
VI = VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
DC Output Diode Current (IOK
)
Operating Temperature (TA)
74LVQ
V
V
O = −0.5V
−20 mA
+20 mA
−40°C to +85°C
O = VCC + 0.5V
Minimum Input Edge Rate (∆V/∆t)
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
V
IN from 0.8V to 2.0V
CC @ 3.0V
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
or Sink Current (IO)
±50 mA
DC VCC or Ground Current
(ICC or IGND
)
±200 mA
Storage Temperature (TSTG
DC Latch-Up Source or
Sink Current
)
−65°C to +150°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
±100 mA
DC Electrical Characteristics
VCC
T
A = 25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
Typ
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.0
1.5
2.0
0.8
2.9
2.0
V
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
OUT = −50 µA
IN = VIL or VIH (Note 3)
VIL
Maximum Low Level
Input Voltage
3.0
1.5
0.8
V
V
VOH
Minimum High Level
Output Voltage
3.0
3.0
3.0
3.0
2.99
2.9
2.48
0.1
V
V
V
I
V
2.58
0.1
I
I
OH = −12 mA
OUT = 50 µA
VOL
Maximum Low Level
Output Voltage
0.002
V
IN = VIL or VIH (Note 3)
0.36
±0.1
0.44
I
OL = 12 mA
IIN
Maximum Input Leakage Current
Minimum Dynamic (Note 4)
Output Current
3.6
3.6
3.6
±1.0
36
µA
mA
mA
V
V
V
I = VCC, GND
IOLD
IOHD
ICC
OLD = 0.8V Max (Note 5)
OHD = 2.0V Min (Note 5)
−25
Maximum Quiescent
Supply Current
3.6
3.3
3.3
3.3
3.3
2.0
0.8
20.0
µA
V
V
IN = VCC or GND
VOLP
VOLV
VIHD
VILD
Quiet Output
0.5
−0.5
1.8
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Maximum Dynamic VOL
Quiet Output
−0.8
2.0
V
Minimum Dynamic VOL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
V
1.8
0.8
V
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 20 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f = 1 MHz.
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2
AC Electrical Characteristics
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
VCC
C
L = 50 pF
C
Units
(V)
2.7
Min
2.0
2.0
2.0
2.0
Typ
7.2
6.0
7.8
6.5
1.0
1.0
Max
16.2
11.5
16.2
11.5
1.5
Min
tPLH
Propagation Delay
1.5
1.5
1.5
1.5
18.0
12.5
18.0
12.5
1.5
ns
ns
ns
3.3 ± 0.3
2.7
tPHL
Propagation Delay
3.3 ± 0.3
2.7
tOSHL
,
Output to Output Skew
(Note 9)
tOSLH
3.3 ± 0.3
1.5
1.5
Note 9: Skews defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Note 10: CPD is measured at 10 MHz.
Typ
4.5
23
Units
pF
Conditions
CC = Open
CIN
CPD (Note 10)
V
pF
VCC = 3.3V
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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