74V2G74STR [ETC]
FLIP-FLOP|SINGLE|D TYPE|CMOS|TSSOP|8PIN|PLASTIC ; 触发器|单| D型| CMOS | TSSOP | 8PIN |塑料\n
| 型号： | 74V2G74STR |
| 厂家： | 
ETC |
| 描述： | FLIP-FLOP|SINGLE|D TYPE|CMOS|TSSOP|8PIN|PLASTIC
|
| 文件： | 总13页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74V2G74
SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR
■
■
■
HIGH SPEED:
= 170 MHz (TYP.) at V = 5V
f
MAX
CC
LOW POWER DISSIPATION:
= 1 µA (MAX.) at T =25°C
I
CC
A
HIGH NOISE IMMUNITY:
= V = 28% V (MIN.)
V
NIH
NIL
CC
SOT23-8L
SOT323-8L
T & R
■
■
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 8 mA (MIN)
OH
OL
■
■
■
■
BALANCED PROPAGATION DELAYS:
ORDER CODES
t
t
PLH
PHL
PACKAGE
OPERATING VOLTAGE RANGE:
(OPR) = 2V to 5.5V
SOT23-8L
74V2G70STR
74V2G70CTR
V
CC
SOT323-8L
FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
DESCRIPTION
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
The 74V2G74 is an advanced high-speed CMOS
SINGLE D-TYPE FLIP FLOP WITH PRESET
AND CLEAR fabricated with sub-micron silicon
2
gate and double-layer metal wiring C MOS
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
tecnology.
A signal on the D INPUT is transfered to the Q and
Q OUTPUTS during the positive going transition
of the clock pulse.
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 2001
1/13
74V2G74
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
Asyncronous Reset -
Direct Input
6
CLR
2
1
D
Data Input
CK
Clock Input
(LOW to HIGH, Edge
Triggered)
7
PR
Asyncronous Set - Direct
Input
5
3
Q
Q
True Flip-Flop Output
Complement Flip-Flop
Output
4
8
GND
Ground (0V)
V
Positive Supply Voltage
CC
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
L
H
L
X
X
X
L
X
X
X
L
H
H
L
H
L
CLEAR
PRESET
L
H
H
H
H
H
H
H
H
X
H
L
Q
Q
H
NO CHANGE
n
n
X= Don’t care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/13
74V2G74
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
I
O
IK
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V
+ 0.5
CC
V
I
− 20
mA
mA
mA
mA
°C
°C
I
− 20
± 25
OK
I
O
I
or I
T
DC V
or Ground Current
CC
± 50
CC
GND
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
2 to 5.5
0 to 5.5
Unit
V
Supply Voltage
V
V
CC
V
Input Voltage
I
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
°C
op
Input Rise and Fall Time (note 1) (V
= 3.3 ± 0.3V)
0 to 100
0 to 20
CC
dt/dv
ns/V
(V = 5.0 ± 0.5V)
CC
1) V from 30% to 70% of V
IN
CC
3/13
74V2G74
DC SPECIFICATIONS
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
2.0
1.5
1.5
1.5
IH
V
V
3.0 to
5.5
0.7VCC
0.7VCC
0.7VCC
V
Low Level Input
Voltage
2.0
0.5
0.5
0.5
IL
3.0 to
5.5
0.3VCC
0.3VCC
0.3VCC
V
High Level Output
Voltage
I =-50 µA
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
1.9
2.9
2.0
3.0
4.5
1.9
2.9
1.9
2.9
4.4
2.4
3.7
OH
O
I =-50 µA
O
I =-50 µA
4.4
4.4
V
V
O
I =-4 mA
2.58
3.94
2.48
3.8
O
I =-8 mA
O
V
Low Level Output
Voltage
I =50 µA
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
OL
O
I =50 µA
O
I =50 µA
0.1
0.1
0.1
O
I =4 mA
0.36
0.36
0.44
0.44
0.55
0.55
O
I =8 mA
O
I
Input Leakage
Current
0 to
5.5
I
V = 5.5V or GND
± 0.1
± 1
± 1
µA
µA
I
I
Quiescent Supply
Current
CC
V = V
or GND
CC
5.5
2
20
20
I
4/13
74V2G74
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3ns)
r
f
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T = 25°C
Symbol
Parameter
A
V
C
L
(V) (pF)
CC
(*)
t
Propagation Delay
Time CK to Q or Q
15
6.7
9.2
4.6
6.1
7.6
11.9
15.4
7.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
7.0
5.0
7.0
5.0
7.0
5.0
0.5
0.5
5.0
3.0
70
14.0
17.5
8.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
7.0
5.0
7.0
5.0
7.0
5.0
0.5
0.5
5.0
3.0
70
14.0
17.5
8.5
PLH
3.3
t
(*)
PHL
50
15
50
15
50
15
50
3.3
ns
ns
(**)
(**)
(*)
5.0
5.0
9.3
10.5
14.5
18.0
9.0
10.5
14.5
18.0
9.0
t
Propagation Delay
Time PR or CLR to
Q or Q
12.3
PLH
3.3
t
(*)
PHL
10.1 15.8
3.3
(**)
(**)
(*)
4.8
6.3
7.7
9.7
5.0
5.0
11.0
11.0
t
CK Pulse Width
HIGH or LOW
6.0
5.0
6.0
5.0
6.0
5.0
0.5
0.5
5.0
3.0
80
W
3.3
ns
ns
ns
ns
ns
(**)
5.0
(*)
t
W
3.3
PR or CLR Pulse
Width LOW
(**)
(*)
5.0
t
Setup Time D to CK
HIGH or LOW
s
3.3
(**)
5.0
3.3
(*)
t
Hold Time D to CK
HIGH or LOW
h
(**)
(*)
5.0
t
Removal Time
PR or CLR to CK
REM
3.3
(**)
5.0
3.3
3.3
(*)
(*)
f
Maximum Clock
Frequency
15
50
15
50
125
75
MAX
50
45
45
MHz
(**)
130
90
170
115
110
75
110
75
5.0
5.0
(**)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
3.3
4
10
10
10
pF
pF
IN
C
Power Dissipation
Capacitance
(note 1)
PD
f
= 10MHz
3.3
22
IN
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I
PD CC IN CC
CC(opr)
5/13
74V2G74
TEST CIRCUIT
C
R
=15/50pF or equivalent (includes jig and probe capacitance)
L
T
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (D TO CK), CK MAXIMUM
FREQUENCY , CK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
6/13
74V2G74
WAVEFORM 2: PROPAGATION DELAYS MINIMUM PULSE WIDTH (CLR AND PR) (f=1MHz; 50%
duty cycle)
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
7/13
74V2G74
WAVEFORM 4: PULSE WIDTHS
8/13
74V2G74
SOT23-8L MECHANICAL DATA
mm.
mils
TYP.
DIM.
MIN.
0.90
0.00
0.90
0.22
0.09
2.80
2.60
1.50
TYP
MAX.
1.45
0.15
1.30
0.38
0.20
3.00
3.00
1.75
MIN.
35.4
0.0
MAX.
57.1
5.9
A
A1
A2
b
35.4
8.6
51.2
14.9
7.8
C
3.5
D
110.2
102.3
59.0
118.1
118.1
68.8
E
E1
e
0
.65
25.6
76.7
e1
L
1.95
0.35
0.55
13.7
21.6
9/13
74V2G74
SOT323-8L MECHANICAL DATA
mm.
mils
TYP.
DIM.
MIN.
0.80
0.00
0.80
0.13
0.10
1.80
1.80
1.15
TYP
MAX.
1.10
0.10
1.00
0.28
0.18
2.20
2.40
1.35
MIN.
31.5
0.0
MAX.
43.3
3.9
A
A1
A2
b
31.5
5.1
34.9
11.0
7.1
C
3.9
D
70.9
70.9
45.3
86.6
94.5
53.1
E
E1
e
0.5
1.5
19.7
59.0
e1
L
0.10
0.30
3.9
11.8
10/13
74V2G74
Tape & Reel SOT23-xL MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
180
MIN.
MAX.
7.086
0.519
A
C
12.8
20.2
60
13.0
13.2
0.504
0.795
2.362
0.512
D
N
T
14.4
3.33
3.27
1.47
4.1
0.567
0.131
0.128
0.0.58
0.161
0.161
Ao
Bo
Ko
Po
P
3.13
3.07
1.27
3.9
3.23
3.17
1.37
4.0
0.123
0.120
0.050
0.153
0.153
0.127
0.124
0.054
0.157
0.157
3.9
4.0
4.1
11/13
74V2G74
Tape & Reel SOT323-xL MECHANICAL DATA
mm.
TYP
180
13
inch
TYP.
7.086
0.512
DIM.
MIN.
175
MAX.
185
MIN.
6.889
0.504
0.795
MAX.
7.283
0.519
A
C
12.8
20.2
59.5
13.2
D
N
60
60.5
14.4
2.362
T
0.567
Ao
Bo
Ko
Po
P
2.25
2.7
1.2
4
0.088
0.106
0.047
0.157
0.157
3.98
3.98
4.2
4.2
0.156
0.156
0.165
0.165
4
12/13
74V2G74
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use ofsuch information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent orpatent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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13/13
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