74VCX32244GX [ETC]
BUFFER/DRIVER|OCTAL|4-BIT|VCX-CMOS|BGA|96PIN|PLASTIC ;
| 型号： | 74VCX32244GX |
| 厂家： | 
ETC |
| 描述： | BUFFER/DRIVER|OCTAL|4-BIT|VCX-CMOS|BGA|96PIN|PLASTIC 逻辑集成电路 驱动 |
| 文件： | 总8页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2000
Revised August 2001
74VCX32244
Low Voltage 32-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
Features
I 1.65V–3.6V VCC supply operation
The VCX32244 contains thirty-two non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for 8-bit, 16-bit or full 32-bit operation.
I 3.6V tolerant inputs and outputs
I tPD
2.5 ns max for 3.0V to 3.6V VCC
3.0 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
The 74VCX32244 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
I Power-off high impedance inputs and outputs
I Supports live insertion and withdrawal (Note 1)
The 74VCX32244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
I Static Drive (IOH/IOL
)
24 mA @ 3.0V VCC
18 mA @ 2.3V VCC
6 mA @ 1.8V VCC
I Uses patented noise/EMI reduction circuitry
I Latch-up performance exceeds 300 mA
I ESD performance:
Human body model > 2000V
Machine model > 200V
I Packages in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX32244GX
(Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
Note 2: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500416
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Connection Diagram
Truth Tables
Inputs
OE1
Outputs
O0-O3
I0-I3
L
L
L
H
X
L
H
Z
H
Inputs
OE2
Outputs
O4-O7
I4-I7
L
L
L
H
X
L
H
Z
H
Inputs
OE3
Outputs
O8–O11
I8-I11
L
L
L
H
X
L
H
Z
H
Inputs
OE4
Outputs
O12-O15
(Top Thru View)
I12-I15
Pin Descriptions
L
L
L
H
X
L
H
Z
Pin Names
Description
H
OEn
Output Enable Input (Active LOW)
Inputs
OE5
Outputs
O16-O19
I0–I31
O0–O31
Inputs
I16-I19
Outputs
L
L
L
H
X
L
H
Z
FBGA Pin Assignments
H
1
2
3
4
5
6
Inputs
OE6
Outputs
O20-O23
A
B
C
D
E
F
O1
O3
O0
O2
OE1
OE2
I0
I2
I1
I3
I20-I23
GND GND
VCC VCC
O5
O4
I4
I5
L
L
L
H
X
L
H
Z
O7
O6
GND GND
GND GND
I6
I7
O9
O8
I8
I9
H
O11
O13
O10
O12
VCC
VCC
I10
I12
I11
I13
Inputs
OE7
Outputs
O24-O27
G
GND GND
I24-I27
H
O14
O15
OE4
OE5
OE3
OE6
I15
I14
L
L
L
H
X
L
H
Z
J
K
L
O17
O19
O21
O23
O25
O27
O29
O16
018
I16
I18
I20
I22
I24
I26
I28
I17
I19
I21
I23
I25
I27
I29
GND GND
VCC VCC
H
O20
O22
O24
O26
O28
Inputs
OE8
Outputs
O28-O31
M
N
P
R
GND GND
GND GND
I28-I31
L
L
L
H
X
L
H
Z
VCC
GND GND
OE8 OE7
VCC
H
T
O30
O31
I31
I30
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
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2
Functional Description
The 74VCX32244 contains thirty-two non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dent of each other. The control pins may be shorted
together to obtain full 32-bit operation.The 3-STATE out-
puts are controlled by an Output Enable (OEn) input. When
OEn is LOW, the outputs are in the 2-state mode. When
OEn is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs.
Logic Diagrams
Byte 1
Byte 2
Byte 3
Byte 4
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions (Note 5)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
1.65V to 3.6V
1.2V to 3.6V
Outputs 3-STATED
−0.5V to +4.6V
−0.5V to VCC +0.5V
−50 mA
Data Retention Only
Input Voltage
Outputs Active (Note 4)
DC Input Diode Current (IIK) VI < 0V
−0.3V to +3.6V
Output Voltage (VO)
Output in Active States
Output in 3-State
DC Output Diode Current (IOK
VO < 0V
)
0V to VCC
−50 mA
+50 mA
0.0V to 3.6V
VO > VCC
Output Current in IOH/IOL
VCC = 3.0V to 3.6V
DC Output Source/Sink Current
(IOH/IOL
24 mA
18 mA
)
50 mA
VCC = 2.3V to 2.7V
DC VCC or GND Current per
Supply Pin (ICC or GND)
VCC = 1.65V to 2.3V
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
VIN = 0.8V to 2.0V, VCC = 3.0V
6 mA
100 mA
−40°C to +85°C
Storage Temperature Range (TSTG
)
−65°C to +150°C
10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < VCC ≤ 3.6V)
VCC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7–3.6
2.7–3.6
2.7–3.6
2.7
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
2.0
V
V
VIL
0.8
VOH
IOH = −100 µA
IOH = −12 mA
IOH = −18 mA
IOH = −24 mA
IOL = 100 µA
IOL = 12 mA
IOL = 18 mA
IOL = 24 mA
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
VCC − 0.2
2.2
V
V
3.0
2.4
V
3.0
2.2
V
VOL
LOW Level Output Voltage
2.7–3.6
2.7
0.2
0.4
V
V
3.0
0.4
V
3.0
0.55
5.0
V
II
Input Leakage Current
2.7–3.6
µA
IOZ
3-STATE Output Leakage
2.7–3.6
10
µA
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (VI, VO) ≤ 3.6V
0
10
40
µA
µA
µA
µA
VI = VCC or GND
2.7–3.6
2.7–3.6
2.7–3.6
VCC ≤ (VI, VO) ≤ 3.6V (Note 6)
VIH = VCC −0.6V
40
∆ICC
Increase in ICC per Input
750
Note 6: Outputs disabled or 3-STATE only.
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4
DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V)
VCC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.3–2.7
2.3–2.7
2.3–2.7
2.3
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
1.6
V
V
VIL
0.7
VOH
IOH = −100 µA
VCC − 0.2
2.0
V
IOH = −6 mA
V
IOH = −12 mA
2.3
1.8
V
IOH = −18 mA
2.3
1.7
V
VOL
LOW Level Output Voltage
IOL = 100 µA
2.3–2.7
2.3
0.2
0.4
0.6
5.0
V
IOL = 12 mA
V
IOL = 18 mA
2.3
V
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
2.3–2.7
µA
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 3.6V
2.3–2.7
10
µA
VI = VIH or VIL
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
VCC ≤ (VI, VO) ≤ 3.6V (Note 7)
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0
10
40
40
µA
µA
µA
2.3–2.7
2.3–2.7
Note 7: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V ≤ VCC < 2.3V)
VCC
(V)
Symbol
Parameter
Conditions
Min
Max
Units
VIH
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
1.65−2.3 0.65 × VCC
1.65−2.3
V
V
VIL
0.35 × VCC
VOH
IOH = −100 µA
IOH = −6 mA
IOL = 100 µA
IOL = 6 mA
1.65−2.3
1.65
VCC − 0.2
V
1.25
V
VOL
LOW Level Output Voltage
1.65−2.3
1.65
0.2
0.3
5.0
V
V
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
1.65−2.3
µA
IOZ
3-STATE Output Leakage
1.65−2.3
10
µA
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (VI, VO) ≤ 3.6V
0
10
40
40
µA
µA
µA
VI = VCC or GND
1.65−2.3
1.65−2.3
VCC ≤ (VI, VO) ≤ 3.6V (Note 8)
Note 8: Outputs disabled or 3-STATE only.
5
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AC Electrical Characteristics (Note 9)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V 0.3V VCC = 2.5V 0.2V VCC = 1.8V 0.15V
Units
Min
0.8
0.8
0.8
Max
2.5
3.5
3.5
Min
1.0
1.0
1.0
Max
3.0
Min
1.5
1.5
1.5
Max
6.0
tPHL, tPLH
Propagation Delay
ns
ns
ns
t
PZL, tPZH
Output Enable Time
Output Disable Time
4.1
3.8
8.2
tPLZ, tPHZ
6.8
Note 9: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Dynamic Switching Characteristics
VCC
TA = +25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Typical
0.25
0.6
Quiet Output Dynamic Peak VOL
CL = 30 pF, VIH = VCC, VIL = 0V
V
0.8
VOLV
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
−0.25
−0.6
−0.8
1.5
V
V
VOHV
1.9
2.2
Capacitance
TA = +25°C
Symbol
Parameter
Conditions
VCC = 1.8, 2.5V or 3.3V, VI = 0V or VCC
Units
Typical
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
6
7
pF
pF
pF
COUT
CPD
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V
20
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6
AC Loading and Waveforms
TEST
SWITCH
t
PLH, tPHL
PZL, tPLZ
Open
t
6V at VCC = 3.3 0.3V;
VCC x 2 at VCC = 2.5 0.2V; 1.8V 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
VOL +0.3V
VOH −0.3V
VOL +0.15V
VOH −0.15V
VOL +0.15V
VOH −0.15V
VY
7
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Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA96A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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