80C03_技术文档

80C03

AutoDUPLEX^TMCMOS Ethernet

Data Link Controller

96253

Note: Check for latest Data Sheet revision

before starting any designs.

Features

■ Low Power CMOS Technology

SEEQ Data Sheets are now on the Web, at

www.lsilogic.com.

■ Optimized for Embedded Ethernet Applications

■ Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards

for Ethernet (10Base-5) Thin Net (10Base-2)

(10Base-T) and Twisted Pair

This document is an LSI Logic document. Any

reference to SEEQ Technology should be

considered LSI Logic.

■ 10 MHz Serial/Parallel Conversion

■ Preamble Generation and Removal

■ Compatible with SEEQ 8003 and Provides

Additional Features

■ Automatic 32-Bit FCS (CRC) Generation and

Checking

- 64 bit Multicast Filter

■ Collision Handling, Transmission Deferral and

Retransmission with Automatic Jam and

Backoff Functions

- Transmit Collision Counter

- Total Collision Counter

- Reports Status of “Carrier” and “SQE” During

Transmits

■ Error Interrupt and Status Generation

- Transmit No CRC Mode

■ Available as “Ethernet Core” for Custom ASIC

- Transmit No Preamble Mode

- Transmit Packet Autopadding Mode

- Receive CRC Mode

Applications

■ Single 5 V± 10% Power Supply

- Receive Own Transmit Disable Mode

- Group Address Mode

- Fast Receive Discard Mode

- Full Duplex Mode

■ Standard CPU and Peripheral Interface

Control Signals

■ Loopback Capability for Diagnostics

■ Single Phase Clock

■ Supports AutoDUPLEX Mode for Automatic Full

Duplex Operation— Provides 20 MBits/sec

Bandwidth for Switched Networks

■ Inputs and Outputs TTL Compatible

■ 40 Pin DIP Package, 44 Pin PLCC

Functional Block Diagram

TxD

A2

A1

A0

CS

TRANSMIT

BYTE

COUNTER

RD

WR

ENCODER

BACKOFF

CONTROLLER

INTERFACE

INT

ATTEMPT

COUNTER

COMMAND/

STATUS

INTERFACE

INTERRUPT

AND

CONTROL

REGISTER

FILE

R x DC

T x RET

TRANSMIT

BYTE

CONTROL

COLL

TxEN

CdSt (0 – 7)

CRC

GENERATOR

M

U

X

TxWR

PARALLEL

/SERIAL

TxRDY

RESET

CSN

16-BYTE

TRANSMIT

FIFO

RECEIVE BIT

CONTROL

PLA

RxTxD (0 – 7)

RxTxEOF

DATA

INTERFACE

CRC

CHECKER

DECODER

INTERFACE

RxD

16-BYTE

RECEIVE

FIFO

CRC

STRIPPER

SERIAL

/PARALLEL

RxRDY

RxRD

ADDRESS

CHECKER

RxC

TxC

RECEIVE

BYTE

CONTROL

CLOCK

DRIVERS

RECEIVE

COUNTER

AutoDUPLEX is a trademark of SEEQ Technology Inc.

4-11

MD400121/C

80C03

Description

The SEEQ Ethernet Data Link Controller (EDLC^®) is

designed to support Data Link Layer (layer 2) of the

EthernetspecificationforLocalAreaNetworks(LAN). The

system interface is optimized for ease of connection to

commonly available DMA Controllers and specifically for

BURST MODE OPERATION. The 80C03 interfaces di-

rectly to the 8023A and 8020 Manchester Code Convert-

ers (MCC^TM) to complete the station resident Ethernet

functions. The protocol used is Carrier Sense, Multiple

Access with Collision Detection (CSMA/CD). The 80C03

EDLC chip is a single VLSI device which is designed to

greatly simplify the development of Ethernet communica-

tion in computer based systems. The 80C03 provides an

economic solution for the construction of an Ethernet

node, providing high speed data communication at 10

Megabits/second and sees applications in terminals,

workstations, personal computers, small business sys-

tems, and large computer systems, in both the office and

industrial environment. The 80C03 EDLC chip has a

universal system interface compatible with almost any

microprocessor, microcomputer, or system bus, allowing

the system designer to make the price/performance

tradeoffs for each application. The transmit and receive

sections of the EDLC chip are independent and can

operate simultaneously to allow reception of a transmitted

frame for use in loopback diagnostics modes.

on demand are: 64 bit Multicast filter, Transmit Collision

Counter, Total Collision Counter, Status Reporting of

Carrier and SQE during transmits, Transmit no CRC,

Transmit no Preamble, Transmit Packet Autopadding,

Receive CRC, Receive Own Transmit disable, Receive

Group Address mode, Fast Receive Discard Mode, and

Full Duplex Mode.

Functional Description

Frame Format

On an Ethernet communication network, information is

transmitted and received in packets or frames. An Eth-

ernet frame consists of a preamble, two address fields, a

byte-count field, a data field and a frame check sequence

(FCS). Each field has a specific format which is described

in detail below. An Ethernet frame has a minimum length

of 64 bytes and a maximum length of 1518 bytes exclusive

of the preamble. The Ethernet frame format is shown

below.

ETHERNET FRAME

PREAMBLE

(8)

SOURCE

ADDRESS

(6)

DATA

(46-1500)

FCS

(4)

DESTINATION

ADDRESS

(6)

BYTE

COUNT

(2)

The 80C03 is compatible with SEEQ 8003 and provides

additional programmable features. The features enabled

NOTE:

Field length in bytes in parentheses.

V

1

40

39

38

37

36

A1

A0

CC

2

A2

3

TxEN

TxD

CS

4

RD

TxRET

5

WR

7

8

9

V

39 CdSt 0

SS

RxTxD0

RxTxD1

RxTxD2

RxTxD3

RxTxD4

RxTxD5

RxTxD6

6

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

CdSt0

CdSt1

CdSt2

CdSt3

CdSt4

CdSt5

CdSt6

RxTxD1

RxTxD2

CdSt 1

CdSt 2

CdSt 3

CdSt 4

38

37

36

35

34

33

32

31

7

8

RxTxD3 10

RxTxD4 11

RxTxD5 12

9

10

11

12

CdSt 5

CdSt 6

RxTxD6

RxTxD7

13

14

RxTxD7

TxC

13

14

15

16

17

18

19

20

CdSt7

RxC

CdSt

RxC

7

RxDC

INT

TxWR

TxC 15

TxRDY

RxTxEOF

RxRD

V

16

17

30 ADUPLX*

29

SS

TxWR

COLL

RESET

CSN

V

SS

RxRDY

V

SS

RxD

Figure 1. Dual-In-Line

Top View

Figure 2. Plastic Leaded Chip Carrier

Top view

EDLC is a registered trademark of SEEQ Technology Inc.

MCC is a trademarks of SEEQ Technology Inc.

2

4-2

MD400121/C

80C03

Preamble: The preamble is a 64-bit field consisting of 62

alternating “1”s and “0”s followed by a “11” End-of-Pre-

amble indicator.

FIRST BYTE

A7 . . . . . . A0

A15 . . . . . . A8

A23 . . . . . . A16

A31 . . . . . . A24

A39 . . . . . . A32

A47 . . . . . . A40

B7 . . . . . . B0

B15 . . . . . . B8

B23 . . . . . . B16

B31 . . . . . . B24

B39 . . . . . . B32

B47 . . . . . . B40

T7 . . . . . . T0

T15 . . . . . . T8

D7 . . . . . . D0

DESTINATION

ADDRESS

(6 BYTES)

Destination Address: The Destination Address is a 6-

byte field containing either a specific Station Address, a

Broadcast Address, or a Multicast Address to which this

frame is directed.

SOURCE

ADDRESS

(6 BYTES)

Source Address: The Source Address is a 6-byte field

containing the specific Station Address from which this

frame originated.

BYTE COUNT

(2 BYTES)

Byte-Count Field: The Byte-Count Field consists of two

bytes providing the number of valid data bytes in the Data

Field, 46 to 1500. This field is uninterpreted at the Data

Link Layer, and is passed through the EDLC chip to be

handled at the Client Layer.

DATA

(46 – 1500

BYTES)

LAST BYTE

Data Field: The Data Field consists of 46 to 1500 bytes of

information which are fully transparent in the sense that

any arbitrary sequence of bytes may occur.

Figure 3. Typical Frame Buffer Format for

Byte-Organized Memory

Frame Check Sequence: The Frame Check Sequence

(FCS) field is a 32-bit cyclic redundancy check (CRC)

value computed as a function of the Destination Address

Field, Source Address Field, Type Field and Data Field.

TheFCSisappendedtoeachtransmittedframe, andused

at reception to determine if the received frame is valid.

EDLC chip encapsulates these fields into an Ethernet

frame by inserting a preamble prior to these information

fields and appending a CRC after the information fields.

The chip can be programmed to exclude inclusion of the

preambleand/ortheFCSfromthetransmitdatastream. In

this case it is assumed that the preamble and FCS are

provided as part of the data written to the chip.

Transmitting

The transmit data stream consists of the Preamble, four

information fields, and the FCS which is computed in real

time by the EDLC chip and automatically appended to the

frame at the end of the serial data. The Preamble is also

generated by the EDLC chip and transmitted immediately

prior to the Destination Address. Destination Address,

Source Address, Type Field and Data Field are prepared

in the buffer memory prior to initiating transmission. The

Transmission Initiation/Deferral

The Ethernet node initiates a transmission by storing the

entire information content of the frame to be transmitted in

an external buffer memory, and then transferring initial

frame bytes to the EDLC Transmit FIFO. “Transmit-buffer

to FIFO” transfers are coordinated via the TxWR and

TxRDY handshake interface, i.e., bytes are written to the

BIT

NAME

NO.

RxTxD0

RxTxD1

RxTxD2

RxTxD3

RxTxD4

RxTxD5

RxTxD6

RxTxD7

6

7

8

9

10

11

12

13

. . .

FIRST BYTE

SIXTH BYTE

PREAMBLE

A0 . . . A7

A8 . . . A15

. . . . . . A40 . . . A47

SOURCE ADDRESS . . .

DESTINATION ADDRESS

BITS WITHIN A BYTE TRANSMITTED/RECEIVED BIT NO. "0" FIRST THROUGH BIT NO. "7" LAST.

Figure 4. Bit Serialization/Deserialization

4-33

MD400121/C

80C03

FIFO via TxWR only when TxRDY is HIGH. Actual

transmission of the data onto the network will only occur if

the network has not been busy for the minimum defer time

(9.6 µs) and any Backoff time requirements have been

satisfied. When transmission begins, the EDLC chip

activatesthetransmitenable(TxEN)lineconcurrentlywith

the transmission of the first bit of the Preamble and keeps

it active for the duration of the transmission.

sion status bit is set, transmit Collision Counter is updated,

the TxRET signal is generated, and the Backoff interval

begun.

Underflow: Transmit data is not ready when needed for

transmission. Once transmission has begun, the EDLC

chip on average requires one transmit byte every 800 ns

in order to avoid Transmit FIFO underflow (starvation). If

this condition occurs, the EDLC chip terminates the trans-

mission, issues a TxRET signal, and sets the Transmit-

Underflow status bit.

Collision

When concurrent transmissions from two or more Eth-

ernet nodes occur (collision), the EDLC chip halts the

transmission of the data bytes in the Transmit FIFO and

transmits a Jam pattern consisting of 55555555 hex. At

the end of the Jam transmission, the EDLC chip issues a

TxRET signal to the CPU and begins the Backoff wait

period.

16 Transmission Attempts: If a Collision occurs for the

sixteenth consecutive time, the 16-Transmission-At-

tempts status bit is set, the Collision status bit is set, the

TxRET signal is generated, and the Backoff interval be-

gun. The counter that keeps track of the number of

collisions is modulo 16 and therefore rolls over on the 17th

collision. Bits 15 to 11 on the Collision Count Registers

(80C03 mode) indicates the attempt counter used for

Collision back-off. These can be read and cleared as

described in the Transmit Command register description.

To reinitiate transmission, the initial bytes of the frame

information fields must be reloaded into the EDLC Trans-

mit FIFO. The TxRET is used to indicate to the buffer

manager the need for frame reinitialization. The reloading

of the Transmit FIFO may be done prior to the Backoff

interval elapsing, so that no additional delay need be

incurred to retransmission.

At the completion of every transmission or retransmission,

new status information is loaded into the Transmit Status

Register. Dependent upon the bits enabled in the Trans-

mit Command Register, an interrupt will be generated for

the just completed transmission. In both collision and

underflow the TxRET signal is activated.

Scheduling of retransmission is determined by a con-

trolled randomization process called Truncated Binary

Exponential Backoff. The EDLC chip waits a random

interval between 0 and 2^Kslot times (51.2 µs per slot time)

before attempting retransmission, where “K” is the current

transmission attempt number (not to exceed 10).

Receiving

The EDLC chip is continuously monitoring the network.

When activity is recognized via the Carrier Sense (CSN)

line going active, the EDLC chip synchronizes itself to the

incoming data stream during the Preamble, and then

examines the destination address field of the frame. De-

pending on the Address Match Mode specified, the EDLC

chip will either recognize the frame as being addressed to

itself in a general or specific fashion or abort the frame

reception. The 80C03 also allows counting of all collisions

seen on the network.

When 16 consecutive attempts have been made at trans-

mission and all have been terminated due to collision, the

EDLC Transmit Control sets an error status bit and issues

an interrupt to the CPU if enabled.

Terminating Transmission

Transmission Terminates under the following conditions:

Normal: The frame has been transmitted successfully

without contention. Loading of the last data byte into the

Transmit FIFO is signaled to the EDLC chip by activation

of the RxTxEOF signal concurrently with the last byte of

data loaded into the Transmit FIFO. This line acts as a

ninth bit in the Transmit FIFO. When this last byte is

serialized, ifthechipisnotinTransmitNoCRCmode, then

the CRC is appended and transmitted concluding frame

transmission. The Transmission Successful bit of the

Transmit Status Register will be set by a normal termina-

tion.

Preamble Processing

The EDLC chip recognizes activity on the Ethernet via the

Carrier Sense line. The Preamble is normally 64 bits (8

bytes) long. The Preamble consists of a sequence of 62

alternating “1”s and “0”s followed by “11”, with the frame

information fields immediately following. In order for the

decoder phase-lock to occur, the EDLC chip waits 16 bit

timesbeforelookingforthe“11”endofpreambleindicator.

If the EDLC chip receives a “00” before receiving the “11”

in the Preamble, an error condition has occurred. The

frame is not received, and the EDLC chip begins monitor-

ing the network for a carrier again.

Collision: Transmission attempted by two or more Eth-

ernet nodes. The Jam sequence is transmitted, the Colli-

4

4-4

MD400121/C

80C03

TRANSMIT

RECEIVE

DATA

DMA/

BUFFER

CONTROL

BUFFER

8020 or 8023

MANCHESTER

CODE

BUS

TRANSCEIVER

80C03

EDLC

CONVERTER (MCC)

COLLISION TRANSMIT

RECEIVE

SYSTEM

MEMORY

CPU

TO 83C92 CMOS COAX TRANSCEIVER

83C94 CMOS TWISTED PAIR TRANSCEIVER

Figure 5. Typical Ethernet Node Configuration

Address Matching

Ethernet addresses consist of two 6-byte fields. The first

bit of the address signifies whether it is a Station Address

or a Multicast/Broadcast Address.

mine which byte is selected and bits 3 thru 5 to determine

which bit according to the following tables:

FCS Bits

Byte Selected

0

1

2

First Bit

Address

0

Station Address (Physical)

0

1

0

1

0

1

0

1

Byte 0

Byte 1

Byte 2

Byte 3

Byte 7

1

Multicast/Broadcast Address

(logical)

Address matching occurs as follows:

FCS Bits

Bit Selected

4

5

6

Station Address: All destination address bytes must

match the corresponding bytes found in the Station Ad-

dressRegister. IfGroupAddressmodeisenabled,thelast

4bitsofthestationaddressaremaskedoutduringaddress

matching.

0

1

0

1

0

1

0

1

Bit 0

Bit 1

Bit 2

Bit 3

Bit 7

After computing the FCS on the first six bytes of the

address field (Destination address), the 80C03 uses bits 0

thru 5 as an address to the Multi-cast address filter

register. Bit 0 of the FCS is assumed to be where receive

data enters the FCS generation circuitry. If the corre-

sponding bit addressed in the Multicast address filter

register is a ‘1’ the 80C03 will receive the frame, otherwise

it will discard the frame. Addressing of the Multicast

address filter register occurs using bits 0 thru 2 to deter-

Multicast Address: If the first bit of the incoming address

is a 1 and the EDLC chip is programmed to accept

Multicast Addresses without using Hash filtering, the

frame is received. The 80C03 also can be programmed to

use hash filter for determining acceptance of multicast

addresses.

4-55

MD400121/C

80C03

Broadcast Address: The six incoming destination ad-

dress bytes must all be FF hex. If the EDLC chip is

programmed to accept broadcast or Multicast Addresses

the frame will be received.

Good Frame: A frame is received that does not have a

CRC error, Shortframe or Overflow Condition.

System Interface

TheEDLCchipsysteminterfaceconsistsoftwoindepend-

ent busses and respective control signals. Data is read

and written over the Receive/Transmit Data Bus RxTxD

(0-7). These transfers are controlled by the TxRDY and

TxWR signals for transmitted data and RxRDY and RxRD

for received data. All Commands and Station Addresses

are written, and all status read over a separate Command/

Status Bus CdSt (0-7). These transfers are controlled by

the CS, RD , WR and A0-A2 signals. The EDLC chip’s

command and status registers may be accessed at any

time. However, it is recommended that writing to the

command register be done only during interframe gaps.

If the incoming frame is addressed to the EDLC chip

specifically (Destination Address matches the contents of

the Station Address Register), or is of general or group

interest (Broadcast or Multicast Address), the EDLC chip

will pass the frame exclusive of Preamble and FCS to the

CPU buffer and indicate any error conditions at the end of

the frame. If, however, the address does not match, as

soon as the mismatch is recognized the EDLC chip will

terminate reception and issue an RxDC.

The EDLC chip may be programmed via the Match Mode

bits of the Receive Command Register to ignore all frames

(Disable Receiver), accept all frames (Promiscuous

mode), accept frames with the proper Station Address or

the Broadcast Address (Station/Broadcast), or accept all

frames with the proper Station Address, the Broadcast

Address, or all Multicast Addresses (Station/Broadcast/

Multicast).

With the exception of the two Match Mode bits in the

Receive Command Register, all bits in both command

registers are interrupt enable bits. Changing the interrupt

enable bits during frame transmission does not affect the

frame integrity. Asynchronous error events, however,

e.g., overflow, underflow, etc., may cause chip operation

to vary, if their corresponding enable bits are being altered

at the same time.

Terminating Reception

Reception is terminated when either of the following con-

ditions occur:

Reading the status registers may also occur at any time

during transmission or reception.

Carrier Sense Inactive: Indicates that traffic is no longer

Internal Register Addressing (8003 mode)

Register

present on the Ethernet cable.

Overflow: The host node for some reason is not able to

empty the Receive FIFO as rapidly as it is filled, and an

erroroccursasframedataislost. OnaveragetheReceive

FIFOmustbeservicedevery800nstoavoidthiscondition.

Address

Register Description

A2 A1 A0

Read

Write

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

Station Addr 0

Station Addr 1

Station Addr 2

Station Addr 3

Station Addr 4

Station Addr 5

Rx Command

Tx Command

Frame Reception Conditions

Upon terminating reception, the EDLC chip will determine

the status of the received frame and conditionally load it

into the Receive Status Register. An interrupt will be

issued if the appropriate conditions as specified in the

Receive Command Register are present. The EDLC chip

may report the following conditions at the end of frame

reception:

—

Rx Status

Tx Status

Status Registers are read only registers. Command and

Station Address registers are write only registers. Access

to these registers is via the CPU interface: Control signals

CS, RD , WR , and the Command/Status Data Bus

CdSt (0-7).

Overflow: The EDLC internal Receive FIFO overflows.

Dribble Error: Carrier Sense did not go inactive on a

receive data byte boundary.

Station Address Register

CRC Error: The 32-bit CRC transmitted with the frame

The Station Address Register is 6 bytes in length. The

contents may be written in any order, with bit “0” of byte “0”

corresponding to the first bit received in the data stream,

and indicating whether the address is physical or logical.

Bit 7 of station address byte 5 is compared to the last bit of

does not match that calculated upon reception.

Short Frame: A frame containing less than 64 bytes of

information was received (including FCS).

6

4-6

MD400121/C

80C03

the received destination address. The Station Address

should be programmed prior to enabling the receiver.

The OLD/NEW status bit is set each time the Transmit

Status Register is read, and reset each time new status is

loaded into the Transmit Status Register. The OLD/NEW

status bit is SET, and all other bits CLEARED upon chip

reset.

Transmit Command Register

The Transmit Command Register is an interrupt mask

register, which provides for control of the conditions al-

lowed to generate transmit interrupts. Each of the four

least significant bits of the register may be individually set

or cleared. When set, the occurrence of the associated

condition will cause an interrupt to be generated. The four

specific conditions for which interrupts may be generated

are:

Transmit Status Register Format

7

6

x

5

x

4

x

3

2

1

0

BIT

Transmit Underflow

Transmit Collision

16 Transmission Attempts

• Underflow

• Collision

• 16 Collisions

• Transmission Successful

Transmission Successful

Old/New Status

The interrupt signal INT will be set when one or more of the

specified transmission termination conditions occurs and

the associated command bit has been set. The interrupt

signal INT will be cleared when the Transmit Status

Register is read.

Receive Command Register

The Receive Command Register has two primary func-

tions, it specifies the Address Match Mode, and it specifies

Frames-of Interest. i.e. frames whose arrival must be

communicated to the CPU via interrupts and status regis-

ter updates. Frames-of-Interest are frames whose status

mustbesavedforinspection,evenattheexpenseoflosing

subsequent frames.

All bits of the Transmit Command Register are cleared

upon chip reset.

Transmit Command Register Format

Receive Command Register Format

7

0

6

0

5

0

4

0

3

2

1

0

BIT

7

6

5

4

3

2

1

0

BIT

Interrupt on Transmit Underflow

Interrupt on Transmit Collision

If ‘0’ 8003 Mode

If ‘1’ Enable

Additional Features

Interrupt on Overflow Error

Interrupt on CRC Error

Interrupt on Dribble Error

Interrupt on Short Frame

Interrupt on End of Frame

Interrupt on Good Frames

Match Mode 0

Interrupt on 16 Transmission

Attempts

Interrupt on Transmission

Successful

Transmission Successful is set only on the successful

transmission or retransmission of a frame.

Match Mode 1

Bits 0-5 specify Interrupt and Frame-of-Interest when set.

Bit 4, End of Frame, specifies any type of frame except

overflow.

80C03 provides additional new features which are en-

abled depending on writing ‘1’s to bits 7,6,5,4 of the

transmitcommandregister. Ifthesefourbitsarealways‘0’

then the 80C03 will be exactly compatible to SEEQ 8003

EDLC.

The bits 6,5 of transmit command register are used to

address new registers on 80C03 together with the A2, A1,

A0, RD WR, CS pins. (see table Page 9)

Transmit Status Register

The Transmit Status Register is loaded at the conclusion

of each frame transmission or retransmission attempt. It

provides for the reporting of both the normal and error

termination conditions of each transmission.

4-77

MD400121/C

80C03

protected. TheOld/NewStatusbitisclearedwheneverthe

status of a new Frame-of-Interest is loaded into the Re-

ceive Status Register and is set after that status is read.

When zero, it indicates “new status for a Frame-of-

Interest”.

Match Match

Mode Mode

1

0

1

0

1

0

Function

0

1

2

Receiver Disable

Receive All Frames

Thus the status of any frame received following the recep-

tion of a Frame-of-Interest will not be loaded into the

Receive Status Register unless the previous status has

been read. If any following frame is received before the

status of the previous Frame-of-Interest has been read,

the new status will not be loaded, the Receive Discard

(RxDC) signal will be issued and the Receive FIFO will be

cleared.

Receive Station or Broadcast

Frames

3

1

Receive Station,

Broadcast/Multicast Frames

Match Mode Definition

Changing the receive Match Mode bits during frame re-

ceptionmaychangechipoperationandgiveunpredictable

results.

With this one exception caused by a write-protect condi-

tion, the status of each frame is always loaded into the

Receive Status Register on completion of reception.

Interrupt Enable and Frames-of-Interest

Any frame received will cause an interrupt to be generated

if the corresponding Interrupt Enable bit is set. This

interrupt is reset upon reading the Receive Status Regis-

ter.

Bits 0-5 when set specify interrupt generation on occur-

rence of the corresponding frame reception condition.

They also specify the corresponding types of frames to be

Frames-of-Interest for use by the Receive Status Register

to control status loading.

These conditions ensure that a maximum number of good

frames are received and retained.

Receive Status Register

The Receive Status Register is normally loaded with the

status of each received frame when the frame has been

receivedorframereceptionhasbeenterminatedduetoan

error condition. In addition, this register contains the Old/

New Status bit which is set when the Receive Status

Register is read or the chip is reset, and cleared only when

status is loaded for a Frame-of-Interest (as defined by bits

0-5 of the Receive Command Register). All other bits are

cleared upon chip reset.

7

6

x

5

4

3

2

1

0

BIT

Received Frame with Overflow Error

Received Frame with CRC Error

Received Frame with Dribble Error

Received Short Frame

Received End of Frame

Received Good Frame

Old/New Status

Receive Status Register Format

The Old/New Status bit write-protects the Receive Status

Register while it contains unread status for a Frame-of-

Interest. When this bit is zero, the register is write-

8

4-8

MD400121/C

80C03

Internal Register Addressing (80C03 mode)

Transmit

Command

Register

Bits

Register

Address

Register Description

6

0

5

0

A2 A1 A0

Read

Write

0

1

2

3

0

1

0

1

0

1

Transmit Collision Counter LSB

Transmit Collision Counter MSB

Total Collision Counter LSB

Total Collision Counter MSB

Station Addr 0

Station Addr 1

Station Addr 2

Station Addr 3

4

5

0

1

0

1

“For Test Only” Do Not Use

Bit 0 — SQE Flag

Station Addr 4

Station Addr 5

Bit 1 — txen_no_ carrier flag

6

7

0

1

0

1

Rx Status

Tx Status

Rx Command

Tx Command

0

1

2

3

4

5

0

1

0

1

0

1

0

1

0

1

0

1

—

Multicast Filter LSB Register 0

Multicast Filter Register 1

Multicast Filter Register 2

Multicast Filter Register 3

Multicast Filter Register 4

Multicast Filter Register 5

0

1

0

1

—

Multicast Filter Register 6

Multicast Filter MSB Register 7

2

3

4

5

6

7

1

0

1

0

1

0

1

0

1

0

1

—

Reserved. Set to All ‘0’

Tx Control Register

TX-RX Config. Register

Reserved

Note: For register reads, the transmit command register bits 5 & 6 are a don’t care.

4-99

MD400121/C

80C03

Transmit Control Register

Available in 80C03 mode only. Allows for control of trans-

mit Collision Counter, total Collision Counter, SQE func-

tion,carrierlossontransmitreporting,Multi-casthashfilter

reception of runt frames. Set to all ‘0’s after reset.

indicates the attempt counter used in SEEQ for collision

back off. These can be read and cleared as described in

register section.

TxEN_no_carrier

7

6

5 4 3 2 1 0

When txen goes from 1 to 0, if there is no carrier this bit is

set. Once set this will stay set until cleared. These can be

read and cleared as described in register section.

X

Bit 0 = ‘1’ Enables Transmit

Collision Counter

Test Mode

Bit 0 = ‘0’ Clears Transmit

Collision Counter

Bits 7 and 4 of the Transmit command register are used for

testing purposes only. For normal operation these bits

should be set to ‘0’.

Bit 1 = ‘1’ Enables

Collision Counter

Bit 1 = ‘0’ Clears

Collision Counter

Tx-Rx Configuration Register

Availablein80C03modeonly. Allowsforcontrolofvarious

transmit and receive features. Set to all 0’s after reset.

Bit 2 = ‘1’ Enables

sqe Function

Bit 2 = ‘0’ Clears

sqe Flag

7

6

5 4 3 2 1 0

Bit 3 = ‘1’ Enables

Hash Filter for Multicast

Bit 0 = ‘1’ Enables Group

Address Mode

Bit 3 = ‘0’ Disables

Hash Filter for Multicast

Bit 4 = ‘1’ Disables

The Reception of Frames

Shorter Than 13 Bytes

Bit 1 = ‘1’ Enables Transmit

Packet Autopad Mode

Bit 5 = ‘1’ Enables

txen_no_carrier Function

Bit 2 = ‘1’ Enables Transmit No

Preamble Mode

Bit 5 = ‘0’ Clears

txen_no_carrier Flag

Bit 3 = ‘1’ Enables Receive Own

Traansmit Disable Mode

Multicast Mode

There is a 64 bit multicast address filter register on 80C03

which can accessed as shown in table (page 9). When the

SEEQ 80C03 is programmed to receive multicast frames

(match mode 3), after computing the CRC on the address

field of the receiving frame (first 6 bytes), it will index to the

multicast address filter register depending on bits 0 to 5 of

the CRC. If the corresponding bit is a ‘1’ it will receive the

frame, otherwise it will discard the frame.

Bit 4 = ‘1’ Enables Transmit No

CRC Mode

Bit 5 = ‘1’ Enables Full Duplex

Mode

Bit 6 = ‘1’ Enables Receive CRC

Mode

SQE Status Bit

After transmitting a frame if 80C03 does not receive a

collision with in a 4.0 µs period this bit will be set. Once set

this will stay set until cleared. This can read and cleared

as explained in the register section.

Bit 7 = ‘1’ Enables Fast Receive

Discard Mode

Group Address Mode

In this mode the last 4 bits of the serial receive data stream

for the destination address are masked out in address

comparison. This means that when the destination ad-

dress is compared against the value programmed in the

station address register that the packet will not be rejected

due to incorrect address even its last 4 bits did not match.

Collision Count Registers

There are two 16 bit read only collision count registers

which are cleared on reset. One counts the collisions on

transmission and the other counts all the collisions except

the ones in the SQE_WINDOW. The transmit collision

counter is eleven bits wide. Bits 15 to 11 of this register

10

4-10

MD400121/C

80C03

Transmit Packet Autopad Mode

RxC Receive Data (Input): 10 MHz, 50% duty cycle

nominal. The receive clock is used to synchronize incom-

ing data to the EDLC chip from the decoder. This clock

runs continuously, and is asynchronous to TxC.

This feature automatically pads packets to be transmitted

with less than 60 bytes of data out to a minimum IEEE

802.3 standard packet length of 60 bytes excluding FCS.

Padding is done with bytes of 00 hex.

Transmit No Preamble Mode

This mode prevents the transmitter from adding a pre-

amble pattern at the beginning of data to be transmitted.

RxD Receive Data (Input): Serial input data to the EDLC

chip from the decoder. Active HIGH.

CSN Carrier Sense (Input): Indicates traffic on the coax-

ial cable to the EDLC chip. Becomes active with the first

bitofthePreamblereceived, andinactiveonebittimeafter

the last bit of the frame is received. Active HIGH.

Receive Own Transmit Disable Mode

This mode prevents the 80C03 from receiving a packet if

it is also transmitting a packet.

Transmit No CRC Mode

This mode prevents the transmitter from appending trans-

mit data with an FCS.

COLL Collision (Input): Indicates transmission conten-

tion of the Ethernet cable. the Collision input is latched

internally. Sampledduringtransmission,Collisionissetby

an active high pulse on the COLL input and automatically

reset at the end of transmission of the JAM sequence.

AutoDUPLEX Mode

In this mode the transmitter will ignore carrier sense and

will not defer to it if it is ready to transmit a packet.

Data Buffer Interface

Receive CRC Mode

RxTxD (0-7) Receive/Transmit Data Bus (I/O): Carries

Receive/Transmit data byte from/to the EDLC chip Re-

ceive/Transmit FIFOs.

In this mode the receiver loads the 4 bytes of FCS into the

receive FIFO along with the data allowing the FCS value

to be read out.

RxTxEOF Receive/Transmit End of Frame (I/O): Indi-

cates last byte of data on the Receive/Transmit Data Bus.

Effectively a ninth bit in the FIFOs with identical timing to

RxTxD (0-7). Active HIGH.

Fast Receive Discard Mode

In this mode the receive discard signal RxDC occurs a

maximum of 400 ns after carrier sense goes low.

Pin Description

RxRDY Receive Ready (Output): Indicates that at least

one byte of received data is available in the Receive FIFO.

This signal will remain active high as long as one byte of

data remains in the Receive FIFO. When this condition no

longer exists, RxRDY will be deasserted with respect to

the leading edge of the RxRD strobe that removes the last

byte of data from the Receive FIFO. RxRD should not be

activated if RxRDY is low. Active HIGH and cleared by

Reset.

The EDLC chip has four groups of interface signals:

• Power Supply

• Encoder/Decoder

•Data Buffer

•Command/Status

Power Supply

V_CC..........................................................................+5V

V_SS.....................................................................Ground

Encoder/Decoder Interface

TxC Transmit Clock (Input): 10 MHz, 50% duty cycle

transmit clock used to synchronize the transmit data from

the EDLC chip to the encoder. This clock runs continu-

ously, and is asynchronous to RxC.

RxRD Receive Read Strobe (Input): Enables transfer of

received data from the EDLC Receive FIFO to the RxTxD

Bus. Data is valid from the EDLC Receive FIFO at the

RxTxD pins on the rising edge of this signal. This signal

shouldnotbeactivatedunlessRxRdyishigh. ActiveLOW.

TxD Transmit Data (Output): Serial Data output to the

encoder. Active HIGH.

RxDC Receive Discard (Output): Asserted when one of

the following conditions occurs, and the associated Inter-

rupt Enable bit in the Receive Command Register is reset.

(1)ReceiveFIFOoverflow. (2)CRCError.(3)ShortFrame

Error. (4) Receive frame address nonmatch or (5) current

frame status lost because previous status was not read.

TxEN Transmit Enable (Output): This signal is used to

activate the encoder. It becomes active when the first bit

of the Preamble is transmitted and inactive when the last

bit of the frame is transmitted. Active HIGH and cleared by

Reset.

41-111

MD400121/C

80C03

RxDC does not activate on errors when the associated

Interrupt Enable bit is set. In this case, EOF will be

generated instead when the Receive FIFO is read out.

This allows reception of frames with errors. RxDC acts

internally to clear the Receive FIFO.

initializationinformationbetweentheEDLCchipandCPU.

These lines are nominally high impedance until activated

by CS and RD being simultaneously active.

A0-A2 Address (0-2) (Input): Address lines to select the

proper EDLC internal registers for reading or writing.

TxRDY Transmit Ready (Output): Indicates that the

Transmit FIFO has space available for at least one data

byte. Thissignalwillremainactivehighaslongasonebyte

of space exists for transmitted data to be written into.

When this condition no longer exists, TxRDY will be

deasserted with respect to the leading edge of the TxWR

strobe that fills the Transmit FIFO. TxRDY is forced

inactive during Reset, and when TxRET is active. Active

HIGH. Goes high after Reset.

CS Chip Select (Input): Chip Select input, must be active

in conjunction with RD or WR to successfully access the

EDLC internal registers. Active LOW.

RD Read (Input): Enables reading of the EDLC internal

registers in conjunction with CS. Data from the internal

registers is enabled via the falling edge of RD and is valid

on the rising edge of the signal. Active LOW.

TxWR Transmit Write (Input): Synchronizes data trans-

fer from the RxTxD Bus to the Transmit FIFO. Data is

written to the FIFO on the rising edge of this signal. This

signal should not be active unless TxRDY is high. Active

LOW.

WR Write (Input): Enables writing of the EDLC internal

registers in conjunction with CS. Write data on the Cdst

(0-7) data lines must be set up relative to the rising edge

of the signal. Active LOW.

INT Interrupt (Output): Enabled as outlined above by a

variety of transmit and receive conditions. Remains active

until the status register containing the reason for the

interrupt is read. Active HIGH.

TxRet Transmit Retransmit (Output): Asserted when-

ever either transmit underflow or transmit collision condi-

tions occur. It is nominally 800 ns in width. Active HIGH.

Asserted by Reset. TxRET clears the internal Transmit

FIFO.

RESET (Input): Initializes control logic, clears command

registers, clears the Transmit Status Register, clears bits

0-5 of the Receive Status Register, sets the Old/New

Status bit (bit 7 of the Receive Status Register), asserts

RxDC and TxRET and clears the Receive and Transmit

FIFOs. In addition, TxRDY is forced low during a reset.

TxRDY goes high when RESET goes high, indicating the

EDLC chip is ready to transmit. RESET is active LOW.

ADUPLX* - Input (PLCC Package Only): Active low

input used to set 80C03 in AutoDUPLEX Mode. In this

mode the transmitter will not defer to active carrier sense

signal.

Command/Status Interface

CdSt(0-7)Command/StatusDataBus(I/O):Theselines

carry commands and status as well as station address

12

4-12

MD400121/C

80C03

Absolute Maximum Ratings

Operating Conditions

Ambient Temperature

Ambient Temperature Range...................... 0°C to 70°C

_CCPower Supply ................................ 4.50 V to 5.50 V

Under Bias ........................................... –10°C to + 80°C

Storage Temperature .......................... –65°C to +150°C

All Input or Output Voltages

V

with Respect to Ground ........................... +6V to –0.3V

Package Maximum Power Dissipation ............ 1.5 Watts

DC Characteristics T_A= 0° C to 70°C, V_CC= 5 V to 5%

Limits^[1]

Symbol

Parameter

Min.

Typ.

Max.

Units

Condition

I_IN

Input Leakage Current

Output Leakage Current

V_CCCurrent

10

40

6

µA

mA

V

V_IN= 0.45 V to 5.25 V

V_OUT= 0.45 V to 5.25 V

I_O

I_CC

30

V_CH

V_CL

V_IL

Clock Input High Voltage

Clock Input Low Voltage

Input Low Voltage

3.5

0.8

6

V

V_IH1

V_{IH 2}

V_OL

V_OH

Input High Voltage

Output Low Voltage

Output High Voltage

2.0

3.0

V

Except TxWR and RxRD

TxWR and RxRD

I_OL= 2.1 mA

6

V

0.4

V

2.4

V

I_OH= –400 µA

NOTE:

1. Typical values are for T_A= 25°C and nominal supply voltages.

41-133

MD400121/C

80C03

Capacitance^[6]T_A= 25°C, F_C= 1 MHz

AC Test Conditions

Output Load: 1 Schottky TTL Gate + CL = 100 pF

(All pins except TxEN, TxD)

Symbol Parameter

Maximum

Condition

V_IN= 0 V

V_I/O= 0 V

TxEN, TxD Load: 1 Schottky TTL Gate + CL = 35 pF

Input Pulse Level:0.4 V to 2.4 V

Timing Reference Level:1.5 V

C_IN

Input Capacitance 15 pF

C_I/O

I/O Capacitance

15 pF

AC Characteristics T_A= 0° C to 70°C, V_CC= 5 V ± 5%

Limits

Typ.

Units

Symbol^[5]

DATA AND COMMAND/STATUS INTERFACE TIMING

Parameter

Min.

Max.

(ns)

Condition

TDBD

TDBR

TDBS

TDRY

THAR

THDA

THRW

TSAR

TSCS

TSRT

TWCH

TWCL

RxTx/CdSt Bus Data Delay

RxTx/CdSt Bus Release Delay

RxTx/CdSt Bus Siezure Delay

RxRDY/TxRDY Clear Delay

A_0-2/CS Hold

40

ns

10

20

40

10

0

RxTx/CdSt Bus Hold

RxRD/TxWR Hold

0

A_0-2/CS Setup

0

CdSt Bus Setup

20

50

RxTx Bus Setup

RxRD/TxWR/RD/WR High Width

RxRD/TWR/RD/WR Low Width

10,000

SERIAL TRANSMIT AND RECEIVE INTEFACE TIMING

TDDC

TDIC

RxDC Set Delay

INT Clear Delay

TxRET Set Delay

Receive INT Delay

TxD/TxEN Delay

Transmit INT Delay

RxD Hold

950

1650

45

ns

NOTE 1

TDRE

TDRI

2400

1150

20

3400

1850

60

NOTE 3

NOTE 2

CI = 35 pF

NOTE 4

TDTD

TDTI

2600

20

3600

THRD

TPCK

TSRD

TWDC

TWRC

TWRE

TWRS

TWTC

TWCO

RxC/TxC Clock Period

RxD Setup

95

1000

30

RxDC High Width

RxC High/Low Width

TxRET High Width

RESET Low Width

TxC High/Low Width

COLL Width

800

45

800

10,000

45

200

NOTES:

1. For frame reception with Shortframe or CRC Error. If frame reception is terminated due to Overflow, RxDC will be issued within 1.2 µs of Overflow. If frame

reception is terminated due to non-match of address, RxDC wil be issued within 2.4 µs of the receipt of the last address bit. If Fast Receive Discard Mode

is enabled, the maximum delay of RXDC is 400 ns.

2. Normal frame reception without Overflow. If frame reception is terminated due to Overflow, INT will be issued within 1.2µ of Overflow.

3. For TxRET caused by Collision or 16 Collision condition. If transmission is terminated due to UnderflowTxRET will be issued within 1.2 µs of the Underflow.

4. For INT caused by Collision or 16 Collision condition. If caused by Underflow, INT will be issued within 1.1 µs. If caused by normal termination, INT will

be issued within 200 ns of TxEN going LOW.

5. Italics indicate input requirement, non-italics indicate output timing.

6

Characterized. Not tested.

14

4-14

MD400121/C

80C03

RECEIVE DATA INTERFACE TIMING

R x FIFO (BOTTOM) EMPTY

THRW

TDRY

RxRDY

TWCL

RxRD

TWCL

TDBD

TWCH

TDBR

TDBD

TDBR

TDBS

RxTxD(0 – 7)

RxTxEOF

NOTE 1

TRANSMIT DATA INTERFACE TIMING

T x FIFO (TOP) FULL

TxRDY

TWCL

TxWR

THRW

TWCH

TWCL

RxTxD(0 – 7)

RxTxEOF

TSRT

THDA

TSRT

THDA

COMMAND/STATUS INTERFACE TIMING

TSAR

THAR

A0 – A2, CS

TWCL

RD

TSAR

TWCL

THAR

TWCH

WR

TDBD

TDBR

TWCH

CdSt (0 – 7)

NOTE 1

TSCS

THDA

TDBS

NOTE 1: Bus is driven at this time. However, no valid information present.

41-155

MD400121/C

80C03

SERIAL TRANSMIT INTERFACE TIMING

SERIAL RECEIVE INTERFACE TIMING

TWTC

TWRC

TPCK

TxC

RxC

TDTD

TSRD

TxD

RxD

CSN

THRD

TDTD

TxEN

TWCO

TDRE

TDTD

TDDC

TWDC

COLL

RxDC

INT

TWRE

TDRI

TxRET

TDIC

TDTI

INT

RD

TDIC

RD

16

4-16

MD400121/C

80C03

Ordering Information

D Q 80C03

PACKAGE

TYPE

TEMPERATURE

RANGE

PART TYPE

EDLC

D – CERAMIC DIP

Q – 0°C to +70°C

P – PLASTIC DIP

N – PLCC

Revision History

9/9/96

- Pages 18, 19, Dimension diagrams have been added to this data sheet.

41-177

MD400121/C

80C03

Surface Mount Packages

44-Pin Plastic Leaded Chip Carrier Type N

PIN NO. 1 IDENTIFIER

.500 (12.70)

REF.

.048 (1.22) x 45°

.042 (1.07) x 45°

PIN NO. 1

.695 (17.65)

.685 (17.40)

.500 (12.70)

REF.

.656 (16.66)

.650 (16.51)

.656 (16.66)

.650 (16.51)

.050 (1.27)

BSC

.695 (17.65)

.685 (17.40)

.0103 (.261)

.0097 (.246)

.056 (1.42)

.042 (1.07)

R .045 (1.14)

R .025 (.64)

.021 (0.53)

.013 (0.33)

.630 (16.00)

.590 (14.99)

.112 (2.84)

.100 (2.54)

.020 (0.51) min.

Notes

1. All dimensions are in inches and (millimeters).

.180 (4.57)

.165 (4.19)

2. Dimensions do not include mold flash. Maximum allowable flash is .008 (.20).

3. Formed Leads shall be planar with respect to one another within 0.004 inches.

18

4-18

MD400121/C

80C03

Ceramic Dual-In-Line Packages

40 Lead Hermetic Cerdip Package Type D

2.085 (52.96)

2.035 (51.69)

.600 (15.24)

.510 (12.95)

PIN 1

.090 (2.29) MAX.

.625 (15.88)

.065 (1.65)

.045 (1.14)

.600 (15.24)

(NOTE 3)

.225 (5.72) MAX.

.005 (.13) MIN.

SEATING

PLANE

.150 (3.81)

MIN.

0°/15°

REF.

.012 (.30)

.008 (.20)

.070 (1.78)

.015 (0.38)

PIN 1

SEE NOTE 1

.160 (4.06)

.125 (3.18)

.021 (0.53)

.015 (0.38)

.110 (2.79)

.090 (2.29)

.720 (18.29)

.588 (14.94)

Notes

1. For solder dipped leads, thickness will be .020 max.

2. All dimensions in inches and (millimeters).

3. Dimension is measured from outside shoulder-to-shoulder.

41-199

MD400121/C


型号：	80C03
厂家：	ETC
描述：	80C03 AutoDUPLEX CMOS Ethernet Data Link Controller manual 9/96 80C03自动双面打印CMOS以太网数据链路控制器手册9/96 控制器以太网
文件：	总19页 (文件大小：249K)
中文：	中文翻译
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