821INSTSET [ETC]
MPC821 PowerPC Instruction Set ; MPC821 PowerPC指令集\n
| 型号： | 821INSTSET |
| 厂家： | 
ETC |
| 描述： | MPC821 PowerPC Instruction Set
|
| 文件： | 总186页 (文件大小：703K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPCxxx Instruction Set
This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that
each entry includes the instruction formats and a quick reference ‘legend’ that provides
such information as the level(s) of the PowerPC architecture in which the instruction may
be found—user instruction set architecture (UISA), virtual environment architecture
(VEA), and operating environment architecture (OEA); and the privilege level of the
instruction—user- or supervisor-level (an instruction is assumed to be user-level unless
the legend specifies that it is supervisor-level); and the instruction formats. The format
diagrams show, horizontally, all valid combinations of instruction fields.
Note that the architecture specification refers to user-level and supervisor-level as
problem state and privileged state, respectively.
Instruction Formats
Instructions are four bytes long and word-aligned, so when instruction addresses are
presented to the processor (as in branch instructions) the two low-order bits are ignored.
Similarly, whenever the processor develops an instruction address, its two low-order bits
are zero. Bits 0–5 always specify the primary opcode. Many instructions also have an
extended opcode. The remaining bits of the instruction contain one or more fields for the
different instruction formats.
Some instruction fields are reserved or must contain a predefined value as shown in the
individual instruction layouts. If a reserved field does not have all bits cleared, or if a field
that must contain a particular value does not contain that value, the instruction form is
invalid.
Split-Field Notation
Some instruction fields occupy more than one contiguous sequence of bits or occupy a
contiguous sequence of bits used in permuted order. Such a field is called a split field.
Split fields that represent the concatenation of the sequences from left to right are shown
in lowercase letters. These split fields— spr, and tbr—are described in Table 1.
Table 1. Split-Field Notation and Conventions
Field
Description
spr (11–20)
tbr (11–20)
This field is used to specify a special-purpose register for themtspr and mfspr instructions.
This field is used to specify either the time base lower (TBL) or time base upper (TBU).
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MPCxxx INSTRUCTION SET
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Split fields that represent the concatenation of the sequences in some order, which need
not be left to right (as described for each affected instruction) are shown in uppercase
letters. These split fields—MB, ME, and SH—are described in Table 2.
Instruction Fields
Table 2 describes the instruction fields used in the various instruction formats.
Table 2. Instruction Syntax Conventions
Field
AA (30)
Description
Absolute address bit.
0 The immediate field represents an address relative to the current instruction address (CIA).
The effective (logical) address of the branch is either the sum of the LI field sign-extended to
32 bits and the address of the branch instruction or the sum of the BD field sign-extended to 32
bits and the address of the branch instruction.
1 The immediate field represents an absolute address. The effective address (EA) of the branch
is the LI field sign-extended to 32 bits or the BD field sign-extended to 32 bits.
Note:The LI and BD fields are sign-extended to 32.
BD (16–29)
BI (11–15)
Immediate field specifying a 14-bit signed two's complement branch displacement that is
concatenated on the right with 0b00 and sign-extended to 32 bits.
This field is used to specify a bit in the CR to be used as the condition of a branch conditional
instruction.
BO (6–10)
This field is used to specify options for the branch conditional instructions.
This field is used to specify a bit in the CR to be used as a source.
crbA (11–15)
crbB (16–20)
CRM (12–19)
d (16–31)
This field is used to specify a bit in the CR to be used as a source.
This field mask is used to identify the CR fields that are to be updated by themtcrf instruction.
Immediate field specifying a 16-bit signed two's complement integer that is sign-extended to 32
bits.
frC (21–25)
frD (6–10)
frS (6–10)
IMM (16–19)
LI (6–29)
NOT USED BY MPCxxx.
NOT USED BY MPCxxx.
NOT USED BY MPCxxx.
NOT USED BY MPCxxx.
Immediate field specifying a 24-bit signed two's complement integer that is concatenated on the
right with 0b00 and sign-extended to 32 bits.
LK (31)
Link bit.
0 Does not update the link register (LR).
1 Updates the LR. If the instruction is a branch instruction, the address of the instruction
following the branch instruction is placed into the LR.
MB (21–25) and
ME (26–30)
These fields are used in rotate instructions to specify a 32-bit mask.
NB (16–20)
OE (21)
This field is used to specify the number of bytes to move in an immediate string load or store.
This field is used for extended arithmetic to enable setting OV and SO in the XER.
Primary opcode field
OPCD (0–5)
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Table 2. Instruction Syntax Conventions (Continued)
Field
Description
rA (11–15)
rB (16–20)
Rc (31)
This field is used to specify a GPR to be used as a source or destination.
This field is used to specify a GPR to be used as a source.
Record bit.
0 Does not update the condition register (CR).
1 Updates the CR to reflect the result of the operation.
For integer instructions, CR bits 0–2 are set to reflect the result as a signed quantity and CR bit
3 receives a copy of the summary overflow bit, XER[SO].The result as an unsigned quantity or
a bit string can be deduced from the EQ bit.
(Note that exceptions are referred to as interrupts in the architecture specification.)
rD (6–10)
This field is used to specify a GPR to be used as a destination.
This field is used to specify a GPR to be used as a source.
This field is used to specify a shift amount.
rS (6–10)
SH (16–20)
SIMM (16–31)
TO (6–10)
This immediate field is used to specify a 16-bit signed integer.
This field is used to specify the conditions on which to trap.
This immediate field is used to specify a 16-bit unsigned integer.
Extended opcode field.
UIMM (16–31)
XO (21–30,
22–30, 26–30)
Notation and Conventions
The operation of some instructions is described by a semiformal language (pseudocode).
See Table 3 for a list of pseudocode notation and conventions used throughout this
chapter.
Table 3. Notation and Conventions
Notation/Convention
Meaning
Assignment
←
←iea
Assignment of an instruction effective address.
NOT logical operator
¬
Multiplication
÷
Division (yielding quotient)
+
Two’s-complement addition
–
Two’s-complement subtraction, unary minus
Equals and Not Equals relations
Signed comparison relations
=, ≠
<, ≤, >, ≥
. (period)
Update. When used as a character of an instruction mnemonic, a period (.) means that
the instruction updates the condition register field.
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MPCxxx INSTRUCTION SET
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Table 3. Notation and Conventions (Continued)
Notation/Convention
Meaning
c
Carry. When used as a character of an instruction mnemonic, a ‘c’ indicates a carry out
in XER[CA].
e
o
Extended Precision.
When used as the last character of an instruction mnemonic, an ‘e’ indicates the use of
XER[CA] as an operand in the instruction and records a carry out in XER[CA].
Overflow. When used as a character of an instruction mnemonic, an ‘o’ indicates the
record of an overflow in XER[OV] and CR0[SO] for integer instructions.
<U, >U
Unsigned comparison relations
Unordered comparison relation
AND, OR logical operators
?
&, |
||
Used to describe the concatenation of two values (that is, 010 || 111 is the same as
010111)
, ≡
Exclusive-OR, Equivalence logical operators (for example, (a ≡ b) = (a
¬ b))
0bnnnn
0xnnnn
(n)x
A number expressed in binary format.
A number expressed in hexadecimal format.
The replication of x, n times (that is, x concatenated to itself n – 1 times).
(n)0 and (n)1 are special cases. A description of the special cases follows:
• (n)0 means a field of n bits with each bit equal to 0. Thus (5)0 is equivalent to
0b00000.
• (n)1 means a field of n bits with each bit equal to 1. Thus (5)1 is equivalent to
0b11111.
(rA|0)
(rX)
The contents of rA if the rA field has the value 1–31, or the value 0 if the rA field is 0.
The contents of rX
x[n]
n is a bit or field within x, where x is a register
x is raised to the nth power
n
x
ABS(x)
Absolute value of x
CEIL(x)
Least integer ≥ x
Characterization
CIA
Reference to the setting of status bits in a standard way that is explained in the text.
Current instruction address.
The 32-bit address of the instruction being described by a sequence of pseudocode.
Used by relative branches to set the next instruction address (NIA) and by branch
instructions with LK = 1 to set the link register. Does not correspond to any architected
register.
Clear
Clear the leftmost or rightmost n bits of a register to 0. This operation is used for rotate
and shift instructions.
Clear left and shift left
Clear the leftmost b bits of a register, then shift the register left by n bits. This operation
can be used to scale a known non-negative array index by the width of an element.
These operations are used for rotate and shift instructions.
Cleared
Bits are set to 0.
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Table 3. Notation and Conventions (Continued)
Notation/Convention
Do
Meaning
Do loop.
• Indenting shows range.
• “To” and/or “by” clauses specify incrementing an iteration variable.
• “While” clauses give termination conditions.
Extract
Select a field of n bits starting at bit position b in the source register, right or left justify
this field in the target register, and clear all other bits of the target register to zero. This
operation is used for rotate and shift instructions.
EXTS(x)
GPR(x)
Result of extending x on the left with sign bits
General-purpose register x
if...then...else...
Insert
Conditional execution, indenting shows range, else is optional.
Select a field of n bits in the source register, insert this field starting at bit positionb of
the target register, and leave other bits of the target register unchanged. (Nosimplified
mnemonic is provided for insertion of a field when operating on double words; such an
insertion requires more than one instruction.) This operation is used for rotate and shift
instructions. (Note that simplified mnemonics are referred to as extended mnemonics in
the architecture specification.)
Leave
Leave innermost do loop, or the do loop described in leave statement.
Mask having ones in positions x through y (wrapping if x > y) and zeros elsewhere.
Contents of y bytes of memory starting at address x.
MASK(x, y)
MEM(x, y)
NIA
Next instruction address, which is the 32-bit address of the next instruction to be
executed (the branch destination) after a successful branch. In pseudocode, a
successful branch is indicated by assigning a value to NIA. For instructions which do not
branch, the next instruction address is CIA + 4. Does not correspond to any architected
register.
OEA
PowerPC operating environment architecture
Rotate
Rotate the contents of a register right or left n bits without masking. This operation is
used for rotate and shift instructions.
Set
Bits are set to 1.
Shift
Shift the contents of a register right or left n bits, clearing vacated bits (logical shift).This
operation is used for rotate and shift instructions.
SPR(x)
TRAP
Special-purpose register x
Invoke the system trap handler.
Undefined
An undefined value. The value may vary from one implementation to another, and from
one execution to another on the same implementation.
UISA
VEA
PowerPC user instruction set architecture
PowerPC virtual environment architecture
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MPCxxx INSTRUCTION SET
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Table 4 describes instruction field notation conventions used throughout this document.
Table 4. Instruction Field Conventions
The Architecture
Equivalent to:
Specification
BA, BB, BT
crbA, crbB, crbD (respectively)
D
d
DS
ds
FXM
CRM
RA, RB, RT, RS
rA, rB, rD, rS (respectively)
SI
SIMM
U
IMM
UI
UIMM
/, //, ///
0...0 (shaded)
Precedence rules for pseudocode operators are summarized in Table 5.
Table 5. Precedence Rules
Operators
Associativity
x[n], function evaluation
Left to right
Right to left
(n)x or replication,
x(n) or exponentiation
unary –, ¬
Right to left
Left to right
Left to right
Left to right
Left to right
Left to right
Left to right
None
, ÷
+, –
||
=, ≠, <, ≤, >, ≥, <U, >U, ?
&, , ≡
|
– (range)
←, ←iea
None
Operators higher in Table 5 are applied before those lower in the table. Operators at the
same level in the table associate from left to right, from right to left, or not at all, as shown.
For example, “–” (unary minus) associates from left to right, so a – b – c = (a – b) – c.
Parentheses are used to override the evaluation order implied by Table 5, or to increase
clarity; parenthesized expressions are evaluated before serving as operands.
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MPCxxx INSTRUCTION SET
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MPCxxx Instruction Set
The remainder of this chapter lists and describes the instruction set for the MPCxxx. The
instructions are listed in alphabetical order by mnemonic. Figure 1 shows the format for
each instruction description page.
Instruction name
Instruction syntax
addx
addx
Add
add
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
add.
addo
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
addo.
]
Instruction encoding
31
D
A
B
OE
20 21 22
266
Rc
30 31
0
5
6
10 11
15 16
Pseudocode description of
instruction operation
rD← (rA) + (rB)
The sum (rA) + (rB) is placed into rD.
Text description of
instruction operation
Registers altered by instruction
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
XER:
•
Affected: SO, OV(if OE = 1)
PowerPC Architecture Level SupervisorLevel
UISA
64-Bit
Optional
Form
XO
Quick reference legend
Instruction Description
Note that the execution unit that executes the instruction may not be the same for all
PowerPC processors.
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MPCxxx INSTRUCTION SET
7
addx
addx
Add
add
rD,rA,rB (OE = 0 Rc = 0)
rD,rA,rB (OE = 0 Rc = 1)
rD,rA,rB (OE = 1 Rc = 0)
rD,rA,rB (OE = 1 Rc = 1)
add.
addo
addo.
31
D
A
B
OE
266
Rc
0
5 6
rD← (rA) + (rB)
10 11
15 16
20 21 22
30 31
The sum (rA) + (rB) is placed into rD.
The add instruction is preferred for addition because it sets few status bits.
Other registers altered:
•
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
XER:
Affected: SO, OV
(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
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MPCxxx INSTRUCTION SET
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addcx
addcx
Add Carrying
addc
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
addc.
addco
addco.
31
D
A
B
OE
10
Rc
0
5 6
10 11
15 16
20 21 22
30 31
rD ¨ (rA) + (rB)
The sum (rA) + (rB) is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV
(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
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MPCxxx INSTRUCTION SET
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addex
addex
Add Extended
adde
rD,rA,rB (OE = 0 Rc = 0)
rD,rA,rB (OE = 0 Rc = 1)
rD,rA,rB (OE = 1 Rc = 0)
rD,rA,rB (OE = 1 Rc = 1)
adde.
addeo
addeo.
31
D
A
B
OE
138
Rc
0
5 6
10 11
15 16
20 21 22
30 31
rD ¨ (rA) + (rB) + XER[CA]
The sum (rA) + (rB) + XER[CA] is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV
(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
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MPCxxx INSTRUCTION SET
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addi
addi
Add Immediate
addi
rD,rA,SIMM
14
D
A
SIMM
0
5 6
10 11
15 16
31
if rA = 0 then rD ¨ EXTS(SIMM)
else rD ¨ rA + EXTS(SIMM)
The sum (rA|0) + SIMM is placed into rD.
The addi instruction is preferred for addition because it sets few status bits. Note that addi
uses the value 0, not the contents of GPR0, if rA = 0.
Other registers altered:
•
None
Simplified mnemonics:
li
la
rD,value
rD,disp(rA)
equivalent to
equivalent to
equivalent to
addi rD,0,value
addi rD,rA,disp
addi rD,rA,–value
subi rD,rA,value
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
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MPCxxx INSTRUCTION SET
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addic
addic
Add Immediate Carrying
addic
rD,rA,SIMM
12
D
A
SIMM
0
5 6
10 11
15 16
31
rD ¨ (rA) + EXTS(SIMM)
The sum (rA) + SIMM is placed into rD.
Other registers altered:
•
XER:
Affected: CA
Simplified mnemonics:
subic rD,rA,value
equivalent to
addic rD,rA,–value
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
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MPCxxx INSTRUCTION SET
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addic.
addic.
Add Immediate Carrying and Record
addic.
rD,rA,SIMM
13
D
A
SIMM
0
5 6
10 11
15 16
31
rD ¨ (rA) + EXTS(SIMM)
The sum (rA) + SIMM is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Simplified mnemonics:
subic.rD,rA,value
equivalent to
addic.rD,rA,–value
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
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MPCxxx INSTRUCTION SET
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addis
addis
Add Immediate Shifted
addis
rD,rA,SIMM
15
D
A
SIMM
0
5 6
10 11
15 16
31
if rA = 0 then rD ¨ EXTS(SIMM || (16)0)
else rD ¨ (rA) + EXTS(SIMM || (16)0)
The sum (rA|0) + (SIMM || 0x0000) is placed into rD.
The addis instruction is preferred for addition because it sets few status bits. Note that
addis uses the value 0, not the contents of GPR0, if rA = 0.
Other registers altered:
•
None
Simplified mnemonics:
lis rD,value
equivalent to
equivalent to
addis rD,0,value
addis rD,rA,–value
subis rD,rA,value
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
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addmex
addmex
Add to Minus One Extended
addme
rD,rA
rD,rA
rD,rA
rD,rA
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
addme.
addmeo
addmeo.
Reserved
31
D
A
0 0 0 0 0
15 16
OE
234
Rc
0
5 6
10 11
20 21 22
30 31
rD ¨ (rA) + XER[CA] – 1
The sum (rA) + XER[CA] + 0xFFFF_FFFF_FFFF_FFFF is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV
(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
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MPCxxx INSTRUCTION SET
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addzex
addzex
Add to Zero Extended
addze
rD,rA
rD,rA
rD,rA
rD,rA
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
addze.
addzeo
addzeo.
Reserved
31
D
A
0 0 0 0 0
15 16
OE
202
Rc
0
5 6
10 11
20 21 22
30 31
rD ¨ (rA) + XER[CA]
The sum (rA) + XER[CA] is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV
(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
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MPCxxx INSTRUCTION SET
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andx
andx
AND
and
and.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
28
Rc
0
5 6
rA← (rS) & (rB)
10 11
15 16
20 21
30 31
The contents of rS are ANDed with the contents of rB and the result is placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
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MPCxxx INSTRUCTION SET
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andcx
andcx
AND with Complement
andc
andc.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
60
Rc
0
5 6
rA← (rS) + ¬ (rB)
10 11
15 16
20 21
30 31
The contents of rS are ANDed with the one’s complement of the contents of rB and the
result is placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
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MPCxxx INSTRUCTION SET
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andi.
andi.
AND Immediate
andi.
rA,rS,UIMM
28
S
A
UIMM
0
5 6
10 11
15 16
31
rA← (rS) & ((16)0 || UIMM)
The contents of rS are ANDed with 0x0000 || UIMM and the result is placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
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MPCxxx INSTRUCTION SET
19
andis.
andis.
AND Immediate Shifted
andis.
rA,rS,UIMM
29
S
A
UIMM
0
5 6
10 11
15 16
31
rA← (rS) + (UIMM || (16)0)
The contents of rS are ANDed with UIMM || 0x0000 and the result is placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
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MPCxxx INSTRUCTION SET
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bx
bx
Branch
b
ba
bl
target_addr
target_addr
target_addr
target_addr
(AA = 0 LK = 0)
(AA = 1 LK = 0)
(AA = 0 LK = 1)
(AA = 1 LK = 1)
bla
18
LI
AA LK
0
5 6
29 30 31
if AA then NIA←iea EXTS(LI || 0b00)
else NIA←iea CIA + EXTS(LI || 0b00)
if LK then LR←iea CIA + 4
target_addr specifies the branch target address.
If AA = 0, then the branch target address is the sum of LI || 0b00 sign-extended and the
address of this instruction. If AA = 1, then the branch target address is the value LI || 0b00
sign-extended. If LK = 1, then the effective address of the instruction following the branch
instruction is placed into the link register.
Other registers altered:
Affected: Link Register (LR)
(if LK = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
I
Motorola
MPCxxx INSTRUCTION SET
21
bcx
bcx
Branch Conditional
bc
bca
bcl
BO,BI,target_addr
(AA = 0 LK = 0)
(AA = 1 LK = 0)
(AA = 0 LK = 1)
(AA = 1 LK = 1)
BO,BI,target_addr
BO,BI,target_addr
BO,BI,target_addr
bcla
16
BO
BI
BD
AA LK
0
5 6
10 11
15 16
29 30 31
m ← 32
if ¬ BO[2] then CTR ← CTR – 1
ctr_ok ← BO[2] | (BO[3])
cond_ok ← BO[0] | (CR[BI] ≡ BO[1])
if ctr_ok & cond_ok then
if AA then NIA ←iea EXTS(BD || 0b00)
else NIA ←iea CIA + EXTS(BD || 0b00)
if LK then LR ←iea CIA + 4
The BI field specifies the bit in the condition register (CR) to be used as the condition of
the branch. The BO field is encoded as described in Table 6.
Table 6. BO Operand Encodings
BO
Description
0000y
0001y
001zy
0100y
0101y
011zy
1z00y
1z01y
1z1zz
Decrement the count register (CTR), then branch if the condition is FALSE.
Decrement the CTR, then branch if the condition is FALSE.
Branch if the condition is FALSE.
Decrement the CTR, then branch if the condition is TRUE.
Decrement the CTR, then branch if the condition is TRUE.
Branch if the condition is TRUE.
Decrement the CTR, then branch if the decremented CTR ≠ 0.
Decrement the CTR, then branch if the decremented CTR = 0.
Branch always.
In this table, z indicates a bit that is ignored.
Note that the z bits should be cleared, as they may be assigned a meaning in some future
version of the MPCxxx.
The y bit provides a hint about whether a conditional branch is likely to be taken.
target_addr specifies the branch target address.
22
MPCxxx INSTRUCTION SET
Motorola
If AA = 0, the branch target address is the sum of BD || 0b00 sign-extended and the
address of this instruction. If AA = 1, the branch target address is the value BD || 0b00
sign-extended. If LK = 1, the effective address of the instruction following the branch
instruction is placed into the link register.
Other registers altered:
Affected: Count Register (CTR)
Affected: Link Register (LR)
(if BO[2] = 0)
(if LK = 1)
Simplified mnemonics:
blt target
bne cr2,target
bdnz target
equivalent to
equivalent to
equivalent to
bc
bc
bc
12,0,target
4,10,target
16,0,target
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
B
Motorola
MPCxxx INSTRUCTION SET
23
bcctrx
bcctrx
Branch Conditional to Count Register
bcctr
bcctrl
BO,BI
BO,BI
(LK = 0)
(LK = 1)
Reserved
19
BO
BI
0 0 0 0 0
528
LK
0
5 6
10 11
15 16
20 21
30 31
cond_ok ← BO[0] | (CR[BI] ≡ BO[1])
if cond_ok then
NIA ←iea CTR || 0b00
if LK then LR ←iea CIA + 4
The BI field specifies the bit in the condition register to be used as the condition of the
branch. The BO field is encoded as described in Table 7.
Table 7. BO Operand Encodings
BO
Description
0000y
0001y
001zy
0100y
0101y
011zy
1z00y
1z01y
1z1zz
Decrement the count register (CTR), then branch if the condition is FALSE.
Decrement the CTR, then branch if the condition is FALSE.
Branch if the condition is FALSE.
Decrement the CTR, then branch if the condition is TRUE.
Decrement the CTR, then branch if the condition is TRUE.
Branch if the condition is TRUE.
Decrement the CTR, then branch if the decremented CTR ≠ 0.
Decrement the CTR, then branch if the decremented CTR = 0.
Branch always.
In this table, z indicates a bit that is ignored.
Note that the z bits should be cleared, as they may be assigned a meaning in some future
version of the MPCxxx.
The y bit provides a hint about whether a conditional branch is likely to be taken.
The branch target address is CTR || 0b00.
If LK = 1, the effective address of the instruction following the branch instruction is placed
into the link register.
If the “decrement and test CTR” option is specified (BO[2] = 0), the instruction form is
invalid.
24
MPCxxx INSTRUCTION SET
Motorola
Other registers altered:
Affected: Link Register (LR)
(if LK = 1)
Simplified mnemonics:
bltctr
bnectr cr2
equivalent to
equivalent to
bcctr 12,0
bcctr 4,10
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
Motorola
MPCxxx INSTRUCTION SET
25
bclrx
bclrx
Branch Conditional to Link Register
bclr
bclrl
BO,BI
BO,BI
(LK = 0)
(LK = 1)
Reserved
19
BO
BI
0 0 0 0 0
16
LK
0
5 6
10 11
15 16
20 21
30 31
m ← 32
if ¬ BO[2] then CTR ← CTR – 1
ctr_ok ← BO[2] | ((CTR ≠ 0)
BO[3])
cond_ok ← BO[0] | (CR[BI] ≡ BO[1])
if ctr_ok & cond_ok then
NIA ←iea LR || 0b00
if LK then LR ←iea CIA + 4
The BI field specifies the bit in the condition register to be used as the condition of the
branch. The BO field is encoded as described in Table 8.
Table 8. BO Operand Encodings
BO
Description
0000y
0001y
001zy
0100y
0101y
011zy
1z00y
1z01y
1z1zz
Decrement the CTR, then branch if the condition is FALSE.
Decrement the CTR, then branch if the condition is FALSE.
Branch if the condition is FALSE.
Decrement the CTR, then branch if the condition is TRUE.
Decrement the CTR, then branch if the condition is TRUE.
Branch if the condition is TRUE.
Decrement the CTR, then branch if the decremented CTR ≠ 0.
Decrement the CTR, then branch if the decremented CTR = 0.
Branch always.
In this table, z indicates a bit that is ignored.
Note that the z bits should be cleared, as they may be assigned a meaning in some future version of the
MPCxxx.
The y bit provides a hint about whether a conditional branch is likely to be taken.
The branch target address is LR[0-29] || 0b00.
If LK = 1, then the effective address of the instruction following the branch instruction is
placed into the link register.
26
MPCxxx INSTRUCTION SET
Motorola
Other registers altered:
Affected: Count Register (CTR)
Affected: Link Register (LR)
Simplified mnemonics:
(if BO[2] = 0)
(if LK = 1)
bltlr
bnelr cr2
bdnzlr
equivalent to
equivalent to
equivalent to
bclr 12,0
bclr 4,10
bclr 16,0
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
Motorola
MPCxxx INSTRUCTION SET
27
cmp
cmp
Compare
cmp
crfD,L,rA,rB
Reserved
31
crfD
0
L
A
B
0 0 0 0 0 0 0 0 0 0
0
0
5 6
8 9 10 11
15 16
20 21
30 31
a ← EXTS(rA)
b ← EXTS(rB)
ifa < b then c ← 0b100
else if a > b then c ← 0b010
else c ← 0b001
CR[4 crfD–4 crfD + 3] ← c || XER[SO]
The contents of rA are compared with the contents of rB treating the operands as signed
integers. The result of the comparison is placed into CR field crfD.
Other registers altered:
•
Condition Register (CR field specified by operand crfD):
Affected: LT, GT, EQ, SO
Simplified mnemonics:
cmpd rA,rB
cmpw cr3,rA,rB
equivalent to
equivalent to
cmp 0,1,rA,rB
cmp 3,0,rA,rB
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
28
MPCxxx INSTRUCTION SET
Motorola
cmpi
cmpi
Compare Immediate
cmpi
crfD,L,rA,SIMM
Reserved
31
11
crfD
0
L
A
SIMM
0
5 6
8 9 10 11
15 16
a← (rA)
ifa < EXTS(SIMM) then c ← 0b100
else if a > EXTS(SIMM) then c ← 0b010
else c ← 0b001
CR[4 crfD–4 crfD + 3] ← c || XER[SO]
The contents of rA are compared with the sign-extended value of the SIMM field, treating
the operands as signed integers.The result of the comparison is placed into CR field crfD.
Other registers altered:
•
Condition Register (CR field specified by operand crfD):
Affected: LT, GT, EQ, SO
Simplified mnemonics:
cmpdirA,value
cmpwi cr3,rA,value
equivalent to
equivalent to
cmpi 0,1,rA,value
cmpi 3,0,rA,value
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
29
cmpl
cmpl
Compare Logical
cmpl
crfD,L,rA,rB
Reserved
31
crfD
0
L
A
B
32
0
0
5 6
8 9 10 11
15 16
20 21
31
a ← rA
b← rB
ifa <U b then c ← 0b100
else if a >U b then c ← 0b010
else c ← 0b001
CR[4 crfD–4 crfD + 3] ← c || XER[SO]
The contents of rA are compared with the contents of rB, treating the operands as
unsigned integers. The result of the comparison is placed into CR field crfD.
Other registers altered:
•
Condition Register (CR field specified by operand crfD):
Affected: LT, GT, EQ, SO
Simplified mnemonics:
cmpldrA,rB
cmplw cr3,rA,rB
equivalent to
equivalent to
cmpl 0,1,rA,rB
cmpl 3,0,rA,rB
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
30
MPCxxx INSTRUCTION SET
Motorola
cmpli
cmpli
Compare Logical Immediate
cmpli
crfD,L,rA,UIMM
Reserved
31
10
crfD
0
L
A
UIMM
0
5 6
8 9 10 11
15 16
a ← (rA)
ifa <U ((16)0 || UIMM) then c ← 0b100
else if a >U ((16)0 || UIMM) then c ← 0b010
else c ← 0b001
CR[4 crfD–4 crfD + 3] ← c || XER[SO]
The contents of rA are compared with 0x0000|| UIMM, treating the operands as unsigned
integers. The result of the comparison is placed into CR field crfD.
Other registers altered:
•
Condition Register (CR field specified by operand crfD):
Affected: LT, GT, EQ, SO
Simplified mnemonics:
cmpldir A,value
cmplwi cr3,rA,value
equivalent to
equivalent to
cmpli 0,1,rA,value
cmpli 3,0,rA,value
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
31
cntlzwx
cntlzwx
Count Leading Zeros Word
cntlzw
cntlzw.
rA,rS
rA,rS
(Rc = 0)
(Rc = 1)
Reserved
31
S
A
0 0 0 0 0
26
Rc
0
5 6
10 11
15 16
20 21
30 31
n ← 0
do while n < 32
if rS[n] = 1 then leave
n ← n + 1
rA ← n
A count of the number of consecutive zero bits starting at bit 0 of rS is placed into rA.This
number ranges from 0 to 32, inclusive.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
Note: If Rc = 1, then LT is cleared in the CR0 field.
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
32
MPCxxx INSTRUCTION SET
Motorola
crand
crand
Condition Register AND
crand
crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
257
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← CR[crbA] & CR[crbB]
The bit in the condition register specified by crbA is ANDed with the bit in the condition
register specified by crbB. The result is placed into the condition register bit specified by
crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by operand crbD
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
Motorola
MPCxxx INSTRUCTION SET
33
crandc
crandc
Condition Register AND with Complement
crandc crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
129
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← CR[crbA] & ¬ CR[crbB]
The bit in the condition register specified by crbA is ANDed with the complement of the
bit in the condition register specified by crbB and the result is placed into the condition
register bit specified by crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by operand crbD
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
34
MPCxxx INSTRUCTION SET
Motorola
creqv
creqv
Condition Register Equivalent
creqv
crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
289
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← CR[crbA] ≡ CR[crbB]
The bit in the condition register specified by crbA is XORed with the bit in the condition
register specified by crbB and the complemented result is placed into the condition
register bit specified by crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by operand crbD
Simplified mnemonics:
crset crbD
equivalent to
creqv crbD,crbD,crbD
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
Motorola
MPCxxx INSTRUCTION SET
35
crnand
crnand
Condition Register NAND
crnand crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
225
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← ¬ (CR[crbA] & CR[crbB])
The bit in the condition register specified by crbA is ANDed with the bit in the condition
register specified by crbB and the complemented result is placed into the condition
register bit specified by crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by operand crbD
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
36
MPCxxx INSTRUCTION SET
Motorola
crnor
crnor
Condition Register NOR
crnor
crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
33
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← ¬ (CR[crbA] | CR[crbB])
The bit in the condition register specified by crbA is ORed with the bit in the condition
register specified by crbB and the complemented result is placed into the condition
register bit specified by crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by operand crbD
Simplified mnemonics:
crnot crbD,crbA
equivalent to
crnor crbD,crbA,crbA
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
Motorola
MPCxxx INSTRUCTION SET
37
cror
cror
Condition Register OR
cror
crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
449
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← CR[crbA] | CR[crbB]
The bit in the condition register specified by crbA is ORed with the bit in the condition
register specified by crbB. The result is placed into the condition register bit specified by
crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by operand crbD
Simplified mnemonics:
crmove crbD,crbA
equivalent to
cror crbD,crbA,crbA
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
38
MPCxxx INSTRUCTION SET
Motorola
crorc
crorc
Condition Register OR with Complement
crorc
crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
417
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← CR[crbA] | ¬ CR[crbB]
The bit in the condition register specified by crbA is ORed with the complement of the
condition register bit specified by crbB and the result is placed into the condition register
bit specified by crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by operand crbD
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
Motorola
MPCxxx INSTRUCTION SET
39
crxor
crxor
Condition Register XOR
crxor
crbD,crbA,crbB
Reserved
19
crbD
crbA
crbB
193
0
0
5 6
10 11
15 16
20 21
30 31
CR[crbD] ← CR[crbA]
CR[crbB]
The bit in the condition register specified by crbA is XORed with the bit in the condition
register specified by crbB and the result is placed into the condition register specified by
crbD.
Other registers altered:
•
Condition Register:
Affected: Bit specified by crbD
Simplified mnemonics:
crclr crbD
equivalent to
crxor crbD,crbD,crbD
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
40
MPCxxx INSTRUCTION SET
Motorola
dcbf
dcbf
Data Cache Block Flush
dcbf
rA,rB
Reserved
31
0 0 0 0 0
A
B
86
0
0
5 6
10 11
15 16
20 21
30 31
EA is the sum (rA|0) + (rB).
The dcbf instruction invalidates the block in the data cache addressed by EA, copying the
block to memory first, if there is any dirty data in it. If the processor is a multiprocessor
implementation and the block is marked coherency-required, the processor will, if
necessary, send an address-only broadcast to other processors. The broadcast of the
dcbf instruction causes another processor to copy the block to memory, if it has dirty data,
and then invalidate the block from the cache.
The action taken depends on the memory mode associated with the block containing the
byte addressed by EA and on the state of that block. The list below describes the action
taken for the various states of the memory coherency attribute (M bit).
•
Coherency required
— Unmodified block—Invalidates copies of the block in the data caches of all
processors.
— Modified block—Copies the block to memory. Invalidates copies of the block in
the data caches of all processors.
— Absent block—If modified copies of the block are in the data caches of other
processors, causes them to be copied to memory and invalidated in those data
caches.If unmodified copies are in the data caches of other processors, causes
those copies to be invalidated in those data caches.
•
Coherency not required
— Unmodified block—Invalidates the block in the processor’s data cache.
— Modified block—Copies the block to memory. Invalidates the block in the
processor’s data cache.
— Absent block (target block not in cache)—No action is taken.
The function of this instruction is independent of the write-through, write-back and
caching-inhibited/allowed modes of the block containing the byte addressed by EA.
Motorola
MPCxxx INSTRUCTION SET
41
This instruction may be treated as a load from the addressed byte with respect to address
translation and memory protection. It may also be treated as a load for referenced and
changed bit recording except that referenced and changed bit recording may not occur.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
42
MPCxxx INSTRUCTION SET
Motorola
dcbi
dcbi
Data Cache Block Invalidate
dcbi
rA,rB
Reserved
31
0 0 0 0 0
A
B
470
0
0
5 6
10 11
15 16
20 21
30 31
EA is the sum (rA|0) + (rB).
The action taken is dependent on the memory mode associated with the block containing
the byte addressed by EA and on the state of that block. The list below describes the
action taken if the block containing the byte addressed by EA is or is not in the cache.
•
Coherency required
— Unmodified block—Invalidates copies of the block in the data caches of all
processors.
— Modified block—Invalidates copies of the block in the data caches of all
processors. (Discards the modified contents.)
— Absent block—If copies of the block are in the data caches of any other
processor, causes the copies to be invalidated in those data caches. (Discards
any modified contents.)
•
Coherency not required
— Unmodified block—Invalidates the block in the processor’s data cache.
— Modified block—Invalidates the block in the processor’s data cache. (Discards
the modified contents.)
— Absent block (target block not in cache)—No action is taken.
When data address translation is enabled, MSR[DR] = 1, and the virtual address has no
translation, a DSI exception occurs. The function of this instruction is independent of the
write-through and caching-inhibited/allowed modes of the block containing the byte
addressed by EA. This instruction operates as a store to the addressed byte with respect
to address translation and protection. The referenced and changed bits are modified
appropriately. This is a supervisor-level instruction.
Other registers altered:
•
None
PowerPC Architecture Level
OEA
Supervisor Level
Optional
Form
X
√
Motorola
MPCxxx INSTRUCTION SET
43
dcbst
dcbst
Data Cache Block Store
dcbst
rA,rB
Reserved
31
0 0 0 0 0
A
B
54
0
0
5 6
10 11
15 16
20 21
30 31
EA is the sum (rA|0) + (rB).
The dcbst instruction executes as follows:
•
If the block containing the byte addressed by EA is in coherency-required mode,
and a block containing the byte addressed by EA is in the data cache of any
processor and has been modified, the writing of it to main memory is initiated.
•
If the block containing the byte addressed by EA is in coherency-not-required
mode, and a block containing the byte addressed by EA is in the data cache of this
processor and has been modified, the writing of it to main memory is initiated.
The function of this instruction is independent of the write-through and caching-
inhibited/allowed modes of the block containing the byte addressed by EA.The processor
treats this instruction as a load from the addressed byte with respect to address
translation and memory protection. It may also be treated as a load for referenced and
changed bit recording except that referenced and changed bit recording may not occur.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
44
MPCxxx INSTRUCTION SET
Motorola
dcbt
dcbt
Data Cache Block Touch
dcbt
rA,rB
Reserved
31
0 0 0 0 0
A
B
278
0
0
5 6
10 11
15 16
20 21
30 31
EA is the sum (rA|0) + (rB).
This instruction is a hint that performance will probably be improved if the block containing
the byte addressed by EA is fetched into the data cache, because the program will
probably soon load from the addressed byte. The hint is ignored if the block is caching-
inhibited. Executing dcbt does not cause the system alignment error handler to be
invoked.
This instruction may be treated as a load from the addressed byte with respect to address
translation, memory protection, and reference and change recording, except that no
exception occurs in the case of a translation fault or protection violation.
The program uses the dcbt instruction to request a cache block fetch before it is actually
needed by the program. The program can later execute load instructions to put data into
registers. However, the processor is not obliged to load the addressed block into the data
cache.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
45
dcbtst
dcbtst
Data Cache Block Touch for Store
dcbtst rA,rB
Reserved
31
0 0 0 0 0
A
B
246
0
0
5 6
10 11
15 16
20 21
30 31
EA is the sum (rA|0) + (rB).
This instruction is a hint that performance will be improved if the block containing the byte
addressed by EA is fetched into the data cache, because the program will probably soon
store into the addressed byte. The hint is ignored if the block is caching-inhibited.
Executing dcbtst does not cause the system alignment error handler to be invoked.
This instruction operates as a load from the addressed byte with respect to address
translation and protection, except that no exception occurs in the case of a translation fault
or protection violation. Also, if the referenced and changed bits are recorded, they are
recorded as if the access was a load.
The program uses dcbtst to request a cache block fetch to guarantee that a subsequent
store will be to a cached location. The program can later execute store instructions to put
data into memory. However, the processor is not obliged to load the addressed cache
block into the data cache.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
46
MPCxxx INSTRUCTION SET
Motorola
dcbz
dcbz
Data Cache Block Set to Zero
dcbz
rA,rB
Reserved
31
0 0 0 0 0
A
B
1014
0
0
5 6
10 11
15 16
20 21
30 31
EA is the sum (rA|0) + (rB).
The dcbz instruction executes as follows:
•
If the cache block containing the byte addressed by EA is in the data cache, all
bytes are cleared.
•
If the cache block containing the byte addressed by EA is not in the data cache and
the corresponding page is caching-allowed, the cache block is allocated in the data
cache (without fetching the block from main memory), and all bytes are cleared.
•
•
If the page containing the byte addressed by EA is in caching-inhibited or write-
through mode, either all bytes of main memory that correspond to the addressed
cache block are cleared or the alignment exception handler is invoked. The
exception handler clears all bytes in main memory that corresponds to the
addressed cache block.
If the cache block containing the byte addressed by EA is in coherency-required
mode, and the cache block exists in the data cache(s) of any other processor(s), it
is kept coherent in those caches.
This instruction is treated as a store to the addressed byte with respect to address
translation, memory protection, referenced and changed recording and the ordering
enforced by eieio or by the combination of caching-inhibited and guarded attributes for a
page.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
47
divwx
divwx
Divide Word
divw
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
divw.
divwo
divwo.
31
D
A
B
OE
491
Rc
0
5 6
10 11
15 16
20 21 22
30 31
dividend← (rA)
divisor ← (rB)
rD ← dividend ÷ divisor
The dividend is the contents of rA. The divisor is the contents of rB. The 32-bit quotient is
formed and placed in rD. The remainder is not supplied as a result.
Both the operands and the quotient are interpreted as signed integers.The quotient is the
unique signed integer that satisfies the equation—dividend = (quotient * divisor) + r where
0 ≤ r < |divisor| (if the dividend is non-negative), and –|divisor| < r ≤ 0 (if the dividend is
negative).
If an attempt is made to perform any of the divisions—0x8000_0000 ÷ –1or <anything> ÷
0—then the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits
of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set.
The 32-bit signed remainder of dividing the contents of rA by the contents of rB can be
computed as follows, except in the case that the contents of rA = –231 and the contents
of rB = –1.
divw
mullw
subf
rD,rA,rB
rD,rD,rB
rD,rD,rA
# rD = quotient
# rD = quotient divisor
# rD = remainder
48
MPCxxx INSTRUCTION SET
Motorola
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
XER:
(if Rc = 1)
(if OE = 1)
•
Affected: SO, OV
Note:The setting of the affected bits in the XER is mode-independent, and reflects
overflow of the 32-bit result.
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
Motorola
MPCxxx INSTRUCTION SET
49
divwux
divwux
Divide Word Unsigned
divwu
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
divwu.
divwuo
divwuo.
31
D
A
B
OE
459
Rc
0
5 6
10 11
15 16
20 21 22
30 31
dividend ← (rA)
divisor ← (rB)
rD ← dividend ÷ divisor
The dividend is the contents of rA. The divisor is the contents of rB. A 32-bit quotient is
formed. The 32-bit quotient is placed into rD. The remainder is not supplied as a result.
Both operands and the quotient are interpreted as unsigned integers, except that if Rc =
1 the first three bits of CR0 field are set by signed comparison of the result to zero. The
quotient is the unique unsigned integer that satisfies the equation—dividend = (quotient
divisor) + r (where 0 ≤ r < divisor). If an attempt is made to perform the
division—<anything> ÷ 0—then the contents of rD are undefined as are the contents of
the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = 1 then OV is set.
The 32-bit unsigned remainder of dividing the contents of rA by the contents of rB can be
computed as follows:
divwu
mullw
subf
rD,rA,rB
rD,rD,rB
rD,rD,rA
# rD = quotient
# rD = quotient * divisor
# rD = remainder
50
MPCxxx INSTRUCTION SET
Motorola
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
XER:
(if Rc = 1)
(if OE = 1)
•
Affected: SO, OV
Note:The setting of the affected bits in the XER is mode-independent, and reflects
overflow of the 32-bit result.
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
Motorola
MPCxxx INSTRUCTION SET
51
eciwx
eciwx
External Control In Word Indexed
eciwx
rD,rA,rB
Reserved
31
D
A
B
310
0
0
5 6
10 11
15 16
20 21
30 31
The eciwx instruction allows the system designer to map special devices in an alternative
way. The MMU translation of the EA is not used to select the special device, as it is used
in most instructions such as loads and stores. Rather, it is used as an address operand
that is passed to the device over the address bus. Four other pins (the burst and size pins
on the 60x bus) are used to select the device; these four pins output the 4-bit resource ID
(RID) field that is located in the EAR register. The eciwx instruction also loads a word from
the data bus that is output by the special device.
The eciwx instruction and the EAR register can be very efficient when mapping special
devices such as graphics devices that use addresses as pointers.
if rA = 0 then b ← 0
else b← (rA)
EA ← b + (rB)
paddr ← address translation of EA
send load word request for paddr to device identified by EAR[RID]
rD ← word from device
EA is the sum (rA|0) + (rB).
A load word request for the physical address (referred to as real address in the
architecture specification) corresponding to EA is sent to the device identified by
EAR[RID], bypassing the cache. The word returned by the device is placed in rD. EAR[E]
must be 1. If it is not, a DSI exception is generated.
EA must be a multiple of four. If it is not, one of the following occurs:
•
•
•
A system alignment exception is generated.
A DSI exception is generated (possible only if EAR[E] = 0).
The results are boundedly undefined.
The eciwx instruction is supported for EAs that reference memory segments in which
SR[T] = 1 and for EAs mapped by the DBAT registers. If the EA references a direct-store
segment (SR[T] = 1), either a DSI exception occurs or the results are boundedly
undefined. However, note that the direct-store facility is being phased out of the
architecture and will not likely be supported in future devices. Thus, software should not
depend on its effects.
52
MPCxxx INSTRUCTION SET
Motorola
If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are
boundedly undefined. This instruction is treated as a load from the addressed byte with
respect to address translation, memory protection, referenced and changed bit recording,
and the ordering performed by eieio. This instruction is optional in the PowerPC
architecture.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
√
Motorola
MPCxxx INSTRUCTION SET
53
ecowx
ecowx
External Control Out Word Indexed
ecowx
rS,rA,rB
Reserved
31
S
A
B
438
0
0
5 6
10 11
15 16
20 21
30 31
The ecowx instruction and the EAR register can be very efficient when mapping special
devices such as graphics devices that use addresses as pointers.
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + (rB)
paddr ← address translation of EA
send store word request for paddr to device identified by EAR[RID]
send rS to device
EA is the sum (rA|0) + (rB). A store word request for the physical address corresponding
to EA and the contents of rS are sent to the device identified by EAR[RID], bypassing the
cache. EAR[E] must be 1, if it is not, a DSI exception is generated. EA must be a multiple
of four. If it is not, one of the following occurs:
•
•
•
A system alignment exception is generated.
A DSI exception is generated (possible only if EAR[E] = 0).
The results are boundedly undefined.
The ecowx instruction is supported for effective addresses that reference memory
segments in which SR[T] = 0, and for EAs mapped by the DBAT registers. If the EA
references a direct-store segment (SR[T] = 1), either a DSI exception occurs or the results
are boundedly undefined. However, note that the direct-store facility is being phased out
of the architecture and will not likely be supported in future devices.Thus, software should
not depend on its effects.
If this instruction is executed when MSR[DR] = 0 (real addressing mode), the results are
boundedly undefined. This instruction is treated as a store from the addressed byte with
respect to address translation, memory protection, nd referenced and changed bit
recording, and the ordering performed by eieio.This instruction is optional in the PowerPC
architecture.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
√
54
MPCxxx INSTRUCTION SET
Motorola
eieio
eieio
Enforce In-Order Execution of I/O
Reserved
31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
854
0
0
5 6
10 11
15 16
20 21
30 31
The eieio instruction provides an ordering function for the effects of load and store
instructions executed by a processor. These loads and stores are divided into two sets,
which are ordered separately. The memory accesses caused by a dcbz instruction are
ordered like a store. The two sets follow:
1. Loads and stores to memory that is both caching-inhibited and guarded, and stores
to memory that is write-through required.
The eieio instruction controls the order in which the accesses are performed in
main memory. It ensures that all applicable memory accesses caused by
instructions preceding the eieio instruction have completed with respect to main
memory before any applicable memory accesses caused by instructions following
the eieio instruction access main memory. It acts like a barrier that flows through
the memory queues and to main memory, preventing the reordering of memory
accesses across the barrier. No ordering is performed for dcbz if the instruction
causes the system alignment error handler to be invoked.
All accesses in this set are ordered as a single set—that is, there is not one order
for loads and stores to caching-inhibited and guarded memory and another order
for stores to write-through required memory.
2. Stores to memory that have all of the following attributes—caching-allowed, write-
through not required, and memory-coherency required.
The eieio instruction controls the order in which the accesses are performed with
respect to coherent memory. It ensures that all applicable stores caused by
instructions preceding the eieio instruction have completed with respect to
coherent memory before any applicable stores caused by instructions following the
eieio instruction complete with respect to coherent memory.
With the exception of dcbz, eieio does not affect the order of cache operations (whether
caused explicitly by execution of a cache management instruction, or implicitly by the
cache coherency mechanism).The eieio instruction does not affect the order of accesses
in one set with respect to accesses in the other set.
The eieio instruction may complete before memory accesses caused by instructions
preceding the eieio instruction have been performed with respect to main memory or
coherent memory as appropriate.
The eieio instruction is intended for use in managing shared data structures, in accessing
memory-mapped I/O, and in preventing load/store combining operations in main memory.
For the first use, the shared data structure and the lock that protects it must be altered
only by stores that are in the same set (1 or 2; see previous discussion). For the second
use, eieio can be thought of as placing a barrier into the stream of memory accesses
Motorola
MPCxxx INSTRUCTION SET
55
issued by a processor, such that any given memory access appears to be on the same
side of the barrier to both the processor and the I/O device.
Because the processor performs store operations in order to memory that is designated
as both caching-inhibited and guarded, the eieio instruction is needed for such memory
only when loads must be ordered with respect to stores or with respect to other loads.
Note that the eieio instruction does not connect hardware considerations to it such as
multiprocessor implementations that send an eieio address-only broadcast (useful in
some designs). For example, if a design has an external buffer that re-orders loads and
stores for better bus efficiency, the eieio broadcast signals to that buffer that previous
loads/stores (marked caching-inhibited, guarded, or write-through required) must
complete before any following loads/stores (marked caching-inhibited, guarded, or write-
through required).
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
56
MPCxxx INSTRUCTION SET
Motorola
eqvx
eqvx
Equivalent
eqv
eqv.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
284
Rc
0
5 6
rA ← (rS) ≡ (rB)
10 11
15 16
21 22
30 31
The contents of rS are XORed with the contents of rB and the complemented result is
placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
57
extsbx
extsbx
Extend Sign Byte
extsb
extsb.
rA,rS
rA,rS
(Rc = 0)
(Rc = 1)
Reserved
31
S
A
0 0 0 0 0
954
Rc
0
5 6
10 11
15 16
20 21
30 31
S ← rS[24]
rA[24-31] ← rS[24-31]
rA[0–23] ← (24)S
The contents of rS[24-31] are placed into rA[24-31]. Bit 24 of rS is placed into rA[0-23].
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
58
MPCxxx INSTRUCTION SET
Motorola
extshx
extshx
Extend Sign Half Word
extsh
extsh.
rA,rS
rA,rS
(Rc = 0)
(Rc = 1)
Reserved
31
S
A
0 0 0 0 0
922
Rc
0
5 6
10 11
15 16
20 21
30 31
S ← rS[16]
rA[16-31]← rS[16-31]
rA[0-15] ← (16)S
The contents of rS[16-31] are placed into rA[16-31]. Bit 16 of rS is placed into rA[0–15].
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
59
icbi
icbi
Instruction Cache Block Invalidate
icbi
rA,rB
Reserved
31
0 0 0 0 0
A
B
982
0
0
5 6
10 11
15 16
20 21
30 31
EA is the sum (rA|0) + (rB).
If the block containing the byte addressed by EA is in coherency-required mode, and a
block containing the byte addressed by EA is in the instruction cache of any processor,
the block is made invalid in all such instruction caches, so that subsequent references
cause the block to be refetched.
If the block containing the byte addressed by EA is in coherency-not-required mode, and
a block containing the byte addressed by EA is in the instruction cache of this processor,
the block is made invalid in that instruction cache, so that subsequent references cause
the block to be refetched. The function of this instruction is independent of the write-
through, write-back, and caching-inhibited/allowed modes of the block containing the byte
addressed by EA.
This instruction is treated as a load from the addressed byte with respect to address
translation and memory protection. It may also be treated as a load for referenced and
changed bit recording except that referenced and changed bit recording may not occur.
Implementations with a combined data and instruction cache treat the icbi instruction as
a no-op, except that they may invalidate the target block in the instruction caches of other
processors if the block is in coherency-required mode.
The icbi instruction invalidates the block at EA (rA|0 + rB). If the processor is a
multiprocessor implementation and the block is marked coherency-required, the
processor will send an address-only broadcast to other processors causing those
processors to invalidate the block from their instruction caches.
For faster processing, many implementations will not compare the entire EA (rA|0 + rB)
with the tag in the instruction cache. Instead, they will use the bits in the EA to locate the
set that the block is in, and invalidate all blocks in that set.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
X
60
MPCxxx INSTRUCTION SET
Motorola
isync
isync
Instruction Synchronize
isync
Reserved
19
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
150
0
0
5 6
10 11
15 16
20 21
30 31
The isync instruction provides an ordering function for the effects of all instructions
executed by a processor. Executing an isync instruction ensures that all instructions
preceding the the isync instruction have completed before the isync instruction
completes, except that memory accesses caused by those instructions need not have
been performed with respect to other processors and mechanisms. It also ensures that
no subsequent instructions are initiated by the processor until after the isync instruction
completes. Finally, it causes the processor to discard any prefetched instructions, with the
effect that subsequent instructions will be fetched and executed in the context established
by the instructions preceding the isync instruction. The isync instruction has no effect on
the other processors or on their caches. This instruction is context synchronizing.
Context synchronization is necessary after certain code sequences that perform complex
operations within the processor. These code sequences are usually operating system
tasks that involve memory management. For example, if an instruction “A” changes the
memory translation rules in the memory management unit (MMU), the isync instruction
should be executed so that the instructions following instruction “A” will be discarded from
the pipeline and refetched according to the new translation rules. This instruction is
context synchronizing.
Other registers altered:
•
None
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
XL
Motorola
MPCxxx INSTRUCTION SET
61
lbz
lbz
Load Byte and Zero
lbz
rD,d(rA)
34
D
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + EXTS(d)
rD ← (24)0 || MEM(EA, 1)
EA is the sum (rA|0) + d.The byte in memory addressed by EA is loaded into the low-order
eight bits of rD. The remaining bits in rD are cleared.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
62
MPCxxx INSTRUCTION SET
Motorola
lbzu
lbzu
Load Byte and Zero with Update
lbzu
rD,d(rA)
35
D
A
d
0
5 6
10 11
15 16
31
EA ← (rA) + EXTS(d)
rD← (24)0 || MEM(EA, 1)
rA← EA
EA is the sum (rA) + d.The byte in memory addressed by EA is loaded into the low-order
eight bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0, or
rA = rD, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
63
lbzux
lbzux
Load Byte and Zero with Update Indexed
lbzux
rD,rA,rB
Reserved
31
D
A
B
119
0
0
5 6
10 11
15 16
20 21
30 31
EA ← (rA) + (rB)
rD ← (24)0 || MEM(EA, 1)
rA ← EA
EA is the sum (rA) + (rB). The byte in memory addressed by EA is loaded into the low-
order eight bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0
or rA = rD, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
64
MPCxxx INSTRUCTION SET
Motorola
lbzx
lbzx
Load Byte and Zero Indexed
lbzx
rD,rA,rB
Reserved
31
D
A
B
87
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + (rB)
rD ← (24)0 || MEM(EA, 1)
EA is the sum (rA|0) + (rB). The byte in memory addressed by EA is loaded into the low-
order eight bits of rD. The remaining bits in rD are cleared.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
65
lha
lha
Load Half Word Algebraic
lha
rD,d(rA)
42
D
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + EXTS(d)
rD ← EXTS(MEM(EA, 2))
EA is the sum (rA|0) + d.The half word in memory addressed by EA is loaded into the low-
order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant
bit of the loaded half word.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
66
MPCxxx INSTRUCTION SET
Motorola
lhau
lhau
Load Half Word Algebraic with Update
lhau
rD,d(rA)
43
D
A
d
0
5 6
10 11
15 16
31
EA ← (rA) + EXTS(d)
rD ← EXTS(MEM(EA, 2))
rA ← EA
EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the low-
order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant
bit of the loaded half word. EA is placed into rA. If rA = 0 or rA = rD, the instruction form
is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
67
lhaux
lhaux
Load Half Word Algebraic with Update Indexed
lhaux
rD,rA,rB
Reserved
31
D
A
B
375
0
0
5 6
10 11
15 16
20 21
30 31
EA ← (rA) + (rB)
rD ← EXTS(MEM(EA, 2))
rA ← EA
EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the
low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-
significant bit of the loaded half word. EA is placed into rA. If rA = 0 or rA = rD, the
instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
68
MPCxxx INSTRUCTION SET
Motorola
lhax
lhax
Load Half Word Algebraic Indexed
lhax
rD,rA,rB
Reserved
31
D
A
B
343
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + (rB)
rD ← EXTS(MEM(EA, 2))
EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the
low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-
significant bit of the loaded half word.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
69
lhbrx
lhbrx
Load Half Word Byte-Reverse Indexed
lhbrx
rD,rA,rB
Reserved
31
D
A
B
790
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + (rB)
rD ← (16)0 || MEM(EA + 1, 1) || MEM(EA, 1)
EA is the sum (rA|0) + (rB). Bits 0–7 of the half word in memory addressed by EA are
loaded into the low-order eight bits of rD. Bits 8–15 of the half word in memory addressed
by EA are loaded into the subsequent low-order eight bits of rD. The remaining bits in rD
are cleared.
The PowerPC architecture cautions programmers that some implementations of the
architecture may run the lhbrx instructions with greater latency than other types of load
instructions.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
70
MPCxxx INSTRUCTION SET
Motorola
lhz
lhz
Load Half Word and Zero
lhz
rD,d(rA)
40
D
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b← 0
else b← (rA)
EA← b + EXTS(d)
rD← (16)0 || MEM(EA, 2)
EA is the sum (rA|0) + d.The half word in memory addressed by EA is loaded into the low-
order 16 bits of rD. The remaining bits in rD are cleared.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
71
lhzu
lhzu
Load Half Word and Zero with Update
lhzu
rD,d(rA)
41
D
A
d
0
5 6
10 11
15 16
31
EA ← rA + EXTS(d)
rD← (16)0 || MEM(EA, 2)
rA← EA
EA is the sum (rA) + d. The half word in memory addressed by EA is loaded into the low-
order 16 bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA = 0 or
rA = rD, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
72
MPCxxx INSTRUCTION SET
Motorola
lhzux
lhzux
Load Half Word and Zero with Update Indexed
lhzux
rD,rA,rB
Reserved
31
D
A
B
311
0
0
5 6
10 11
15 16
20 21
30 31
EA ← (rA) + (rB)
rD← (16)0 || MEM(EA, 2)
rA← EA
EA is the sum (rA) + (rB). The half word in memory addressed by EA is loaded into the
low-order 16 bits of rD. The remaining bits in rD are cleared. EA is placed into rA. If rA =
0 or rA = rD, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
73
lhzx
lhzx
Load Half Word and Zero Indexed
lhzx
rD,rA,rB
Reserved
31
D
A
B
279
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
rD← (16)0 || MEM(EA, 2)
EA is the sum (rA|0) + (rB). The half word in memory addressed by EA is loaded into the
low-order 16 bits of rD. The remaining bits in rD are cleared.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
74
MPCxxx INSTRUCTION SET
Motorola
lmw
lmw
Load Multiple Word
lmw
rD,d(rA)
46
D
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b← 0
elseb← (rA)
EA← b + EXTS(d)
r← rD
do while r ≤ 31
GPR(r)← MEM(EA, 4)
r← r + 1
EA← EA + 4
EA is the sum (rA|0) + d. n = (32 – rD). n consecutive words starting at EA are loaded into
GPRs rD through r31.
EA must be a multiple of four. If it is not, either the system alignment exception handler is
invoked or the results are boundedly undefined. If rA is in the range of registers specified
to be loaded, including the case in which rA = 0, the instruction form is invalid.
Note that, in some implementations, this instruction is likely to have a greater latency and
take longer to execute, perhaps much longer, than a sequence of individual load or store
instructions that produce the same results.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
75
lswi
lswi
Load String Word Immediate
lswi
rD,rA,NB
Reserved
31
D
A
NB
597
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then EA← 0
else EA← (rA)
if NB = 0 then n ← 32
elsen ← NB
r← rD – 1
i← 32
do while n > 0
if i = 32 then
r← r + 1 (mod 32)
GPR(r)← 0
GPR(r)[i–i + 7] ← MEM(EA, 1)
i← i + 8
if i = 32 then i ← 0
EA ← EA + 1
n ← n – 1
EA is (rA|0). Let n = NB if NB ≠ 0, n = 32 if NB = 0; n is the number of bytes to load. Let
nr = CEIL(n ÷ 4); nr is the number of registers to be loaded with data.
n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr – 1. Bytes are
loaded left to right in each register. The sequence of registers wraps around to r0 if
required. If the 4 bytes of register rD + nr – 1 are only partially filled, the unfilled low-order
byte(s) of that register are cleared.
If rA is in the range of registers specified to be loaded, including the case in which rA = 0,
the instruction form is invalid. Under certain conditions (for example, segment boundary
crossing) the data alignment exception handler may be invoked.
76
MPCxxx INSTRUCTION SET
Motorola
Note that, in some implementations, this instruction is likely to have greater latency and
take longer to execute, perhaps much longer, than a sequence of individual load or store
instructions that produce the same results.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
77
lswx
lswx
Load String Word Indexed
lswx
rD,rA,rB
Reserved
31
D
A
B
533
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
else b← (rA)
EA← b + (rB)
n ← XER[25–31]
r← rD – 1
i← 32
rD ← undefined
do while n > 0
if i = 32 then
r← r + 1 (mod 32)
GPR(r)← 0
GPR(r)[i–i + 7]← MEM(EA, 1)
i← i + 8
if i = 32 then i ← 0
EA ← EA + 1
n ← n – 1
EA is the sum (rA|0) + (rB). Let n = XER[25–31]; n is the number of bytes to load. Let
nr = CEIL(n ÷ 4); nr is the number of registers to receive data. If n > 0, n consecutive bytes
starting at EA are loaded into GPRs rD through rD + nr – 1.
Bytes are loaded left to right in each register. The sequence of registers wraps around
through r0 if required. If the four bytes of rD + nr – 1 are only partially filled, the unfilled
low-order byte(s) of that register are cleared. If n = 0, the contents of rD are undefined.
If rA or rB is in the range of registers specified to be loaded, including the case in which
rA = 0, either the system illegal instruction error handler is invoked or the results are
boundedly undefined. If rD = rA or rD = rB, the instruction form is invalid. If rD and rA both
specify GPR0, the form is invalid.
78
MPCxxx INSTRUCTION SET
Motorola
Under certain conditions (for example, segment boundary crossing) the data alignment
exception handler may be invoked. Note that, in some implementations, this instruction is
likely to have a greater latency and take longer to execute, perhaps much longer, than a
sequence of individual load or store instructions that produce the same results.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
79
lwarx
lwarx
Load Word and Reserve Indexed
lwarx
rD,rA,rB
Reserved
31
D
A
B
20
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
else b← (rA)
EA← b + (rB)
RESERVE← 1
RESERVE_ADDR← physical_addr(EA)
rD← MEM(EA,4)
EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into rD.
This instruction creates a reservation for use by a store word conditional indexed
(stwcx.)instruction. The physical address computed from EA is associated with the
reservation, and replaces any address previously associated with the reservation. EA
must be a multiple of four. If it is not, either the system alignment exception handler is
invoked or the results are boundedly undefined.
When the RESERVE bit is set, the processor enables hardware snooping for the block of
memory addressed by the RESERVE address. If the processor detects that another
processor writes to the block of memory it has reserved, it clears the RESERVE bit. The
stwcx. instruction will only do a store if the RESERVE bit is set. The stwcx. instruction
sets the CR0[EQ] bit if the store was successful and clears it if it failed. The lwarx and
stwcx. combination can be used for atomic read-modify-write sequences. Note that the
atomic sequence is not guaranteed, but its failure can be detected if CR0[EQ] = 0 after the
stwcx. instruction.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
80
MPCxxx INSTRUCTION SET
Motorola
lwbrx
lwbrx
Load Word Byte-Reverse Indexed
lwbrx
rD,rA,rB
Reserved
31
D
A
B
534
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
rD← MEM(EA + 3, 1) || MEM(EA + 2, 1) || MEM(EA + 1, 1) || MEM(EA, 1)
EA is the sum (rA|0) + rB. Bits 0–7 of the word in memory addressed by EA are loaded
into the low-order 8 bits of rD. Bits 8–15 of the word in memory addressed by EA are
loaded into the subsequent low-order 8 bits of rD. Bits 16–23 of the word in memory
addressed by EA are loaded into the subsequent low-order eight bits of rD. Bits 24–31 of
the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of
rD. The MPCxxx may run the lwbrx instructions with greater latency than other types of
load instructions.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
81
lwz
lwz
Load Word and Zero
lwz
rD,d(rA)
32
D
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b← 0
elseb← (rA)
EA← b + EXTS(d)
rD← MEM(EA, 4)
EA is the sum (rA|0) + d. The word in memory addressed by EA is loaded into rD.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
82
MPCxxx INSTRUCTION SET
Motorola
lwzu
lwzu
Load Word and Zero with Update
lwzu
rD,d(rA)
33
D
A
d
0
5 6
10 11
15 16
31
EA ← rA + EXTS(d)
rD← MEM(EA, 4)
rA← EA
EA is the sum (rA) + d. The word in memory addressed by EA is loaded into rD. EA is
placed into rA. If rA = 0, or rA = rD, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
83
lwzux
lwzux
Load Word and Zero with Update Indexed
lwzux
rD,rA,rB
Reserved
31
D
A
B
55
0
0
5 6
10 11
15 16
20 21
30 31
EA ← (rA) + (rB)
rD← MEM(EA, 4)
rA← EA
EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into rD. EA is
placed into rA. If rA = 0, or rA = rD, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
84
MPCxxx INSTRUCTION SET
Motorola
lwzx
lwzx
Load Word and Zero Indexed
lwzx
rD,rA,rB
Reserved
31
D
A
B
23
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + rB
rD← MEM(EA, 4)
EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into rD.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
85
mcrf
mcrf
Move Condition Register Field
mcrf
crfD,crfS
Reserved
19
crfD
0 0
crfS
0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0
0
5 6
8 9 10 11
13 14 15 16
20 21
30 31
CR[4 crfD–4 crfD + 3] ← CR[4 crfS–4 crfS + 3]
The contents of condition register field crfS are copied into condition register field crfD.
All other condition register fields remain unchanged.
Other registers altered:
•
Condition Register (CR field specified by operand crfD):
Affected: LT, GT, EQ, SO
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XL
86
MPCxxx INSTRUCTION SET
Motorola
mcrxr
mcrxr
Move to Condition Register from XER
mcrxr
crfD
Reserved
31
crfD
0 0
0 0 0 0 0
0 0 0 0 0
512
0
0
5 6
8 9 10 11
15 16
20 21
30 31
CR[4 crfD–4 crfD + 3] ← XER[0–3]
XER[0–3]← 0b0000
The contents of XER[0–3] are copied into the condition register field designated by crfD.
All other fields of the condition register remain unchanged. XER[0–3] is cleared.
Other registers altered:
•
Condition Register (CR field specified by operand crfD):
Affected: LT, GT, EQ, SO
•
XER[0–3]
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
87
mfcr
mfcr
Move from Condition Register
mfcr
rD
Reserved
31
D
0 0 0 0 0
0 0 0 0 0
19
0
0
5 6
10 11
15 16
20 21
30 31
rD← CR
The contents of the condition register (CR) are placed into rD.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
89
mfmsr
mfmsr
Move from Machine State Register
mfmsr
rD
Reserved
31
D
0 0 0 0 0
0 0 0 0 0
83
0
0
5 6
10 11
15 16
20 21
30 31
rD← MSR
The contents of the MSR are placed into rD. This is a supervisor-level instruction.
Other registers altered:
•
None
PowerPC Architecture Level
OEA
Supervisor Level
Optional
Form
X
√
90
MPCxxx INSTRUCTION SET
Motorola
mfspr
mfspr
Move from Special-Purpose Register
mfspr
rD,SPR
Reserved
31
D
spr*
339
0
0
5 6
10 11
20 21
30 31
*Note: This is a split field.
n ← spr[5–9] || spr[0–4]
rD← SPR(n)
In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as
shown in Table 9.The contents of the designated special-purpose register are placed into
rD.
Table 9. PowerPC UISA SPR Encodings for mfspr
SPR**
Register Name
Decimal
spr[5–9]
spr[0–4]
1
8
9
00000
00000
00000
00001
01000
01001
XER
LR
CTR
** Note that the order of the two 5-bit halves of the SPR
number is reversed compared with the actual instruction
coding.
If the SPR field contains any value other than one of the values shown in Table 9 (and the
processor is in user mode), one of the following occurs:
•
•
•
The system illegal instruction error handler is invoked.
The system supervisor-level instruction error handler is invoked.
The results are boundedly undefined.
Other registers altered:
None
•
Motorola
MPCxxx INSTRUCTION SET
91
Simplified mnemonics:
mfxer rD
mflr rD
mfctr rD
equivalent to
equivalent to
equivalent to
mfspr rD,1
mfspr rD,8
mfspr rD,9
In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as
shown in Table 10. The contents of the designated SPR are placed into rD. SPR[0] = 1 if
and only if reading the register is supervisor-level. Execution of this instruction specifying
a defined and supervisor-level register when MSR[PR] = 1 will result in a priviledged
instruction type program exception.
If MSR[PR] = 1, the only effect of executing an instruction with an SPR number that is not
shown in Table 10 and has SPR[0] = 1 is to cause a supervisor-level instruction type
program exception or an illegal instruction type program exception. For all other cases,
MSR[PR] = 0 or SPR[0] = 0. If the SPR field contains any value that is not shown in
Table 10, either an illegal instruction type program exception occurs or the results are
boundedly undefined.
Other registers altered:
•
None
Table 10. PowerPC OEA SPR Encodings for mfspr
1
SPR
Register
Access
Name
Decimal
spr[5–9]
spr[0–4]
1
00000
00000
00000
00000
00000
00000
00000
00000
00010
00010
00100
00100
00100
00100
00100
00100
00001
01000
01001
10010
10011
10110
11010
11011
10000
10001
10000
10001
10010
10011
10100
10101
XER
LR
User
8
User
9
CTR
DSISR
DAR
DEC
SRR0
SRR1
User
18
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
19
22
26
27
2
EIE
80
3
EID
81
4
144
145
146
147
148
149
CMPA
4
CMPB
4
CMPC
4
CMPD
4
ICR
4
DER
92
MPCxxx INSTRUCTION SET
Motorola
Table 10. PowerPC OEA SPR Encodings for mfspr (Continued)
1
SPR
Register
Access
Name
Decimal
spr[5–9]
spr[0–4]
4
150
151
152
153
154
155
156
157
158
159
272
273
274
275
287
560
561
562
568
569
570
630
638
784
786
787
789
790
792
793
794
00100
00100
00100
00100
00100
00100
00100
00100
00100
00100
01000
01000
01000
01000
01000
10001
10001
10001
10001
10001
10001
10011
10011
11000
11000
11000
11000
11000
11000
11000
11000
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
10000
10001
10010
10011
11111
10000
10001
10010
11000
11001
11010
10110
11110
10000
10010
10011
10101
10110
11000
11001
11010
COUNTA
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
4
COUNTB
4
CMPE
4
CMPF
4
CMPG
4
CMPH
4
LCTRL1
4
LCTRL2
4
ICTRL
4
BAR
SPRG0
SPRG1
SPRG2
SPRG3
PVR
IC_CST
IC_ADR
IC_DAT
DC_CST
DC_ADR
DC_DAT
4
DPDR
IMMR
MI_CTR
MI_AP
MI_EPN
MI_TWC
MI_RPN
MD_CTR
M_CASID
MD_AP
Motorola
MPCxxx INSTRUCTION SET
93
Table 10. PowerPC OEA SPR Encodings for mfspr (Continued)
1
SPR
Register
Access
Name
Decimal
spr[5–9]
spr[0–4]
795
796
797
798
799
816
817
818
824
825
826
1
11000
11000
11000
11000
11000
11001
11001
11001
11001
11001
11001
11011
11100
11101
11110
11111
10000
10001
10010
11000
11001
11010
MD_EPN
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
M_TWB
MD_TWC
MD_RPN
M_TW
MI_DBCAM
MI_DBRAM0
MI_DBRAM1
MD_DBCAM
MI_DBRAM0
MI_DBRAM1
Note that the order of the two 5-bit halves of the SPR number is reversed
compared with actual instruction coding.
2
Sets EE Bit (Bit 16) in MSR.
3
Clears EE Bit (Bit 16) in MSR.
4
Development Support (Debug) Register.
For mtspr and mfspr instructions, the SPR number coded in assembly
language does not appear directly as a 10-bit binary number in the
instruction. The number coded is split into two 5-bit halves that are
reversed in the instruction, with the high-order five bits appearing in bits
16–20 of the instruction and the low-order five bits in bits 11–15.
PowerPC Architecture Level
UISA/OEA
Supervisor Level
Optional
Form
XFX
√*
* Note that mfspr is supervisor-level only if SPR[0] = 1.
94
MPCxxx INSTRUCTION SET
Motorola
mftb
mftb
Move from Time Base
mftb
rD,TBR
Reserved
31
D
tbr*
371
0
0
5 6
10 11
20 21
30 31
*Note: This is a split field.
n ← tbr[5–9] || tbr[0–4]
if n = 268 then
rD← TBL
else if n = 269 then
rD← TBU
Table 11. TBR Encodings for mftb
TBR*
Register
Access
Name
Decimal
tbr[5–9]
tbr[0–4]
268
269
01000
01000
01100
01101
TB Read
User
User
TBU Read
*Note that the order of the two 5-bit halves of the TBR number is
reversed.
If the TBR field contains any value other than one of the values shown in Table 11, then
one of the following occurs:
•
•
•
The system illegal instruction error handler is invoked.
The system supervisor-level instruction error handler is invoked.
The results are boundedly undefined.
It is important to note that some implementations may implement mftb and mfspr
identically, therefore, a TBR number must not match an SPR number.
Other registers altered:
•
None
Motorola
MPCxxx INSTRUCTION SET
95
Simplified mnemonics:
mftb rD
mftbu rD
equivalent to
equivalent to
mftb rD,268
mftb rD,269
PowerPC Architecture Level
VEA
Supervisor Level
Optional
Form
XFX
96
MPCxxx INSTRUCTION SET
Motorola
mtcrf
mtcrf
Move to Condition Register Fields
mtcrf
CRM,rS
Reserved
31
S
0
CRM
0
144
0
0
5
6
10 11 12
19 20 21
30 31
mask← (4)(CRM[0]) || (4)(CRM[1]) ||... (4)(CRM[7])
CR← (rS & mask) | (CR & ¬ mask)
The contents of rS are placed into the condition register under control of the field mask
specified by CRM. The field mask identifies the 4-bit fields affected. Let i be an integer in
the range 0–7. If CRM(i) = 1, CR field i (CR bits 4 i through 4 i + 3) is set to the contents
of the corresponding field of rS.
Note that updating a subset of the eight fields of the condition register may have
substantially poorer performance on some implementations than updating all of the fields.
Other registers altered:
•
CR fields selected by mask
Simplified mnemonics:
mtcr rS
equivalent to
mtcrf 0xFF,rS
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XFX
Motorola
MPCxxx INSTRUCTION SET
97
mtmsr
mtmsr
Move to Machine State Register
mtmsr
rS
Reserved
31
S
0 0 0 0 0
0 0 0 0 0
146
0
0
5 6
MSR← (rS)
10 11
15 16
20 21
30 31
The contents of rS are placed into the MSR.This is a supervisor-level instruction. It is also
an execution synchronizing instruction except with respect to alterations to the POW and
LE bits.
In addition, alterations to the MSR[EE] and MSR[RI] bits are effective as soon as the
instruction completes. Thus if MSR[EE] = 0 and an external or decrementer exception is
pending, executing an mtmsr instruction that sets MSR[EE] = 1 will cause the external or
decrementer exception to be taken before the next instruction is executed, if no higher
priority exception exists.
Other registers altered:
•
MSR
PowerPC Architecture Level
OEA
Supervisor Level
Optional
Form
X
√
98
MPCxxx INSTRUCTION SET
Motorola
mtspr
mtspr
Move to Special-Purpose Register
mtspr
SPR,rS
Reserved
31
S
spr*
467
0
0
5 6
10 11
20 21
30 31
*Note: This is a split field.
n ← spr[5–9] || spr[0–4]
SPR(n)← rS
In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as
shown in Table 12. The contents of rS are placed into the designated special-purpose
register.
Table 12. PowerPC UISA SPR Encodings for mtspr
SPR**
Register Name
Decimal
spr[5–9]
spr[0–4]
1
8
9
00000
00000
00000
00001
01000
01001
XER
LR
CTR
** Note that the order of the two 5-bit halves of the SPR
number is reversed compared with actual instruction coding.
If the SPR field contains any value other than one of the values shown in Table 12, and
the processor is operating in user mode, one of the following occurs:
•
•
•
The system illegal instruction error handler is invoked.
The system supervisor instruction error handler is invoked.
The results are boundedly undefined.
Other registers altered:
See Table 12.
•
Motorola
MPCxxx INSTRUCTION SET
99
Simplified mnemonics:
mtxer rD
mtlr rD
mtctr rD
equivalent to
equivalent to
equivalent to
mtspr 1,rD
mtspr 8,rD
mtspr 9,rD
In the PowerPC OEA, the SPR field denotes a special-purpose register, encoded as
shown in Table 13. The contents of rS are placed into the designated special-purpose
register. For this instruction, SPRs TBL and TBU are treated as separate 32-bit registers;
setting one leaves the other unaltered.
The value of SPR[0] = 1 if and only if writing the register is a supervisor-level operation.
Execution of this instruction specifying a defined and supervisor-level register when
MSR[PR] = 1 results in a priviledged instruction type program exception.
If MSR[PR] = 1 then the only effect of executing an instruction with an SPR number that
is not shown in Table 13 and has SPR[0] = 1 is to cause a priviledged instruction type
program exception or an illegal instruction type program exception. For all other cases,
MSR[PR] = 0 or SPR[0] = 0, if the SPR field contains any value that is not shown in
Table 13, either an illegal instruction type program exception occurs or the results are
boundedly undefined.
Other registers altered:
•
See Table 13.
Table 13. PowerPC OEA SPR Encodings for mtspr
1
SPR
Register
Name
Access
Decimal
spr[5–9]
spr[0–4]
1
00000
00000
00000
00000
00000
00000
00000
00000
00010
00010
00100
00100
00100
00100
00001
01000
01001
10010
10011
10110
11010
11011
10000
10001
10000
10001
10010
10011
XER
User
8
LR
User
9
CTR
User
18
19
22
26
27
80
81
DSISR
DAR
DEC
SRR0
SRR1
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
2
EIE
3
EID
4
144
145
146
147
CMPA
4
4
CMPB
CMPC
4
CMPD
100
MPCxxx INSTRUCTION SET
Motorola
Table 13. PowerPC OEA SPR Encodings for mtspr (Continued)
1
SPR
Register
Access
Name
Decimal
148
spr[5–9]
spr[0–4]
4
ICR
00100
00100
00100
00100
00100
00100
00100
00100
00100
00100
00100
00100
01000
01000
01000
01000
01000
01000
10001
10001
10001
10001
10001
10001
10011
10011
11000
11000
11000
11000
11000
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
10000
10001
10010
10011
11100
11101
10000
10001
10010
11000
11001
11010
10110
11110
10000
10010
10011
10101
10110
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
4
149
150
151
152
153
154
155
156
157
158
159
272
273
274
275
284
285
560
561
562
568
569
570
630
638
784
786
787
789
790
DER
4
COUNTA
4
COUNTB
4
CMPE
4
CMPF
4
CMPG
4
CMPH
4
LCTRL1
4
LCTRL2
4
ICTRL
4
BAR
SPRG0
SPRG1
SPRG2
SPRG3
TB Write
TBU Write
IC_CST
IC_ADR
IC_DAT
DC_CST
DC_ADR
DC_DAT
4
DPDR
IMMR
MI_CTR
MI_AP
MI_EPN
MI_TWC
MI_RPN
Motorola
MPCxxx INSTRUCTION SET
101
Table 13. PowerPC OEA SPR Encodings for mtspr (Continued)
1
SPR
Register
Access
Name
Decimal
792
spr[5–9]
spr[0–4]
11000
11000
11000
11000
11000
11000
11000
11000
11001
11001
11001
11001
11001
11001
11000
11001
11010
11011
11100
11101
11110
11111
10000
10001
10010
11000
11001
11010
MD_CTR
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
793
794
795
796
797
798
799
816
817
818
824
825
826
1
M_CASID
MD_AP
MD_EPN
M_TWB
MD_TWC
MD_RPN
M_TW
MI_DBCAM
MI_DBRAM0
MI_DBRAM1
MD_DBCAM
MI_DBRAM0
MI_DBRAM1
Note that the order of the two 5-bit halves of the SPR number is reversed. For mtspr
and mfspr instructions, the SPR number coded in assembly language does not appear
directly as a 10-bit binary number in the instruction. The number coded is split into two
5-bit halves that are reversed in the instruction, with the high-order five bits appearing
in bits 16–20 of the instruction and the low-order five bits in bits 11–15. .
2
Sets EE Bit (Bit 16) in MSR.
3
Clears EE Bit (Bit 16) in MSR.
4
Development Support (Debug) Register.
PowerPC Architecture Level
UISA/OEA
Supervisor Level
Optional
Form
XFX
√*
* Note that mtspr is supervisor-level only if SPR[0] = 1.
102
MPCxxx INSTRUCTION SET
Motorola
mulhwx
mulhwx
Multiply High Word
mulhw
mulhw.
rD,rA,rB
rD,rA,rB
(Rc = 0)
(Rc = 1)
Reserved
31
D
A
B
0
75
Rc
0
5 6
10 11
15 16
20 21 22
30 31
prod[0–63]← rA
rD ← prod[0–31]
rB
The 64 -bit product is formed from the contents of rA and rB.The high-order 32 bits of the
64-bit product of the operands are placed into rD. Both the operands and the product are
interpreted as signed integers. This instruction may execute faster on some
implementations if rB contains the operand having the smaller absolute value.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
Motorola
MPCxxx INSTRUCTION SET
103
mulhwux
mulhwux
Multiply High Word Unsigned
mulhwu
mulhwu.
rD,rA,rB
rD,rA,rB
(Rc = 0)
(Rc = 1)
Reserved
31
D
A
B
0
11
Rc
0
5 6
10 11
15 16
20 21 22
30 31
prod[0–63] ← rA
rD ← prod[0–31]
rB
The 32-bit operands are the contents of rA and rB. The high-order 32 bits of the 64-bit
product of the operands are placed into rD. Both the operands and the product are
interpreted as unsigned integers, except that if Rc = 1 the first three bits of CR0 field are
set by signed comparison of the result to zero. This instruction may execute faster on
some implementations if rB contains the operand having the smaller absolute value.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
104
MPCxxx INSTRUCTION SET
Motorola
mulli
mulli
Multiply Low Immediate
mulli
rD,rA,SIMM
07
D
A
SIMM
0
5 6
10 11
15 16
31
prod[0–48] ← (rA) SIMM
rD← prod[16-48]
The first operand is (rA). The 16-bit second operand is the value of the SIMM field. The
low-order 32-bits of the 48-bit product of the operands are placed into rD. Both the
operands and the product are interpreted as signed integers. The low-order 32 bits of the
product are calculated independently of whether the operands are treated as signed or
unsigned 32-bit integers.This instruction can be used with mulhdx or mulhwx to calculate
a full 64-bit product.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
105
mullwx
mullwx
Multiply Low Word
mullw
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
mullw.
mullwo
mullwo.
31
D
A
B
OE
235
Rc
0
5 6
rD← rA
10 11
15 16
20 21 22
30 31
rB
The 32-bit operands are the contents of rA and rB. The low-order 32 bits of the 64-bit
product (rA) * (rB) are placed into rD. The low-order 32 bits of the product are the correct
32-bit product for 32-bit implementations. The low-order 32-bits of the product are
independent of whether the operands are regarded as signed or unsigned 32-bit integers.
If OE = 1, then OV is set if the product cannot be represented in 32 bits. Both the operands
and the product are interpreted as signed integers.
Note that this instruction may execute faster on some implementations if rB contains the
operand having the smaller absolute value.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: SO, OV(if OE = 1)
Note:The setting of the affected bits in the XER is mode-independent, and reflects
overflow of the 32-bit result.
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
106
MPCxxx INSTRUCTION SET
Motorola
nandx
nandx
NAND
nand
nand.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
476
Rc
0
5 6
10 11
15 16
20 21
30 31
rA← ¬ ((rS) & (rB))
The contents of rS are ANDed with the contents of rB and the complemented result is
placed into rA. nand with rS = rB can be used to obtain the one's complement.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
107
negx
negx
Negate
neg
rD,rA
rD,rA
rD,rA
rD,rA
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
neg.
nego
nego.
Reserved
31
D
A
0 0 0 0 0
15 16
OE
104
Rc
0
5 6
rD← ¬ (rA) + 1
10 11
20 21 22
30 31
The value 1 is added to the complement of the value in rA, and the resulting two’s
complement is placed into rD. If rA contains the most negative 32-bit number
(0x8000_0000), the result is the most negative number and, if OE = 1, OV is set.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
XER:
•
Affected: SO OV(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
108
MPCxxx INSTRUCTION SET
Motorola
norx
norx
NOR
nor
nor.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
124
Rc
0
5 6
10 11
15 16
20 21
30 31
rA← ¬ ((rS) | (rB))
The contents of rS are ORed with the contents of rB and the complemented result is
placed into rA. nor with rS = rB can be used to obtain the one’s complement.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
Simplified mnemonics:
not rD,rS
equivalent to
nor rA,rS,rS
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
109
orx
orx
OR
or
or.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
444
Rc
0
5 6
rA← (rS) | (rB)
10 11
15 16
20 21
30 31
The contents of rS are ORed with the contents of rB and the result is placed into rA. The
simplified mnemonic mr (shown below) demonstrates the use of the or instruction to move
register contents.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
Simplified mnemonics:
mr
rA,rS
equivalent to
or
rA,rS,rS
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
110
MPCxxx INSTRUCTION SET
Motorola
orcx
orcx
OR with Complement
orc
orc.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
412
Rc
0
5 6
rA← (rS) | ¬ (rB)
10 11
15 16
20 21
30 31
The contents of rS are ORed with the complement of the contents of rB and the result is
placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
111
ori
ori
OR Immediate
ori
rA,rS,UIMM
24
S
A
UIMM
0
5 6
10 11
15 16
31
rA← (rS) | ((16)0 || UIMM)
The contents of rS are ORed with 0x0000|| UIMM and the result is placed into rA. The
preferred no-op (an instruction that does nothing) is ori 0,0,0.
Other registers altered:
•
None
Simplified mnemonics:
nop
equivalent to
ori
0,0,0
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
112
MPCxxx INSTRUCTION SET
Motorola
oris
oris
OR Immediate Shifted
oris
rA,rS,UIMM
25
S
A
UIMM
0
5 6
10 11
15 16
31
rA← (rS) | (UIMM || (16)0)
The contents of rS are ORed with UIMM || 0x0000 and the result is placed into rA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
113
rfi
rfi
Return from Interrupt
Reserved
19
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
50
0
0
5 6
10 11
15 16
20 21
30 31
MSR[16–23, 25–27, 30–31] ← SRR1[16–23, 25–27, 30–31]
NIA←iea SRR0[0–29] || 0b00
Bits SRR1[0,5-9,16-31] are placed into the corresponding bits of the MSR. If the new MSR
value does not enable any pending exceptions, then the next instruction is fetched, under
control of the new MSR value, from the address SRR0[0–29] || 0b00. If the new MSR value
enables one or more pending exceptions, the exception associated with the highest
priority pending exception is generated; in this case the value placed into SRR0 by the
exception processing mechanism is the address of the instruction that would have been
executed next had the exception not occurred. Note that an implementation may define
addtional MSR bits, and in this case, may also cause them to be saved to SRR1 from MSR
on an exception and restored to MSR from SRR1 on an rfi. This is a supervisor-level,
context synchronizing instruction.
Other registers altered:
•
MSR
PowerPC Architecture Level
OEA
Supervisor Level
Optional
Form
XL
√
114
MPCxxx INSTRUCTION SET
Motorola
rlwimix
rlwimix
Rotate Left Word Immediate then Mask Insert
rlwimi
rlwimi.
rA,rS,SH,MB,ME
rA,rS,SH,MB,ME
(Rc = 0)
(Rc = 1)
20
S
A
SH
MB
ME
Rc
0
5 6
10 11
15 16
20 21
25 26
30 31
n ← SH
r← ROTL(rS, n)
m← MASK(MB, ME)
rA← (r & m) | (rA & ¬ m)
The contents of rS are rotated left the number of bits specified by operand SH. A mask is
generated having 1 bits from bit MB through bit ME and 0 bits elsewhere.The rotated data
is inserted into rA under control of the generated mask.
Note that rlwimi can be used to insert a bit field into the contents of rA using the methods
shown below:
•
To insert an n-bit field, that is left-justified rS, into rA starting at bit position b, set
SH = 32 – b, MB = b, and
ME = (b + n) – 1.
•
To insert an n-bit field, that is right-justified in rS, into rA starting at bit position b,
set SH = 32 – (b + n), MB = b, and ME = (b + n) – 1.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
•
Simplified mnemonics:
inslwi rA,rS,n,b
insrwi rA,rS,n,b (n > 0)
equivalent to rlwimi
equivalent to rlwimi
rA,rS,32 – b,b,b + n – 1
rA,rS,32 – (b + n),b,(b + n) – 1
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
M
Motorola
MPCxxx INSTRUCTION SET
115
rlwinmx
rlwinmx
Rotate Left Word Immediate then AND with Mask
rlwinm
rlwinm.
rA,rS,SH,MB,ME
rA,rS,SH,MB,ME
(Rc = 0)
(Rc = 1)
21
S
A
SH
MB
ME
Rc
0
5 6
10 11
15 16
20 21
25 26
30 31
n ← SH
r← ROTL(rS, n)
m← MASK(MB, ME)
rA← r & m
The contents of rS are rotated left the number of bits specified by operand SH. A mask is
generated having 1 bits from bit MB through bit ME and 0 bits elsewhere.The rotated data
is ANDed with the generated mask and the result is placed into rA.
Note that rlwinm can be used to extract, rotate, shift, and clear bit fields using the
methods shown below:
•
To extract an n-bit field, that starts at bit position b in rS, right-justified into rA
(clearing the remaining 32 – n bits of rA), set SH = b + n,
MB = 32 – n, and ME = 31.
•
•
•
To extract an n-bit field, that starts at bit position b in rS, left-justified into rA
(clearing the remaining 32 – n bits of rA), set SH = b, MB = 0, and ME = n – 1.
To rotate the contents of a register left (or right) by n bits, set SH = n (32 – n),
MB = 0, and ME = 31.
To shift the contents of a register right by n bits, by setting SH = 32 – n, MB = n,
and ME = 31. It can be used to clear the high-order b bits of a register and then
shift the result left by n bits by setting SH = n, MB = b – n and ME = 31 – n.
•
To clear the low-order n bits of a register, by setting SH = 0, MB = 0, and
ME = 31 – n.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
•
116
MPCxxx INSTRUCTION SET
Motorola
Simplified mnemonics:
extlwi rA,rS,n,b (n > 0)
extrwi rA,rS,n,b (n > 0)
rotlwi rA,rS,n
equivalent to
equivalent to
equivalent to
equivalent to
equivalent to
equivalent to
equivalent to
equivalent to
rlwinm rA,rS,b,0,n – 1
rlwinm rA,rS,b + n,32 – n,31
rlwinm rA,rS,n,0,31
rlwinm rA,rS,32 – n,0,31
rlwinm rA,rS,n,0,31–n
rlwinm rA,rS,32 – n,n,31
rlwinm rA,rS,0,n,31
rotrwi rA,rS,n
slwi rA,rS,n (n < 32)
srwi rA,rS,n (n < 32)
clrlwi rA,rS,n (n < 32)
clrrwi rA,rS,n (n < 32)
rlwinm rA,rS,0,0,31 – n
rlwinm rA,rS,n,b – n,31 – n
clrlslwi rA,rS,b,n (n ≤ b < 32) equivalent to
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
M
Motorola
MPCxxx INSTRUCTION SET
117
rlwnmx
rlwnmx
Rotate Left Word then AND with Mask
rlwnm
rlwnm.
rA,rS,rB,MB,ME
rA,rS,rB,MB,ME
(Rc = 0)
(Rc = 1)
23
S
A
B
MB
ME
Rc
0
5 6
10 11
15 16
20 21
25 26
30 31
n ← rB[27-31]
r← ROTL(rS, n)
m← MASK(MB, ME)
rA← r & m
The contents of rS are rotated left the number of bits specified by the low-order five bits
of rB. A mask is generated having 1 bits from bit MB through bit ME and 0 bits elsewhere.
The rotated data is ANDed with the generated mask and the result is placed into rA.
Note that rlwnm can be used to extract and rotate bit fields using the methods shown as
follows:
•
•
•
To extract an n-bit field, that starts at variable bit position b in rS, right-justified into
rA (clearing the remaining 32 – n bits of rA), by setting the low-order five bits of rB
to b + n, MB = 32 – n, and ME = 31.
To extract an n-bit field, that starts at variable bit position b in rS, left-justified into
rA (clearing the remaining 32 – n bits of rA), by setting the low-order five bits of rB
to b, MB = 0, and ME = n – 1.
To rotate the contents of a register left (or right) by n bits, by setting the low-order
five bits of rB to n (32 – n), MB = 0, and ME = 31.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
•
Simplified mnemonics:
rotlw rA,rS,rB
equivalent to
rlwnmrA,rS,rB,0,31
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
M
118
MPCxxx INSTRUCTION SET
Motorola
sc
sc
System Call
Reserved
17
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
0
0
5 6
10 11
15 16
29 30 31
The sc instruction calls the operating system to perform a service. When control is
returned to the program that executed the system call, the content of the registers
depends on the register conventions used by the program providing the system service.
The effective address of the instruction following the sc instruction is placed into SRR0.
Bits 0, 5-9, and 16-31 of the MSR are placed into the corresponding bits of SRR1, and bits
1-4 and 10-15 of SRR1 are set to undefined values. An sc exception is generated. The
exception alters the MSR. The exception causes the next instruction to be fetched from
offset 0xC00 from the base real address indicated by the new setting of MSR[IP].
Other registers altered:
•
•
•
•
Dependent on the system service
SRR0
SRR1
MSR
PowerPC Architecture Level
UISA/OEA
Supervisor Level
Optional
Form
SC
Motorola
MPCxxx INSTRUCTION SET
119
slwx
slwx
Shift Left Word
slw
slw.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
24
Rc
0
5 6
10 11
15 16
20 21
30 31
n ← rB[27-31]
rA ← ROTL(rS, n)
If bit 26 of rB = 0, the contents of rS are shifted left the number of bits specified by
rB[27–31]. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated
positions on the right.The 32-bit result is placed into rA. If bit 26 of rB = 1, 32 zeros
are placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
120
MPCxxx INSTRUCTION SET
Motorola
srawx
srawx
Shift Right Algebraic Word
sraw
sraw.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
792
Rc
0
5 6
10 11
15 16
20 21
30 31
n ← rB[27-31]
rA ← ROTL(rS, n)
If rB[26] = 0,then the contents of rS are shifted right the number of bits specified by
rB[27–31]. Bits shifted out of position 31 are lost.The result is padded on the left with sign
bits before being placed into rA. If rB[26] = 1, then rA is filled with 32 sign bits (bit 0) from
rS. CR0 is set based on the value written into rA. XER[CA] is set if rS contains a negative
number and any 1 bits are shifted out of position 31; otherwise XER[CA] is cleared. A shift
amount of zero causes XER[CA] to be cleared.
n
Note that the sraw instruction, followed by addze, can by used to divide quickly by 2 .The
setting of the XER[CA] bit, by sraw, is independent of mode.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
XER:
•
Affected: CA
Motorola
MPCxxx INSTRUCTION SET
121
srawix
srawix
Shift Right Algebraic Word Immediate
srawi
srawi.
rA,rS,SH
rA,rS,SH
(Rc = 0)
(Rc = 1)
31
S
A
SH
824
Rc
0
5 6
10 11
15 16
20 21
30 31
n ← SH
r← ROTL(rS, 32 – n)
The contents of rS are shifted right the number of bits specified by operand SH. Bits
shifted out of position 31 are lost. The shifted value is sign-extended before being placed
in rA. The 32-bit result is placed into rA. XER[CA] is set if rS contains a negative number
and any 1 bits are shifted out of position 31; otherwise XER[CA] is cleared. A shift amount
of zero causes XER[CA] to be cleared.
n
Note that the srawi instruction, followed by addze, can be used to divide quickly by 2 .
The setting of the CA bit, by srawi, is independent of mode.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
XER:
•
Affected: CA
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
122
MPCxxx INSTRUCTION SET
Motorola
srwx
srwx
Shift Right Word
srw
srw.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
536
Rc
0
5 6
10 11
15 16
20 21
30 31
n ← rB[27-31]
r← ROTL(rS, 32 –n)
The contents of rS are shifted right the number of bits specified by the low-order six bits
of rB. Bits shifted out of position 31 are lost. Zeros are supplied to the vacated positions
on the left. The result is placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
123
stb
stb
Store Byte
stb
rS,d(rA)
38
S
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b← 0
elseb← (rA)
EA← b + EXTS(d)
MEM(EA, 1)← rS[24-31]
EA is the sum (rA|0) + d. The contents of the low-order eight bits of rS are stored into the
byte in memory addressed by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
124
MPCxxx INSTRUCTION SET
Motorola
stbu
stbu
Store Byte with Update
stbu
rS,d(rA)
39
S
A
d
0
5 6
10 11
15 16
31
EA← (rA) + EXTS(d)
MEM(EA, 1)← rS[24-31]
rA← EA
EA is the sum (rA) + d. The contents of the low-order eight bits of rS are stored into the
byte in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is
invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
125
stbux
stbux
Store Byte with Update Indexed
stbux
rS,rA,rB
Reserved
31
S
A
B
247
0
0
5 6
10 11
15 16
21 22
30 31
EA← (rA) + (rB)
MEM(EA, 1)← rS[24-31]
rA← EA
EA is the sum (rA) + (rB).The contents of the low-order eight bits of rS are stored into the
byte in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is
invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
126
MPCxxx INSTRUCTION SET
Motorola
stbx
stbx
Store Byte Indexed
stbx
rS,rA,rB
Reserved
31
S
A
B
215
0
0
5 6
10 11
15 16
21 22
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
MEM(EA, 1) ← rS[24-31]
EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into
the byte in memory addressed by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
127
sth
sth
Store Half Word
sth
rS,d(rA)
44
S
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b← 0
elseb← (rA)
EA← b + EXTS(d)
MEM(EA, 2)← rS[16-31]
EA is the sum (rA|0) + d. The contents of the low-order 16 bits of rS are stored into the
half word in memory addressed by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
128
MPCxxx INSTRUCTION SET
Motorola
sthbrx
sthbrx
Store Half Word Byte-Reverse Indexed
sthbrx
rS,rA,rB
Reserved
31
S
A
B
918
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
MEM(EA, 2)← rS[24-31] || rS[16-23]
EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into
bits 0–7 of the half word in memory addressed by EA. The contents of the subsequent
low-order eight bits of rS are stored into bits 8–15 of the half word in memory addressed
by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
129
sthu
sthu
Store Half Word with Update
sthu
rS,d(rA)
45
S
A
d
0
5 6
10 11
15 16
31
EA← (rA) + EXTS(d)
MEM(EA, 2)← rS[16-31]
rA← EA
EA is the sum (rA) + d. The contents of the low-order 16 bits of rS are stored into the half
word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form is
invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
130
MPCxxx INSTRUCTION SET
Motorola
sthux
sthux
Store Half Word with Update Indexed
sthux
rS,rA,rB
Reserved
31
S
A
B
439
0
0
5 6
10 11
15 16
20 21
30 31
EA← (rA) + (rB)
MEM(EA, 2)← rS[16-31]
rA← EA
EA is the sum (rA) + (rB). The contents of the low-order 16 bits of rS are stored into the
half word in memory addressed by EA. EA is placed into rA. If rA = 0, the instruction form
is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
131
sthx
sthx
Store Half Word Indexed
sthx
rS,rA,rB
Reserved
31
S
A
B
407
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
MEM(EA, 2)← rS[16-31]
EA is the sum (rA|0) + (rB). The contents of the low-order 16 bits of rS are stored into the
half word in memory addressed by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
132
MPCxxx INSTRUCTION SET
Motorola
stmw
stmw
Store Multiple Word
stmw
rS,d(rA)
47
S
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b← 0
elseb← (rA)
EA← b + EXTS(d)
r← rS
do while r ≤ 31
MEM(EA, 4)← GPR(r)
r← r + 1
EA← EA + 4
EA is the sum (rA|0) + d. n = (32 – rS). n consecutive words starting at EA are stored from
the GPRs rS through r31. For example, if rS = 30, 2 words are stored. EA must be a
multiple of four. If it is not, either the system alignment exception handler is invoked or the
results are boundedly undefined.
Note that this instruction is likely to have a greater latency and take longer to execute,
perhaps much longer, than a sequence of individual load or store instructions that produce
the same results.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
133
stswi
stswi
Store String Word Immediate
stswi
rS,rA,NB
Reserved
31
S
A
NB
725
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then EA← 0
elseEA← (rA)
if NB = 0 then n ← 32
elsen ← NB
r← rS – 1
i← 32
do while n > 0
if i = 32 then r← r + 1 (mod 32)
MEM(EA, 1)← GPR(r)[i–i + 7]
i← i + 8
if i = 64 then i← 32
EA← EA + 1
n ← n – 1
EA is (rA|0). Let n = NB if NB ≠ 0, n = 32 if NB = 0; n is the number of bytes to store. Let
nr = CEIL(n ÷ 4); nr is the number of registers to supply data. n consecutive bytes starting
at EA are stored from GPRs rS through rS + nr – 1. Bytes are stored left to right from each
register. The sequence of registers wraps around through r0 if required. Under certain
conditions (for example, segment boundary crossing) the data alignment exception
handler may be invoked.
Note that, in some implementations, this instruction is likely to have a greater latency and
take longer to execute, perhaps much longer, than a sequence of individual load or store
instructions that produce the same results.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
134
MPCxxx INSTRUCTION SET
Motorola
stswx
stswx
Store String Word Indexed
stswx
rS,rA,rB
Reserved
31
S
A
B
661
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
n ← XER[25–31]
r← rS – 1
i← 32
do while n > 0
if i = 32 then r← r + 1 (mod 32)
MEM(EA, 1) ← GPR(r)[i–i + 7]
i← i + 8
if i = 64 then i← 32
EA← EA + 1
n ← n – 1
EA is the sum (rA|0) + (rB). Let n = XER[25–31]; n is the number of bytes to store. Let
nr = CEIL(n ÷ 4); nr is the number of registers to supply data. n consecutive bytes starting
at EA are stored from GPRs rS through rS + nr – 1. Bytes are stored left to right from each
register. The sequence of registers wraps around through r0 if required. If n = 0, no bytes
are stored. Under certain conditions (for example, segment boundary crossing) the data
alignment exception handler may be invoked.
Note that, in some implementations, this instruction is likely to have a greater latency and
take longer to execute, perhaps much longer, than a sequence of individual load or store
instructions that produce the same results.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
135
stw
stw
Store Word
stw
rS,d(rA)
36
S
A
d
0
5 6
10 11
15 16
31
if rA = 0 then b← 0
elseb← (rA)
EA← b + EXTS(d)
MEM(EA, 4)← rS
EA is the sum (rA|0) + d.The contents of rS are stored into the word in memory addressed
by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
136
MPCxxx INSTRUCTION SET
Motorola
stwbrx
stwbrx
Store Word Byte-Reverse Indexed
stwbrx
rS,rA,rB
Reserved
31
S
A
B
662
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
MEM(EA, 4)← rS[24-31] || rS[16-23] || rS[8-15] || rS[0-7]
EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into
bits 0–7 of the word in memory addressed by EA. The contents of the subsequent eight
low-order bits of rS are stored into bits 8–15 of the word in memory addressed by EA.The
contents of the subsequent eight low-order bits of rS are stored into bits 16–23 of the word
in memory addressed by EA. The contents of the subsequent eight low-order bits of rS
are stored into bits 24–31 of the word in memory addressed by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
137
stwcx.
stwcx.
Store Word Conditional Indexed
stwcx.
rS,rA,rB
31
S
A
B
150
1
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
else b← (rA)
EA← b + (rB)
if RESERVE then
if RESERVE_ADDR = physical_addr(EA)
MEM(EA, 4)← rS
CR0← 0b00 || 0b1 || XER[SO]
else
u ← undefined 1-bit value
if u then MEM(EA, 4) ← rS
CR0← 0b00 || u || XER[SO]
RESERVE ← 0
else
CR0← 0b00 || 0b0 || XER[SO]
EA is the sum (rA|0) + (rB). If the reserved bit is set, the stwcx. instruction stores rS to
effective address (rA + rB), clears the reserved bit, and sets CR0[EQ]. If the reserved bit
is not set, the stwcx. instruction does not do a store; it leaves the reserved bit cleared and
clears CR0[EQ]. Software must look at CR0[EQ] to see if the stwcx. was successful.
The reserved bit is set by the lwarx instruction. The reserved bit is cleared by any stwcx.
instruction to any address, and also by snooping logic if it detects that another processor
does any kind of store to the block indicated in the reservation buffer when reserved is set.
If a reservation exists, and the memory address specified by the stwcx. instruction is the
same as that specified by the load and reserve instruction that established the
reservation, the contents of rS are stored into the word in memory addressed by EA and
the reservation is cleared.
If a reservation exists, but the memory address specified by the stwcx. instruction is not
the same as that specified by the load and reserve instruction that established the
reservation, the reservation is cleared, and it is undefined whether the contents of rS are
stored into the word in memory addressed by EA.
If no reservation exists, the instruction completes without altering memory.
CR0 field is set to reflect whether the store operation was performed as follows.
CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO]
138
MPCxxx INSTRUCTION SET
Motorola
EA must be a multiple of four. If it is not, either the system alignment exception handler is
invoked or the results are boundedly undefined.
The granularity with which reservations are managed is implementation-dependent.
Therefore, the memory to be accessed by the load and reserve and store conditional
instructions should be allocated by a system library program.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
139
stwu
stwu
Store Word with Update
stwu
rS,d(rA)
37
S
A
d
0
5 6
10 11
15 16
31
EA← (rA) + EXTS(d)
MEM(EA, 4)← rS
rA← EA
EA is the sum (rA) + d. The contents of rS are stored into the word in memory addressed
by EA. EA is placed into rA. If rA = 0, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
140
MPCxxx INSTRUCTION SET
Motorola
stwux
stwux
Store Word with Update Indexed
stwux
rS,rA,rB
Reserved
31
S
A
B
183
0
0
5 6
10 11
15 16
20 21
30 31
EA← (rA) + (rB)
MEM(EA, 4)← rS
rA← EA
EA is the sum (rA) + (rB). The contents of rS are stored into the word in memory
addressed by EA. EA is placed into rA. If rA = 0, the instruction form is invalid.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
141
stwx
stwx
Store Word Indexed
stwx
rS,rA,rB
Reserved
31
S
A
B
151
0
0
5 6
10 11
15 16
20 21
30 31
if rA = 0 then b← 0
elseb← (rA)
EA← b + (rB)
MEM(EA, 4)← rS
EA is the sum (rA|0) + (rB). The contents of rS are is stored into the word in memory
addressed by EA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
142
MPCxxx INSTRUCTION SET
Motorola
subfx
subfx
Subtract From
subf
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
subf.
subfo
subfo.
31
D
A
B
OE
40
Rc
0
5 6
10 11
15 16
20 21 22
30 31
rD← ¬ (rA) + (rB) + 1
The sum ¬ (rA) + (rB) + 1 is placed into rD.The subf instruction is preferred for subtraction
because it sets few status bits.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
XER:
•
Affected: SO, OV(if OE = 1)
Simplified mnemonics:
sub rD,rA,rB
equivalent to
subf rD,rB,rA
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
Motorola
MPCxxx INSTRUCTION SET
143
subfcx
subfcx
Subtract from Carrying
subfc
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
subfc.
subfco
subfco.
31
D
A
B
OE
8
Rc
0
5 6
10 11
15 16
20 21 22
30 31
rD← ¬ (rA) + (rB) + 1
The sum ¬ (rA) + (rB) + 1 is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV (if OE = 1)
Simplified mnemonics:
subc rD,rA,rB
equivalent to
subfc rD,rB,rA
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
144
MPCxxx INSTRUCTION SET
Motorola
subfex
subfex
Subtract from Extended
subfe
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
subfe.
subfeo
subfeo.
31
D
A
B
OE
136
Rc
0
5 6
10 11
15 16
20 21 22
30 31
rD← ¬ (rA) + (rB) + XER[CA]
The sum ¬ (rA) + (rB) + XER[CA] is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
Motorola
MPCxxx INSTRUCTION SET
145
subfic
subfic
Subtract from Immediate Carrying
subfic
rD,rA,SIMM
08
D
A
SIMM
0
5 6
10 11
15 16
31
rD← ¬ (rA) + EXTS(SIMM) + 1
The sum ¬ (rA) + EXTS(SIMM) + 1 is placed into rD.
Other registers altered:
•
XER:
Affected: CA
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
146
MPCxxx INSTRUCTION SET
Motorola
subfmex
subfmex
Subtract from Minus One Extended
subfme
rD,rA
rD,rA
rD,rA
rD,rA
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
subfme.
subfmeo
subfmeo.
Reserved
31
D
A
0 0 0 0 0
15 16
OE
232
Rc
0
5 6
10 11
20 21 22
30 31
rD← ¬ (rA) + XER[CA] – 1
The sum ¬ (rA) + XER[CA] + (32)1 is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
Motorola
MPCxxx INSTRUCTION SET
147
subfzex
subfzex
Subtract from Zero Extended
subfze
rD,rA
(OE = 0 Rc = 0)
(OE = 0 Rc = 1)
(OE = 1 Rc = 0)
(OE = 1 Rc = 1)
subfze.
subfzeo
subfzeo.
rD,rA
rD,rA
rD,rA
Reserved
31
D
A
0 0 0 0 0
15 16
OE
200
Rc
0
5 6
10 11
20 21 22
30 31
rD← ¬ (rA) + XER[CA]
The sum ¬ (rA) + XER[CA] is placed into rD.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
Note: CR0 field may not reflect the “true” (infinitely precise) result if overflow occurs
(see XER below).
•
XER:
Affected: CA
Affected: SO, OV(if OE = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
XO
148
MPCxxx INSTRUCTION SET
Motorola
sync
sync
Synchronize
Reserved
31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
598
0
0
5 6
10 11
15 16
20 21
30 31
The sync instruction provides an ordering function for the effects of all instructions
executed by a given processor. Executing a sync instruction ensures that all instructions
preceding the sync instruction appear to have completed before the sync instruction
completes, and that no subsequent instructions are initiated by the processor until after
the sync instruction completes. When the sync instruction completes, all external
accesses caused by instructions preceding the sync instruction will have been performed
with respect to all other mechanisms that access memory.
Multiprocessor implementations also send a sync address-only broadcast that is useful
in some designs. For example, if a design has an external buffer that re-orders loads and
stores for better bus efficiency, the sync broadcast signals to that buffer that previous
loads/stores must be completed before any following loads/stores.
The sync instruction can be used to ensure that the results of all stores into a data
structure, caused by store instructions executed in a “critical section” of a program, are
seen by other processors before the data structure is seen as unlocked.
The functions performed by the sync instruction will normally take a significant amount of
time to complete, so indiscriminate use of this instruction may adversely affect
performance. In addition, the time required to execute sync may vary from one execution
to another. The eieio instruction may be more appropriate than sync for many cases.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
149
tlbia
tlbia
Translation Lookaside Buffer Invalidate All
Reserved
31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
370
0
0
5 6
10 11
15 16
20 21
30 31
All TLB entries← invalid
The entire translation lookaside buffer (TLB) is invalidated (that is, all entries are
removed).The TLB is invalidated regardless of the settings of MSR[IR] and MSR[DR].The
invalidation is done without reference to the SLB or segment table. This instruction does
not cause the entries to be invalidated in other processors. This is a supervisor-level
instructon.
Other registers altered:
•
None
PowerPC Architecture Level
OEA
Supervisor Level
Optional
Form
X
√
√
150
MPCxxx INSTRUCTION SET
Motorola
tlbie
tlbie
Translation Lookaside Buffer Invalidate Entry
tlbie
rB
Reserved
31
0 0 0 0 0
0 0 0 0 0
B
30k6
0
0
5 6
10 11
15 16
20 21
30 31
VPS ← rB[4-19]
Identify TLB entries corresponding to VPS
Each such TLB entry ← invalid
EA is the contents of rB. If the translation lookaside buffer (TLB) contains an entry
corresponding to EA, that entry is made invalid (that is, removed from the TLB).
Multiprocessing implementations (for example, the 601, and 604) send a tlbie address-
only broadcast over the address bus to tell other processors to invalidate the same TLB
entry in their TLBs.
The TLB search is done regardless of the settings of MSR[IR] and MSR[DR]. The search
is done based on a portion of the logical page number within a segment. All entries
matching the search criteria are invalidated.
Block address translation for EA, if any, is ignored.
This is a supervisor-level instruction.
Other registers altered:
•
None
PowerPC Architecture Level
OEA
Supervisor Level
Optional
Form
X
√
√
Motorola
MPCxxx INSTRUCTION SET
151
tlbsync
tlbsync
TLB Synchronize
Reserved
31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
566
0
0
5 6
10 11
15 16
20 21
30 31
If an implementation sends a broadcast for tlbie then it will also send a broadcast for
tlbsync. Executing a tlbsync instruction ensures that all tlbie instructions previously
executed by the processor executing the tlbsync instruction have completed on all other
processors. The operation performed by this instruction is treated as a caching-inhibited
and guarded data access with respect to the ordering done by eieio. This instruction is
supervisor-level.
Other registers altered:
•
None
PowerPC Architecture Level
OEA
Supervisor Level
Optional
Form
X
√
√
152
MPCxxx INSTRUCTION SET
Motorola
tw
tw
Trap Word
tw
TO,rA,rB
Reserved
31
TO
A
B
4
0
0
5 6
10 11
15 16
20 21
30 31
a← EXTS(rA)
b← EXTS(rB)
if (a < b) & TO[0] then TRAP
if (a > b) & TO[1] then TRAP
if (a = b) & TO[2] then TRAP
if (a <U b) & TO[3] then TRAP
if (a >U b) & TO[4] then TRAP
The contents of rA are compared with the contents of rB. If any bit in the TO field is set
and its corresponding condition is met by the result of the comparison, then the system
trap handler is invoked.
Other registers altered:
•
None
Simplified mnemonics:
tweq rA,rB
twlge rA,rB
trap
equivalent to
equivalent to
equivalent to
tw
tw
tw
4,rA,rB
5,rA,rB
31,0,0
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
153
twi
twi
Trap Word Immediate
twi
TO,rA,SIMM
03
TO
A
SIMM
0
5 6
10 11
15 16
31
a← EXTS(rA)
if (a < EXTS(SIMM)) & TO[0] then TRAP
if (a > EXTS(SIMM)) & TO[1] then TRAP
if (a = EXTS(SIMM)) & TO[2] then TRAP
if (a <U EXTS(SIMM)) & TO[3] then TRAP
if (a >U EXTS(SIMM)) & TO[4] then TRAP
The contents of rA are compared with the sign-extended value of the SIMM field. If any bit
in the TO field is set and its corresponding condition is met by the result of the comparison,
then the system trap handler is invoked.
Other registers altered:
•
None
Simplified mnemonics:
twgti rA,value
twllei rA,value
equivalent to
equivalent to
twi
twi
8,rA,value
6,rA,value
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
154
MPCxxx INSTRUCTION SET
Motorola
xorx
xorx
XOR
xor
xor.
rA,rS,rB
rA,rS,rB
(Rc = 0)
(Rc = 1)
31
S
A
B
316
Rc
0
5 6
rA← (rS)
10 11
15 16
20 21
30 31
(rB)
The contents of rS is XORed with the contents of rB and the result is placed into rA.
Other registers altered:
•
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
X
Motorola
MPCxxx INSTRUCTION SET
155
xori
xori
XOR Immediate
xori
rA,rS,UIMM
26
S
A
UIMM
0
5 6
10 11
15 16
31
rA← (rS)
((16)0 || UIMM)
The contents of rS are XORed with 0x0000 || UIMM and the result is placed into rA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
156
MPCxxx INSTRUCTION SET
Motorola
xoris
xoris
XOR Immediate Shifted
xoris
rA,rS,UIMM
27
S
A
UIMM
0
5 6
rA← (rS)
10 11
(UIMM || (16)0)
15 16
31
The contents of rS are XORed with UIMM || 0x0000 and the result is placed into rA.
Other registers altered:
•
None
PowerPC Architecture Level
UISA
Supervisor Level
Optional
Form
D
Motorola
MPCxxx INSTRUCTION SET
157
Appendix
MPCxxx Instruction Set Listings
This appendix lists the MPCxxx’s instruction set. Instructions are sorted by mnemonic,
opcode, function, and form. Also included in this appendix is a quick reference table that
contains general information, such as the architecture level, privilege level, and form.
Note that split fields, which represent the concatenation of sequences from left to right,
are shown in lowercase.
Instructions Sorted by Mnemonic
Table 1 lists the instructions implemented in the MPCxxx in alphabetical order by
mnemonic.
Key:
Reserved bits
Table 1. Complete Instruction List Sorted by Mnemonic
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
addx
31
31
31
14
12
13
15
31
31
31
31
28
29
D
D
D
D
D
D
D
D
D
S
S
S
S
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
OE
OE
OE
266
10
Rc
Rc
Rc
addcx
addex
addi
138
SIMM
SIMM
SIMM
SIMM
addic
addic.
addis
addmex
addzex
andx
0 0 0 0 0
OE
OE
234
202
Rc
Rc
Rc
Rc
0 0 0 0 0
B
B
28
60
andcx
andi.
UIMM
UIMM
andis.
Motorola
MPCxxx INSTRUCTION SET
1
0
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
bx
18
16
19
19
31
11
31
10
31
19
19
19
19
19
19
19
19
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
19
LI
AA LK
AA LK
LK
bcx
bcctrx
bclrx
BO
BO
BO
BI
BD
BI
0 0 0 0 0
0 0 0 0 0
B
528
16
0
BI
LK
cmp
crfD
crfD
crfD
crfD
0
0
0
0
L
L
L
L
A
0
cmpi
A
SIMM
cmpl
A
B
32
0
cmpli
cntlzwx
crand
crandc
creqv
crnand
crnor
cror
A
UIMM
S
A
0 0 0 0 0
26
257
129
289
225
33
Rc
0
crbD
crbD
crbD
crbD
crbD
crbD
crbD
crbD
crbA
crbB
crbA
crbB
0
crbA
crbB
0
crbA
crbB
0
crbA
crbB
0
crbA
crbB
449
417
193
86
0
crorc
crxor
dcbf
crbA
crbB
0
crbA
crbB
0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
D
A
B
0
1
dcbi
A
B
470
54
0
dcbst
dcbt
A
B
0
A
B
278
246
1014
0
dcbtst
dcbz
A
B
0
A
B
0
divwx
divwux
eciwx
ecowx
eieio
A
B
OE
OE
491
459
310
Rc
Rc
0
D
A
B
D
A
B
B
S
A
438
854
284
954
922
982
150
0
0 0 0 0 0
S
0 0 0 0 0
0 0 0 0 0
B
0
eqvx
A
Rc
Rc
Rc
0
extsbx
extshx
icbi
S
A
0 0 0 0 0
0 0 0 0 0
B
S
A
A
0 0 0 0 0
0 0 0 0 0
isync
0 0 0 0 0
0 0 0 0 0
0
2
MPCxxx INSTRUCTION SET
Motorola
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
lbz
34
35
31
31
42
43
31
31
31
40
41
31
31
46
31
31
31
31
32
33
31
31
19
31
31
31
31
31
31
31
31
31
31
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
d
d
lbzu
lbzux
lbzx
lha
B
B
119
87
0
0
d
d
lhau
lhaux
lhax
lhbrx
lhz
B
B
B
375
343
790
0
0
0
d
d
lhzu
lhzux
lhzx
B
B
311
279
0
0
3
lmw
d
3
lswi
NB
B
597
533
20
0
0
0
0
3
lswx
lwarx
lwbrx
lwz
B
B
534
d
d
lwzu
lwzux
lwzx
B
55
23
0
0
0
0
0
0
0
0
0
0
0
0
0
B
mcrf
mcrxr
mfcr
crfD
crfD
0 0
0 0
crfS
0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
512
19
D
D
D
D
D
D
S
S
S
1
mfmsr
83
2
mfspr
spr
339
595
659
371
144
146
467
1
SR
mfsr
0
0
0 0 0 0 0
B
1
mfsrin
0 0 0 0 0
mftb
tbr
CRM
mtcrf
0
1
mtmsr
0 0 0 0 0
0 0 0 0 0
2
mtspr
spr
Motorola
MPCxxx INSTRUCTION SET
3
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
1
1
SR
mtsr
mtsrin
31
31
31
31
7
S
S
D
D
D
D
S
D
S
S
S
S
S
0
0 0 0 0 0
210
242
0
0 0 0 0 0
B
B
B
0
mulhwx
mulhwux
mulli
mullwx
nandx
negx
A
0
0
75
Rc
Rc
A
11
A
SIMM
31
31
31
31
31
31
24
25
19
20
21
23
17
31
31
31
31
38
39
31
31
44
31
45
31
31
47
31
A
B
OE
OE
235
Rc
Rc
Rc
Rc
Rc
Rc
A
B
476
104
124
A
0 0 0 0 0
norx
A
B
B
B
orx
A
444
412
orcx
A
ori
A
UIMM
UIMM
oris
A
1
rfi
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
50
0
rlwimix
rlwinmx
rlwnmx
sc
S
A
SH
SH
B
MB
MB
MB
ME
ME
ME
Rc
Rc
Rc
0
S
A
S
A
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
slwx
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
24
792
824
536
d
Rc
Rc
Rc
Rc
srawx
srawix
srwx
SH
B
stb
stbu
d
stbux
stbx
B
B
247
215
d
0
0
sth
sthbrx
sthu
B
918
0
d
sthux
sthx
B
B
439
407
d
0
0
3
stmw
3
stswi
NB
725
0
4
MPCxxx INSTRUCTION SET
Motorola
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
3
stswx
31
36
31
31
37
31
31
31
31
31
08
31
31
31
31
31
31
31
03
31
26
27
S
S
S
S
S
S
S
D
D
D
D
D
D
A
B
661
0
stw
stwbrx
stwcx.
stwu
A
d
d
A
B
B
662
150
0
1
A
A
stwux
stwx
A
B
B
B
B
B
183
151
0
A
0
subfx
A
OE
OE
OE
40
Rc
Rc
Rc
subfcx
subfex
subfic
subfmex
subfzex
sync
A
8
A
136
A
SIMM
A
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
B
OE
OE
232
200
Rc
Rc
0
A
0 0 0 0 0
0 0 0 0 0
598
1,4
tlbia
0 0 0 0 0
0 0 0 0 0
370
306
566
4
0
1,4
tlbie
0 0 0 0 0
0 0 0 0 0
0
1,4
tlbsync
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
B
0
tw
twi
TO
TO
S
A
A
A
A
A
0
SIMM
xorx
xori
xoris
B
316
Rc
S
UIMM
UIMM
S
1
2
3
4
Supervisor-level instruction
Supervisor- and user-level instruction
Load and store string or multiple instruction
PowerPC Optional instruction
Motorola
MPCxxx INSTRUCTION SET
5
Instructions Sorted by Opcode
Table 2 lists the instructions defined for the MPCxxx in numeric order by opcode.
Key:
Reserved bits
Table 2. Complete Instruction List Sorted by Opcode
Name
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
twi
0 0 0 0 1 1
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 0 1
TO
D
A
SIMM
SIMM
SIMM
UIMM
SIMM
SIMM
SIMM
SIMM
SIMM
mulli
subfic
cmpli
cmpi
addic
addic.
addi
A
D
A
crfD
crfD
0
0
L
L
A
A
D
D
D
D
A
A
A
addis
bcx
A
BI
BO
0 0 0 0 0
BD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AA LK
sc
0 0 0 0 0
1 0
bx
LI
AA LK
mcrf
bclrx
crnor
crfD
BO
0 0
crfS
0 0
0 0 0 0 0
0 0 0 0 0
crbB
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 0 1 1 0 0 1 0
0 0 1 0 0 0 0 0 0 1
0 0 1 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 1
0 0 1 1 1 0 0 0 0 1
0 1 0 0 0 0 0 0 0 1
0 1 0 0 1 0 0 0 0 1
0 1 1 0 1 0 0 0 0 1
0 1 1 1 0 0 0 0 0 1
1 0 0 0 0 1 0 0 0 0
0
LK
0
BI
crbD
0 0 0 0 0
crbD
0 0 0 0 0
crbD
crbD
crbD
crbD
crbD
crbD
BO
crbA
0 0 0 0 0
crbA
0 0 0 0 0
crbA
crbA
crbA
crbA
crbA
crbA
BI
1
rfi
0 0 0 0 0
crbB
0
crandc
isync
0
0 0 0 0 0
crbB
0
crxor
0
crnand
crand
creqv
crorc
crbB
0
crbB
0
crbB
0
crbB
0
cror
crbB
0
bcctrx
rlwimix
rlwinmx
0 0 0 0 0
SH
LK
Rc
Rc
S
A
MB
MB
ME
ME
S
A
SH
Motorola
MPCxxx INSTRUCTION SET
6
Name
rlwnmx
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 0 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
S
S
S
S
S
S
S
A
B
MB
ME
Rc
ori
oris
A
UIMM
UIMM
UIMM
UIMM
UIMM
UIMM
A
xori
A
xoris
A
andi.
A
andis.
cmp
A
crfD
0
L
A
B
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 1 0
0 0 0 0 0 0 1 0 1 1
0 0 0 0 0 1 0 0 1 1
0 0 0 0 0 1 0 1 0 0
0 0 0 0 0 1 0 1 1 1
0 0 0 0 0 1 1 0 0 0
0 0 0 0 0 1 1 0 1 0
0 0 0 0 0 1 1 1 0 0
0 0 0 0 1 0 0 0 0 0
0 0 0 0 1 0 1 0 0 0
0 0 0 0 1 1 0 1 1 0
0 0 0 0 1 1 0 1 1 1
0 0 0 0 1 1 1 1 0 0
0 0 0 1 0 0 1 0 1 1
0 0 0 1 0 1 0 0 1 1
0 0 0 1 0 1 0 1 1 0
0 0 0 1 0 1 0 1 1 1
0 0 0 1 1 0 1 0 0 0
0 0 0 1 1 1 0 1 1 1
0 0 0 1 1 1 1 1 0 0
0 0 1 0 0 0 1 0 0 0
0 0 1 0 0 0 1 0 1 0
0 0 1 0 0 1 0 0 0 0
0
0
tw
TO
D
D
D
D
D
D
S
A
B
subfcx
addcx
mulhwux
mfcr
A
B
OE
OE
0
Rc
Rc
Rc
0
A
B
A
B
0 0 0 0 0
0 0 0 0 0
lwarx
lwzx
A
B
0
A
B
0
slwx
A
B
Rc
Rc
Rc
0
cntlzwx
andx
S
A
0 0 0 0 0
S
A
B
cmpl
crfD
0
L
A
B
subfx
dcbst
lwzux
andcx
mulhwx
D
A
B
OE
Rc
0
0 0 0 0 0
A
B
D
A
B
0
S
A
B
Rc
Rc
0
D
A
B
0
1
mfmsr
D
0 0 0 0 0
0 0 0 0 0
dcbf
lbzx
0 0 0 0 0
A
A
A
A
A
A
A
B
0
D
D
D
S
D
D
S
B
0
negx
0 0 0 0 0
OE
Rc
0
lbzux
norx
B
B
B
B
Rc
Rc
Rc
0
subfex
addex
mtcrf
OE
OE
CRM
0
0
7
MPCxxx INSTRUCTION SET
Motorola
Name
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1
mtmsr
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
S
S
S
S
D
D
S
S
D
D
D
S
0 0 0 0 0
0 0 0 0 0
0 0 1 0 0 1 0 0 1 0
0 0 1 0 0 1 0 1 1 0
0 0 1 0 0 1 0 1 1 1
0 0 1 0 1 1 0 1 1 1
0 0 1 1 0 0 1 0 0 0
0 0 1 1 0 0 1 0 1 0
0 0 1 1 0 1 0 0 1 0
0 0 1 1 0 1 0 1 1 1
0 0 1 1 1 0 1 0 0 0
0 0 1 1 1 0 1 0 1 0
0 0 1 1 1 0 1 0 1 1
0 0 1 1 1 1 0 0 1 0
0 0 1 1 1 1 0 1 1 0
0 0 1 1 1 1 0 1 1 1
0 1 0 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 1 0
0 1 0 0 0 1 0 1 1 1
0 1 0 0 0 1 1 1 0 0
0 1 0 0 1 1 0 0 1 0
0 1 0 0 1 1 0 1 1 0
0 1 0 0 1 1 0 1 1 1
0 1 0 0 1 1 1 1 0 0
0 1 0 1 0 1 0 0 1 1
0 1 0 1 0 1 0 1 1 1
0 1 0 1 1 1 0 0 1 0
0 1 0 1 1 1 0 0 1 1
0 1 0 1 1 1 0 1 1 1
0 1 1 0 0 1 0 1 1 1
0 1 1 0 0 1 1 1 0 0
0 1 1 0 1 1 0 1 1 0
0 1 1 0 1 1 0 1 1 1
0 1 1 0 1 1 1 1 0 0
0 1 1 1 0 0 1 0 1 1
0
1
stwcx.
stwx
A
B
A
B
0
stwux
A
B
0
subfzex
addzex
A
0 0 0 0 0
OE
OE
Rc
Rc
0
A
0 0 0 0 0
1
SR
mtsr
0
0 0 0 0 0
stbx
subfmex
addmex
mullwx
A
B
0
A
0 0 0 0 0
OE
OE
OE
Rc
Rc
Rc
0
A
0 0 0 0 0
A
B
B
B
B
B
B
B
B
B
B
B
B
1
mtsrin
0 0 0 0 0
dcbtst
stbux
addx
dcbt
0 0 0 0 0
A
0
S
A
0
D
A
OE
Rc
0
0 0 0 0 0
A
lhzx
D
A
0
eqvx
S
A
Rc
0
1,4
tlbie
0 0 0 0 0
0 0 0 0 0
eciwx
lhzux
xorx
D
A
A
A
0
D
0
S
Rc
0
2
mfspr
D
spr
tbr
lhax
D
A
B
0
1,4
tlbia
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0
mftb
lhaux
sthx
D
D
S
S
S
S
S
D
0
A
A
A
A
A
A
A
B
B
B
B
B
B
B
0
0
orcx
Rc
0
ecowx
sthux
orx
0
Rc
Rc
divwux
OE
Motorola
MPCxxx INSTRUCTION SET
8
Name
mtspr
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
2
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 0
S
spr
0 1 1 1 0 1 0 0 1 1
0 1 1 1 0 1 0 1 1 0
0 1 1 1 0 1 1 1 0 0
0 1 1 1 1 0 1 0 1 1
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 0 1 0 1 1 1
1 0 0 0 0 1 1 0 0 0
1 0 0 0 1 1 0 1 1 0
1 0 0 1 0 1 0 0 1 1
1 0 0 1 0 1 0 1 0 1
1 0 0 1 0 1 0 1 1 0
1 0 0 1 0 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1
1 0 1 0 0 1 0 0 1 1
1 0 1 0 0 1 0 1 0 1
1 0 1 0 0 1 0 1 1 0
1 0 1 1 0 1 0 1 0 1
1 1 0 0 0 1 0 1 1 0
1 1 0 0 0 1 1 0 0 0
1 1 0 0 1 1 1 0 0 0
1 1 0 1 0 1 0 1 1 0
1 1 1 0 0 1 0 1 1 0
1 1 1 0 0 1 1 0 1 0
1 1 1 0 1 1 1 0 1 0
1 1 1 1 0 1 0 1 1 0
1 1 1 1 1 1 0 1 1 0
d
0
0
1
dcbi
0 0 0 0 0
A
B
nandx
divwx
mcrxr
S
D
A
B
Rc
Rc
0
A
B
OE
crfD
0 0
0 0 0 0 0
0 0 0 0 0
3
lswx
D
D
D
S
A
B
0
lwbrx
lfsx
A
B
0
A
A
B
0
srwx
B
Rc
0
1,4
tlbsync
0 0 0 0 0
0 0 0 0 0
SR
0 0 0 0 0
1
3
mfsr
lswi
D
0
0 0 0 0 0
0
D
A
NB
0
sync
lfdx
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0
D
A
B
0
lfdux
D
A
B
0
1
mfsrin
D
0 0 0 0 0
B
0
3
stswx
S
A
B
0
stwbrx
S
A
B
0
3
stswi
S
A
NB
0
lhbrx
srawx
srawix
eieio
sthbrx
extshx
extsbx
icbi
D
A
B
0
S
A
B
Rc
Rc
0
S
A
SH
0 0 0 0 0
B
0 0 0 0 0
0 0 0 0 0
S
A
A
A
A
A
A
A
A
A
A
0
S
0 0 0 0 0
0 0 0 0 0
B
Rc
Rc
0
S
0 0 0 0 0
dcbz
lwz
0 0 0 0 0
B
0
D
D
D
D
S
lwzu
lbz
d
d
lbzu
d
stw
d
9
MPCxxx INSTRUCTION SET
Motorola
Name
stwu
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 0 0 1 0 1
1 0 0 1 1 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1
S
S
S
D
D
D
D
S
S
D
S
A
A
A
A
A
A
A
A
A
A
A
d
d
d
d
d
d
d
d
d
d
d
stb
stbu
lhz
lhzu
lha
lhau
sth
sthu
3
lmw
3
stmw
1
2
3
4
Supervisor-level instruction
Supervisor- and user-level instruction
Load and store string or multiple instruction
PowerPC Optional instruction
Motorola
MPCxxx INSTRUCTION SET
10
Instructions Grouped by Functional Categories
Tables 3 through 30 list the PowerPC instructions grouped by function.
Key:
Reserved bits
Table 3. Integer Arithmetic Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
addx
31
31
31
14
12
13
15
31
31
31
31
31
31
07
31
31
31
31
08
31
31
31
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
OE
OE
OE
266
10
Rc
Rc
Rc
addcx
addex
138
addi
SIMM
SIMM
SIMM
SIMM
addic
addic.
addis
addmex
addzex
divwx
0 0 0 0 0
OE
OE
OE
OE
0
234
202
491
459
75
Rc
Rc
Rc
Rc
Rc
Rc
0 0 0 0 0
B
B
B
B
divwux
mulhwx
mulhwux
mulli
0
11
SIMM
mullwx
negx
B
OE
OE
OE
OE
235
104
40
Rc
Rc
Rc
Rc
0 0 0 0 0
subfx
B
B
subfcx
subficx
subfex
subfmex
subfzex
8
SIMM
B
OE
OE
OE
136
232
200
Rc
Rc
Rc
0 0 0 0 0
0 0 0 0 0
Motorola
MPCxxx INSTRUCTION SET
11
Table 4. Integer Compare Instructions
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
cmp
31
11
31
10
crfD
crfD
crfD
crfD
0
0
0
0
L
L
L
L
A
A
A
A
B
0 0 0 0 0 0 0 0 0 0
0
cmpi
cmpl
cmpli
SIMM
32
B
0
UIMM
Table 5. Integer Logical Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
andx
andcx
andi.
andis.
cntlzwx
eqvx
31
31
28
29
31
31
31
31
31
31
31
31
24
25
31
26
27
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
28
60
Rc
Rc
UIMM
UIMM
0 0 0 0 0
26
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
B
284
954
922
476
124
444
412
extsbx
extshx
nandx
norx
0 0 0 0 0
0 0 0 0 0
B
B
B
B
orx
orcx
ori
UIMM
UIMM
oris
xorx
B
316
Rc
xori
UIMM
UIMM
xoris
Table 6. Integer Rotate Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
rlwimix
rlwinmx
rlwnmx
22
20
21
S
S
S
A
A
A
SH
SH
SH
MB
MB
MB
ME
ME
ME
Rc
Rc
Rc
12
MPCxxx INSTRUCTION SET
Motorola
Table 7. Integer Shift Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
slwx
31
31
31
31
S
S
S
S
A
A
A
A
B
B
24
Rc
Rc
Rc
Rc
srawx
srawix
srwx
792
824
536
SH
B
Table 8. Integer Load Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
lbz
lbzu
lbzux
lbzx
lha
34
35
31
31
42
43
31
31
40
41
31
31
32
33
31
31
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
d
d
B
B
119
87
0
0
d
d
lhau
lhaux
lhax
lhz
B
B
375
343
0
0
d
d
lhzu
lhzux
lhzx
lwz
B
B
311
279
0
0
d
d
lwzu
lwzux
lwzx
B
B
55
23
0
0
Motorola
MPCxxx INSTRUCTION SET
13
Table 9. Integer Store Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
stb
38
39
31
31
44
45
31
31
36
37
31
31
S
S
S
S
S
S
S
S
S
S
S
S
A
A
A
A
A
A
A
A
A
A
A
A
d
d
stbu
stbux
stbx
B
B
247
215
0
0
sth
d
d
sthu
sthux
sthx
B
B
439
407
0
0
stw
d
d
stwu
stwux
stwx
B
B
183
151
0
0
Table 10. Integer Load and Store with Byte Reverse Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
lhbrx
31
31
31
31
D
D
S
S
A
A
A
A
B
B
B
B
790
534
918
662
0
0
0
0
lwbrx
sthbrx
stwbrx
Table 11. Integer Load and Store Multiple Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
3
lmw
46
47
D
S
A
A
d
d
3
stmw
Table 12. Integer Load and Store String Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
3
lswi
31
31
31
31
D
D
S
S
A
A
A
A
NB
B
597
533
725
661
0
0
0
0
3
lswx
3
stswi
NB
B
3
stswx
14
MPCxxx INSTRUCTION SET
Motorola
Table 13. Memory Synchronization Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
eieio
31
19
31
31
31
0 0 0 0 0
0 0 0 0 0
D
0 0 0 0 0
0 0 0 0 0
A
0 0 0 0 0
0 0 0 0 0
B
854
150
20
0
0
0
1
0
isync
lwarx
stwcx.
sync
S
A
B
150
598
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Table 14. Branch Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
bx
bcx
18
16
19
19
LI
AA LK
AA LK
LK
BO
BO
BO
BI
BI
BI
BD
bcctrx
bclrx
0 0 0 0 0
0 0 0 0 0
528
16
LK
Table 15. Condition Register Logical Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
crand
crandc
creqv
crnand
crnor
cror
19
19
19
19
19
19
19
19
19
crbD
crbD
crbD
crbD
crbD
crbD
crbD
crbD
crbA
crbA
crbA
crbA
crbA
crbA
crbA
crbA
crbB
crbB
257
0
0
0
0
0
0
0
0
0
129
crbB
289
crbB
225
crbB
33
crbB
449
crorc
crxor
mcrf
crbB
417
193
crbB
crfD
0 0
crfS
0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
Table 16. System Linkage Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
1
rfi
19
17
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
50
0
0
sc
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Motorola
MPCxxx INSTRUCTION SET
15
Table 17. Trap Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
tw
twi
31
03
TO
TO
A
A
B
4
0
SIMM
Table 18. Processor Control Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
mcrxr
31
crfS
0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
512
19
0
0
0
0
0
0
0
0
mfcr
31
31
31
31
31
31
31
D
D
D
D
S
S
D
1
mfmsr
83
2
mfspr
spr
tpr
339
371
144
146
467
mftb
CRM
mtcrf
0
0
1
mtmsr
0 0 0 0 0
0 0 0 0 0
2
mtspr
spr
Table 19. Cache Management Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
dcbf
31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
A
A
A
A
A
A
A
B
B
B
B
B
B
B
86
470
54
0
0
0
0
0
0
0
1
dcbi
31
31
31
31
31
31
dcbst
dcbt
278
246
1014
982
dcbtst
dcbz
icbi
Table 20. Lookaside Buffer Management Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
1,4
1,4
1,4
tlbia
tlbie
31
31
31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
B
370
306
566
0
0
0
tlbsync
0 0 0 0 0
16
MPCxxx INSTRUCTION SET
Motorola
Table 21. External Control Instructions
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
eciwx
ecowx
31
31
D
S
A
A
B
B
310
438
0
0
1
Supervisor-level instruction
Supervisor- and user-level instruction
Load and store string or multiple instruction
2
3
Motorola
MPCxxx INSTRUCTION SET
17
Instructions Sorted by Form
Tables 23 through 32 list the MPCxxx instructions grouped by form.
Key:
Reserved bits
AA LK
Table 23. I-Form
OPCD
LI
Specific Instruction
Name
bx
0
0
0
5
5
5
6
6
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
18
LI
AA LK
Table 24. B-Form
OPCD
BO
BI
BD
AA LK
Specific Instruction
Name
bcx
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16
BO
BI
BD
AA LK
Table 25. SC-Form
OPCD
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0
Specific Instruction
Name
sc
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
17
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0
Table 26. D-Form
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
D
D
S
S
A
A
A
A
A
A
A
d
SIMM
d
UIMM
SIMM
UIMM
SIMM
crfD
crfD
0
0
L
L
TO
Motorola
MPCxxx INSTRUCTION SET
19
Specific Instructions
Name
addi
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
14
12
13
15
28
29
11
10
34
35
42
43
40
41
46
32
33
7
D
D
D
D
S
S
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
SIMM
addic
addic.
addis
andi.
andis.
cmpi
cmpli
lbz
SIMM
SIMM
SIMM
UIMM
UIMM
crfD
crfD
0
0
L
L
SIMM
UIMM
D
D
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
S
D
d
lbzu
d
lha
d
lhau
lhz
d
d
lhzu
d
3
lmw
d
lwz
lwzu
mulli
ori
d
d
SIMM
UIMM
UIMM
d
24
25
38
39
44
45
47
36
37
08
03
26
27
oris
stb
stbu
sth
d
d
sthu
d
3
stmw
d
stw
stwu
subfic
twi
d
d
SIMM
SIMM
UIMM
UIMM
TO
S
xori
xoris
S
Table 27 DS-Form
20
MPCxxx INSTRUCTION SET
Motorola
Table 28. X-Form
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
OPCD
D
D
D
D
D
S
S
S
S
S
S
S
S
S
A
A
B
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
XO
0
0
NB
0 0 0 0 0
0 0 0 0 0
SR
B
0 0 0 0 0
0 0 0 0 0
B
0
0
0
0
A
Rc
1
A
B
A
B
0
A
A
NB
0
0 0 0 0 0
B
Rc
0
0 0 0 0 0
0 0 0 0 0
SR
0 0 0 0 0
0 0 0 0 0
SH
0
0
0
A
A
A
Rc
0
crfD
crfD
crfD
crfD
crfD
0
L
B
0 0
B
0
0 0
0 0
0 0
crfS
0 0
0 0 0 0 0
0 0 0 0 0
IMM
0
0 0 0 0 0
0 0 0 0 0
A
0
0
Rc
0
TO
D
B
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
A
B
Rc
Rc
Rc
0
D
0 0 0 0 0
0 0 0 0 0
B
crbD
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
B
0
0 0 0 0 0
0
Specific Instructions
andx
andcx
cmp
31
31
31
31
31
31
S
S
A
B
B
B
B
28
60
0
Rc
Rc
0
A
A
A
crfD
crfD
0
0
L
L
cmpl
32
26
86
0
cntlzwx
dcbf
S
A
A
0 0 0 0 0
B
Rc
0
0 0 0 0 0
Motorola
MPCxxx INSTRUCTION SET
21
1
dcbi
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
0 0 0 0 0
A
B
470
54
0
0
dcbst
dcbt
0 0 0 0 0
A
B
0 0 0 0 0
A
B
278
246
1014
310
438
854
284
954
922
982
119
87
0
dcbtst
dcbz
eciwx
ecowx
eieio
eqvx
0 0 0 0 0
A
B
0
0 0 0 0 0
A
B
0
D
A
B
0
S
A
B
0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0
S
A
B
Rc
Rc
Rc
0
extsbx
extshx
icbi
S
A
0 0 0 0 0
S
A
0 0 0 0 0
0 0 0 0 0
A
B
lbzux
lbzx
D
D
D
D
D
D
D
D
D
D
D
D
D
A
B
0
A
B
0
lhaux
lhax
A
B
375
343
790
311
279
597
533
20
0
A
B
0
lhbrx
lhzux
lhzx
A
B
0
A
B
0
A
B
0
3
lswi
A
NB
0
3
lswx
A
B
0
lwarx
lwbrx
lwzux
lwzx
A
B
0
A
A
B
534
55
0
B
B
0
A
23
0
mcrxr
mfcr
crfD
0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
SR
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
B
512
19
0
D
D
D
D
S
S
S
S
S
0
1
mfmsr
83
0
1
mfsr
0
0
595
659
146
210
242
476
124
0
1
mfsrin
0 0 0 0 0
0 0 0 0 0
SR
0
1
mtmsr
0 0 0 0 0
0 0 0 0 0
B
0
1
mtsr
0
1
mtsrin
0 0 0 0 0
0
nandx
norx
A
A
B
Rc
Rc
B
22
MPCxxx INSTRUCTION SET
Motorola
orx
orcx
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
S
A
B
444
412
24
Rc
Rc
Rc
Rc
Rc
Rc
0
S
A
B
slwx
S
A
B
srawx
srawix
srwx
S
A
B
792
824
536
247
215
918
439
407
725
661
662
150
183
151
598
370
306
566
4
S
A
SH
S
A
B
stbux
stbx
S
A
B
S
A
B
0
sthbrx
sthux
sthx
S
A
B
0
S
A
B
0
S
A
B
0
3
stswi
S
A
NB
0
3
stswx
S
A
B
0
stwbrx
stwcx.
stwux
stwx
S
A
B
0
S
S
A
B
1
A
A
B
0
S
B
0
sync
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
TO
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
A
0 0 0 0 0
0
1,4
tlbia
0 0 0 0 0
0
1,4
tlbie
B
0
1,4
tlbsync
0 0 0 0 0
0
tw
B
B
0
xorx
S
A
316
Rc
Table 29. XL-Form
OPCD
OPCD
OPCD
OPCD
BO
BI
0 0 0 0 0
crbB
XO
LK
crbD
crbA
XO
XO
XO
0
0
0
crfD
0 0
crfS
0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Specific Instructions
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
0
5
6
7
8
bcctrx
bclrx
19
19
19
BO
BO
BI
BI
0 0 0 0 0
0 0 0 0 0
crbB
528
16
LK
LK
0
crand
crbD
crbA
257
Motorola
MPCxxx INSTRUCTION SET
23
crandc
creqv
crnand
crnor
cror
19
19
19
19
19
19
19
19
19
19
crbD
crbD
crbA
crbA
crbB
crbB
129
289
225
33
0
0
0
0
0
0
0
0
0
0
crbD
crbA
crbB
crbD
crbA
crbB
crbD
crbA
crbB
449
417
193
150
0
crorc
crxor
isync
mcrf
crbD
crbA
crbB
crbD
crbA
crbB
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
crfD
0 0
crfS
0 0
1
rfi
0 0 0 0 0
0 0 0 0 0
50
24
MPCxxx INSTRUCTION SET
Motorola
Table 30. XFX-Form
OPCD
OPCD
OPCD
OPCD
D
D
S
D
spr
XO
XO
XO
XO
0
0
0
0
CRM
spr
tbr
0
0
Specific Instructions
Name
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
2
mfspr
31
31
31
31
D
D
S
D
spr
tbr
339
371
144
467
0
0
0
0
mftb
CRM
mtcrf
0
0
2
mtspr
spr
Table 31. XO-Form
OPCD
OPCD
OPCD
D
D
D
A
A
A
B
B
OE
0
XO
Rc
Rc
Rc
XO
XO
0 0 0 0 0
OE
Specific Instructions
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
addx
0
5
6
7
8
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
OE
OE
OE
OE
OE
OE
OE
0
266
10
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
addcx
addex
B
B
138
234
202
491
459
75
addmex
addzex
divwx
0 0 0 0 0
0 0 0 0 0
B
divwux
mulhwx
mulhwux
mullwx
negx
B
B
B
0
11
B
OE
OE
OE
OE
OE
OE
OE
235
104
40
0 0 0 0 0
subfx
B
B
subfcx
subfex
subfmex
subfzex
8
B
136
232
200
0 0 0 0 0
0 0 0 0 0
Motorola
MPCxxx INSTRUCTION SET
25
Table 32. M-Form
OPCD
OPCD
S
S
A
A
SH
B
MB
MB
ME
ME
Rc
Rc
Specific Instructions
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
0
5
6
7
8
rlwimix
rlwinmx
rlwnmx
20
21
23
S
S
S
A
A
A
SH
SH
B
MB
MB
MB
ME
ME
ME
Rc
Rc
Rc
1
Supervisor-level instruction
2
3
4
Supervisor- and user-level instruction
Load and store string or multiple instruction
PowerPC Optional instruction
26
MPCxxx INSTRUCTION SET
Motorola
Instruction Set Legend
Table 33 provides general information on the MPCxxx instruction set (such as the
architectural level, privilege level, and form).
Table 33. MPCxxx Instruction Set Legend
VEA
OEA
Supervisor
Level
UISA
Optional
Form
addx
addcx
addex
addi
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
XO
XO
XO
D
addic
addic.
addis
addmex
addzex
andx
D
D
D
XO
XO
X
andcx
andi.
X
D
andis.
bx
D
I
bcx
B
bcctrx
bclrx
XL
XL
X
cmp
cmpi
D
cmpl
X
cmpli
cntlzwx
crand
crandc
creqv
crnand
crnor
D
X
XL
XL
XL
XL
XL
Motorola
MPCxxx INSTRUCTION SET
27
VEA
OEA
Supervisor
Level
UISA
Optional
Form
cror
crorc
crxor
dcbf
√
√
√
XL
XL
XL
X
√
dcbi
√
√
X
dcbst
dcbt
√
√
√
√
X
X
dcbtst
dcbz
X
X
divwx
divwux
eciwx
ecowx
eieio
√
√
XO
XO
X
√
√
√
√
√
X
X
eqvx
√
√
X
extsbx
extshx
X
√
X
VEA
OEA
Supervisor
Level
UISA
Optional
Form
icbi
isync
lbz
√
√
X
XL
D
√
lbzu
lbzux
lbzx
√
√
D
X
√
X
VEA
OEA
Supervisor
Level
UISA
Optional
Form
lha
lhau
lhaux
lhax
lhbrx
lhz
√
√
√
√
√
√
√
D
D
X
X
X
D
D
lhzu
28
MPCxxx INSTRUCTION SET
Motorola
lhzux
lhzx
√
√
√
√
√
√
√
√
√
√
√
√
√
√
X
X
2
lmw
D
2
lswi
X
2
lswx
X
lwarx
lwbrx
lwz
X
X
D
lwzu
D
lwzux
lwzx
X
X
mcrf
XL
X
mcrxr
mfcr
X
mfmsr
√
√
√
√
√
√
√
√
X
1
mfspr
√
XFX
X
mfsr
√
3
mfsr
√
√
X
mfsrin
√
X
3
mfsrin
√
√
X
VEA
OEA
Supervisor
Level
UISA
Optional
Form
mftb
mtcrf
√
XFX
XFX
X
√
mtmsr
√
√
√
√
√
√
√
√
√
√
√
√
√
√
3
mtmsr
√
X
1
mtspr
√
XFX
X
mtsr
3
mtsr
√
√
X
mtsrin
X
3
mtsrin
X
mulhwx
mulhwux
mulli
√
√
√
√
XO
XO
D
mullwx
XO
Motorola
MPCxxx INSTRUCTION SET
29
nandx
negx
norx
orx
√
√
√
√
√
√
√
X
XO
X
X
orcx
ori
X
D
oris
rfi
D
√
√
√
√
XL
XL
M
3
rfi
√
rlwimix
rlwinmx
rlwnmx
√
√
M
√
M
VEA
OEA
Supervisor
Level
UISA
Optional
Form
sc
slwx
√
√
SC
X
√
srawx
srawix
srwx
stb
√
X
√
X
√
X
√
D
stbu
√
D
stbux
stbx
√
X
√
X
sth
√
D
sthbrx
sthu
√
X
√
√
D
sthux
sthx
X
√
X
VEA
OEA
Supervisor
Level
UISA
Optional
Form
2
stmw
√
√
√
√
√
√
D
X
X
D
X
X
2
stswi
2
stswx
stw
stwbrx
stwcx.
30
MPCxxx INSTRUCTION SET
Motorola
stwu
stwux
stwx
√
√
√
√
√
√
√
√
√
√
D
X
X
subfx
subfcx
subfex
subfic
subfmex
subfzex
sync
XO
XO
XO
D
XO
XO
X
tlbia
√
√
√
√
√
√
√
√
X
tlbie
X
tlbsync
tw
X
√
√
√
√
√
X
twi
D
xorx
X
xori
D
xoris
D
1
2
3
Supervisor- and user-level instruction
Load and store string or multiple instruction
PowerPC Optional instruction
Motorola
MPCxxx INSTRUCTION SET
31
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