89S52 [ETC]
ATmel89S52;
| 型号： | 89S52 |
| 厂家： | 
ETC |
| 描述： | ATmel89S52 |
| 文件： | 总30页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS-51® Products
• 8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
• Dual Data Pointer
• Power-off Flag
Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on
a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
AT89S52
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a
six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S52 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next interrupt
or hardware reset.
Preliminary
Rev. 1919A-07/01
Pin Configurations
PDIP
PLCC
(T2) P1.0
(T2 EX) P1.1
P1.2
1
2
3
4
5
6
7
8
9
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
P1.3
P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
7
8
9
39 P0.4 (AD4)
38 P0.5 (AD5)
37 P0.6 (AD6)
36 P0.7 (AD7)
35 EA/VPP
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
RST 10
(RXD) P3.0 11
NC 12
(RXD) P3.0 10
(TXD) P3.1 11
(INT0) P3.2 12
(INT1) P3.3 13
(T0) P3.4 14
(T1) P3.5 15
(WR) P3.6 16
(RD) P3.7 17
XTAL2 18
34 NC
30 ALE/PROG
29 PSEN
(TXD) P3.1 13
(INT0) P3.2 14
(INT1) P3.3 15
(T0) P3.4 16
(T1) P3.5 17
33 ALE/PROG
32 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
31 P2.7 (A15)
30 P2.6 (A14)
29 P2.5 (A13)
XTAL1 19
GND 20
TQFP
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
1
2
3
4
5
6
7
8
9
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 EA/VPP
(RXD) P3.0
NC
28 NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
27 ALE/PROG
26 PSEN
25 P2.7 (A15)
24 P2.6 (A14)
23 P2.5 (A13)
(T0) P3.4 10
(T1) P3.5 11
AT89S52
2
AT89S52
Block Diagram
P0.0 - P0.7
P2.0 - P2.7
VCC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
PORT 0
LATCH
PORT 2
LATCH
RAM
FLASH
PROGRAM
ADDRESS
REGISTER
B
STACK
POINTER
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DUAL DPTR
WATCH
DOG
PORT 3
LATCH
PORT 1
LATCH
ISP
PORT
OSC
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1 DRIVERS
P1.0 - P1.7
3
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pull-
ups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external
program and data memory. In this mode, P0 has internal
pullups.
Port 3 also serves the functions of various special features
of the AT89S52, as shown in the following table.
Port 0 also receives the code bytes during Flash program-
ming and outputs the code bytes during program verifica-
tion. External pullups are required during program
verification.
Port 3 also receives some control signals for Flash pro-
gramming and verification.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
Port 1
RXD (serial input port)
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during
Flash programming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device. This pin drives
High for 96 oscillator periods after the Watchdog times out.
The DISRTO bit in SFR AUXR (address 8EH) can be used
to disable this feature. In the default state of bit DISRTO,
the RESET HIGH out feature is enabled.
Port Pin
Alternate Functions
P1.0
T2 (external count input to Timer/Counter 2),
clock-out
P1.1
T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
P1.5
P1.6
P1.7
MOSI (used for In-System Programming)
MISO (used for In-System Programming)
SCK (used for In-System Programming)
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching
the low byte of the address during accesses to external
memory. This pin is also the program pulse input (PROG)
during Flash programming.
Port 2
In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency and may be used for external
timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external data
memory.
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
AT89S52
4
AT89S52
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions.
PSEN
Program Store Enable (PSEN) is the read strobe to exter-
nal program memory.
This pin also receives the 12-volt programming enable volt-
age (VPP) during Flash programming.
When the AT89S52 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
EA/VPP
XTAL2
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Output from the inverting oscillator amplifier.
Table 1. AT89S52 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
B
0F0H
00000000
0E8H
ACC
0E0H
00000000
0D8H
PSW
0D0H
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
AUXR1
XXXXXXX0
WDTRST
XXXXXXXX
SCON
00000000
SBUF
XXXXXXXX
P1
11111111
90H
97H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
AUXR
XXX00XX0
88H
8FH
P0
11111111
SP
00000111
DP0L
00000000
DP0H
00000000
DP1L
00000000
DP1H
00000000
PCON
0XXX0000
80H
87H
5
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
Timer 2 Registers: Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap-
ture mode or 16-bit auto-reload mode.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
Interrupt Registers: The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Table 2. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H
Reset Value = 0000 0000B
Bit Addressable
Bit
TF2
7
EXF2
6
RCLK
5
TCLK
4
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Symbol Function
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1
or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
TCLK
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer
2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
AT89S52
6
AT89S52
Table 3a. AUXR: Auxiliary Register
AUXR
Address = 8EH
Reset Value = XXX00XX0B
Not Bit Addressable
–
–
–
WDIDLE
4
DISRTO
3
–
–
DISALE
0
Bit
7
6
5
2
1
–
Reserved for future expansion
Disable/Enable ALE
DISALE
DISALE
Operating Mode
0
1
ALE is emitted at a constant rate of 1/6 the oscillator frequency
ALE is active only during a MOVX or MOVC instruction
DISRTO
WDIDLE
Disable/Enable Reset out
DISRTO
0
1
Reset pin is driven High after WDT times out
Reset pin is input only
Disable/Enable WDT in IDLE mode
WDIDLE
0
1
WDT continues to count in IDLE mode
WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both
internal and external data memory, two banks of 16-bit
Data Pointer Registers are provided: DP0 at SFR address
locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0
in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the
appropriate value before accessing the respective Data
Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit
4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and rest under software control and
is not affected by reset.
Table 3b. AUXR1: Auxiliary Register 1
AUXR1
Address = A2H
Reset Value = XXXXXXX0B
Not Bit Addressable
–
–
–
–
–
–
–
DPS
0
Bit
7
6
5
4
3
2
1
–
Reserved for future expansion
Data Pointer Register Select
DPS
DPS
0
1
Selects DPTR Registers DP0L, DP0H
Selects DPTR Registers DP1L, DP1H
7
Memory Organization
MCS-51 devices have a separate address space for Pro-
gram and Data Memory. Up to 64K bytes each of external
Program and Data Memory can be addressed.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions which use direct
addressing access of the SFR space.
Program Memory
If the EA pin is connected to GND, all program fetches are
directed to external memory.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
On the AT89S52, if EA is connected to VCC, program
fetches to addresses 0000H through 1FFFH are directed to
internal memory and fetches to addresses 2000H through
FFFFH are to external memory.
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. This means that the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
MOV @R0, #data
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
AT89S52
8
AT89S52
To ensure that the WDT does not overflow within a few
states of exiting Power-down, it is best to reset the WDT
just before entering Power-down mode.
Watchdog Timer
(One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations
where the CPU may be subjected to software upsets. The
WDT consists of a 13-bit counter and the Watchdog Timer
Reset (WDTRST) SFR. The WDT is defaulted to disable
from exiting reset. To enable the WDT, a user must write
01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, it will
increment every machine cycle while the oscillator is run-
ning. The WDT timeout period is dependent on the external
clock frequency. There is no way to disable the WDT
except through reset (either hardware reset or WDT over-
flow reset). When WDT overflows, it will drive an output
RESET HIGH pulse at the RST pin.
Before going into the IDLE mode, the WDIDLE bit in SFR
AUXR is used to determine whether the WDT continues to
count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT
from resetting the AT89S52 while in IDLE mode, the user
should always set up a timer that will periodically exit IDLE,
service the WDT, and reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in
IDLE mode and resumes the count upon exit from IDLE.
UART
The UART in the AT89S52 operates the same way as the
UART in the AT89C51 and AT89C52. For further informa-
tion on the UART operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select ‘Prod-
ucts’, then ‘8051-Architecture Flash Microcontroller’, then
‘Product Overview’.
Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in
sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, the user needs to service it by
writing 01EH and 0E1H to WDTRST to avoid a WDT over-
flow. The 13-bit counter overflows when it reaches 8191
(1FFFH), and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the
oscillator is running. This means the user must reset the
WDT at least every 8191 machine cycles. To reset the
WDT the user must write 01EH and 0E1H to WDTRST.
WDTRST is a write-only register. The WDT counter cannot
be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST pin. The RESET pulse
duration is 96xTOSC, where TOSC=1/FOSC. To make the
best use of the WDT, it should be serviced in those sec-
tions of code that will periodically be executed within the
time required to prevent a WDT reset.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way
as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For
further information on the timers’ operation, refer to the
ATMEL Web site (http://www.atmel.com). From the home
page, select ‘Products’, then ‘8051-Architecture Flash
Microcontroller’, then ‘Product Overview’.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscil-
lator periods, the count rate is 1/12 of the oscillator
frequency.
WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the
WDT also stops. While in Power-down mode, the user
does not need to service the WDT. There are two methods
of exiting Power-down mode: by a hardware reset or via a
level-activated external interrupt which is enabled prior to
entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it
normally does whenever the AT89S52 is reset. Exiting
Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabi-
lize. When the interrupt is brought high, the interrupt is
serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started
until the interrupt is pulled high. It is suggested that the
WDT be reset during the interrupt service for the interrupt
used to exit Power-down mode.
Table 3. Timer 2 Operating Modes
RCLK +TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-reload
16-bit Capture
Baud Rate Generator
(Off)
1
X
X
1
0
9
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transi-
tion, the maximum count rate is 1/24 of the oscillator fre-
quency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a 1-
to-0 transition at external input T2EX also causes the
current value in TH2 and TL2 to be captured into RCAP2H
and RCAP2L, respectively. In addition, the transition at
T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,
like TF2, can generate an interrupt. The capture mode is
illustrated in Figure 5.
Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.
Capture Mode
In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
Figure 5. Timer in Capture Mode
÷12
OSC
C/T2 = 0
C/T2 = 1
TH2
TL2
TF2
OVERFLOW
CONTROL
TR2
CAPTURE
T2 PIN
RCAP2H RCAP2L
EXF2
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
T2EX PIN
CONTROL
EXEN2
Figure 6 shows Timer 2 automatically counting up when
DCEN=0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The
overflow also causes the timer registers to be reloaded with
the 16-bit value in RCAP2H and RCAP2L. The values in
Timer in Capture ModeRCAP2H and RCAP2L are preset
by software. If EXEN2 = 1, a 16-bit reload can be triggered
either by an overflow or by a 1-to-0 transition at external
input T2EX. This transition also sets the EXF2 bit. Both the
TF2 and EXF2 bits can generate an interrupt if enabled.
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in
RCAP2H and RCAP2L to be reloaded into the timer regis-
ters, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.
Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 6. In this mode, the T2EX pin controls
AT89S52
10
AT89S52
Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)
÷12
OSC
C/T2 = 0
TH2
TL2
OVERFLOW
CONTROL
TR2
C/T2 = 1
RELOAD
T2 PIN
TIMER 2
INTERRUPT
RCAP2H RCAP2L
TF2
TRANSITION
DETECTOR
EXF2
T2EX PIN
CONTROL
EXEN2
Table 4. T2MOD – Timer 2 Mode Control Register
T2MOD Address = 0C9H
Not Bit Addressable
Reset Value = XXXX XX00B
–
–
–
–
–
–
T2OE
1
DCEN
0
Bit
7
6
5
4
3
2
Symbol
–
Function
Not implemented, reserved for future
Timer 2 Output Enable bit
T2OE
DCEN
When set, this bit allows Timer 2 to be configured as an up/down counter
11
Figure 7. Timer 2 Auto Reload Mode (DCEN = 1)
TOGGLE
(DOWN COUNTING RELOAD VALUE)
0FFH 0FFH
EXF2
OSC
÷12
OVERFLOW
C/T2 = 0
TH2
TL2
TF2
CONTROL
TR2
TIMER 2
INTERRUPT
C/T2 = 1
T2 PIN
RCAP2H RCAP2L
(UP COUNTING RELOAD VALUE)
COUNT
DIRECTION
1=UP
0=DOWN
T2EX PIN
Figure 8. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW
2
÷
"0"
"0"
"1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1
RCLK
2
OSC
÷
C/T2 = 0
"1"
"1"
TH2
TL2
Rx
CLOCK
CONTROL
TR2
÷16
C/T2 = 1
"0"
T2 PIN
TCLK
RCAP2H RCAP2L
Tx
CLOCK
TRANSITION
DETECTOR
16
÷
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
AT89S52
12
AT89S52
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the
baud rates for transmit and receive can be different if Timer
2 is used for the receiver or transmitter and Timer 1 is used
for the other function. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode, as shown in Fig-
ure 8.
increments every state time (at 1/2 the oscillator fre-
quency). The baud rate formula is given below.
Modes 1 and 3
Oscillator Frequency
--------------------------------------- = -------------------------------------------------------------------------------------
Baud Rate 32 x [65536-RCAP2H,RCAP2L)]
The baud rate generator mode is similar to the auto-reload
mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.
where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 8. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not gener-
ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0
transition in T2EX will set EXF2 but will not cause a reload
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer
2 is in use as a baud rate generator, T2EX can be used as
an extra external interrupt.
The baud rates in Modes 1 and 3 are determined by Timer
2’s overflow rate according to the following equation.
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates = -----------------------------------------------------------
16
Note that when Timer 2 is running (TR2 = 1) as a timer in
the baud rate generator mode, TH2 or TL2 should not be
read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or
write may not be accurate. The RCAP2 registers may be
read but should not be written to, because a write might
overlap a reload and cause write and/or reload errors. The
timer should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
The Timer can be configured for either timer or counter
operation. In most applications, it is configured for timer
operation (CP/T2 = 0). The timer operation is different for
Timer 2 when it is used as a baud rate generator. Normally,
as a timer, it increments every machine cycle (at 1/12 the
oscillator frequency). As a baud rate generator, however, it
Figure 9. Timer 2 in Clock-Out Mode
TL2
TH2
÷2
OSC
(8-BITS) (8-BITS)
TR2
RCAP2L RCAP2H
C/T2 BIT
P1.0
(T2)
÷2
T2OE (T2MOD.1)
TRANSITION
DETECTOR
P1.1
(T2EX)
TIMER 2
INTERRUPT
EXF2
EXEN2
13
Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 9. This pin, besides being a regu-
lar I/O pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 4
MHz at a 16 MHz operating frequency.
Table 5. Interrupt Enable (IE) Register
(MSB)
(LSB)
EX0
EA
–
ET2
ES
ET1
EX1
ET0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
To configure the Timer/Counter 2 as a clock generator, bit
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer.
Symbol
Position
Function
EA
IE.7
Disables all interrupts. If EA = 0,
no interrupt is acknowledged. If
EA = 1, each interrupt source is
individually enabled or disabled
by setting or clearing its enable
bit.
The clock-out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
Oscillator Frequency
Clock-Out Frequency = ------------------------------------------------------------------------------------
4 x [65536-(RCAP2H,RCAP2L)]
–
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Reserved.
ET2
ES
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
In the clock-out mode, Timer 2 roll-overs will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock generator simulta-
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.
ET1
EX1
ET0
EX0
User software should never write 1s to unimplemented bits,
because they may be used in future AT89 products.
Interrupts
The AT89S52 has a total of six interrupt vectors: two exter-
nal interrupts (INT0 and INT1), three timer interrupts (Tim-
ers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Figure 10. Interrupt Sources
0
INT0
IE0
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
1
Note that Table 5 shows that bit position IE.6 is unimple-
mented. In the AT89S52, bit position IE.5 is also unimple-
mented. User software should not write 1s to these bit
positions, since they may be used in future AT89 products.
TF0
0
1
INT1
IE1
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
TF1
TI
RI
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
TF2
EXF2
AT89S52
14
AT89S52
active long enough to allow the oscillator to restart
and stabilize.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 11. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 12.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Figure 11. Oscillator Connections
C2
XTAL2
C1
XTAL1
Idle Mode
GND
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note:
C1, C2 = 30 pF 10 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators
Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution
from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to exter-
nal memory.
Figure 12. External Clock Drive Configuration
NC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
Power-down Mode
In the Power-down mode, the oscillator is stopped, and the
instruction that invokes Power-down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the Power-down mode is termi-
nated. Exit from Power-down mode can be initiated either
by a hardware reset or by an enabled external interrupt.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held
Table 6. Status of External Pins During Idle and Power-down Modes
Mode
Program Memory
Internal
ALE
PSEN
PORT0
Data
PORT1
Data
PORT2
Data
PORT3
Data
Idle
1
1
0
0
1
1
0
0
Idle
External
Float
Data
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
External
Float
Data
Data
Data
15
Repeat steps 1 through 5, changing the address
and data for the entire array or until the end of the
object file is reached.
Program Memory Lock Bits
The AT89S52 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table.
Data Polling: The AT89S52 features Data Polling to indi-
cate the end of a byte write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P0.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Table 7. Lock Bit Protection Modes
Program Lock Bits
LB1
U
LB2
U
LB3
U
Protection Type
1
2
No program lock features
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.0 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.0 is pulled high again when programming is
done to indicate READY.
P
U
U
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
internal memory, EA is
sampled and latched on reset,
and further programming of
the Flash memory is disabled
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The status of
the individual lock bits can be verified directly by reading
them back.
3
4
P
P
P
P
U
P
Same as mode 2, but verify is
also disabled
Same as mode 3, but external
execution is also disabled
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 100H, and 200H, except that P3.6 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 52H indicates 89S52
(200H) = 06H
Chip Erase: In the parallel programming mode, a chip
erase operation is initiated by using the proper combination
of control signals and by pulsing ALE/PROG low for a dura-
tion of 200 ns - 500 ns.
Programming the Flash – Parallel Mode
The AT89S52 is shipped with the on-chip Flash memory
array ready to be programmed. The programming interface
needs a high-voltage (12-volt) program enable signal and
is compatible with conventional third-party Flash or
EPROM programmers.
In the serial programming mode, a chip erase operation is
initiated by issuing the Chip Erase instruction. In this mode,
chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location
will return 00H at the data output.
The AT89S52 code memory array is programmed byte-by-
byte.
Programming Algorithm: Before programming the
AT89S52, the address, data, and control signals should be
set up according to the Flash programming mode table and
Figures 13 and 14. To program the AT89S52, take the fol-
lowing steps:
Programming the Flash – Serial Mode
The Code memory array can be programmed using the
serial ISP interface while RST is pulled to VCC. The serial
interface consists of pins SCK, MOSI (input) and MISO
(output). After RST is set high, the Programming Enable
instruction needs to be executed first before other opera-
tions can be executed. Before a reprogramming sequence
can occur, a Chip Erase operation is required.
1. Input the desired memory location on the address
lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
The Chip Erase operation turns the content of every mem-
ory location in the Code array into FFH.
5. Pulse ALE/PROG once to program a byte in the
Flash array or the lock bits. The byte-write cycle is
self-timed and typically takes no more than 50 µs.
Either an external system clock can be supplied at pin
XTAL1 or a crystal needs to be connected across pins
XTAL1 and XTAL2. The maximum serial clock (SCK)
AT89S52
16
AT89S52
frequency should be less than 1/16 of the crystal fre-
quency. With a 33 MHz oscillator clock, the maximum SCK
frequency is 2 MHz.
appropriate Write instruction. The write cycle is self-
timed and typically takes less than 1 ms at 5V.
4. Any memory location can be verified by using the
Read instruction which returns the content at the
selected address at serial output MISO/P1.6.
Serial Programming Algorithm
5. At the end of a programming session, RST can be
set low to commence normal device operation.
To program and verify the AT89S52 in the serial program-
ming mode, the following sequence is recommended:
Power-off sequence (if needed):
Set XTAL1 to “L” (if a crystal is not used).
Set RST to “L”.
1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
Turn VCC power off.
If a crystal is not connected across pins XTAL1 and
XTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pin
and wait for at least 10 milliseconds.
Data Polling: The Data Polling feature is also available in
the serial mode. In this mode, during a write cycle an
attempted read of the last byte written will result in the com-
plement of the MSB of the serial output byte on MISO.
2. Enable serial programming by sending the Pro-
gramming Enable serial instruction to pin
MOSI/P1.5. The frequency of the shift clock sup-
plied at pin SCK/P1.7 needs to be less than the
CPU clock at XTAL1 divided by 16.
Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte
protocol and is shown in Table 10.
3. The Code array is programmed one byte at a time
by supplying the address and data together with the
17
Programming Interface – Parallel Mode
Every code byte in the Flash array can be programmed by
using the appropriate combination of control signals. The
write operation cycle is self-timed and once initiated, will
automatically time itself to completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
Table 8. Flash Programming Modes
P2.4-0
P1.7-0
ALE/
PROG
(2)
EA/
VPP
P0.7-0
Data
Address
Mode
VCC
5V
5V
5V
RST
H
PSEN
P2.6
P2.7
H
P3.3
H
P3.6
H
P3.7
H
Write Code Data
Read Code Data
Write Lock Bit 1
L
L
L
12V
H
L
L
DIN
DOUT
X
A12-8
A12-8
X
A7-0
A7-0
X
H
H
L
L
H
H
(3)
H
12V
H
H
H
H
H
(3)
(3)
Write Lock Bit 2
Write Lock Bit 3
5V
5V
H
H
L
L
12V
12V
H
H
H
L
H
H
L
L
L
X
X
X
X
X
X
H
P0.2,
P0.3,
P0.4
Read Lock Bits
1, 2, 3
5V
5V
H
H
L
L
H
H
H
H
H
L
L
H
L
L
L
X
X
X
X
(1)
Chip Erase
12V
H
X
Read Atmel ID
Read Device ID
Read Device ID
5V
5V
5V
H
H
H
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1EH
52H
06H
X 0000
X 0001
X 0010
00H
00H
00H
Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.
2. Each PROG pulse is 200 ns - 500 ns for Write Code Data.
3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits.
4. RDY/BSY signal is output on P3.0 during programming.
5. X = don’t care.
Figure 13. Programming the Flash Memory
Figure 14. Verifying the Flash Memory (Parallel Mode)
(Parallel Mode)
VCC
AT89S52
VCC
A0 - A7
VCC
AT89S52
ADDR.
P1.0-P1.7
A0 - A7
PGM DATA
(USE 10K
PULLUPS)
0000H/1FFFH
VCC
ADDR.
0000H/1FFFH
P1.0-P1.7
P0
P2.0 - P2.4
A8 - A12
PGM
DATA
P2.0 - P2.4
P0
A8 - A12
P2.6
P2.7
P2.6
P2.7
P3.3
P3.6
ALE
SEE FLASH
PROGRAMMING
MODES TABLE
P3.3
P3.6
P3.7
SEE FLASH
PROGRAMMING
MODES TABLE
ALE
PROG
VIH
P3.7
XTAL2
EA
XTAL2
EA
VIH/VPP
3-33 MHz
3-33 MHz
RDY/
BSY
P3.0
VIH
XTAL1
GND
RST
XTAL1
GND
RST
VIH
PSEN
PSEN
AT89S52
18
AT89S52
Flash Programming and Verification Characteristics (Parallel Mode)
TA = 20°C to 30°C, VCC = 4.5 to 5.5V
Symbol
VPP
Parameter
Min
Max
12.5
10
Units
V
Programming Supply Voltage
Programming Supply Current
VCC Supply Current
11.5
IPP
mA
mA
MHz
ICC
30
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
Oscillator Frequency
3
33
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold After PROG
PROG Width
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
µs
µs
µs
10
0.2
1
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
48tCLCL
48tCLCL
48tCLCL
1.0
0
µs
µs
50
Figure 15. Flash Programming and Verification Waveforms – Parallel Mode
PROGRAMMING
P1.0 - P1.7
P2.0 - P2.5
VERIFICATION
ADDRESS
ADDRESS
tAVQV
P3.4
PORT 0
DATA IN
DATA OUT
tDVGL tGHDX
tAVGL
tSHGL
tGHAX
tGHSL
ALE/PROG
tGLGH
VPP
LOGIC 1
LOGIC 0
EA/VPP
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.0
(RDY/BSY)
BUSY
tWC
READY
19
Figure 16. Flash Memory Serial Downloading
VCC
AT89S52
VCC
INSTRUCTION
P1.5/MOSI
P1.6/MISO
P1.7/SCK
INPUT
DATA OUTPUT
CLOCK IN
XTAL2
3-33 MHz
XTAL1
GND
RST
VIH
Flash Programming and Verification Waveforms – Serial Mode
Figure 17. Serial Programming Waveforms
7
6
5
4
3
2
1
0
AT89S52
20
AT89S52
Table 9. Serial Programming Instruction Set
Instruction
Format
Instruction
Byte 1
Byte 2
Byte 3
Byte 4
Operation
Programming Enable
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
0110 1001
(Output)
Enable Serial Programming
while RST is high
Chip Erase
1010 1100
0010 0000
0100 0000
100x xxxx
xxx
xxxx xxxx
xxxx xxxx
Chip Erase Flash memory
array
Read Program Memory
(Byte Mode)
Read data from Program
memory in the byte mode
Write Program Memory
(Byte Mode)
xxx
Write data to Program
memory in the byte mode
Write Lock Bits(2)
1010 1100
0010 0100
1110 00
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx xx
Write Lock bits. See Note (2).
Read Lock Bits
xxxx xxxx
Read back current status of
the lock bits (a programmed
lock bit reads back as a ‘1’)
Read Signature Bytes(1) 0010 1000
xxx
xxx
xxx xxxx
Byte 0
Signature Byte
Read Signature Byte
Read Program Memory
(Page Mode)
0011 0000
0101 0000
Byte 1...
Byte 255
Read data from Program
memory in the Page Mode
(256 bytes)
Write Program Memory
(Page Mode)
xxx
Byte 0
Byte 1...
Byte 255
Write data to Program
memory in the Page Mode
(256 bytes)
Notes: 1. The signature bytes are not readable in Lock Bit Modes 3 and 4.
2. B1 = 0, B2 = 0 ---> Mode 1, no lock protection
Each of the lock bits needs to be activated sequentially before
Mode 4 can be executed.
B1 = 0, B2 = 1 ---> Mode 2, lock bit 1 activated
B1 = 1, B2 = 0 ---> Mode 3, lock bit 2 activated
B1 = 1, B1 = 1 ---> Mode 4, lock bit 3 activated
}
After Reset signal is high, SCK should be low for at least 64
system clocks before it goes high to clock in the enable
data bytes. No pulsing of Reset signal is necessary. SCK
should be no faster than 1/16 of the system clock at
XTAL1.
For Page Read/Write, the data always starts from byte 0 to
255. After the command byte and upper address byte are
latched, each byte thereafter is treated as data until all 256
bytes are shifted in/out. Then the next instruction will be
ready to be decoded.
21
Serial Programming Characteristics
Figure 18. Serial Programming Timing
MOSI
tSLSH
tOVSH
tSHOX
SCK
tSHSL
MISO
tSLIV
Table 10. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 4.0 - 5.5V (Unless otherwise noted)
Symbol
1/tCLCL
tCLCL
Parameter
Min
0
Typ
Max
Units
MHz
ns
Oscillator Frequency
33
Oscillator Period
30
tSHSL
SCK Pulse Width High
SCK Pulse Width Low
MOSI Setup to SCK High
MOSI Hold after SCK High
SCK Low to MISO Valid
Chip Erase Instruction Cycle Time
Serial Byte Write Cycle Time
2 tCLCL
2 tCLCL
tCLCL
2 tCLCL
10
ns
tSLSH
ns
tOVSH
tSHOX
tSLIV
ns
ns
16
32
500
ns
tERASE
tSWC
ms
µs
64 tCLCL + 400
AT89S52
22
AT89S52
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol
VIL
Parameter
Condition
Min
-0.5
Max
Units
Input Low Voltage
(Except EA)
0.2 VCC-0.1
0.2 VCC-0.3
VCC+0.5
VCC+0.5
0.45
V
V
V
V
V
VIL1
Input Low Voltage (EA)
Input High Voltage
-0.5
VIH
(Except XTAL1, RST)
(XTAL1, RST)
0.2 VCC+0.9
0.7 VCC
VIH1
VOL
Input High Voltage
Output Low Voltage(1) (Ports 1,2,3)
IOL = 1.6 mA
Output Low Voltage(1)
(Port 0, ALE, PSEN)
VOL1
IOL = 3.2 mA
0.45
V
I
OH = -60 µA, VCC = 5V 10%
OH = -25 µA
2.4
V
V
Output High Voltage
(Ports 1,2,3, ALE, PSEN)
VOH
I
0.75 VCC
0.9 VCC
2.4
IOH = -10 µA
V
IOH = -800 µA, VCC = 5V 10%
V
Output High Voltage
(Port 0 in External Bus Mode)
VOH1
I
OH = -300 µA
0.75 VCC
0.9 VCC
V
IOH = -80 µA
VIN = 0.45V
V
IIL
Logical 0 Input Current (Ports 1,2,3)
-50
µA
Logical 1 to 0 Transition Current
(Ports 1,2,3)
ITL
VIN = 2V, VCC = 5V 10%
-650
µA
ILI
Input Leakage Current (Port 0, EA)
Reset Pulldown Resistor
Pin Capacitance
0.45 < VIN < VCC
10
30
µA
KΩ
pF
RRST
CIO
10
Test Freq. = 1 MHz, TA = 25°C
Active Mode, 12 MHz
Idle Mode, 12 MHz
VCC = 5.5V
10
25
mA
mA
µA
Power Supply Current
Power-down Mode(1)
ICC
6.5
50
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
23
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
12 MHz Oscillator
Variable Oscillator
Symbol
1/tCLCL
tLHLL
Parameter
Min
Max
Min
0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator Frequency
33
ALE Pulse Width
127
43
2tCLCL-40
tCLCL-25
tCLCL-25
tAVLL
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
tLLAX
tLLIV
48
233
4tCLCL-65
tLLPL
43
tCLCL-25
tPLPH
tPLIV
205
3tCLCL-45
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
145
59
3tCLCL-60
tCLCL-25
tPXIX
0
0
tPXIZ
tPXAV
tAVIV
75
tCLCL-8
312
10
5tCLCL-80
10
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
400
400
6tCLCL-100
6tCLCL-100
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
252
5tCLCL-90
0
0
Data Float After RD
97
2tCLCL-28
8tCLCL-150
9tCLCL-165
3tCLCL+50
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold After WR
517
585
300
200
203
23
3tCLCL-50
4tCLCL-75
tCLCL-30
433
33
7tCLCL-130
tCLCL-25
RD Low to Address Float
RD or WR High to ALE High
0
0
43
123
tCLCL-25
tCLCL+25
AT89S52
24
AT89S52
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tPLIV
tLLPL
PSEN
tPXAV
tPLAZ
tPXIZ
tPXIX
INSTR IN
tLLAX
A0 - A7
tAVIV
A0 - A7
PORT 0
PORT 2
A8 - A15
A8 - A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tLLAX
tRLAZ
tRHDZ
tRHDX
tRLDV
tAVLL
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
tAVDV
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
25
External Data Memory Write Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
tQVWX
tWHQX
tAVLL
tQVWH
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
tCHCX
tCLCH
tCHCL
VCC - 0.5V
0.7 VCC
0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL
External Clock Drive
Symbol
1/tCLCL
tCLCL
Parameter
Oscillator Frequency
Clock Period
High Time
Min
0
Max
Units
33
MHz
ns
30
12
12
tCHCX
tCLCX
ns
Low Time
ns
tCLCH
Rise Time
5
5
ns
tCHCL
Fall Time
ns
AT89S52
26
AT89S52
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc
Variable Oscillator
Symbol
tXLXL
Parameter
Min
1.0
700
50
Max
Min
12tCLCL
10tCLCL-133
2tCLCL-80
0
Max
Units
µs
Serial Port Clock Cycle Time
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
ns
ns
0
ns
700
10tCLCL-133
ns
Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
tXHQX
1
WRITE TO SBUF
0
2
3
4
5
6
7
tXHDX
SET TI
tXHDV
OUTPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
AC Testing Input/Output Waveforms(1)
Float Waveforms(1)
+ 0.1V
- 0.1V
+ 0.1V
VCC - 0.5V
VOL
VLOAD
0.2 VCC + 0.9V
Timing Reference
Points
VLOAD
TEST POINTS
- 0.1V
0.2 VCC - 0.1V
0.45V
VLOAD
VOL
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
Note:
1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
27
Ordering Information
Speed
Power
(MHz)
Supply
Ordering Code
Package
Operation Range
24
4.0V to 5.5V
AT89S52-24AC
AT89S52-24JC
AT89S52-24PC
44A
44J
Commercial
(0°C to 70°C)
40P6
AT89S52-24AI
AT89S52-24JI
AT89S52-24PI
44A
44J
Industrial
(-40°C to 85°C)
40P6
33
4.5V to 5.5V
AT89S52-33AC
AT89S52-33JC
AT89S52-33PC
44A
44J
Commercial
(0°C to 70°C)
40P6
= Preliminary Availability
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
40P6
40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
AT89S52
28
Packaging Information
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat Package (TQFP)
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)*
.045(1.14) X 30° - 45°
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
12.21(0.478)
11.75(0.458)
SQ
PIN 1 ID
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
0.45(0.018)
0.30(0.012)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
0.80(0.031) BSC
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
10.10(0.394)
9.90(0.386)
.165(4.19)
SQ
1.20(0.047) MAX
0
7
0.20(.008)
0.09(.003)
.022(.559) X 45° MAX (3X)
0.75(0.030) 0.15(0.006)
0.45(0.018) 0.05(0.002)
*Controlling dimension: millimeters
40P6, 40-pin, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.161(4.09)
.125(3.18)
.022(.559)
.014(.356)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0
15
REF
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
AT89S52
29
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