A42MX02-FPL100A [ETC]
40MX and 42MX FPGA Families; 40MX和42MX FPGA系列型号: | A42MX02-FPL100A |
厂家: | ETC |
描述: | 40MX and 42MX FPGA Families |
文件: | 总123页 (文件大小:854K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v6.0
40MX and 42MX FPGA Families
Features
HiRel Features
•
Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
High Capacity
•
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
•
•
•
•
•
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
•
•
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
•
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
High Performance
•
Up to 100% Resource Utilization and 100% Pin
Locking
•
•
•
•
•
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
•
•
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
7.5 ns 35-Bit Address Decode
•
•
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
Clock-to-Out
9.5 ns
9.5 ns
5.6 ns
6.1 ns
6.1 ns
6.3 ns
SRAM Modules
(64x4 or 32x8)
–
–
–
–
–
348
516
2
–
624
928
2
–
954
1,410
2
10
1,230
1,822
6
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
147
1
273
1
User I/O (maximum)
PCI
57
–
69
–
104
–
140
–
176
Yes
Yes
202
Yes
Boundary Scan Test (BST)
–
–
–
–
Yes
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
44, 68
44, 68, 84
84
100, 160
100
176
–
84
84
160, 208
–
100
80
–
–
–
100
80
–
–
–
100, 160, 208
208, 240
100
176
–
–
176
–
–
–
208, 256
272
–
–
–
January 2004
i
© 2004 Actel Corporation
See the Actel website (www.actel.com) for the latest version of this datasheet.
40MX and 42MX FPGA Families
Ordering Information
_
PQ
100
A42MX16
1
ES
Application (Temperature Range)
Blank = Commercial (0 to +70˚C)
I
=
=
=
=
Industrial (–40 to +85˚C)
Military (–55 to +125˚C)
MIL-STD-883
M
B
A
Automotive (–40 to +125˚C)
Package Lead Count
Package Type
PL
=
=
=
=
=
=
Plastic Leaded Chip Carrier
Plastic Quad Flat Pack
PQ
TQ
VQ
BG
CQ
Thin (1.4 mm) Quad Flat Pack
Very Thin (1.0 mm) Quad Flat Pack
Plastic Ball Grid Array
Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1
–2
–3
–F
=
=
=
=
Approximately 15% Faster than Standard
Approximately 25% Faster than Standard
Approximately 35% Faster than Standard
Approximately 40% Slower than Standard
Part Number
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
=
=
=
=
=
3,000 System Gates
6,000 System Gates
14,000 System Gates
24,000 System Gates
36,000 System Gates
54,000 System Gates
=
Plastic Device Resources
User I/Os
PLCC
PLCC
PLCC
PQFP
PQFP
PQFP
PQFP
VQFP
VQFP
TQFP
PBGA
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
44-Pin
68-Pin
84-Pin 100-Pin 160-Pin 208-Pin 240-Pin 80-Pin 100-Pin 176-Pin 272-Pin
34
34
–
57
57
–
–
57
69
83
83
–
–
–
–
–
–
–
57
69
–
–
–
–
–
–
–
69
72
72
72
–
101
125
125
–
–
–
83
83
–
104
140
150
–
–
–
–
140
176
176
–
–
–
–
–
–
–
–
–
–
–
202
–
–
202
Note: Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array
ii
v6.0
40MX and 42MX FPGA Families
Ceramic Device Resources
User I/Os
Device
A42MX36
CQFP 208-Pin
CQFP 256-Pin
176
202
Note: Package Definitions CQFP = Ceramic Quad Flat Pack
Temperature Grade Offerings
Package
PLCC 44
PLCC 68
PLCC 84
PQFP 100
PQFP 160
PQFP 208
PQFP 240
VQFP 80
VQFP 100
TQFP 176
PBGA 272
CQFP 208
CQFP 256
Note:
A40MX02
C, I, M
A40MX04
C, I, M
A42MX09
A42MX16
A42MX24
A42MX36
C, I, A, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, M
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, M
C, M, B
C, M, B
C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
Speed Grade Offerings
– F
Std
✓
–1
✓
–2
✓
–3
✓
C
I
✓
✓
✓
✓
✓
A
M
B
✓
✓
✓
✓
✓
Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.
Contact your local Actel representative for device availability.
v6.0
iii
40MX and 42MX FPGA Families
Table of Contents
40MX and 42MX FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
3.3V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . 1-18
Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Drive Characteristics for 5.0V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Output Drive Characteristics for 3.3V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
J
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Parameter Measurement
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77
Package Pin Assignments
44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
v6.0
v
40MX and 42MX FPGA Families
Table of Contents
100-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
160-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
208-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
240-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
80-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
100-Pin VQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
176-Pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
272-Pin BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
vi
v6.0
40MX and 42MX FPGA Families
40MX and 42MX FPGA Families
General Description
MX Architectural Overview
Actel's 40MX and 42MX families offer a cost-effective
design solution at 5V. The MX devices are single-chip
solutions and provide high performance while
shortening the system design and development cycle.
MX devices can integrate and consolidate logic
implemented in multiple PALs, CPLDs, and FPGAs.
Example applications include high-speed controllers and
address decoding, peripheral bus interfaces, DSP, and co-
processor functions.
The MX devices are composed of fine-grained building
blocks that enable fast, efficient logic designs. All devices
within these families are composed of logic modules, I/O
modules, routing resources and clock networks, which
are the building blocks for fast logic designs. In addition,
the A42MX36 device contains embedded dual-port
SRAM modules, which are optimized for high-speed
datapath functions such as FIFOs, LIFOs and scratchpad
memory. A42MX24 and A42MX36 also contain wide-
decode modules.
The MX device architecture is based on Actel’s patented
antifuse technology implemented in a 0.45µm triple-
metal CMOS process. With capacities ranging from 3,000
to 54,000 system gates, the MX devices provide
performance up to 250 MHz, are live on power-up and
have one-fifth the standby power consumption of
comparable FPGAs. Actel’s MX FPGAs provide up to 202
user I/Os and are available in a wide variety of packages
and speed grades.
Logic Modules
The 40MX logic module is an eight-input, one-output
logic circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources (Figure 1-1).
The logic module can implement the four basic logic
functions (NAND, AND, OR and NOR) in gates of two,
three, or four inputs. The logic module can also
implement a variety of D-latches, exclusivity functions,
AND-ORs and OR-ANDs. No dedicated hard-wired latches
or flip-flops are required in the array; latches and flip-
flops can be constructed from logic modules whenever
required in the application.
Actel’s A42MX24 and A42MX36 devices also feature
MultiPlex I/Os, which support mixed-voltage systems,
enable programmable PCI, deliver high-performance
operation at both 5.0V and 3.3V, and provide a low-
power mode. The devices are fully compliant with the
PCI Local Bus Specification (version 2.1). They deliver
200 MHz on-chip operation and 6.1 ns clock-to-output
performance.
The 42MX24 and 42MX36 devices include system-level
features such as IEEE Standard 1149.1 (JTAG) Boundary
Scan Testing and fast wide-decode modules. In addition,
the A42MX36 device offers dual-port SRAM for
implementing fast FIFOs, LIFOs, and temporary data
storage. The storage elements can efficiently address
applications requiring wide datapath manipulation and
can perform transformation functions such as those
required for telecommunications, networking, and DSP.
All MX devices are fully tested over automotive and
military temperature ranges. In addition, the largest
member of the family, the A42MX36, is available in both
CQ208 and CQ256 ceramic packages screened to MIL-
STD-883 levels. For easy prototyping and conversion from
plastic to ceramic, the CQ208 and PQ208 devices are pin-
compatible.
Figure 1-1 • 40MX Logic Module
v6.0
1-1
40MX and 42MX FPGA Families
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules) and
A0
B0
decode
(D-modules).
Figure 1-2
illustrates
the
S0
combinatorial logic module. The S-module, shown in
Figure 1-3, implements the same combinatorial logic
function as the C-module while adding a sequential
element. The sequential element can be configured as
either a D-flip-flop or a transparent latch. The S-module
register can be bypassed so that it implements purely
combinatorial logic.
D00
D01
D10
D11
Y
S1
A1
B1
Figure 1-2 • 42MX C-Module Implementation
D00
D01
D00
D01
D
D
Q
OUT
Q
OUT
Y
Y
D10
D10
S0
S0
D11
S1
D11
S1
GATE
CLR
Up to 7-Input Function Plus Latch
D00
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D0
D01
D10
D11
Y
OUT
Q
D
Y
OUT
S0
D1
GATE
S
S1
CLR
Up to 8-Input Function (Same as C-Module)
Up to 4-Input Function Plus Latch with Clear
Figure 1-3 • 42MX S-Module Implementation
1-2
v6.0
40MX and 42MX FPGA Families
A42MX24 and A42MX36 devices contain D-modules,
which are arranged around the periphery of the device.
D-modules contain wide-decode circuitry, providing a
fast, wide-input AND function similar to that found in
CPLD architectures (Figure 1-4). The D-module allows
A42MX24 and A42MX36 devices to perform wide-
decode functions at speeds comparable to CPLDs and
PALs. The output of the D-module has a programmable
inverter for active HIGH or LOW assertion. The D-module
output is hardwired to an output pin, and can also be
fed back into the array to be incorporated into other
logic.
highest order address bits (RDAD5 and WRAD5) are not
used. The read and write ports of the SRAM block
contain independent clocks (RCLK and WCLK) with
programmable polarities offering active HIGH or LOW
implementation. The SRAM block contains eight data
inputs (WD[7:0]), and eight outputs (RD[7:0]), which are
connected to segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring
FIFO and LIFO queues. The ACTgen Macro Builder within
Actel's Designer software provides capability to quickly
design memory functions with the SRAM blocks. Unused
SRAM blocks can be used to implement registers for
other user logic within the design.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules
that have been optimized for synchronous or
asynchronous applications. The SRAM modules are
arranged in 256-bit blocks that can be configured as 32x8
or 64x4. SRAM modules can be cascaded together to
form memory spaces of user-definable width and depth.
A block diagram of the A42MX36 dual-port SRAM block
is shown in Figure 1-5.
7 Inputs
Hard-Wire to I/O
Programmable
Inverter
The A42MX36 SRAM modules are true dual-port
structures containing independent read and write ports.
Each SRAM module contains six bits of read and write
addressing (RDAD[5:0] and WRAD[5:0], respectively) for
64x4-bit blocks. When configured in byte mode, the
Feedback to Array
Figure 1-4 • A42MX24 and A42MX36 D-Module
Implementation
Latches
WD[7:0]
[7:0]
[5:0]
RDAD[5:0]
SRAM Module
32 x 8 or 64 x 4 Port
Logic
Latches
Write
Port
Read
Logic
(256 Bits)
[5:0]
WRAD[5:0]
MODE
BLKEN
WEN
Read
Logic
Latches
REN
RD[7:0]
RCLK
Write
Logic
Routing Tracks
WCLK
Figure 1-5 • A42MX36 Dual-Port SRAM Block
v6.0
1-3
40MX and 42MX FPGA Families
Routing Structure
Segmented
Horizontal
Routing
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
continuous or split into segments. Varying segment
lengths allow the interconnect of over 90% of design
tracks to occur with only two antifuse connections.
Segments can be joined together at the ends using
antifuses to increase their lengths up to the full length of
the track. All interconnects can be accomplished with a
maximum of four antifuses.
Logic
Modules
Antifuses
Vertical Routing Tracks
Horizontal Routing
Figure 1-6 • MX Routing Structure
Horizontal routing tracks span the whole row length or
are divided into multiple segments and are located in
between the rows of modules. Any segment that spans
more than one-third of the row length is considered a
long horizontal segment. A typical channel is shown in
Figure 1-6. Within horizontal routing, dedicated routing
tracks are used for global clock networks and for power
and ground tie-off tracks. Non-dedicated tracks are used
for signal nets.
Clock Networks
The 40MX devices have one global clock distribution
network (CLK). A signal can be put on the CLK network
by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout
clock distribution networks, referred to as CLKA and
CLKB. Each network has a clock module (CLKMOD) that
can select the source of the clock signal from any of the
following (Figure 1-7 on page 1-5):
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long. Long tracks span the column length of
the module, and can be divided into multiple segments.
Each segment in an input track is dedicated to the input
of a particular module; each segment in an output track
is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two
above and two below), except near the top and bottom
of the array, where edge effects occur. Long vertical
tracks contain either one or two segments. An example
of vertical routing tracks and segments is shown in
Figure 1-6.
•
•
•
•
Externally from the CLKA pad, using CLKBUF
buffer
Externally from the CLKB pad, using CLKBUF
buffer
Internally from the CLKINTA input, using CLKINT
buffer
Internally from the CLKINTB input, using CLKINT
buffer
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can
also be used as normal I/Os, bypassing the clock
networks.
Antifuse Structures
An antifuse is a "normally open" structure. The use of
antifuses to implement a programmable logic device
results in highly testable structures as well as efficient
programming algorithms. There are no pre-existing
connections; temporary connections can be made using
pass transistors. These temporary connections can isolate
individual antifuses to be programmed and individual
circuit structures to be tested, which can be done before
and after programming. For instance, all metal tracks can
be tested for continuity and shorts between adjacent
tracks, and the functionality of all logic modules can be
verified.
The A42MX36 device has four additional register control
resources, called quadrant clock networks (Figure 1-8 on
page 1-5). Each quadrant clock provides a local, high-
fanout resource to the contiguous logic modules within
its quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
1-4
v6.0
40MX and 42MX FPGA Families
CLKB
CLKA
CLKINB
CLKINA
From
S0
S1
Pads
Internal
Signal
CLKMOD
CLKO(17)
CLKO(16)
CLKO(15)
Clock
Drivers
CLKO(2)
CLKO(1)
Clock Tracks
Figure 1-7 • Clock Networks of 42MX Devices
QCLKA
QCLKC
Quad
Clock
Modul
Quad
Clock
Modul
QCLK1
QCLK3
QCLKD
QCLKB
*QCLK1IN
*QCLK3IN
S0 S1
S1 S0
Quad
Clock
Modul
Quad
Clock
Modul
QCLK2
QCLK4
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
v6.0
1-5
40MX and 42MX FPGA Families
MultiPlex I/O Modules
42MX devices feature Multiplex I/Os and support 5.0V,
3.3V, and mixed 3.3V/5.0V operations.
STD
Signal
The MultiPlex I/O modules provide the interface between
the device pins and the logic array. Figure 1-9 is a block
diagram of the 42MX I/O module. A variety of user
functions, determined by a library macro selection, can
be implemented in the module. (Refer to the Antifuse
Macro Library Guide for more information.) All 42MX I/O
modules contain tristate buffers, with input and output
latches that can be configured for input, output, or
bidirectional operation.
Output
PCI
Drive
PCI Enable
Fuse
Figure 1-10 • PCI Output Structure of A42MX24 and
A42MX36 Devices
All 42MX devices contain flexible I/O structures, where
each output pin has a dedicated output-enable control
(Figure 1-9). The I/O module can be used to latch input or
output data, or both, providing fast set-up time. In
addition, the Actel Designer software tools can build a D-
type flip-flop using a C-module combined with an I/O
module to register input and output signals. Refer to the
Antifuse Macro Library Guide for more details.
Other Architectural Features
Performance
MX devices can operate with internal clock frequencies
of 250 MHz, enabling fast execution of complex logic
functions. MX devices are live on power-up and do not
require auxiliary configuration devices and thus are an
optimal platform to integrate the functionality
contained in multiple programmable logic devices. In
addition, designs that previously would have required a
gate array to meet performance can be integrated into
an MX device with improvements in cost and time-to-
market. Using timing-driven place-and-route (TDPR)
tools, designers can achieve highly deterministic device
performance.
A42MX24 and A42MX36 devices also offer selectable PCI
output drives, enabling 100% compliance with version
2.1 of the PCI specification. For low-power systems, all
inputs and outputs are turned off to reduce current
consumption to below 500µA.
To achieve 5.0V or 3.3V PCI-compliant output drives on
A42MX24 and A42MX36 devices, a chip-wide PCI fuse is
programmed via the Device Selection Wizard in the
Designer software (Figure 1-10). When the PCI fuse is not
programmed, the output drive is standard.
Actel's Designer software development tools provide a
design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
User Security
The Actel FuseLock provides robust security against
design theft. Special security fuses are hidden in the
fabric of the device and prevent unauthorized users from
accessing the programming and/or probe interfaces. It is
virtually impossible to identify or bypass these fuses
without damaging the device, making Actel antifuse
FPGAs immune to both invasive and noninvasive attacks.
EN
Q
D
PAD
From Array
To Array
Special security fuses in 40MX devices include the Probe
Fuse and Program Fuse. The former disables the probing
circuitry while the latter prohibits further programming
of all fuses, including the Probe Fuse. In 42MX devices,
there is the Security Fuse which, when programmed,
both disables the probing circuitry and prohibits further
programming of the device.
G/CLK*
Q
D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (Using
Look for this symbol to ensure your valuable IP is secure.
C-Module)
For more information, refer to Actel's Implementation of
Security in Actel Antifuse FPGAs application note.
Figure 1-9 • 42MX I/O Module
1-6
v6.0
40MX and 42MX FPGA Families
nonprogrammed), Silicon Sculptor II also allows self-test
to verify its own hardware extensively.
™
The procedure for programming an MX device using
Silicon Sculptor II is as follows:
1. Load the .AFM file
u
e
Figure 1-11 • Fuselock
2. Select the device to be programmed
3. Begin programming
Programming
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via In-House
Programming from the factory.
Device programming is supported through the Silicon
Sculptor series of programmers. Silicon Sculptor II is a
compact, robust, single-site and multi-site device
programmer for the PC. With standalone software,
Silicon Sculptor II is designed to allow concurrent
programming of multiple units from the same PC.
For more details on programming MX devices, please
refer to the Programming Antifuse Devices and the
Silicon Sculptor II user's guides.
Silicon Sculptor II programs devices independently to
achieve the fastest programming times possible. After
being programmed, each fuse is verified to insure that it
has been programmed correctly. Furthermore, at the end
of programming, there are integrity tests that are run to
ensure no extra fuses have been programmed. Not only
Power Supply
MX devices are designed to operate in both 5.0V and
3.3V environments. In particular, 42MX devices can
operate in mixed 5.0V/3.3V systems. Table 1 describes the
voltage support of MX devices.
does
it
test
fuses
(both
programmed
and
Table 1 •
Device
40MX
Voltage Support of MX Devices
VCC
5.0V
3.3V
–
VCCA
–
VCCI
–
Maximum Input Tolerance
Nominal Output Voltage
5.5V
3.6V
5.5V
3.6V
5.5V
5.0V
3.3V
5.0V
3.3V
3.3V
–
–
42MX
5.0V
3.3V
5.0V
5.0V
3.3V
3.3V
–
–
Power-Up/Down in Mixed-Voltage Mode
Low Power Mode
When powering up 42MX in mixed voltage mode
(VCCA = 5.0V and VCCI = 3.3V), VCCA must be greater than
or equal to VCCI throughout the power-up sequence. If
VCCI exceeds VCCA during power up, either the I/Os' input
protection junction on the I/Os will be forward-biased or
the I/Os will be at logical HIGH, and ICC rises to high
levels. For power-down, any sequence with VCCA and
VCCI can be implemented.
42MX devices have been designed with a Low Power
Mode. This feature, activated with setting the special LP
pin to HIGH for a period longer than 800 ns, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated. Since the core of the device is
turned off, the states of the registers are lost. The device
must be re-initialized when exiting Low Power Mode. I/
Os can be driven during LP mode, and clock pins should
be driven HIGH or LOW and should not float to avoid
drawing current. To exit LP mode, the LP pin must be
pulled LOW for over 200 µs to allow for charge pumps to
power up, and device initialization will begin.
v6.0
1-7
40MX and 42MX FPGA Families
The power dissipated by a CMOS circuit can be expressed
by the equation:
Power Dissipation
The general power consumption of MX devices is made
up of static and dynamic power and can be expressed
with the following equation:
2
Power (µW) = CEQ * VCCA * F(1)
where:
C
EQ =Equivalent capacitance expressed in picofarads (pF)
CCA =Power supply in volts (V)
V
General Power Equation
F =Switching frequency in megahertz (MHz)
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N
+ IOH * (VCCI – VOH) * M
Equivalent Capacitance
where:
Equivalent capacitance is calculated by measuring
ICCactive at a specified frequency and voltage for each
circuit component of interest. Measurements have been
I
CCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS
switching.
made over a range of frequencies at a fixed value of V
.
CC
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL
M equals the number of outputs driving TTL loads to
VOH
.
C
Values for Actel MX FPGAs
EQ
.
Modules (CEQM)3.5
Accurate values for N and M are difficult to determine
because they depend on the family type, on design
details, and on the system I/O. The power can be divided
into two components: static and active.
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
2
Static Power Component
The static power due to standby current is typically a
small component of the overall power consumption.
Standby power is calculated for commercial, worst-case
conditions. The static power dissipation by TTL loads
depends on the number of outputs driving, and on the
DC load current. For instance, a 32-bit bus sinking 4mA at
0.33V will generate 42mW with all outputs driving LOW,
and 140mW with all outputs driving HIGH. The actual
dissipation will average somewhere in between, as I/Os
switch states with time.
Power = VCCA * [(m x CEQM * fm)Modules
+
(n * CEQI * fn)Inputs + (p * (CEQO + CL) *
fp)outputs
+
0.5 * (q1 * CEQCR * fq1
)
+ (r1
+ (r2
*
*
routed_Clk1
fq1
)
+
routed_Clk1
0.5 * (q2 * CEQCR * fq2
)
routed_Clk2
fq2
)
(2)
routed_Clk2
where:
m
= Number of logic modules switching at
frequency fm
Active Power Component
n
= Number of input buffers switching at
frequency fn
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. Dynamic power
consumption is frequency-dependent and is a function of
the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitances due to
PC board traces and load device inputs. An additional
component of the active power dissipation is the totem
pole current in the CMOS transistor pairs. The net effect
can be associated with an equivalent capacitance that
can be combined with frequency and voltage to
represent active power dissipation.
p
= Number of output buffers switching at
frequency fp
q1
q2
r1
r2
= Number of clock loads on the first routed array
clock
= Number of clock loads on the second routed
array clock
= Fixed capacitance due to first routed array
clock
= Fixed capacitance due to second routed array
clock
1-8
v6.0
40MX and 42MX FPGA Families
resources. Silicon Explorer II's noninvasive method does
not alter timing or loading effects, thus shortening the
debug cycle and providing a true representation of the
device under actual functional situations.
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
C
EQCR = Equivalent capacitance of routed array clock in
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
pF
CL
fm
fn
= Output load capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
fp
fq1
fq2
Silicon Explorer II is used to control the MODE, DCLK, SDI
and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the MODE pin is held HIGH.
Fixed Capacitance Values for MX FPGAs (pF)
r1
r2
Device Type
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
routed_Clk1
routed_Clk2
41.4
68.6
118
165
185
220
N/A
N/A
118
165
185
220
Figure 1-12 illustrates the interconnection between
Silicon Explorer II and 40MX devices, while Figure 1-13
on page 1-10 illustrates the interconnection between
Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must
not be programmed. (Refer to <zBlue>“User Security”
section on page 6 for the security fuses of 40MX and
42MX devices). Table 2 on page 1-10 summarizes the
possible device configurations for probing.
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-
in access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware
and software solution that, in conjunction with the
Designer software, allow users to examine any of the
internal nets of the device while it is operating in a
prototyping or a production system. The user can probe
into an MX device without changing the placement and
routing of the design and without using any additional
PRA and PRB pins are dual-purpose pins. When the
"Reserve
Probe
Pin"
is
checked
in
the
Designer software, PRA and PRB pins are reserved as
dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and
"Reserve Probe Pin" is checked, the layout tool will
override the option and place user I/Os on PRA and PRB
pins.
16 Logic Analyzer Channels
40MX
Serial Connection
to Windows PC
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRA
PRB
Figure 1-12 • Silicon Explorer II Setup with 40MX
v6.0
1-9
40MX and 42MX FPGA Families
16 Logic Analyzer Channels
42MX
Serial Connection
to Windows PC
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRA
PRB
Figure 1-13 • Silicon Explorer II Setup with 42MX
Table 2 •
Device Configuration Options for Probe Capability
Security Fuse(s)
Programmed
MODE
LOW
HIGH
–
PRA, PRB1
User I/Os2
SDI, SDO, DCLK1
User I/Os2
No
No
Probe Circuit Outputs
Probe Circuit Secured
Probe Circuit Inputs
Probe Circuit Secured
Yes
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the <zBlue>“Pin Descriptions” section
on page 77 for information on unused I/O pins.
Each test section is accessed through the TAP, which has
four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode
selector).
Design Consideration
It is recommended to use a series 70Ω termination
resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70Ω series termination is used
The TAP controller is a four-bit state machine. The '1's
to prevent data transmission corruption during probing
and '0's represent the values that must be present at TMS
and reading back the checksum.
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
IEEE Standard 1149.1 Boundary Scan Test
(BST) Circuitry
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
42MX24 and 42MX36 devices are compatible with IEEE
of the test logic architecture. On power-up, the TAP
Standard 1149.1 (informally known as Joint Testing
controller enters the Test-Logic-Reset state. To guarantee
Action Group Standard or JTAG), which defines a set of
a reset of the controller from any of the possible states,
hardware architecture and mechanisms for cost-effective
TMS must remain high for five TCK cycles.
board-level testing. The basic MX boundary-scan logic
42MX24 and 42MX36 devices support three types of test
circuit is composed of the TAP (test access port), TAP
data registers: bypass, device identification, and
controller, test data registers and instruction register
boundary scan. The bypass register is selected when no
(Figure 1-14 on page 1-11). This circuit supports all
other register needs to be accessed in a device. This
mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/
speeds up test data transfer to other devices in a test
PRELOAD and BYPASS) and some optional instructions.
data path. The 32-bit device identification register is a
Table 3 on page 1-11 describes the ports that control
shift register with four fields (lowest significant byte
JTAG testing, while Table 4 on page 1-11 describes the
(LSB), ID number, part number and version). The
test instructions supported by these MX devices.
boundary-scan register observes and controls the state of
each I/O pin.
1-10
v6.0
40MX and 42MX FPGA Families
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Boundary Scan Register
Output
MUX
TDO
Bypass
Register
Control Logic
JTAG
TMS
Instruction
Decode
TAP Controller
TCK
JTAG
TDI
Instruction
Register
Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 3 •
Test Access Port Descriptions
Port
Description
TMS
(Test
Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK).
Select)
TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge
of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency
for TCK is 20 MHz.
TDI (Test Data Input)
Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock.
TDO
Output)
(Test
Data Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high
impedance) when data scanning is not in progress.
Table 4 •
Supported BST Public Instructions
Instruction
IR Code (IR2.IR0)
Instruction Type
Description
EXTEST
000
Mandatory
Allows the external circuitry and board-level interconnections to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
SAMPLE/PRELOAD
HIGH Z
001
101
110
Mandatory
Optional
Optional
Allows a snapshot of the signals at the device pins to be
captured and examined during operation
Tristates all I/Os to allow external signals to drive pins. Please
refer to the IEEE Standard 1149.1 specification.
CLAMP
Allows state of signals driven from component pins to be
determined from the Boundary-Scan Register. Please refer to
the IEEE Standard 1149.1 specification for details.
BYPASS
111
Mandatory
Enables the bypass register between the TDI and TDO pins. The
test data passes through the selected device to adjacent devices
in the test chain.
v6.0
1-11
40MX and 42MX FPGA Families
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer
software by selecting Tools -> Device Selection. This
brings up the Device Selection dialog box as shown in
Figure 1-15. The JTAG test logic circuit can be enabled by
clicking the "Reserve JTAG Pins" check box. Table 5
explains the pins' behavior in either mode.
Figure 1-15 • Device Selection Wizard
Table 5 •
Boundary Scan Pin Configuration and Functionality
Reserve JTAG
TCK
Checked
Unchecked
User I/O
BST input; must be terminated to logical HIGH or LOW to avoid floating
BST input; may float or be tied to HIGH
TDI, TMS
TDO
User I/O
BST output; may float or be connected to TDI of another device
User I/O
TRST Pin and TAP Controller Reset
Boundary Scan Description Language
(BSDL) File
An active reset (TRST) pin is not supported; however, MX
devices contain power-on circuitry that resets the
boundary scan circuitry upon power-up. Also, the TMS
pin is equipped with an internal pull-up resistor. This
allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Conforming to the IEEE Standard 1149.1 requires that
the operation of the various JTAG components be
documented. The BSDL file provides the standard format
to describe the JTAG components that can be used by
automatic test equipment software. The file includes the
instructions that are supported, instruction bit pattern,
and the boundary-scan chain order. For an in-depth
discussion on BSDL files, please refer to Actel BSDL Files
Format Description application note.
Actel BSDL files are grouped into two categories -
generic and device-specific. The generic files assign all
user I/Os as inouts. Device-specific files assign user I/Os as
inputs, outputs or inouts.
Generic files for MX devices are available on Actel's website
at http://www.actel.com/techdocs/models/bsdl.html.
1-12
v6.0
40MX and 42MX FPGA Families
Development Tool Support
Related Documents
The MX family of FPGAs is fully supported by both Actel's
Libero™ Integrated Design Environment and Designer
FPGA Development software. Actel Libero IDE is a design
management environment that streamlines the design
flow. Libero IDE provides an integrated design manager
that seamlessly integrates design tools while guiding the
user through the design flow, managing all design and
log files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. Libero IDE
includes Synplify® for Actel from Synplicity®, ViewDraw
for Actel from Mentor Graphics, ModelSim™ HDL
Simulator from Mentor Graphics®, WaveFormer Lite™
from SynaptiCAD™, and Designer software from Actel.
Refer to the Libero IDE flow (located on Actel’s website)
diagram for more information.
Application Notes
Actel BSDL Files Format Description
www.actel.com/documents/BSDLformat_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/
AntifuseProgram_AN.pdf
Actel's Implementation of Security in Actel Antifuse
FPGAs
www.actel.com/documents/Antifuse_Security_AN.pdf
User’s Guides and Manuals
Antifuse Macro Library Guide
www.actel.com/documents/libguide_UG.pdf
Silicon Sculptor II
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
www.actel.com/techdocs/manuals/default.asp#programmers
timing-driven place-and-route, and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can lock his/her
design pins before layout while minimally impacting the
results of place-and-route. Additionally, the back-
annotation flow is compatible with all the major
simulators and the simulation results can be cross-probed
with Silicon Explorer II, Actel’s integrated verification
and logic analysis tool. Another tool included in the
Designer software is the ACTgen macro builder, which
easily creates popular and commonly used logic
functions for implementation into your schematic or HDL
design. Actel's Designer software is compatible with the
most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
Miscellaneous
Libero IDE Flow Diagram
www.actel.com/products/tools/libero/flow.html
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synplicity, Synopsys,
and Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
v6.0
1-13
40MX and 42MX FPGA Families
5.0V Operating Conditions
Table 6 •
Symbol
VCC
Absolute Maximum Ratings for 40MX Devices*
Parameter
Limits
Units
DC Supply Voltage
Input Voltage
–0.5 to +7.0
V
V
VI
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–65 to +150
VO
Output Voltage
V
tSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 7 •
Symbol
VCCI
Absolute Maximum Ratings for 42MX Devices*
Parameter
Limits
Units
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
–0.5 to +7.0
V
V
VCCA
VI
–0.5 to +7.0
–0.5 to VCCI+0.5
–0.5 to VCCI+0.5
–65 to +150
V
VO
Output Voltage
V
tSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 8 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
-40 to +85
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
Military
–55 to +125
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
Units
Temperature Range*
VCC (40MX)
0 to +70
°C
V
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
VCCA (42MX)
V
VCCI (42MX)
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.
1-14
v6.0
40MX and 42MX FPGA Families
5V TTL Electrical Specifications
Table 9 •
5V TTL Electrical Specifications
Commercial
Commercial -F
Industrial
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
V
1
VOH
IOH = -10mA
2.4
2.4
IOH = -4mA
3.7
3.7
V
1
VOL
IOL = 10mA
IOL = 6mA
0.5
0.5
V
0.4
0.8
0.4
0.8
V
VIL
-0.3
2.0
2.0
0.8
VCC+0.3
VCCI+0.3
-10
-0.3
2.0
2.0
0.8
VCC+0.3
VCCI+0.3
-10
-0.3
2.0
2.0
-0.3
2.0
2.0
V
VIH (40MX)
VCC+0.3
VCCI+0.3
-10
VCC+0.3
VCCI+0.3
-10
V
VIH (42MX)
V
IIL
VIN = 0.5V
VIN = 2.7V
µA
µA
ns
IIH
-10
-10
-10
-10
Input
Transition
500
500
500
500
Time, TR and TF
C
IO I/O Capacitance
10
3
10
25
10
10
10
25
pF
Standby
ICC
Current,
A40MX02,
A40MX04
mA
2
A42MX09
A42MX16
5
6
25
25
25
25
25
25
25
25
25
mA
mA
mA
A42MX24,
A42MX36
20
Low-Power
Standby Current
Mode 42MX devices
only
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
IIO, I/O source sink Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
current
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
v6.0
1-15
40MX and 42MX FPGA Families
3.3V Operating Conditions
Table 10 • Absolute Maximum Ratings for 40MX Devices*
Symbol
VCC
Parameter
DC Supply Voltage
Limits
Units
–0.5 to +7.0
V
V
VI
Input Voltage
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–65 to +150
VO
Output Voltage
Storage Temperature
V
tSTG
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 11 • Absolute Maximum Ratings for 42MX Devices*
Symbol
VCCI
VCCA
VI
Parameter
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
Limits
Units
–0.5 to +7.0
V
V
–0.5 to +7.0
–0.5 to VCCI+0.5
–0.5 to VCCI+0.5
–65 to +150
V
VO
Output Voltage
V
tSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 12 • Recommended Operating Conditions
Parameter
Commercial
0 to +70
Industrial
–40 to +85
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
Military
–55 to +125
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
Units
Temperature Range*
VCC (40MX)
°C
V
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
VCCA (42MX)
V
VCCI (42MX)
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.
1-16
v6.0
40MX and 42MX FPGA Families
3.3V LVTTL Electrical Specifications
Table 13 • 3.3V LVTTL Electrical Specifications
Commercial
Commercial -F
Industrial
Military
Symbol
Parameter
IOH = –4mA
IOL = 6mA
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
1
VOH
2.15
2.15
2.4
2.4
V
1
VOL
0.4
0.8
0.4
0.8
0.48
0.8
0.48
0.8
V
V
VIL
–0.3
2.0
–0.3
2.0
–0.3
2.0
–0.3
2.0
VIH (40MX)
VCC+0.3
VCCI+0.3
–10
VCC+0.3
VCCI+0.3
–10
VCC+0.3
VCCI+0.3
–10
VCC+0.3
VCCI+0.3
–10
V
VIH (42MX)
2.0
2.0
2.0
2.0
V
IIL
µA
µA
ns
IIH
–10
–10
–10
–10
Input Transition Time,
TR and TF
500
500
500
500
CIO I/O Capacitance
10
3
10
25
10
10
10
25
pF
2
Standby Current, ICC
A40MX02,
A40MX04
mA
A42MX09
A42MX16
5
6
25
25
25
25
25
25
25
25
25
mA
mA
mA
A42MX24,
A42MX36
15
Low-Power
Mode
42MX
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
Standby Current
devices only
IIO, I/O source sink Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
current
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
v6.0
1-17
40MX and 42MX FPGA Families
Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only)
Table 14 • Absolute Maximum Ratings*
Symbol
VCCI
VCCA
VI
Parameter
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
Limits
Units
–0.5 to +7.0
V
V
–0.5 to +7.0
–0.5 to VCCI+0.5
–0.5 to VCCI+0.5
–65 to +150
V
VO
Output Voltage
V
tSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 15 • Recommended Operating Conditions
Parameter
Temperature Range*
VCCA
Commercial
0 to +70
Industrial
-40 to +85
4.5 to 5.5
3.0 to 3.6
Military
–55 to +125
4.5 to 5.5
3.0 to 3.6
Units
°C
V
4.75 to 5.25
3.14 to 3.47
VCCI
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.
Mixed 5.0V/3.3V Electrical Specifications
Table 16 • Mixed 5.0V/3.3V Electrical Specifications
Commercial Commercial '-F 'Industrial
Military
Symbol
Parameter
Min. Max.
Min.
Max. Min. Max. Min. Max. Units
1
VOH
IOH = –10mA
2.4
2.4
V
I
OH = –4mA
3.7
3.7
V
V
1
VOL
IOL = 10mA
IOL = 6mA
0.5
0.5
0.8
0.4
0.8
0.4
0.8
V
VIL
VIH
IL
–0.3
0.8
–0.3
–0.3
–0.3
V
2.0 VCCI+0.3 2.0
VCCI+0.3 2.0 VCCI+0.3 2.0 VCCI+0.3
V
VIN = 0.5V
VIN = 2.7V
–10
–10
500
10
5
–10
–10
500
10
–10
–10
500
10
–10
–10
500
10
µA
µA
ns
pF
mA
mA
mA
IH
Input Transition Time, TR and TF
CIO I/O Capacitance
2
Standby Current, ICC
A42MX09
A42MX16
25
25
25
6
25
25
25
A42MX24, A42MX36
20
0.5
25
25
25
Low-Power Mode Standby Current
ICC - 5.0
ICC - 5.0
ICC - 5.0 mA
IIO I/O source sink current
Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
Notes:
1. Only one output tested at a time. VCCI = min.
2. All outputs unloaded. All inputs = VCCI or GND.
1-18
v6.0
40MX and 42MX FPGA Families
Output Drive Characteristics for 5.0V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-16 on page 1-21 shows
the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus
Specification.
Table 17 • DC Specification (5.0V PCI Signaling)1
PCI
MX
Symbol
VCCI
VIH
Parameter
Condition
Min.
4.75
2.0
Max.
5.25
Min.
4.75
2.0
Max.
5.252
VCCI + 0.3
0.8
Units
V
Supply Voltage for I/Os
Input High Voltage
VCC + 0.5
0.8
V
VIL
Input Low Voltage
–0.5
–0.3
—
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
VIN = 2.7V
VIN=0.5V
70
10
µA
µA
V
IIL
–70
—
–10
VOH
IOUT = –2 mA
2.4
I
OUT = –6 mA
3.84
—
VOL
Output Low Voltage
IOUT = 3 mA,
6 mA
0.55
0.33
V
CIN
Input Pin Capacitance
CLK Pin Capacitance
Pin Inductance
10
12
20
—
—
—
10
10
pF
pF
CCLK
LPIN
5
< 8 nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Table 18 • AC Specifications (5.0V PCI Signaling)*
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN +1)
/0.015
–60
–10
mA
Slew (r)
Slew (f)
Output Rise Slew Rate
Output Fall Slew Rate
0.4V to 2.4V load
2.4V to 0.4V load
1
1
5
5
1.8
2.8
2.8
4.3
V/ns
V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
v6.0
1-19
40MX and 42MX FPGA Families
Output Drive Characteristics for 3.3V PCI Signaling
Table 19 • DC Specification (3.3V PCI Signaling)1
PCI
MX
Symbol
VCCI
VIH
Parameter
Supply Voltage for I/Os
Input High Voltage
Condition
Min.
3.0
Max.
3.6
Min.
3.0
Max.
3.6
Units
V
V
0.5
VCC + 0.5
0.8
0.5
VCCI + 0.3
0.8
VIL
Input Low Voltage
–0.5
–0.3
V
IIH
Input High Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
VIN = 2.7V
70
10
µA
µA
V
IIL
–70
–10
VOH
VOL
IOUT = –2 mA
0.9
5
3.3
IOUT = 3 mA,
6 mA
0.1
0.1 VCCI
V
CIN
Input Pin Capacitance
CLK Pin Capacitance
Pin Inductance
10
12
20
10
10
pF
pF
CCLK
LPIN
< 8 nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Table 20 • AC Specifications for (3.3V PCI Signaling)*
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN +1)
/0.015
–60
–10
mA
Slew (r)
Slew (f)
Output Rise Slew Rate
Output Fall Slew Rate
0.2V to 0.6V load
0.6V to 0.2V load
1
1
4
4
1.8
2.8
2.8
4.0
V/ns
V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
1-20
v6.0
40MX and 42MX FPGA Families
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
–0.05
–0.10
–0.15
–0.20
PCI I OL Maximum
MX PCI IOL
PCI I OL Minimum
0
1
2
3
4
5
6
PCI I OH Maximum
MX PCI IOH
PCI I OH Minimum
Voltage Out (V)
Figure 1-16 • Typical Output Drive Characteristics (Based Upon Measured Data)
v6.0
1-21
40MX and 42MX FPGA Families
P = Power
= Junction to ambient of package. θ numbers are
located in the Package Thermal Characteristics table
below.
Junction Temperature (T )
J
θ
ja
ja
The temperature variable in the Designer software refers
to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature. EQ 1-1,
shown below, can be used to calculate junction
temperature.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates.
EQ 1-1
Junction Temperature = ∆T + Ta(1)
The maximum junction temperature is 150°C.
Where:
Maximum power dissipation for commercial- and
Ta = Ambient Temperature
industrial-grade devices is a function of θ .
ja
∆T = Temperature gradient between junction (silicon)
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 176-pin package at
commercial temperature and still air is as follow:
and ambient
∆T = θja * P(2)
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C
--------------------------------------------------------------------------------------------------------------------------------- ----------------------------------
= 2.86W
Maximum Power Allowed =
=
θja(°C/W)
28°C/W
The maximum power dissipation for military-grade devices is a function of θ . A sample calculation of the absolute
jc
maximum power dissipation allowed for CQFP 208-pin package at military temperature and still air is as follows:
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 125°C
--------------------------------------------------------------------------------------------------------------------------------- -------------------------------------
Maximum Power Allowed =
=
= 3.97W
θjc(°C/W)
6.3°C/W
Table 21 • Package Thermal Characteristics
θja
1.0 m/s
2.5 m/s
Plastic Packages
Pin Count
100
160
208
240
44
θjc
12.0
10.0
8.0
Still Air
27.8
26.2
26.1
25.6
20.0
25.0
22.5
24.7
38.2
35.3
18.3
200 ft/min. 500 ft/min.
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Plastic Quad Flat Pack
23.4
22.8
22.5
22.3
24.5
21.0
18.9
19.9
31.9
29.4
14.9
21.2
21.1
20.8
20.8
22.0
19.4
17.6
18.0
29.4
27.1
13.9
Plastic Quad Flat Pack
Plastic Quad Flat Pack
Plastic Quad Flat Pack
8.5
Plastic Leaded Chip Carrier
Plastic Leaded Chip Carrier
Plastic Leaded Chip Carrier
Thin Plastic Quad Flat Pack
Very Thin Plastic Quad Flat Pack
Very Thin Plastic Quad Flat Pack
Plastic Ball Grid Array
16.0
13.0
12.0
11.0
12.0
10.0
3.0
68
84
176
80
100
272
Ceramic Packages
Ceramic Quad Flat Pack
Ceramic Quad Flat Pack
208
256
2.0
2.0
22.0
20.0
19.8
16.5
18.0
15.0
°C/W
°C/W
1-22
v6.0
40MX and 42MX FPGA Families
Timing Models
Predicted
Routing
Delays
Input Delay
I/O Module
Internal Delays
Output Delay
I/O Module
t
INYL=0.62 ns
t
IRD2=2.59 ns
Logic Module
t
DLH=3.32 ns
t
t
IRD1=2.09 ns
RD1=1.28 ns
t
t
t
IRD4=3.64 ns
t
ENHZ=7.92 ns
RD2=1.80 ns
PD=1.24 ns
t
t
IRD8=5.73 ns
t
RD4=2.33 ns
CO=1.24 ns
t
RD8=4.93 ns
Array
Clock
t
CKH=4.55 ns
FO=128
F
MAX=180 MHz
Note:
* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.
Figure 1-17 • 40MX Timing Model*
Input Delays
Internal Delays Predicted
Output Delays
Routing
Delays
I/O Module
t
I/O Module
†
IRD1=2.0 ns
t
INYL=0.8 ns
Combinatorial
Logic Module
t
t
DLH=2.5 ns
RD1=0.7 ns
t
t
t
t
D
Q
RD2=1.9 ns
RD4=1.4 ns
RD8=2.3 ns
PD=1.2 ns
I/O Module
G
t
DLH=2.5 ns
Sequential
Logic Module
t
t
t
INH=0.0 ns
INSU=0.3 ns
INGL=1.3 ns
Combin
D
Q
D
G
Q
t
atoria l
-
RD1=0.70 ns
t
ENHZ=4.9 ns
Logic
include
t
t
t
OUTH=0.00 ns
OUTSU=0.3 ns
GLH=2.6 ns
t
t
t
SUD=0.3 ns
HD=0.00 ns
CO=1.3 ns
Array
Clocks
FO = 32
t
CKH=2.70 ns
F
t
MAX=296 MHz
LCO=5.2 ns (light loads, pad-to-pad)
Notes: *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.
† Input module predicted routing delay.
Figure 1-18 • 42MX Timing Model*
v6.0
1-23
40MX and 42MX FPGA Families
Input Delays
Internal Delays Predicted
Output Delays
Routing
Delays
I/O Module
t
I/O Module
†
IRD1=2.0 ns
t
INYL=0.8 ns
Combinatorial
Logic Module
t
t
DLH=2.5 ns
RD1=0.7 ns
t
t
t
t
D
Q
RD2=1.9 ns
RD4=1.4 ns
RD8=2.3 ns
PD=1.2 ns
I/O Module
G
t
DLH=2.5 ns
Sequential
Logic Module
t
t
t
INH=0.0 ns
INSU=0.3 ns
INGL=1.3 ns
Combin
D
Q
D
G
Q
t
atoria l
-
RD1=0.70 ns
t
ENHZ=4.9 ns
Logic
include
t
t
t
OUTH=0.00 ns
OUTSU=0.3 ns
GLH=2.6 ns
t
t
t
SUD=0.3 ns
HD=0.00 ns
CO=1.3 ns
Array
Clocks
FO = 32
t
CKH=2.70 ns
F
t
MAX=296 MHz
LCO=5.2 ns (light loads, pad-to-pad)
Notes: * Values are shown for A42MX36 ‘–3’ at 5.0V worst-case commercial conditions.
** Load-dependent
Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
Input Delays
I/O Module
t
t
INPY=1.0ns
IRD1=2.0ns
D
G
Q
Predicted
Routing
Delays
I/O Module
DLH=2.6ns
t
t
t
t
INSU=0.5ns
INH=0.0ns
INGO=1.4ns
RD [7:0]
RDAD [5:0]
REN
WD [7:0]
t
RD1=0.9ns
WRAD [5:0]
BLKEN
D
G
Q
WEN
WCLK
RCLK
t
t
t
t
t
ADSU=1.6ns
ADSU=1.6ns
GHL=2.9ns
LSU=0.5ns
LH=0.0ns
t
t
ADH=0.0ns
ADH=0.0ns
Array
t
t
WENSU=2.7ns
RENSU=0.6ns
Clocks
t
t
BENS=2.8ns
RCO=3.4ns
FMAX =167 MHz
Note: *Values are shown for A42MX36 ‘–3 at 5.0V worst-case commercial conditions.
Figure 1-20 • 42MX Timing Model (SRAM Functions)
1-24
v6.0
40MX and 42MX FPGA Families
Parameter Measurement
E
D
To AC test loads (shown below)
PAD
TRIBUFF
In
E
E
50% 50%
50% 50%
VCCI
50%
VOH
50%
VOH
1.5V
1.5V
PAD
1.5V
PAD
GND
PAD
90%
t
ENHZ
1.5V
10%
ENLZ
VOL
VOL
t
t
DHL
t
t
DLH
t
ENZL
ENZH
Figure 1-21 • Output Buffer Delays
Load 1
Load 2
(Used to measure propagation delay)
(Used to measure rising/falling edges)
VCCI
GND
To the output under test
t
t
t
R to V
for PLZ/ PZL
CCI
t
35 pF
R to GND for PHZ/ PZH
R=1k
Ω
To the output under test
35 pF
Figure 1-22 • AC Test Loads
S
Y
A
Y
PA D
INBUF
B
S, A or B
Y
50% 50%
50%
3V
1.5V 1.5V
50%
PAD
0V
VCCI
50%
t
PLH
PHL
t
50%
Y
GND
Y
50%
50%
t
t
t
PHL
PLH
INYL
INYH
Figure 1-24 • Module Delays
Figure 1-23 • Input Buffer Delays
v6.0
1-25
40MX and 42MX FPGA Families
Sequential Module Timing Characteristics
PRE
CLR
Y
D
E
CLK
(Positive Edge-Triggered)
t
HD
D*
G, CLK
t
t
A
t
SUD
WCLKA
t
t
SU EN A
WCLKI
t
HENA
E
t
CO
Q
t
RS
PRE, CLR
t
WASYN
Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 1-25 • Flip-Flops and Latches
1-26
v6.0
40MX and 42MX FPGA Families
Sequential Timing Characteristics
PA D
G
DATA
IBDL
CLK PA D
DATA
t
INH
G
t
INSU
t
HEXT
CLK
t
SU EXT
Figure 1-26 • Input Buffer Latches
D
PAD
OBDLHS
G
D
G
t
OUTSU
t
OUTH
Figure 1-27 • Output Buffer Latches
v6.0
1-27
40MX and 42MX FPGA Families
Decode Module Timing
A
B
C
D
E
Y
H
F
G
A–G, H
Y
50%
t
PHL
t
PLH
Figure 1-28 • Decode Module Timing
SRAM Timing Characteristics
Read Port
Write Port
WRAD [5:0]
BLKEN
RDAD [5:0]
LEW
RAM Array
32x8 or 64x4
(256 Bits)
WEN
REN
WCLK
RCLK
WD [7:0]
RD [7:0]
Figure 1-29 • SRAM Timing Characteristics
Dual-Port SRAM Timing Waveforms
tRCKHL
tRCKHL
WCLK
tADSU
tADH
WD[7:0]
WRAD[5:0]
Valid
tWENSU
tWENH
WEN
tBENSU
tBENH
Valid
BLKEN
Note: Identical timing for falling edge clock.
Figure 1-30 • 42MX SRAM Write Operation
1-28
v6.0
40MX and 42MX FPGA Families
tCKHL
tRCKHL
RCLK
REN
tRENSU
tRENH
tADSU
Valid
tADH
RDAD[5:0]
tRCO
tDOH
Old Data
New Data
RD[7:0]
Note: Identical timing for falling edge clock.
Figure 1-31 • 42MX SRAM Synchronous Read Operation
t RDADV
ADDR1
RDAD[5:0]
RD[7:0]
ADDR2
tRPD
tDOH
Data 1
Data 2
Figure 1-32 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)
WEN
tWENSU
tWENH
WD[7:0]
WRAD[5:0]
BLKEN
Valid
tADH
tADSU
WCLK
tRPD
tDOH
Old Data
New Data
RD[7:0]
Figure 1-33 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)
v6.0
1-29
40MX and 42MX FPGA Families
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on
Critical Nets and Typical Nets
the resistive and capacitive loading of the routing tracks,
the interconnect elements, and the module inputs being
driven. Propagation delay increases as the length of
routing tracks, the number of interconnect elements, or
the number of inputs increases.
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment in Actel's Designer software prior to
placement and routing. Up to 6% of the nets in a design
may be designated as critical.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout
usually requires some paths to have longer routing
tracks.
Long Tracks
The MX FPGAs deliver a tight fanout delay distribution,
which is achieved in two ways: by decreasing the delay of
the interconnect elements and by decreasing the number
of interconnect elements per path.
Some nets in the design use long tracks, which are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and
sometimes four antifuse connections, which increase
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically, up to
6 percent of nets in a fully utilized device require long
tracks. Long tracks add approximately a 3 ns to a 6 ns
delay, which is represented statistically in higher fanout
(FO=8) routing delays in the data sheet specifications
section, shown in Table 28 on page 1-36.
Actel’s patented antifuse offers a very low resistive/
capacitive interconnect. The antifuses, fabricated in
0.45 µm lithography, offer nominal levels of 100Ω
resistance and 7.0fF capacitance per antifuse.
MX fanout distribution is also tight due to the low
number of antifuses required for each interconnect path.
The proprietary architecture limits the number of
antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
Timing Derating
MX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature and worst-case processing.
Timing Characteristics
Device timing characteristics fall into three categories:
family-dependent, device-dependent, and design-
dependent. The input and output buffer characteristics
are common to all MX devices. Internal routing delays
are device-dependent; actual delays are not determined
until after place-and-route of the user's design is
complete. Delay values may then be determined by using
the Designer software utility or by performing
simulation with post-layout delays.
1-30
v6.0
40MX and 42MX FPGA Families
Temperature and Voltage Derating Factors
Table 22 • 42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 5.0V)
Temperature
25°C
42MX Voltage
–55°C
0.93
0.88
0.85
0.84
0.83
–40°C
0.95
0.90
0.87
0.86
0.85
0°C
1.05
1.00
0.96
0.95
0.94
70°C
1.25
1.18
1.15
1.12
1.10
85°C
1.29
1.22
1.18
1.14
1.13
125°C
1.41
1.34
1.29
1.28
1.26
4.50
4.75
5.00
5.25
5.50
1.09
1.03
1.00
0.97
0.96
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
–55˚C
–40˚C
0˚C
25˚C
70˚C
85˚C
125˚C
4.50
4.75
5.00
5.25
5.50
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-34 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 5.0V)
v6.0
1-31
40MX and 42MX FPGA Families
Table 23 • 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 5.0V)
Temperature
25°C
40MX Voltage
–55°C
0.89
0.84
0.82
0.80
0.79
–40°C
0.93
0.88
0.85
0.82
0.82
0°C
1.02
0.97
0.94
0.91
0.90
70°C
1.25
1.18
1.15
1.12
1.10
85°C
1.31
1.24
1.20
1.16
1.15
125°C
1.45
1.37
1.33
1.29
1.28
4.50
4.75
5.00
5.25
5.50
1.09
1.03
1.00
0.97
0.96
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
–55˚C
–40˚C
0˚C
25˚C
70˚C
85˚C
125˚C
4.50
4.75
5.00
Voltage (V)
5.25
5.50
Note: This derating factor applies to all routing and propagation delays.
Figure 1-35 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 5.0V)
1-32
v6.0
40MX and 42MX FPGA Families
Table 24 • 42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 3.3V)
Temperature
25°C
42MX Voltage
–55°C
0.97
–40°C
1.00
0°C
1.10
0.96
0.92
70°C
1.32
1.15
1.10
85°C
1.36
1.18
1.13
125°C
1.45
3.00
3.30
3.60
1.15
0.84
0.87
1.00
1.26
0.81
0.84
0.96
1.21
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
55˚C
40˚C
0˚C
25˚C
70˚C
85˚C
125˚C
3.00
3.30
3.60
Voltage (V)
(V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-36 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 3.3V)
v6.0
1-33
40MX and 42MX FPGA Families
Table 25 • 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 3.3V)
Temperature
25°C
40MX Voltage
–55°C
1.08
–40°C
1.12
0°C
1.21
0.96
0.92
70°C
1.50
1.19
1.14
85°C
1.64
1.30
1.25
125°C
2.00
3.00
3.30
3.60
1.26
0.86
0.89
1.00
1.59
0.83
0.85
0.96
1.53
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
55˚C
40˚C
0˚C
25˚C
70˚C
85˚C
125˚C
3.00
3.30
Voltage (V)
3.60
Note: This derating factor applies to all routing and propagation delays.
Figure 1-37 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 3.3V)
1-34
v6.0
40MX and 42MX FPGA Families
PCI System Timing Specification
Table 26 and Table 27 list the critical PCI timing
parameters and the corresponding timing parameters
for the MX PCI-compliant devices.
PCI Models
Actel provides synthesizable VHDL and Verilog-HDL
models for a PCI Target interface, a PCI Target and
Target+DMA Master interface. Contact your Actel sales
representative for more details.
Table 26 • Clock Specification for 33 MHz PCI
PCI
A42MX24
Min. Max.
A42MX36
Min. Max.
Symbol
tCYC
Parameter
Min.
30
Max.
Units
ns
CLK Cycle Time
CLK High Time
CLK Low Time
–
–
–
4.0
1.9
1.9
–
–
–
4.0
1.9
1.9
–
–
–
tHIGH
11
ns
tLOW
11
ns
Table 27 • Timing Parameters for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
tVAL
Parameter
Min.
Max.
Min.
Max.
9.0
9.0
4.0
8.31
–
Min.
Max.
9.0
9.0
4.0
8.31
–
Units
ns
CLK to Signal Valid—Bused Signals
CLK to Signal Valid—Point-to-Point
Float to Active
2
2 2
2
11
12
–
2.0
2.0
2.0
–
2.0
2.0
2.0
–
tVAL(PTP)
tON
ns
ns
tOFF
Active to Float
–
28
–
ns
tSU
Input Set-Up Time to CLK—Bused Signals
Input Set-Up Time to CLK—Point-to-Point
Input Hold to CLK
7
1.5
1.5
0
1.5
1.5
0
ns
tSU(PTP)
tH
10, 12 2
–
–
–
ns
0
–
–
–
ns
Notes:
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed signals.
GNT# has a setup of 10; REW# has a setup of 12.
v6.0
1-35
40MX and 42MX FPGA Families
Timing Characteristics
Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.2
2.7
1.2
1.2
1.2
1.4
3.1
1.4
1.4
1.4
1.6
3.5
1.6
1.6
1.6
1.9
4.1
1.9
1.9
1.9
2.7
5.7
2.7
2.7
2.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.8
2.3
2.9
4.9
1.5
2.1
2.7
3.3
5.7
1.7
2.4
3.0
3.7
6.5
2.0
2.8
3.6
4.4
7.6
2.8
3.9
ns
ns
ns
ns
ns
5.0
6.1
10.6
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Set-Up 3.1
3.5
0.0
3.5
0.0
3.8
4.0
0.0
4.0
0.0
4.3
4.7
0.0
4.7
0.0
5.0
6.6
0.0
6.6
0.0
7.0
ns
ns
ns
ns
ns
3
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
3.1
0.0
3.3
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
4.8
3.8
5.6
4.3
6.3
5.0
7.5
7.0
ns
tA
Flip-Flop Clock Input Period
10.4
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
181
168
154
134
80
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
Pad-to-Y LOW
0.7
0.6
0.8
0.7
0.9
0.8
1.1
1.0
1.5
1.3
ns
ns
tINYL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
1-36
v6.0
40MX and 42MX FPGA Families
Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.1
2.6
3.1
3.6
5.7
2.4
3.0
3.6
4.2
6.6
2.2
3.4
4.1
4.8
7.5
3.2
4.0
4.8
5.6
8.8
4.5
5.6
ns
ns
ns
ns
ns
6.7
7.8
12.4
Global Clock Network
tCKH Input Low to HIGH FO = 16
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
ns
FO = 128
tCKL
Input High to LOW FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
tPWH
tPWL
tCKSW
tP
Minimum Pulse
Width HIGH
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
Minimum Pulse
Width LOW
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
Maximum Skew
FO = 16
FO = 128
0.4
0.5
0.5
0.6
0.5
0.7
0.6
0.8
0.8
1.2
ns
Minimum Period
FO = 16
FO = 128
4.7
4.8
5.4
5.6
6.1
6.3
7.2
7.5
10.0
10.4
ns
fMAX
Notes:
Maximum
Frequency
FO = 16
FO = 128
188
181
175
168
160
154
139
134
83
80
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
v6.0
1-37
40MX and 42MX FPGA Families
Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing4
tDLH
tDHL
tENZH
Data-to-Pad HIGH
Data-to-Pad LOW
3.3
4.0
3.7
3.8
4.6
4.3
4.3
5.2
4.9
5.1
6.1
5.8
7.2
8.6
8.0
ns
ns
ns
Enable Pad
HIGH
Z
to
to
tENZL
tENHZ
tENLZ
Enable Pad
LOW
Z
4.7
7.9
5.9
5.4
9.1
6.8
6.1
10.4
7.7
7.2
12.2
9.0
10.1
17.1
12.6
ns
ns
ns
Enable Pad HIGH to
Z
Enable Pad LOW to
Z
dTLH
dTHL
Delta LOW to HIGH
Delta HIGH to LOW
0.02
0.03
0.02
0.03
0.03
0.03
0.03
0.04
0.04
0.06
ns/pF
ns/pF
CMOS Output Module Timing4
tDLH
tDHL
tENZH
Data-to-Pad HIGH
Data-to-Pad LOW
3.9
3.4
3.4
4.5
3.9
3.9
5.1
4.4
4.4
6.05
5.2
8.5
7.3
7.3
ns
ns
ns
Enable Pad
HIGH
Z
to
to
5.2
tENZL
tENHZ
tENLZ
Enable Pad
LOW
Z
4.9
7.9
5.9
5.6
9.1
6.8
6.4
10.4
7.7
7.5
12.2
9.0
10.5
17.0
12.6
ns
ns
ns
Enable Pad HIGH to
Z
Enable Pad LOW to
Z
dTLH
Delta LOW to HIGH
Delta HIGH to LOW
0.03
0.02
0.04
0.02
0.04
0.03
0.05
0.03
0.07
0.04
ns/pF
ns/pF
dTHL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
1-38
v6.0
40MX and 42MX FPGA Families
Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.7
3.7
1.7
1.7
1.7
2.0
4.3
2.0
2.0
2.0
2.3
4.9
2.3
2.3
2.3
2.7
5.7
2.7
2.7
2.7
3.7
8.0
3.7
3.7
3.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.0
2.7
3.4
4.2
7.1
2.2
3.1
3.9
4.8
8.2
2.5
3.5
4.4
5.4
9.2
3.0
4.1
4.2
5.7
ns
ns
ns
ns
ns
5.2
7.3
6.3
8.9
10.9
15.2
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Set-Up 4.3
4.9
0.0
4.9
0.0
5.3
5.6
0.0
5.6
0.0
6.0
6.6
0.0
6.6
0.0
7.0
9.2
0.0
9.2
0.0
9.8
ns
ns
ns
ns
ns
3
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
4.3
0.0
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active 4.6
Pulse Width
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
7.8
6.0
8.9
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
109
101
92
80
48
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
Pad-to-Y LOW
1.0
0.9
1.1
1.0
1.3
1.1
1.5
1.3
2.1
1.9
ns
ns
tINYL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-39
40MX and 42MX FPGA Families
Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.9
3.6
4.4
5.1
8.0
3.4
4.2
3.8
4.8
4.5
5.6
6.3
7.8
ns
ns
ns
ns
ns
5.0
5.7
6.7
9.4
5.9
6.7
7.8
11.0
17.3
9.26
10.5
12.6
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input LOW to HIGH FO = 16
6.4
6.4
7.4
7.4
8.3
8.3
9.8
9.8
13.7
13.7
ns
ns
FO = 128
Input HIGH to LOW FO = 16
FO = 128
6.7
6.7
7.8
7.8
8.8
8.8
10.4
10.4
14.5
14.5
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
Maximum Skew
FO = 16
0.6
0.8
0.6
0.9
0.7
1.0
0.8
1.2
1.2
1.6
ns
FO = 128
Minimum Period
FO = 16
6.5
6.8
7.5
7.8
8.5
8.9
10.1
10.4
14.1
14.6
ns
FO = 128
fMAX
Maximum Frequency FO = 16
FO = 128
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.6
5.4
6.4
6.1
7.3
7.2
8.6
10.0
12.0
11.3
14.1
23.9
17.7
0.06
0.08
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
tENLZ
dTLH
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
5.2
6.0
6.8
8.1
ns
6.6
7.6
8.6
10.1
17.1
12.6
0.04
0.06
ns
11.1
8.2
12.8
9.5
14.5
10.7
0.04
0.05
ns
ns
0.03
0.04
0.03
0.04
ns/pF
ns/pF
dTHL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1-40
v6.0
40MX and 42MX FPGA Families
Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
5.5
4.8
6.4
5.5
7.2
6.2
8.5
7.3
11.9
10.2
10.2
14.7
23.9
17.7
0.10
0.06
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
tENLZ
dTLH
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
4.7
5.5
6.2
7.3
ns
6.8
7.9
8.9
10.5
17.1
12.6
0.07
0.04
ns
11.1
8.2
12.8
9.5
14.5
10.7
0.06
0.04
ns
ns
0.05
0.03
0.05
0.03
ns/pF
ns/pF
dTHL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-41
40MX and 42MX FPGA Families
Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.2
2.3
1.2
1.2
1.2
1.4
3.1
1.4
1.4
1.4
1.6
3.5
1.6
1.6
1.6
1.9
4.1
1.9
1.9
1.9
2.7
5.7
2.7
2.7
2.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.2
1.9
2.4
2.9
5.0
1.6
2.2
2.8
3.4
5.8
1.8
2.5
3.2
3.9
6.6
2.1
2.9
3.7
4.5
7.8
3.0
4.1
ns
ns
ns
ns
ns
5.2
6.3
10.9
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Set-Up 3.1
3.5
0.0
3.5
0.0
3.8
4.0
0.0
4.0
0.0
4.3
4.7
0.0
4.7
0.0
5.0
6.6
0.0
6.6
0.0
7.0
ns
ns
ns
ns
ns
3
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
3.1
0.0
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active 3.3
Pulse Width
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
5.6
4.3
6.3
5.0
7.5
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
10.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
181
167
154
134
80
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
Pad-to-Y LOW
0.7
0.6
0.8
0.7
0.9
0.8
1.1
1.0
1.5
1.3
ns
ns
tINYL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1-42
v6.0
40MX and 42MX FPGA Families
Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.1
2.6
3.1
3.6
5.7
2.4
3.0
3.6
4.2
6.6
2.2
3.4
4.1
4.8
7.5
3.2
4.0
4.8
5.6
8.8
4.5
5.6
ns
ns
ns
ns
ns
6.7
7.8
12.4
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input Low to HIGH FO = 16
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
ns
FO = 128
Input High to LOW FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
Minimum
Width HIGH
Pulse FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
Minimum
Width LOW
Pulse FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
Maximum Skew
FO = 16
0.4
0.5
0.5
0.6
0.5
0.7
0.6
0.8
0.8
1.2
ns
FO = 128
Minimum Period
FO = 16
4.7
4.8
5.4
5.6
6.1
6.3
7.2
7.5
10.0
10.4
ns
FO = 128
fMAX
Maximum
Frequency
FO = 16
FO = 128
188
181
175
168
160
154
139
134
83
80
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
3.3
4.0
3.8
4.6
4.3
5.2
5.1
6.1
7.2
ns
ns
tDHL
Data-to-Pad LOW
8.6
tENZH
tENZL
tENHZ
tENLZ
dTLH
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
3.7
4.3
4.9
5.8
8.0
ns
4.7
5.4
6.1
7.2
10.1
17.1
12.6
0.04
0.06
ns
7.9
9.1
10.4
7.7
12.2
9.0
ns
5.9
6.8
ns
0.02
0.03
0.02
0.03
0.03
0.03
0.03
0.04
ns/pF
ns/pF
dTHL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-43
40MX and 42MX FPGA Families
Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
3.9
3.4
4.5
3.9
5.1
4.4
6.05
5.2
8.5
ns
ns
tDHL
Data-to-Pad LOW
7.3
tENZH
tENZL
tENHZ
tENLZ
dTLH
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
3.4
3.9
4.4
5.2
7.3
ns
4.9
5.6
6.4
7.5
10.5
17.0
12.6
0.07
0.04
ns
7.9
9.1
10.4
7.7
12.2
9.0
ns
5.9
6.8
ns
0.03
0.02
0.04
0.02
0.04
0.03
0.05
0.03
ns/pF
ns/pF
dTHL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1-44
v6.0
40MX and 42MX FPGA Families
Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.7
3.7
1.7
1.7
1.7
2.0
4.3
2.0
2.0
2.0
2.3
4.9
2.3
2.3
2.3
2.7
5.7
2.7
2.7
2.7
3.7
8.0
3.7
3.7
3.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.9
2.7
3.4
4.1
7.1
2.2
3.1
3.9
4.8
8.1
2.5
3.5
4.4
5.4
9.2
3.0
4.1
4.2
5.7
ns
ns
ns
ns
ns
5.2
7.3
6.3
8.9
10.9
15.2
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Set-Up 4.3
5.0
0.0
5.0
0.0
5.3
5.6
0.0
5.6
0.0
5.6
6.6
0.0
6.6
0.0
7.0
9.2
0.0
9.2
0.0
9.8
ns
ns
ns
ns
ns
3
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
4.3
0.0
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active 4.6
Pulse Width
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
7.8
5.6
8.9
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
109
101
92
80
48
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
Pad-to-Y LOW
1.0
0.9
1.1
1.0
1.3
1.1
1.5
1.3
2.1
1.9
ns
ns
tINYL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-45
40MX and 42MX FPGA Families
Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.9
3.6
4.4
5.1
8.0
3.3
4.2
5.0
5.9
9.3
3.8
4.8
4.5
5.6
6.3
7.8
ns
ns
ns
ns
ns
5.7
6.7
9.4
6.7
7.8
11.0
17.2
10.5
12.4
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input LOW to HIGH FO = 16
6.4
6.4
7.4
7.4
8.4
8.4
9.9
9.9
13.8
13.8
ns
ns
FO = 128
Input HIGH to LOW FO = 16
FO = 128
6.8
6.8
7.8
7.8
8.9
8.9
10.4
10.4
14.6
14.6
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
Maximum Skew
FO = 16
0.6
0.8
0.6
0.9
0.7
1.0
0.8
1.2
1.2
1.6
ns
FO = 128
Minimum Period
FO = 16
6.5
6.8
7.5
7.8
8.5
8.9
10.1
10.4
14.1
14.6
ns
FO = 128
fMAX
Maximum Frequency FO = 16
FO = 128
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.6
5.4
6.4
6.1
7.3
7.2
8.6
10.0
12.0
11.3
14.1
23.9
17.7
0.06
0.08
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
tENLZ
dTLH
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
5.2
6.0
6.9
8.1
ns
6.6
7.6
8.6
10.1
17.1
12.6
0.04
0.06
ns
11.1
8.2
12.8
9.5
14.5
10.7
0.04
0.05
ns
ns
0.03
0.04
0.03
0.04
ns/pF
ns/pF
dTHL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1-46
v6.0
40MX and 42MX FPGA Families
Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
5.5
4.8
6.4
5.5
7.2
6.2
8.5
7.3
11.9
10.2
10.2
14.7
23.9
17.7
0.10
0.06
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
tENLZ
dTLH
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
4.7
5.5
6.2
7.3
ns
6.8
7.9
8.9
10.5
17.1
12.6
0.07
0.04
ns
11.1
8.2
12.8
9.5
14.5
10.7
0.06
0.04
ns
ns
0.05
0.03
0.05
0.03
ns/pF
ns/pF
dTHL
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-47
40MX and 42MX FPGA Families
Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.2
1.3
1.2
1.2
1.3
1.4
1.4
1.6
1.5
1.6
1.6
1.8
1.8
1.9
1.8
2.1
2.5
2.7
2.6
2.9
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.7
0.9
1.2
1.4
2.3
0.8
1.0
1.3
1.5
2.6
0.9
1.2
1.5
1.7
2.9
1.0
1.4
1.7
2.0
3.4
1.4
1.9
2.4
2.9
4.8
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up 0.3
0.4
0.0
0.5
0.0
3.8
0.4
0.0
0.5
0.0
4.3
0.5
0.0
0.6
0.0
5.0
0.7
0.0
0.8
0.0
7.0
ns
ns
ns
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
0.4
0.0
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active 3.4
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 4.5
Pulse Width
4.9
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
3.5
0.0
0.3
0.0
0.3
3.8
0.0
0.3
0.0
0.3
4.3
0.0
0.4
0.0
0.4
5.1
0.0
0.4
0.0
0.4
7.1
0.0
0.6
0.0
0.6
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
ns
ns
ns
268
244
224
195
117
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-48
v6.0
40MX and 42MX FPGA Families
Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.0
0.8
1.3
1.3
1.2
0.9
1.4
1.4
1.3
1.0
1.6
1.6
1.6
1.2
1.9
1.9
2.2
1.7
2.7
2.7
ns
ns
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.0
2.3
2.5
2.8
3.7
2.2
2.5
2.8
3.1
4.1
2.5
2.9
3.2
3.5
4.7
3.0
3.4
3.7
4.1
5.5
4.2
4.7
5.2
5.7
7.7
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
2.4
2.7
2.7
3.0
3.0
3.4
3.6
4.0
5.0
5.5
ns
ns
FO = 256
tCKL
tPWH
tPWL
Input HIGH to LOW FO = 32
FO = 256
3.5
3.9
3.9
4.3
4.4
4.9
5.2
5.7
7.3
8.0
ns
ns
Minimum Pulse
Width HIGH
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
Minimum Pulse
Width LOW
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tCKSW
tSUEXT
tHEXT
tP
Maximum Skew
FO = 32
FO = 256
0.3
0.3
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
ns
ns
Input Latch External FO = 32
Set-Up FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO = 32
Hold
2.3
2.2
2.6
2.4
3.0
3.3
3.5
3.9
4.9
5.5
ns
ns
FO = 256
Minimum Period
FO = 32
FO = 256
3.4
3.7
3.7
4.1
4.0
4.5
4.7
5.2
7.8
8.6
ns
ns
fMAX
Notes:
Maximum Frequency FO = 32
FO = 256
296
268
269
244
247
224
215
195
129
117
MHz
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-49
40MX and 42MX FPGA Families
Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
2.5
2.9
2.6
2.9
4.9
5.3
2.6
2.6
2.7
3.2
2.9
3.2
5.4
5.9
2.9
2.9
3.1
3.6
3.3
3.7
6.2
6.7
3.3
3.3
3.6
4.3
3.9
4.3
7.3
7.9
3.8
3.8
5.1
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
6.1
10.2
11.1
5.3
G-to-Pad LOW
5.3
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
5.2
7.4
5.8
8.2
6.6
9.3
7.7
10.8
15.3
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
10.9
ns
dTLH
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
0.03
0.04
0.03
0.04
0.03
0.04
0.04
0.05
0.06 ns/pF
0.07 ns/pF
dTHL
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-50
v6.0
40MX and 42MX FPGA Families
Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
2.4
2.9
2.7
2.9
4.9
5.3
4.2
4.2
2.7
3.2
2.9
3.2
5.4
5.9
4.6
4.6
3.1
3.6
3.3
3.7
6.2
6.7
5.2
5.2
3.6
4.3
3.9
4.3
7.3
7.9
6.1
6.1
5.1
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
6.1
10.2
11.1
8.6
G-to-Pad LOW
8.6
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
5.2
7.4
5.8
8.2
6.6
9.3
7.7
10.8
15.3
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
10.9
ns
dTLH
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
0.03
0.04
0.03
0.04
0.03
0.04
0.04
0.05
0.06 ns/pF
0.07 ns/pF
dTHL
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-51
40MX and 42MX FPGA Families
Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.6
1.8
1.7
2.0
1.8
2.0
1.9
2.2
2.1
2.3
2.1
2.5
2.5
2.7
2.5
2.9
3.5
3.8
3.5
4.1
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.0
1.3
1.6
1.9
3.2
1.1
1.4
1.8
2.1
3.6
1.2
1.6
2.0
2.4
4.1
1.4
1.9
2.4
2.9
4.8
2.0
2.7
3.3
4.0
6.7
ns
ns
ns
ns
ns
Logic Module Sequential Timing 3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up 0.5
0.5
0.0
0.6
0.0
5.3
0.6
0.0
0.7
0.0
6.0
0.7
0.0
0.8
0.0
7.0
0.9
0.0
1.2
0.0
9.8
ns
ns
ns
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
0.6
0.0
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active 4.7
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 6.2
Pulse Width
6.9
7.8
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
5.0
0.0
0.3
0.0
0.3
5.6
0.0
0.3
0.0
0.3
6.2
0.0
0.3
0.0
0.3
7.1
0.0
0.4
0.0
0.4
9.9
0.0
0.6
0.0
0.6
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
ns
ns
ns
Flip-Flop (Latch) Clock
Frequency
161
146
135
117
70
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-52
v6.0
40MX and 42MX FPGA Families
Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.5
1.2
1.8
1.8
1.6
1.3
2.0
2.0
1.8
1.4
2.3
2.3
2.17
1.7
2.7
3.0
2.4
3.7
3.7
ns
ns
ns
ns
2.7
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.8
3.2
3.5
3.9
5.2
3.2
3.5
3.9
4.3
5.8
3.6
4.0
4.4
4.9
6.6
4.2
4.7
5.2
5.7
7.7
5.9
6.6
ns
ns
ns
ns
ns
7.3
8.0
10.8
Global Clock Network
tCKH Input LOW to HIGH FO = 32
4.1
4.5
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
ns
FO = 256
tCKL
tPWH
tPWL
Input HIGH to LOW FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
ns
Minimum
Width HIGH
Pulse FO = 32
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
Minimum
Width LOW
Pulse FO = 32
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
tCKSW
tSUEXT
tHEXT
tP
Maximum Skew
FO = 32
FO = 256
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
0.9
0.9
ns
ns
Input Latch External FO = 32
Set-Up FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO = 32
Hold
3.3
3.7
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
ns
FO = 256
Minimum Period
FO = 32
FO = 256
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
ns
fMAX
Notes:
Maximum
Frequency
FO = 32
FO = 256
177
161
161
146
148
135
129
117
77
70
MHz
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-53
40MX and 42MX FPGA Families
Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5
tDLH
tDHL
tENZH
Data-to-Pad HIGH
Data-to-Pad LOW
3.4
4.0
3.7
3.8
4.5
4.1
4.3
5.1
4.6
5.1
6.1
5.5
7.1
8.3
7.6
ns
ns
ns
Enable Pad
HIGH
Z
to
to
tENZL
tENHZ
tENLZ
Enable Pad
LOW
Z
4.1
6.9
7.5
4.5
7.6
8.3
5.1
8.6
9.4
6.1
8.5
ns
ns
ns
Enable Pad HIGH to
Z
10.2
11.1
14.2
15.5
Enable Pad LOW to
Z
tGLH
tGHL
tLSU
tLH
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Set-Up
I/O Latch Hold
5.8
5.8
6.5
6.5
7.3
7.3
8.6
8.6
12.0
12.0
ns
ns
ns
ns
ns
0.7
0.0
0.8
0.0
0.9
0.0
1.0
0.0
1.4
0.0
tLCO
I/O Latch Clock-to-
Out (Pad-to-Pad),
64 Clock Loading
8.7
9.7
10.9
15.4
12.9
18.1
18.0
25.3
tACO
Array Clock-to-Out
(Pad-to-Pad),
12.2
13.5
ns
64 Clock Loading
dTLH
Capacity Loading,
LOW to HIGH
0.00
0.09
0.00
0.10
0.00
0.10
0.10
0.10
0.01 ns/pF
0.10 ns/pF
dTHL
Capacity Loading,
HIGH to LOW
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-54
v6.0
40MX and 42MX FPGA Families
Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.4
4.1
3.7
4.1
6.9
7.5
5.8
5.8
3.8
4.5
4.1
4.5
7.6
8.3
6.5
6.5
5.5
4.2
4.6
5.1
8.6
9.4
7.3
7.3
6.4
5.0
9.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
7.6
6.1
8.5
10.2
11.1
8.6
14.2
15.5
12.0
12.0
G-to-Pad LOW
8.6
I/O Latch Set-Up
0.7
0.0
0.8
0.0
0.9
0.0
1.0
0.0
1.4
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
8.7
9.7
10.9
15.4
12.9
18.1
18.0
25.3
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
12.2
13.5
ns
dTLH
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
0.04
0.05
0.04
0.05
0.05
0.06
0.06
0.07
0.08 ns/pF
0.10 ns/pF
dTHL
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-55
40MX and 42MX FPGA Families
Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.4
1.4
1.4
1.6
1.5
1.6
1.5
1.7
1.7
1.8
1.7
2.0
2.0
2.1
2.0
2.3
2.8
3.0
2.8
3.3
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.8
1.0
1.3
1.6
2.6
0.9
1.2
1.4
1.7
2.9
1.0
1.3
1.6
2.0
3.2
1.2
1.5
1.9
2.3
3.8
1.6
2.1
2.7
3.2
5.3
ns
ns
ns
ns
ns
Logic Module Sequential Timing3,4
tSUD
Flip-Flop (Latch) Data Input Set-Up 0.3
0.4
0.0
0.8
0.0
3.8
0.4
0.0
0.9
0.0
4.3
0.5
0.0
1.0
0.0
5.0
0.7
0.0
1.4
0.0
7.1
ns
ns
ns
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
0.7
0.0
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active 3.4
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 4.5
Pulse Width
5.0
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
6.8
0.0
0.5
0.0
0.5
7.6
0.0
0.5
0.0
0.5
8.6
0.0
0.6
0.0
0.6
10.1
0.0
0.7
0.0
0.7
14.1
0.0
1.0
0.0
1.0
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
ns
ns
ns
215
195
179
156
94
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-56
v6.0
40MX and 42MX FPGA Families
Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.1
0.8
1.4
1.4
1.2
0.9
1.6
1.6
1.3
1.0
1.8
1.8
1.6
1.2
2.1
2.1
2.2
1.7
2.9
2.9
ns
ns
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.8
2.1
2.3
2.6
3.6
2.0
2.3
2.6
3.0
4.0
2.3
2.6
3.0
3.3
4.6
2.7
3.1
3.5
3.9
5.4
4.0
4.3
4.9
5.4
7.5
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
ns
FO = 384
tCKL
tPWH
tPWL
Input HIGH to LOW FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
5.6
6.6
7.8
9.2
ns
ns
Minimum
Width HIGH
Pulse FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
Minimum
Width LOW
Pulse FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
tCKSW
tSUEXT
tHEXT
tP
Maximum Skew
FO = 32
FO = 384
0.3
0.3
0.4
0.4
0.4
0.4
0.5
0.5
0.7
0.7
ns
ns
Input Latch External FO = 32
Set-Up FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO = 32
Hold
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
ns
FO = 384
Minimum Period
FO = 32
FO = 384
4.2
4.6
4.67
5.1
5.1
5.6
5.8
6.4
9.7
10.7
ns
ns
fMAX
Notes:
Maximum
Frequency
FO = 32
FO = 384
237
215
215
195
198
179
172
156
103
94
MHz
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-57
40MX and 42MX FPGA Families
Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLCO
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
2.5
3.0
2.7
3.0
5.4
5.0
2.9
2.9
5.7
2.8
3.3
3.0
3.3
6.0
5.6
3.2
3.2
6.3
3.2
3.7
3.4
3.8
6.8
6.3
3.6
3.6
7.1
3.7
4.4
4.0
4.4
8.0
7.4
4.3
4.3
8.4
5.2
6.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.6
6.2
11.2
10.4
6.0
G-to-Pad LOW
6.0
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
11.9
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
dTLH
dTHL
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.03
0.04
0.03
0.04
0.03
0.04
0.04
0.05
0.06 ns/pF
0.07 ns/pF
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLCO
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.2
2.5
2.7
3.0
5.4
5.0
5.1
5.1
5.7
3.6
2.7
3.0
3.3
6.0
5.6
5.6
5.6
6.3
4.0
3.1
3.4
3.8
6.8
6.3
6.4
6.4
7.1
4.7
3.6
4.0
4.4
8.0
7.4
7.5
7.5
8.4
6.6
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.6
6.2
11.2
10.4
10.5
10.5
11.9
G-to-Pad LOW
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
0.03
11.9
0.04
16.7
ns
dTLH
Capacitive Loading, LOW to HIGH
0.03
0.03
0.06 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-58
v6.0
40MX and 42MX FPGA Families
Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.9
2.0
1.9
2.2
2.1
2.2
2.1
2.4
2.4
2.5
2.4
2.8
2.8
3.0
2.8
3.3
4.0
4.2
4.0
4.6
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.1
1.5
1.8
2.2
3.6
1.2
1.6
2.0
2.4
4.0
1.4
1.8
2.3
2.7
4.5
1.6
2.1
2.7
3.2
5.3
2.3
3.0
3.8
4.5
7.5
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up 0.5
0.5
0.0
1.1
0.0
5.3
0.6
0.0
1.2
0.0
6.0
0.7
0.0
1.4
0.0
7.1
0.9
0.0
2.0
0.0
9.9
ns
ns
ns
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
1.0
0.0
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active 4.8
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 6.2
Pulse Width
6.9
7.9
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
9.5
0.0
0.7
0.0
0.7
10.6
0.0
0.8
0.0
0.8
12.0
0.0
14.1
0.0
19.8
0.0
1.4
0.0
1.4
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
0.9
1.01
0.0
ns
0.0
ns
0.89
1.01
ns
129
117
108
94
56
MHz
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-59
40MX and 42MX FPGA Families
Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.5
1.1
2.0
2.0
1.6
1.3
2.2
2.2
1.9
1.4
2.5
2.5
2.2
1.7
2.9
2.9
3.1
2.4
4.1
4.1
ns
ns
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.6
2.9
3.3
3.6
5.1
2.9
3.2
3.6
4.0
5.6
3.2
3.7
4.1
4.6
6.4
3.8
4.3
4.9
5.4
7.5
5.3
6.1
ns
ns
ns
ns
ns
6.8
7.6
10.5
Global Clock Network
tCKH Input LOW to HIGH FO = 32
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.0
9.9
ns
ns
FO = 384
tCKL
tPWH
tPWL
Input HIGH to LOW FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
Minimum Pulse
Width HIGH
FO = 32
FO = 384
5.7
6.6
6.3
7.4
7.1
8.3
8.4
9.8
11.8
13.7
ns
ns
Minimum Pulse
Width LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tCKSW
tSUEXT
tHEXT
tP
Maximum Skew
FO = 32
FO = 384
0.5
2.2
0.5
2.4
0.6
2.7
0.7
3.2
1.0
4.5
ns
ns
Input Latch External FO = 32
Set-Up FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO = 32
Hold
3.9
4.5
4.3
4.9
4.9
5.6
5.7
6.6
8.0
9.2
ns
ns
FO = 384
Minimum Period
FO = 32
FO = 384
7.0
7.7
7.8
8.6
8.4
9.3
9.7
10.7
16.2
17.8
ns
ns
fMAX
Notes:
Maximum Frequency FO = 32
FO = 384
142
129
129
117
119
108
103
94
62
56
MHz
MHz
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-60
v6.0
40MX and 42MX FPGA Families
Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLCO
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.5
4.1
3.8
4.2
7.6
7.0
4.8
4.8
8.0
3.9
4.6
4.2
4.6
8.4
7.8
5.3
5.3
8.9
4.4
5.2
4.8
5.3
9.5
8.8
6.0
6.0
10.1
5.2
6.1
7.3
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.6
7.8
6.2
8.7
11.2
10.4
7.2
15.7
14.5
10.0
10.0
16.7
G-to-Pad LOW
7.2
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
11.9
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
dTHL
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.05
0.04
0.05
0.05
0.06
0.06
0.07
0.08 ns/pF
0.10 ns/pF
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLCO
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
4.5
3.4
3.8
4.2
7.6
7.0
7.1
7.1
8.0
5.0
3.8
4.2
4.6
8.4
7.8
7.9
7.9
8.9
5.6
4.3
4.8
5.3
9.5
8.8
8.9
8.9
10.1
6.6
5.1
9.3
7.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.6
7.8
6.2
8.7
11.2
10.4
10.5
10.5
11.9
15.7
14.5
14.7
14.7
16.7
G-to-Pad LOW
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.05
0.04
0.05
0.05
0.06
0.06
0.07
0.08 ns/pF
0.10 ns/pF
dTHL
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-61
40MX and 42MX FPGA Families
Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.2
1.4
1.3
1.6
1.5
1.8
1.8
2.1
2.5
3.0
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.8
1.0
1.3
1.5
2.4
0.9
1.2
1.4
1.7
2.7
1.0
1.3
1.6
1.9
3.0
1.2
1.5
1.9
2.2
3.6
1.7
2.1
2.6
3.1
5.0
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
Latch Gate-to-Output
1.3
1.2
1.4
1.3
1.6
1.5
1.9
1.8
2.7
2.5
ns
ns
ns
ns
ns
ns
ns
ns
tGO
tSUD
tHD
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.3
0.0
0.4
0.0
0.4
0.0
0.5
0.0
0.7
0.0
tRO
1.4
1.6
1.8
2.1
2.9
tSUENA
tHENA
tWCLKA
0.4
0.0
0.5
0.0
3.7
0.5
0.0
4.2
0.6
0.0
4.9
0.8
0.0
6.9
Flip-Flop (Latch) Clock Active 3.3
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 4.4
Pulse Width
4.8
5.3
6.5
9.0
ns
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
1.0
1.3
1.1
1.4
1.3
1.6
1.5
1.9
2.1
2.6
ns
ns
ns
ns
ns
0.0
0.5
4.7
0.0
0.5
5.2
0.0
0.6
5.9
0.0
0.7
6.9
0.0
1.0
9.7
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-62
v6.0
40MX and 42MX FPGA Families
Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.8
2.1
2.3
2.5
3.4
2.0
2.3
2.5
2.8
3.8
2.3
2.6
2.9
3.2
4.3
2.7
3.1
3.4
3.7
5.1
3.8
4.3
4.8
5.2
7.1
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input LOW to HIGH FO=32
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
5.9
ns
ns
FO=486
tCKL
tPWH
tPWL
Input HIGH to LOW FO=32
FO=486
3.7
4.3
4.1
4.7
4.6
5.4
5.4
6.3
7.6
8.8
ns
ns
Minimum Pulse
Width HIGH
FO=32
FO=486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
Minimum Pulse
Width LOW
FO=32
FO=486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tCKSW
tSUEXT
tHEXT
tP
Maximum Skew
FO=32
FO=486
0.5
0.5
0.6
0.6
0.7
0.7
0.8
0.8
1.1
1.1
ns
ns
Input Latch External FO=32
Set-Up FO=486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO=32
Hold
2.8
3.3
3.1
3.7
3.5
4.2
4.1
4.9
5.7
6.9
ns
ns
FO=486
Minimum Period
FO=32
FO=486
4.7
5.1
5.2
5.7
5.7
6.2
6.5
7.1
10.9
11.9
ns
ns
(1/fMAX
)
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-63
40MX and 42MX FPGA Families
Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
2.4
2.8
2.5
2.8
5.2
4.8
2.9
2.9
2.7
3.2
2.8
3.1
5.7
5.3
3.2
3.2
3.1
3.6
3.2
3.5
6.5
6.0
3.6
3.6
3.6
4.2
3.8
4.2
7.6
7.1
4.3
4.3
5.1
5.9
5.3
5.9
10.7
9.9
6.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Output Set-Up
I/O Latch Output Hold
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.6
6.1
6.9
8.1
11.4
22.0
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
ns
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.03
0.04
0.03
0.04
0.03
0.05
0.04
0.07 ns/pF
0.06 ns/pF
dTHL
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-64
v6.0
40MX and 42MX FPGA Families
Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.1
2.4
2.5
2.8
5.2
4.8
4.9
4.9
3.5
2.6
2.8
3.1
5.7
5.3
5.4
5.4
3.9
3.0
3.2
3.5
6.5
6.0
6.2
6.2
4.6
3.5
3.8
4.2
7.6
7.1
7.2
7.2
6.4
4.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.3
5.8
10.7
9.9
10.1
10.1
G-to-Pad LOW
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
5.5
6.1
6.9
8.1
11.3
22.0
tACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
10.6
11.8
13.4
15.7
ns
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.03
0.04
0.03
0.04
0.03
0.05
0.04
0.07 ns/pF
0.06 ns/pF
dTHL
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-65
40MX and 42MX FPGA Families
Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
2.0
1.1
1.8
2.2
2.1
2.5
2.5
3.0
3.4
4.2
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.7
2.0
1.1
1.5
1.8
1.3
1.6
2.0
2.3
3.7
1.4
1.8
2.2
2.6
4.2
1.7
2.1
2.6
3.1
5.0
2.3
3.0
3.7
4.3
7.0
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
Latch Gate-to-Output
2.1
3.4
2.0
1.9
2.3
2.1
2.7
2.5
3.7
3.4
ns
ns
ns
ns
ns
ns
ns
ns
tGO
tSUD
tHD
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.4
0.0
0.5
0.0
0.6
0.0
0.7
0.0
0.9
0.0
tRO
2.0
2.2
2.5
2.9
4.1
tSUENA
tHENA
tWCLKA
0.6
0.0
0.6
0.0
5.2
0.7
0.0
5.8
0.8
0.0
6.9
1.2
0.0
9.6
Flip-Flop (Latch) Clock Active 4.6
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 6.1
Pulse Width
6.8
7.7
9.0
12.6
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.8
1.6
1.9
1.8
2.2
2.2
2.6
3.0
3.6
ns
ns
tINGO
Input Latch Gate-to-
Output
tINH
Input Latch Hold
0.0
0.7
6.5
0.0
0.7
7.3
0.0
0.8
8.2
0.0
1.0
9.7
0.0
1.4
ns
ns
ns
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
13.5
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-66
v6.0
40MX and 42MX FPGA Families
Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.6
2.9
3.2
3.5
4.8
2.9
3.2
3.6
3.9
5.3
3.2
3.6
4.0
4.4
6.1
3.8
4.3
4.8
5.2
7.1
5.3
6.0
ns
ns
ns
ns
ns
6.6
7.3
10.0
Global Clock Network
tCKH
Input LOW to HIGH FO=32
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.1
10.0
ns
ns
FO=486
tCKL
Input HIGH to LOW FO=32
FO=486
5.1
6.0
5.7
6.6
6.4
7.5
7.6
8.8
10.6
12.4
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
Minimum Pulse
Width HIGH
FO=32
FO=486
3.0
3.3
3.3
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
Minimum Pulse
Width LOW
FO=32
FO=486
3.0
3.3
3.4
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
Maximum Skew
FO=32
FO=486
0.8
0.8
0.8
0.8
1.0
1.0
1.1
1.1
1.6
1.6
ns
ns
Input Latch External FO=32
Set-Up FO=486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.4
4.0
3.6
3.9
7.2
6.7
4.8
4.8
3.8
4.4
4.0
4.4
8.0
7.5
5.3
5.3
4.3
5.0
4.5
5.0
9.1
8.5
6.0
6.0
5.0
5.9
5.3
5.8
10.7
9.9
7.2
7.2
7.1
8.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
7.4
8.2
14.9
13.9
10.0
10.0
tGHL
G-to-Pad LOW
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-67
40MX and 42MX FPGA Families
Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5 (Continued)
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
22.0
15.9
30.8
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
ns
dTLH
dTHL
Capacitive Loading, LOW to HIGH
0.05
0.04
0.05
0.04
0.06
0.05
0.07
0.06
0.10 ns/pF
0.08 ns/pF
Capacitive Loading, HIGH to LOW
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
4.8
3.5
3.6
3.4
7.2
6.7
6.8
6.8
5.3
3.9
4.0
4.0
8.0
7.5
7.6
7.6
5.5
4.1
4.5
5.0
9.0
8.5
8.6
8.6
6.4
4.9
9.0
6.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.3
7.4
5.8
8.2
10.7
9.9
14.9
13.9
14.2
14.2
10.1
10.1
G-to-Pad LOW
I/O Latch Set-Up
0.7
0.0
0.7
0.0
0.8
0.0
1.0
0.0
1.4
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
22.0
15.9
30.8
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
ns
dTLH
dTHL
tHEXT
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
Input Latch External FO=32
0.05
0.04
0.05
0.04
0.06
0.05
0.07
0.06
0.10 ns/pF
0.08 ns/pF
3.9
4.6
4.3
5.2
4.9
5.8
5.7
6.9
8.1
9.6
ns
ns
Hold
FO=486
tP
Minimum Period
FO=32
FO=486
7.8
8.6
8.7
9.5
9.5
10.4
10.8
11.9
18.2
19.9
ns
ns
(1/fMAX
)
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-68
v6.0
40MX and 42MX FPGA Families
Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.3
1.6
1.5
1.8
1.7
2.0
2.0
2.4
2.7
3.3
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
0.9
1.3
1.6
2.0
3.3
0.3
1.0
1.4
1.8
2.2
3.7
0.4
1.2
1.6
2.0
2.5
4.2
0.4
1.4
1.9
2.4
2.9
4.9
0.5
2.0
2.7
3.4
4.1
6.9
0.7
ns
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
Latch Gate-to-Output
1.3
1.3
1.4
1.4
1.6
1.6
1.9
1.9
2.7
2.7
ns
ns
ns
ns
ns
ns
ns
ns
tGO
tSUD
tHD
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.3
0.0
0.3
0.0
0.4
0.0
0.5
0.0
0.7
0.0
tRO
1.6
1.7
2.0
2.3
3.2
tSUENA
tHENA
tWCLKA
0.7
0.0
0.8
0.0
3.7
0.9
0.0
4.2
1.0
0.0
4.9
1.4
0.0
6.9
Flip-Flop (Latch) Clock Active 3.3
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 4.4
Pulse Width
4.8
5.5
6.4
9.0
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
6.8
6.8
3.4
7.5
7.5
3.8
8.5
8.5
4.3
10.0
10.0
5.0
14.0
14.0
7.0
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
Clock HIGH/LOW Time
Data Valid After Clock HIGH/LOW
Address/Data Set-Up Time
3.4
3.8
4.3
5.0
7.0
tADSU
Notes:
1.6
1.8
2.0
2.4
3.4
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-69
40MX and 42MX FPGA Families
Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Synchronous SRAM Operations (Continued)
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
tADH
Address/Data Hold Time
Read Enable Set-Up
Read Enable Hold
0.0
0.6
3.4
2.7
0.0
2.8
0.0
0.0
0.7
3.8
3.0
0.0
3.1
0.0
0.0
0.8
4.3
3.4
0.0
3.5
0.0
0.0
0.9
5.0
4.0
0.0
4.1
0.0
0.0
1.3
7.0
5.6
0.0
5.7
0.0
ns
ns
ns
ns
ns
ns
ns
tRENSU
tRENH
tWENSU
tWENH
tBENS
Write Enable Set-Up
Write Enable Hold
Block Enable Set-Up
Block Enable Hold
tBENH
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
Read Address Valid
8.1
9.0
10.2
12.0
16.8
ns
ns
ns
ns
ns
tRDADV
tADSU
tADH
8.8
1.6
0.0
9.8
1.8
0.0
0.7
11.1
2.0
13.0
2.4
18.2
3.4
0.0
Address/Data Set-Up Time
Address/Data Hold Time
0.0
0.0
tRENSUA
Read Enable Set-Up to Address 0.6
Valid
0.8
0.9
1.3
tRENHA
tWENSU
tWENH
tDOH
Read Enable Hold
Write Enable Set-Up
Write Enable Hold
Data Out Hold Time
3.4
2.7
0.0
3.8
3.0
0.0
4.3
3.4
0.0
5.0
4.0
0.0
7.0
5.6
0.0
ns
ns
ns
ns
1.2
1.3
1.5
1.8
2.5
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
1.0
1.4
1.1
1.6
1.3
1.8
1.5
2.1
2.1
2.9
ns
ns
ns
ns
ns
0.0
0.5
4.7
0.0
0.5
5.2
0.0
0.6
5.9
0.0
0.7
6.9
0.0
1.0
9.7
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-70
v6.0
40MX and 42MX FPGA Families
Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.0
2.3
2.6
3.0
4.3
2.2
2.6
2.9
3.3
4.8
2.5
2.9
3.3
3.8
5.5
2.9
3.4
3.9
4.4
6.4
4.1
4.8
5.5
6.2
9.0
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input LOW to HIGH FO=32
2.7
3.0
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
FO=635
tCKL
Input HIGH to LOW FO=32
FO=635
3.8
4.9
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse
Width HIGH
FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
Minimum Pulse
Width LOW
FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
Maximum Skew
FO=32
FO=635
0.8
0.8
0.8
0.8
0.9
0.9
1.0
1.0
1.4
1.4
ns
ns
Input Latch External FO=32
Set-Up FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO=32
Hold
2.8
3.3
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
FO=635
Minimum Period
FO=32
FO=635
5.5
6.0
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
(1/fMAX
)
fMAX
Maximum Datapath FO=32
Frequency FO=635
180
166
164
151
151
139
131
121
79
73
MHz
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
2.6
3.0
2.7
3.0
5.3
2.8
3.3
3.0
3.3
5.8
3.2
3.7
3.3
3.7
6.6
3.8
4.4
3.9
4.3
7.8
5.3
6.2
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
5.5
6.1
10.9
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-71
40MX and 42MX FPGA Families
Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5 (Continued)
tENLZ
tGLH
tGHL
tLSU
tLH
Enable Pad LOW to Z
G-to-Pad HIGH
4.9
2.9
2.9
5.5
3.3
3.3
6.2
3.7
3.7
7.3
4.4
4.4
10.2
6.1
ns
ns
ns
ns
ns
ns
G-to-Pad LOW
6.1
I/O Latch Output Set-Up
I/O Latch Output Hold
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
5.7
7.8
6.3
8.6
7.1
9.8
8.4
11.8
16.1
tACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
11.5
ns
dTLH
dTHL
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.07
0.07
0.08
0.08
0.09
0.09
0.10
0.10
0.14 ns/pF
0.14 ns/pF
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.5
2.5
2.7
2.9
5.3
4.9
5.0
5.0
3.9
2.7
3.0
3.3
5.8
5.5
5.6
5.6
4.5
3.1
3.3
3.7
6.6
6.2
6.3
6.3
5.2
3.6
3.9
4.3
7.8
7.3
7.5
7.5
7.3
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
6.1
10.9
10.2
10.4
10.4
G-to-Pad LOW
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
5.7
7.8
6.3
8.6
7.1
9.8
8.4
11.8
16.1
tACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
11.5
ns
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.07
0.07
0.08
0.08
0.09
0.09
0.10
0.10
0.14 ns/pF
0.14 ns/pF
dTHL
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-72
v6.0
40MX and 42MX FPGA Families
Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.9
2.2
2.1
2.5
2.3
2.8
2.7
3.3
3.8
4.7
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.3
1.8
2.3
2.8
4.6
0.5
1.5
2.0
2.5
3.1
5.2
0.5
1.7
2.3
2.8
3.5
5.8
0.6
2.0
2.7
3.4
4.1
6.9
0.7
2.7
3.7
4.7
5.7
9.6
1.0
ns
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
Latch Gate-to-Output
1.8
1.8
2.0
2.0
2.3
2.3
2.7
2.7
3.7
3.7
ns
ns
ns
ns
ns
ns
ns
ns
tGO
tSUD
tHD
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.4
0.0
0.5
0.0
0.6
0.0
0.7
0.0
0.9
0.0
tRO
2.2
2.4
2.7
3.2
4.5
tSUENA
tHENA
tWCLKA
1.0
0.0
1.1
0.0
5.2
1.2
0.0
5.8
1.4
0.0
6.9
2.0
0.0
9.6
Flip-Flop (Latch) Clock Active 4.6
Pulse Width
tWASYN
Flip-Flop (Latch) Asynchronous 6.1
Pulse Width
6.8
7.7
9.0
12.6
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
9.5
9.5
4.8
10.5
10.5
5.3
11.9
11.9
6.0
14.0
14.0
7.0
19.6
19.6
9.8
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
Clock HIGH/LOW Time
Data Valid After Clock HIGH/LOW
Address/Data Set-Up Time
4.8
5.3
6.0
7.0
9.8
tADSU
Notes:
2.3
2.5
2.8
3.4
4.8
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-73
40MX and 42MX FPGA Families
Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Synchronous SRAM Operations (Continued)
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
tADH
Address/Data Hold Time
Read Enable Set-Up
Read Enable Hold
0.0
0.9
4.8
3.8
0.0
3.9
0.0
0.0
1.0
5.3
4.2
0.0
4.3
0.0
0.0
1.1
6.0
4.8
0.0
4.9
0.0
0.0
1.3
7.0
5.6
0.0
5.7
0.0
0.0
1.8
9.8
7.8
0.0
8.0
0.0
ns
ns
ns
ns
ns
ns
ns
tRENSU
tRENH
tWENSU
tWENH
tBENS
Write Enable Set-Up
Write Enable Hold
Block Enable Set-Up
Block Enable Hold
tBENH
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
Read Address Valid
11.3
12.6
14.3
16.8
23.5
ns
ns
ns
ns
ns
tRDADV
tADSU
tADH
12.3
2.3
13.7
2.5
15.5
2.8
18.2
3.4
25.5
4.8
0.0
Address/Data Set-Up Time
Address/Data Hold Time
0.0
0.0
0.0
0.0
tRENSUA
Read Enable Set-Up to Address 0.9
Valid
1.0
1.1
1.3
1.8
tRENHA
tWENSU
tWENH
tDOH
Read Enable Hold
Write Enable Set-Up
Write Enable Hold
Data Out Hold Time
4.8
3.8
0.0
5.3
4.2
0.0
6.0
4.8
0.0
7.0
5.6
0.0
9.8
7.8
0.0
ns
ns
ns
ns
1.8
2.0
2.1
2.5
3.5
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
2.0
1.6
2.2
1.8
2.5
2.1
2.9
3.0
4.1
ns
ns
tINGO
Input Latch Gate-to-
Output
tINH
Input Latch Hold
0.0
0.7
6.5
0.0
0.7
7.3
0.0
0.8
8.2
0.0
1.0
9.7
0.0
1.4
ns
ns
ns
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
13.5
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-74
v6.0
40MX and 42MX FPGA Families
Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.8
3.2
3.7
4.2
6.1
3.1
3.5
4.1
4.6
6.8
3.5
4.1
4.7
5.3
7.7
4.1
4.8
5.5
6.2
9.0
5.7
6.7
ns
ns
ns
ns
ns
7.7
8.7
12.6
Global Clock Network
tCKH Input LOW to HIGH FO=32
4.6
5.0
5.1
5.6
5.7
6.3
6.7
7.4
9.3
10.3
ns
ns
FO=635
tCKL
Input HIGH to LOW FO=32
FO=635
5.3
6.8
5.9
7.6
6.7
8.6
7.8
10.1
11.0
14.1
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse
Width HIGH
FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
Minimum Pulse
Width LOW
FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
Maximum Skew
FO=32
FO=635
1.0
1.0
1.2
1.2
1.3
1.3
1.5
1.5
2.2
2.2
ns
ns
Input Latch
External Set-Up
FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch
External Hold
FO=32
FO=635
4.0
4.6
4.4
5.2
5.0
5.9
5.9
6.9
8.2
9.6
ns
ns
Minimum Period
FO=32
FO=635
9.2
9.9
10.2
11.0
11.1
12.0
12.7
13.8
21.2
23.0
ns
ns
(1/fMAX
)
fMAX
Maximum Datapath FO=32
Frequency FO=635
108
100
98
91
90
83
79
73
47
44
MHz
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.6
4.2
4.0
4.6
4.2
4.6
8.2
4.5
5.2
4.7
5.2
9.3
5.3
6.2
7.4
8.6
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
3.7
5.5
7.7
4.1
6.1
8.5
7.34
10.9
15.3
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-75
40MX and 42MX FPGA Families
Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed ‘Std’ Speed ‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5
tENLZ
tGLH
tGHL
tLSU
tLH
Enable Pad LOW to Z
G-to-Pad HIGH
6.9
4.9
4.9
7.6
5.5
5.5
8.7
6.2
6.2
10.2
7.3
14.3
10.2
10.2
ns
ns
ns
ns
ns
ns
G-to-Pad LOW
7.3
I/O Latch Output Set-Up
I/O Latch Output Hold
0.7
0.0
0.7
0.0
0.8
0.0
1.0
0.0
1.4
0.0
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
7.9
8.8
10.0
13.7
11.8
16.1
16.5
22.5
tACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
10.9
12.1
ns
dTLH
dTHL
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.10
0.10
0.11
0.11
0.12
0.12
0.14
0.14
0.20 ns/pF
0.20 ns/pF
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
4.9
3.4
3.7
4.1
7.4
6.9
7.0
7.0
5.5
3.8
4.1
4.6
8.2
7.6
7.8
7.8
6.2
4.3
4.7
5.2
9.3
8.7
8.9
8.9
7.3
5.1
10.3
7.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
7.7
6.1
8.5
10.9
10.2
10.4
10.4
15.3
14.3
14.6
14.6
G-to-Pad LOW
I/O Latch Set-Up
0.7
0.0
0.7
0.0
0.8
0.0
1.0
0.0
1.4
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
7.9
8.8
10.0
11.8
16.5
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-76
v6.0
40MX and 42MX FPGA Families
Pin Descriptions
CLK/A/B, I/O
Global Clock
PRA, I/O
PRB, I/O
Probe A/B
Clock inputs for clock distribution networks. CLK is for
40MX while CLKA and CLKB are for 42MX devices. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
The Probe pin is used to output data from any user-
defined design node within the device. Each diagnostic
pin can be used in conjunction with the other probe pin
to allow real-time diagnostic output of any signal path
within the device. The Probe pin can be used as a user-
defined I/O when verification has been completed. The
pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. The Probe
pin is accessible when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
DCLK, I/O
Diagnostic Clock
Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Ground
Input LOW supply voltage.
QCLKA/B/C/D, I/O Quadrant Clock
I/O
Input/Output
Quadrant clock inputs for A42MX36 devices. When not
used as a register control signal, these pins can function
as user I/Os.
Input, output, tristate or bi-directional buffer. Input and
output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by
the Designer software as shown in Table 40.
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
Table 40 • Configuration of Unused I/Os
Device
Configuration
Pulled LOW
Pulled LOW
Tristated
SDO, I/O
Serial Data Output
A40MX02, A40MX04
A42MX09, A42MX16
A42MX24, A42MX36
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is available for 42MX devices only.
In all cases, it is recommended to tie all unused MX I/O
pins to LOW on the board. This applies to all dual-
purpose pins when configured as I/Os as well.
When Silicon Explorer II is being used, SDO will act as an
output while the "checksum" command is run. It will
return to user I/O when "checksum" is complete.
LP
Low Power Mode
TCK, I/O
Test Clock
Controls the low power mode of all 42MX devices. The
device is placed in the low power mode by connecting
the LP pin to logic HIGH. In low power mode, all I/Os are
tristated, all input buffers are turned OFF, and the core
of the device is turned OFF. To exit the low power mode,
the LP pin must be set LOW. The device enters the low
power mode 800ns after the LP pin is driven to a logic
HIGH. It will resume normal operation in 200µs after the
LP pin is driven to a logic LOW.
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when
"Reserve JTAG" is not checked in the Designer Software.
BST pins are only available in A42MX24 and A42MX36
devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when "Reserve JTAG" is not checked in the
Designer Software. BST pins are only available in
A42MX24 and A42MX36 devices.
MODE
Mode
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). The MODE pin is held HIGH to provide
verification capability. The MODE pin should be
terminated to GND through a 10kΩ resistor so that the
MODE pin can be pulled HIGH when required.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This
pin functions as an I/O when "Reserve JTAG" is not
checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
v6.0
1-77
40MX and 42MX FPGA Families
TMS, I/O
Test Mode Select
V
Supply Voltage
CC
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins
are boundary scan pins. Once the boundary scan pins are
in test mode, they will remain in that mode until the
internal boundary scan state machine reaches the "logic
reset" state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The "logic
reset" state is reached 5 TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10kΩ pull-up resistor on the
pin. BST pins are only available in A42MX24 and
A42MX36 devices.
Input supply voltage for 40MX devices
V
Supply Voltage
CCA
Supply voltage for array in 42MX devices
V
Supply Voltage
CCI
Supply voltage for I/Os in 42MX devices
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device
this pin can be used as a dedicated output from the wide
decode module. This direct connection eliminates
additional interconnect delays associated with regular
logic modules. To implement the direct I/O connection,
connect an output buffer of any type to the output of
the wide decode macro and place this output on one of
the reserved WD pins.
1-78
v6.0
40MX and 42MX FPGA Families
Package Pin Assignments
44-Pin PLCC
1
44
44-Pin
PLCC
Figure 2-1 • 44-Pin PLCC
44-pin PLCC
44-pin PLCC
Pin Number A40MX02 Function A40MX04 Function
Pin Number A40MX02 Function A40MX04 Function
1
2
I/O
I/O
I/O
I/O
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I/O
I/O
I/O
3
VCC
I/O
VCC
I/O
VCC
VCC
4
I/O
I/O
5
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
I/O
GND
I/O
GND
CLK, I/O
MODE
VCC
GND
CLK, I/O
MODE
VCC
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
v6.0
2-1
40MX and 42MX FPGA Families
68-Pin PLCC
1 68
68-Pin
PLCC
Figure 2-2 • 68-Pin PLCC
44-pin PLCC
44-pin PLCC
44-pin PLCC
Pin
A40MX02 A40MX04
Pin
A40MX02 A40MX04
Pin
A40MX02 A40MX04
Number
Function
Function
Number
Function
Function
Number
Function
Function
1
2
I/O
I/O
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O
I/O
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
3
I/O
I/O
GND
I/O
GND
I/O
4
VCC
I/O
VCC
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
CLK, I/O
I/O
CLK, I/O
I/O
7
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
MODE
VCC
MODE
VCC
9
I/O
I/O
GND
I/O
GND
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
I/O
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
GND
GND
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-2
v6.0
40MX and 42MX FPGA Families
84-Pin PLCC
1 84
84-Pin
PLCC
Figure 2-3 • 84-Pin PLCC
v6.0
2-3
40MX and 42MX FPGA Families
84-Pin PLCC
84-Pin PLCC
Pin
A40MX04 A42MX09 A42MX16 A42MX24
Pin
A40MX04 A42MX09 A42MX16 A42MX24
Number Function Function Function Function
Number Function Function Function Function
1
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
CLKB, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
I/O
2
CLKB, I/O CLKB, I/O
3
I/O
PRB, I/O
I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
4
PRB, I/O
WD, I/O
GND
I/O
I/O
I/O
I/O
5
GND
I/O
I/O
I/O
6
GND
I/O
GND
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
8
I/O
I/O
WD, I/O
WD, I/O
DCLK, I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
9
I/O
I/O
I/O
WD, I/O
WD, I/O
WD, I/O
WD, I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DCLK, I/O DCLK, I/O
I/O
I/O
I/O
I/O
MODE
I/O
I/O
MODE
I/O
VCC
I/O
I/O
I/O
MODE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDO, I/O
I/O
SDO, I/O SDO, TDO, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
VCCI
VCCA
I/O
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
LP
GND
I/O
GND
I/O
GND
I/O
I/O
LP
LP
CLK, I/O
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MODE
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS, I/O
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
2-4
v6.0
40MX and 42MX FPGA Families
84-Pin PLCC
84-Pin PLCC
A40MX04 A42MX09 A42MX16 A42MX24
Pin
A40MX04 A42MX09 A42MX16 A42MX24
Number Function Function Function Function
Pin
Number Function Function Function Function
71
72
73
74
75
76
77
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
78
79
80
81
82
83
84
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
PRA, I/O
I/O
I/O
I/O
I/O
GND
I/O
SDI, I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
CLKA, I/O CLKA, I/O
VCCA VCCA
CLKA, I/O
VCCA
I/O
I/O
v6.0
2-5
40MX and 42MX FPGA Families
100-Pin PQFP Package
100-Pin
PQFP
100
1
Figure 2-4 • 100-Pin PQFP Package (Top View)
2-6
v6.0
40MX and 42MX FPGA Families
100-Pin PQFP
100-Pin PQFP
A40MX02 A40MX04 A42MX09 A42MX16
Pin
A40MX02 A40MX04 A42MX09 A42MX16
Number Function Function Function Function
Pin
Number Function Function Function Function
1
NC
NC
NC
NC
NC
PRB, I/O
I/O
NC
NC
NC
NC
NC
PRB, I/O
I/O
I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
GND
GND
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
2
DCLK, I/O DCLK, I/O
3
I/O
MODE
I/O
I/O
MODE
I/O
I/O
I/O
4
I/O
I/O
I/O
I/O
5
I/O
I/O
VCCA
I/O
VCCA
I/O
6
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
VCC
VCC
I/O
VCC
VCC
I/O
I/O
I/O
9
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
NC
NC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
VCCA
VCCA
I/O
NC
NC
NC
NC
NC
VCC
I/O
I/O
I/O
I/O
I/O
SDO, I/O
I/O
SDO, I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
NC
I/O
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
LP
LP
I/O
I/O
I/O
I/O
VCCA
VCCI
VCCA
I/O
VCCA
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
v6.0
2-7
40MX and 42MX FPGA Families
100-Pin PQFP
100-Pin PQFP
Pin
A40MX02 A40MX04 A42MX09 A42MX16
Pin
A40MX02 A40MX04 A42MX09 A42MX16
Number Function Function Function Function
Number Function Function Function Function
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
GND
I/O
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
GND
I/O
GND
GND
I/O
I/O
PRA, I/O
I/O
I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O CLKA, I/O
I/O
I/O
CLK, I/O
I/O
CLK, I/O
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
MODE
VCC
MODE
VCC
CLKB, I/O
I/O
CLKB, I/O
I/O
I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
VCC
VCC
PRB, I/O
I/O
PRB, I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
GND
I/O
GND
I/O
I/O
I/O
NC
I/O
I/O
I/O
SDI, I/O
SDI, I/O
I/O
I/O
GND
I/O
GND
I/O
DCLK, I/O DCLK, I/O
PRA, I/O PRA, I/O
I/O
I/O
I/O
I/O
2-8
v6.0
40MX and 42MX FPGA Families
160-Pin PQFP Package
160
1
160-Pin
PQFP
Figure 2-5 • 160-Pin PQFP Package (Top View)
v6.0
2-9
40MX and 42MX FPGA Families
160-Pin PQFP
160-Pin PQFP
A42MX09
Function
A42MX16
Function
A42MX24
Function
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
Pin Number
1
I/O
DCLK, I/O
NC
I/O
I/O
DCLK, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
WD, I/O
WD, I/O
SDI, I/O
I/O
2
DCLK, I/O
I/O
I/O
3
SDI, I/O
I/O
SDI, I/O
I/O
4
I/O
I/O
WD, I/O
WD, I/O
VCCI
5
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
6
NC
VCCI
I/O
7
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
NC
I/O
I/O
GND
NC
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
I/O
I/O
I/O
NC
VCCA
I/O
VCCA
I/O
VCCA
CLKA, I/O
I/O
VCCA
CLKA, I/O
I/O
VCCA
CLKA, I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
GND
VCCA
LP
VCCA
VCCI
GND
VCCA
LP
VCCA
VCCI
GND
VCCA
LP
PRA, I/O
NC
PRA, I/O
I/O
PRA, I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
GND
WD, I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
GND
I/O
GND
I/O
NC
VCCI
VCCI
2-10
v6.0
40MX and 42MX FPGA Families
160-Pin PQFP
160-Pin PQFP
A42MX09
Function
A42MX16
Function
A42MX24
Function
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
71
Pin Number
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
72
I/O
I/O
73
I/O
I/O
I/O
I/O
I/O
74
I/O
I/O
I/O
GND
NC
I/O
GND
I/O
GND
I/O
75
NC
I/O
I/O
76
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
77
NC
I/O
I/O
I/O
I/O
78
I/O
I/O
I/O
I/O
I/O
79
NC
I/O
I/O
NC
I/O
VCCI
I/O
VCCI
WD, I/O
WD, I/O
I/O
80
GND
I/O
GND
I/O
GND
I/O
81
NC
I/O
I/O
82
SDO, I/O
I/O
SDO, I/O
I/O
SDO, TDO, I/O
WD, I/O
WD, I/O
I/O
I/O
83
I/O
I/O
TDI, I/O
TMS, I/O
GND
I/O
84
I/O
I/O
I/O
I/O
85
I/O
I/O
GND
I/O
GND
I/O
86
NC
VCCI
I/O
VCCI
I/O
87
I/O
I/O
I/O
I/O
88
I/O
I/O
WD, I/O
GND
I/O
I/O
I/O
I/O
89
GND
NC
GND
I/O
NC
GND
I/O
I/O
I/O
90
GND
I/O
GND
I/O
91
I/O
I/O
I/O
92
I/O
I/O
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
I/O
I/O
I/O
94
I/O
I/O
I/O
NC
GND
I/O
I/O
I/O
95
I/O
I/O
I/O
GND
I/O
GND
I/O
96
I/O
I/O
WD, I/O
I/O
97
I/O
I/O
I/O
I/O
I/O
98
VCCA
GND
NC
VCCA
GND
I/O
VCCA
GND
I/O
I/O
I/O
I/O
99
I/O
I/O
I/O
100
101
102
103
104
105
NC
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
VCCI
GND
VCCA
VCCI
GND
VCCA
VCCI
GND
I/O
I/O
I/O
I/O
I/O
I/O
v6.0
2-11
40MX and 42MX FPGA Families
160-Pin PQFP
160-Pin PQFP
A42MX09
Function
A42MX16
Function
A42MX24
Function
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
141
Pin Number
151
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
142
I/O
152
NC
143
I/O
I/O
I/O
153
NC
I/O
I/O
144
I/O
I/O
I/O
154
NC
I/O
I/O
145
GND
NC
I/O
GND
I/O
GND
I/O
155
GND
I/O
GND
I/O
GND
I/O
146
156
147
I/O
I/O
157
I/O
I/O
I/O
148
I/O
I/O
I/O
158
I/O
I/O
I/O
149
I/O
I/O
I/O
159
MODE
GND
MODE
GND
MODE
GND
150
NC
VCCA
VCCA
160
2-12
v6.0
40MX and 42MX FPGA Families
208-Pin PQFP Package
208
1
208-Pin PQFP
Figure 2-6 • 208-Pin PQFP Package (Top View)
v6.0
2-13
40MX and 42MX FPGA Families
208-Pin PQFP
208-Pin PQFP
A42MX16
Function
A42MX24
A42MX36
Function
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
Function
GND
VCCA
MODE
I/O
Pin Number
1
GND
NC
MODE
I/O
GND
VCCA
MODE
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
I/O
I/O
2
I/O
3
I/O
I/O
I/O
4
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
I/O
9
NC
NC
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
GND
GND
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
GND
GND
TMS, I/O
TDI, I/O
I/O
GND
GND
TMS, I/O
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
NC
NC
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKA, I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
2-14
v6.0
40MX and 42MX FPGA Families
208-Pin PQFP
208-Pin PQFP
A42MX16
Function
A42MX24
Function
A42MX36
Function
A42MX16
A42MX24
Function
A42MX36
Function
Pin Number
71
Pin Number
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Function
NC
I/O
I/O
WD, I/O
I/O
WD, I/O
I/O
VCCA
I/O
VCCA
I/O
72
I/O
73
I/O
I/O
I/O
I/O
I/O
I/O
74
I/O
I/O
I/O
I/O
I/O
I/O
75
I/O
I/O
I/O
I/O
I/O
I/O
76
I/O
I/O
I/O
I/O
I/O
I/O
77
I/O
I/O
I/O
NC
NC
NC
NC
I/O
I/O
I/O
78
GND
VCCA
NC
GND
VCCA
VCCI
I/O
GND
VCCA
VCCI
I/O
I/O
I/O
79
I/O
I/O
80
I/O
I/O
81
I/O
I/O
I/O
82
I/O
I/O
I/O
I/O
I/O
I/O
83
I/O
I/O
I/O
I/O
I/O
I/O
84
I/O
I/O
I/O
I/O
I/O
I/O
85
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
86
I/O
I/O
I/O
I/O
87
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
I/O
I/O
89
NC
I/O
I/O
I/O
I/O
I/O
90
NC
I/O
I/O
I/O
I/O
I/O
91
I/O
I/O
QCLKB, I/O
I/O
GND
I/O
GND
I/O
GND
I/O
92
I/O
I/O
93
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
TCK, I/O
LP
TCK, I/O
LP
94
I/O
LP
95
NC
VCCA
GND
VCCI
VCCA
I/O
VCCA
GND
VCCI
VCCA
I/O
VCCA
GND
VCCI
VCCA
I/O
96
NC
I/O
I/O
97
NC
I/O
I/O
98
VCCI
I/O
VCCI
I/O
VCCI
I/O
99
100
101
102
103
104
105
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
SDO, I/O
I/O
SDO, TDO, I/O SDO, TDO, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
I/O
I/O
I/O
v6.0
2-15
40MX and 42MX FPGA Families
208-Pin PQFP
208-Pin PQFP
A42MX16
Function
A42MX24
Function
A42MX36
Function
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
Pin Number
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
NC
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
GND
I/O
I/O
I/O
CLKA, I/O
NC
CLKA, I/O
I/O
CLKA, I/O
I/O
I/O
I/O
I/O
I/O
NC
VCCI
VCCI
I/O
I/O
VCCA
GND
I/O
VCCA
GND
I/O
VCCA
GND
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
NC
I/O
I/O
NC
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
QCLKC, I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
VCCI
NC
NC
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
VCCI
I/O
VCCI
VCCI
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
NC
I/O
I/O
QCLKD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
I/O
I/O
I/O
2-16
v6.0
40MX and 42MX FPGA Families
240-Pin PQFP Package
240
1
•
•
•
•
•
•
240-Pin
PQFP
Figure 2-7 • 240-Pin PQFP Package (Top View)
v6.0
2-17
40MX and 42MX FPGA Families
240-Pin PQFP
240-Pin PQFP
240-Pin PQFP
240-Pin PQFP
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Number
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Number
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
1
I/O
DCLK, I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
71
VCCI
I/O
I/O
I/O
2
72
3
73
I/O
VCCI
I/O
4
I/O
74
I/O
5
I/O
I/O
75
I/O
I/O
6
WD, I/O
WD, I/O
VCCI
I/O
76
I/O
I/O
7
I/O
77
I/O
I/O
8
I/O
78
I/O
I/O
9
I/O
I/O
79
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
QCLKD, I/O
I/O
80
I/O
I/O
I/O
81
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
82
I/O
I/O
I/O
83
I/O
VCCA
GND
GND
GND
I/O
I/O
84
I/O
QCLKC, I/O
I/O
I/O
85
VCCA
I/O
I/O
86
WD, I/O
WD, I/O
I/O
VCCI
I/O
87
I/O
88
VCCA
VCCI
VCCA
LP
SDO, TDO, I/O
I/O
WD, I/O
WD, I/O
I/O
89
I/O
90
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
91
SDI, I/O
I/O
92
TCK, I/O
I/O
93
VCCI
I/O
PRB, I/O
I/O
VCCA
GND
GND
I/O
94
GND
I/O
95
I/O
CLKB, I/O
I/O
96
I/O
I/O
97
I/O
WD, I/O
WD, I/O
I/O
GND
VCCA
VCCI
I/O
98
I/O
I/O
99
I/O
I/O
100
101
102
103
104
105
I/O
QCLKB, I/O
I/O
I/O
I/O
I/O
CLKA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-18
v6.0
40MX and 42MX FPGA Families
240-Pin PQFP
240-Pin PQFP
240-Pin PQFP
Pin
A42MX36
Function
Pin
A42MX36
Function
Pin
A42MX36
Function
Number
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
Number
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Number
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
TDI, I/O
TMS, I/O
GND
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCI
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKA, I/O
I/O
I/O
I/O
I/O
GND
MODE
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCI
I/O
I/O
WD, I/O
WD, I/O
VCCA
VCCI
v6.0
2-19
40MX and 42MX FPGA Families
80-Pin VQFP
80
1
80-Pin
VQFP
Figure 2-8 • 80-Pin VQFP
2-20
v6.0
40MX and 42MX FPGA Families
80-Pin VQFP
80-Pin VQFP
80-Pin VQFP
Pin
A40MX02 A40MX04
Pin
A40MX02 A40MX04
Pin
A40MX02 A40MX04
Number
Function
Function
Number
Function
Function
Number
Function
Function
1
I/O
I/O
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
I/O
I/O
55
NC
I/O
2
NC
NC
NC
I/O
I/O
I/O
I/O
56
NC
I/O
3
I/O
I/O
I/O
57
58
SDI, I/O
DCLK, I/O
PRA, I/O
NC
SDI, I/O
DCLK, I/O
PRA, I/O
NC
4
I/O
I/O
I/O
5
I/O
I/O
I/O
59
60
6
I/O
I/O
VCC
I/O
VCC
I/O
7
GND
I/O
GND
I/O
61
PRB, I/O
I/O
PRB, I/O
I/O
8
I/O
I/O
62
9
I/O
I/O
I/O
I/O
63
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
I/O
I/O
I/O
I/O
64
I/O
I/O
I/O
I/O
I/O
I/O
65
I/O
I/O
I/O
I/O
I/O
I/O
66
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
67
I/O
I/O
NC
I/O
68
GND
I/O
GND
I/O
I/O
I/O
NC
I/O
69
I/O
I/O
NC
I/O
70
I/O
I/O
NC
NC
NC
VCC
I/O
I/O
I/O
I/O
71
I/O
I/O
I/O
I/O
I/O
72
I/O
I/O
I/O
I/O
I/O
73
I/O
I/O
VCC
I/O
GND
I/O
GND
I/O
74
VCC
I/O
VCC
I/O
75
I/O
I/O
I/O
I/O
76
I/O
I/O
I/O
I/O
CLK, I/O
I/O
CLK, I/O
I/O
77
I/O
I/O
I/O
I/O
78
I/O
I/O
I/O
I/O
MODE
VCC
NC
MODE
VCC
I/O
79
I/O
I/O
I/O
I/O
80
I/O
I/O
GND
GND
v6.0
2-21
40MX and 42MX FPGA Families
100-Pin VQFP Package
100
1
100-Pin
VQFP
Figure 2-9 • 100-Pin VQFP Package (Top View)
2-22
v6.0
40MX and 42MX FPGA Families
100-Pin VQFP Package
100-Pin VQFP Package
Pin A42MX09 A42MX16
100-Pin VQFP Package
Pin A42MX09 A42MX16
Pin
A42MX09 A42MX16
Number
Function
Function
Number
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Function
Function
Number
Function
Function
1
I/O
I/O
I/O
I/O
71
I/O
I/O
2
MODE
I/O
MODE
I/O
I/O
I/O
72
I/O
I/O
3
VCCA
I/O
VCCA
I/O
73
I/O
I/O
4
I/O
I/O
74
I/O
I/O
5
I/O
I/O
I/O
I/O
75
I/O
I/O
6
I/O
I/O
I/O
I/O
76
I/O
I/O
7
GND
I/O
GND
I/O
I/O
I/O
77
SDI, I/O
I/O
SDI, I/O
I/O
8
I/O
I/O
78
9
I/O
I/O
GND
I/O
GND
I/O
79
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
80
I/O
I/O
I/O
I/O
I/O
I/O
81
I/O
I/O
I/O
I/O
I/O
I/O
82
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
83
VCCA
VCCI
I/O
NC
VCCI
I/O
I/O
I/O
84
I/O
I/O
SDO, I/O
I/O
SDO, I/O
I/O
85
PRA, I/O
I/O
PRA, I/O
I/O
86
I/O
I/O
I/O
I/O
87
CLKA, I/O
VCCA
I/O
CLKA, I/O
VCCA
I/O
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
89
GND
I/O
GND
I/O
GND
I/O
GND
I/O
90
CLKB, I/O
I/O
CLKB, I/O
I/O
91
I/O
I/O
I/O
I/O
92
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
I/O
94
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
95
I/O
I/O
I/O
I/O
96
I/O
I/O
I/O
I/O
LP
LP
97
I/O
I/O
I/O
I/O
VCCA
VCCI
VCCA
I/O
VCCA
VCCI
VCCA
I/O
98
I/O
I/O
I/O
I/O
99
I/O
I/O
I/O
I/O
100
DCLK, I/O
DCLK, I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
v6.0
2-23
40MX and 42MX FPGA Families
176-Pin TQFP Package
176
1
176-Pin
TQFP
Figure 2-10 • 176-Pin TQFP Package (Top View)
2-24
v6.0
40MX and 42MX FPGA Families
176-Pin TQFP
176-Pin TQFP
A42MX09
A42MX16
Function
A42MX24
Function
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
Function
GND
MODE
I/O
Pin Number
1
GND
MODE
I/O
GND
MODE
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCA
I/O
I/O
I/O
I/O
2
NC
NC
I/O
3
I/O
4
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
8
NC
NC
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
NC
I/O
I/O
GND
I/O
GND
TMS, I/O
TDI, I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
VCCI
I/O
GND
NC
GND
I/O
GND
I/O
NC
NC
I/O
I/O
NC
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
GND
NC
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
VCCA
NC
I/O
NC
I/O
NC
I/O
I/O
I/O
VCCI
NC
VCCA
I/O
VCCA
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND
VCCA
I/O
I/O
I/O
I/O
I/O
GND
VCCA
WD, I/O
WD, I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
v6.0
2-25
40MX and 42MX FPGA Families
176-Pin TQFP
176-Pin TQFP
A42MX09
Function
A42MX16
Function
A42MX24
Function
A42MX09
A42MX16
Function
A42MX24
Function
Pin Number
71
Pin Number
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Function
GND
NC
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
72
I/O
73
I/O
I/O
I/O
NC
I/O
TCK, I/O
LP
74
NC
I/O
I/O
I/O
LP
LP
75
I/O
I/O
VCCA
GND
VCCI
VCCA
NC
VCCA
GND
VCCI
VCCA
I/O
VCCA
GND
VCCI
VCCA
I/O
76
I/O
I/O
I/O
77
NC
NC
I/O
NC
I/O
WD, I/O
WD, I/O
I/O
78
79
I/O
80
NC
I/O
I/O
I/O
NC
I/O
I/O
81
I/O
I/O
NC
VCCA
I/O
VCCA
I/O
82
NC
I/O
VCCI
I/O
VCCI
I/O
I/O
83
I/O
I/O
I/O
84
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
I/O
86
NC
SDO, I/O
I/O
I/O
NC
NC
I/O
87
SDO, I/O
I/O
SDO, TDO, I/O
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
89
GND
I/O
GND
I/O
GND
I/O
NC
I/O
I/O
90
NC
I/O
I/O
91
I/O
I/O
I/O
NC
NC
I/O
92
I/O
I/O
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
I/O
I/O
I/O
94
I/O
I/O
I/O
I/O
I/O
I/O
95
I/O
I/O
I/O
I/O
I/O
I/O
96
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
97
I/O
I/O
I/O
I/O
I/O
98
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
99
I/O
I/O
I/O
100
101
102
103
104
105
I/O
I/O
I/O
SDI, I/O
NC
SDI, I/O
I/O
SDI, I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
VCCI
VCCI
2-26
v6.0
40MX and 42MX FPGA Families
176-Pin TQFP
176-Pin TQFP
A42MX09
Function
A42MX16
Function
A42MX24
Function
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
141
Pin Number
159
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
I/O
PRB, I/O
WD, I/O
WD, I/O
I/O
142
I/O
160
PRB, I/O
NC
143
NC
I/O
I/O
161
144
NC
I/O
WD, I/O
WD, I/O
I/O
162
I/O
I/O
145
NC
NC
163
I/O
I/O
146
I/O
I/O
164
I/O
I/O
I/O
147
NC
I/O
I/O
165
NC
NC
WD, I/O
WD, I/O
I/O
148
I/O
I/O
I/O
166
NC
I/O
149
I/O
I/O
I/O
167
I/O
I/O
150
I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
168
NC
I/O
I/O
151
NC
I/O
169
I/O
I/O
I/O
152
PRA, I/O
I/O
PRA, I/O
I/O
170
NC
VCCI
I/O
VCCI
153
171
I/O
WD, I/O
WD, I/O
I/O
154
CLKA, I/O
VCCA
GND
I/O
CLKA, I/O
VCCA
GND
I/O
CLKA, I/O
VCCA
GND
172
I/O
I/O
155
173
NC
I/O
156
174
I/O
I/O
I/O
157
I/O
175
DCLK, I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
158
CLKB, I/O
CLKB, I/O
CLKB, I/O
176
v6.0
2-27
40MX and 42MX FPGA Families
208-Pin CQFP
)
208207206205204203202201200
164163162161160159158157
Pin #1
Index
1
2
3
4
5
6
7
8
156
155
154
153
152
151
150
149
A42MX36
208-Pin
CQFP
44
45
46
47
48
49
50
51
52
113
112
111
110
109
108
107
106
105
53 54 55 56 57 58 59 60 61
97 98 99 100101102103104
Figure 2-11 • 208-Pin CQFP (Top View)
2-28
v6.0
40MX and 42MX FPGA Families
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Number
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
1
GND
VCCA
MODE
I/O
I/O
I/O
71
WD, I/O
I/O
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
VCCA
I/O
2
72
3
I/O
73
I/O
I/O
4
I/O
74
I/O
I/O
5
I/O
I/O
75
I/O
I/O
6
I/O
I/O
76
I/O
I/O
7
I/O
I/O
77
I/O
I/O
8
I/O
I/O
78
GND
VCCA
VCCI
I/O
I/O
9
I/O
I/O
79
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
80
I/O
I/O
I/O
81
I/O
I/O
I/O
82
I/O
I/O
I/O
I/O
83
I/O
I/O
I/O
I/O
84
I/O
I/O
I/O
I/O
85
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
86
I/O
VCCA
I/O
GND
GND
TMS, I/O
TDI, I/O
I/O
87
I/O
88
I/O
I/O
I/O
89
I/O
I/O
I/O
90
I/O
I/O
I/O
91
QCLKB, I/O
I/O
GND
I/O
GND
I/O
WD, I/O
WD, I/O
I/O
92
93
WD, I/O
WD, I/O
I/O
TCK, I/O
LP
I/O
94
I/O
VCCI
I/O
95
VCCA
GND
VCCI
VCCA
I/O
I/O
96
I/O
GND
VCCI
VCCA
I/O
I/O
97
I/O
I/O
98
VCCI
I/O
I/O
99
QCLKA, I/O
WD, I/O
WD, I/O
I/O
100
101
102
103
104
105
WD, I/O
WD, I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
GND
I/O
v6.0
2-29
40MX and 42MX FPGA Families
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Pin
A42MX36
Function
Pin
A42MX36
Function
Number
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
Number
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
Number
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
I/O
I/O
I/O
SDI, I/O
I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
QCLKC, I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
CLKA, I/O
I/O
I/O
VCCI
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
VCCA
I/O
GND
I/O
I/O
GND
I/O
WD, I/O
WD, I/O
I/O
I/O
VCCI
I/O
CLKB, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
QCLKD, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
DCLK, I/O
I/O
GND
I/O
2-30
v6.0
40MX and 42MX FPGA Families
256-Pin CQFP
256255254253252251250249248
200199198197196195194193
Pin #1
Index
1
2
3
4
5
6
7
8
192
191
190
189
188
187
186
185
A42MX36
256-Pin
CQFP
56
57
58
59
60
61
62
63
64
137
136
135
134
133
132
131
130
129
65 66 67 68 69 70 71 72 73
121122123124125126127128
Figure 2-12 • 256-Pin CQFP (Top View)
v6.0
2-31
40MX and 42MX FPGA Families
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Number
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Number
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
1
NC
GND
I/O
GND
I/O
71
I/O
VCCI
I/O
WD, I/O
I/O
2
72
3
I/O
73
I/O
4
I/O
I/O
74
I/O
WD, I/O
WD, I/O
I/O
5
I/O
I/O
75
I/O
6
I/O
I/O
76
WD, I/O
GND
WD, I/O
I/O
7
I/O
I/O
77
QCLKA, I/O
I/O
8
I/O
I/O
78
9
I/O
I/O
79
GND
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
GND
I/O
I/O
80
QCLKB, I/O
I/O
I/O
81
I/O
I/O
I/O
82
I/O
I/O
I/O
GND
I/O
83
I/O
I/O
I/O
84
I/O
VCCI
I/O
I/O
I/O
85
I/O
I/O
I/O
86
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
87
WD, I/O
WD, I/O
I/O
I/O
I/O
88
I/O
I/O
89
I/O
I/O
I/O
90
I/O
I/O
I/O
I/O
91
I/O
I/O
I/O
I/O
92
I/O
GND
NC
I/O
I/O
93
I/O
I/O
I/O
94
I/O
NC
I/O
VCCA
GND
GND
NC
95
VCCI
VCCA
GND
GND
I/O
NC
VCCA
I/O
96
GND
I/O
97
I/O
98
I/O
VCCA
VCCI
GND
VCCA
LP
NC
99
I/O
NC
100
101
102
103
104
105
I/O
I/O
I/O
I/O
I/O
SDO, TDO, I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
I/O
WD, I/O
WD, I/O
I/O
GND
I/O
WD, I/O
2-32
v6.0
40MX and 42MX FPGA Families
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
Pin
A42MX36
Function
Pin
A42MX36
Function
Pin
A42MX36
Function
Pin
Number
A42MX36
Function
Number
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
Number
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Number
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
246
247
248
249
250
251
252
253
254
255
256
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
GND
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
SDI, I/O
I/O
I/O
I/O
I/O
I/O
CLKB, I/O
I/O
GND
NC
I/O
I/O
I/O
I/O
GND
GND
VCCA
VCCI
I/O
MODE
VCCA
GND
NC
I/O
VCCA
I/O
I/O
I/O
NC
CLKA, I/O
I/O
VCCA
VCCI
GND
I/O
NC
I/O
PRA, I/O
I/O
DCLK, I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
VCCI
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
QCLKD, I/O
I/O
GND
I/O
I/O
WD, I/O
GND
WD, I/O
I/O
I/O
I/O
I/O
QCLKC, I/O
I/O
I/O
v6.0
2-33
40MX and 42MX FPGA Families
272-Pin BGA Package
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
H
J
272-Pin PBGA
K
L
M
N
P
R
T
U
V
W
Y
Figure 2-13 • 272-Pin BGA Package (Top View)
2-34
v6.0
40MX and 42MX FPGA Families
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Pin
A42MX36
Function
Pin
Number
A42MX36
Function
Number
B16
B17
B18
B19
B20
C1
Number
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
A1
GND
GND
I/O
I/O
WD, I/O
I/O
I/O
VCCI
I/O
H2
H3
I/O
I/O
A2
A3
H4
VCCA
I/O
A4
WD, I/O
I/O
GND
GND
I/O
VCCI
I/O
H17
H18
H19
H20
J1
A5
I/O
A6
I/O
VCCA
GND
I/O
I/O
A7
WD, I/O
WD, I/O
I/O
C2
MODE
GND
I/O
I/O
A8
C3
I/O
A9
C4
I/O
J2
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
I/O
C5
WD, I/O
I/O
I/O
J3
I/O
CLKA
I/O
C6
I/O
J4
VCCI
GND
GND
GND
GND
VCCA
I/O
C7
QCLKC, I/O
I/O
E2
I/O
J9
I/O
C8
E3
I/O
J10
J11
J12
J17
J18
J19
J20
K1
I/O
C9
I/O
E4
VCCA
VCCI
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
CLKB
PRA, I/O
WD, I/O
I/O
E17
E18
E19
E20
F1
WD, I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
DCLK, I/O
I/O
QCLKD, I/O
I/O
I/O
I/O
F2
I/O
I/O
WD, I/O
SDI, I/O
I/O
F3
I/O
K2
I/O
B2
F4
VCCI
I/O
K3
I/O
B3
F17
F18
F19
F20
G1
K4
VCCI
GND
GND
GND
GND
I/O
B4
I/O
I/O
K9
B5
I/O
I/O
I/O
K10
K11
K12
K17
K18
K19
K20
L1
B6
I/O
I/O
I/O
B7
WD, I/O
I/O
D2
I/O
I/O
B8
D3
I/O
G2
I/O
B9
PRB, I/O
I/O
D4
I/O
G3
I/O
VCCA
VCCA
LP
B10
B11
B12
B13
B14
B15
D5
VCCI
G4
VCCI
VCCI
I/O
I/O
D6
I/O
G17
G18
G19
G20
H1
WD, I/O
I/O
D7
I/O
I/O
D8
VCCA
WD, I/O
VCCI
I/O
L2
I/O
I/O
D9
I/O
L3
VCCA
VCCA
WD, I/O
D10
I/O
L4
v6.0
2-35
40MX and 42MX FPGA Families
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
Pin
Number
A42MX36
Function
Pin
A42MX36
Function
Pin
A42MX36
Function
Pin
A42MX36
Function
Number
P20
R1
Number
U19
U20
V1
Number
W13
W14
W15
W16
W17
W18
W19
W20
Y1
L9
L10
L11
L12
L17
L18
L19
L20
M1
M2
M3
M4
M9
M10
M11
M12
M17
M18
M19
M20
N1
GND
GND
GND
GND
VCCI
I/O
I/O
I/O
I/O
I/O
WD, I/O
I/O
R2
I/O
I/O
I/O
R3
I/O
V2
I/O
WD, I/O
I/O
R4
VCCI
VCCI
I/O
V3
GND
GND
I/O
R17
R18
R19
R20
T1
V4
WD, I/O
GND
GND
GND
GND
I/O
I/O
V5
TCK, I/O
I/O
I/O
V6
I/O
I/O
V7
I/O
I/O
I/O
V8
WD, I/O
I/O
Y2
I/O
T2
I/O
V9
Y3
VCCI
GND
GND
GND
GND
I/O
T3
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
I/O
Y4
TDI, I/O
WD, I/O
I/O
T4
I/O
I/O
Y5
T17
T18
T19
T20
U1
VCCA
I/O
I/O
Y6
WD, I/O
I/O
Y7
QCLKA, I/O
I/O
I/O
Y8
I/O
WD, I/O
I/O
Y9
I/O
I/O
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
I/O
I/O
U2
I/O
I/O
I/O
I/O
U3
I/O
SDO, TDO,
I/O
I/O
I/O
U4
I/O
I/O
V19
V20
W1
I/O
I/O
N2
I/O
U5
VCCI
WD, I/O
I/O
I/O
N3
I/O
U6
I/O
GND
GND
I/O
N4
VCCI
VCCI
I/O
U7
I/O
W2
N17
N18
N19
N20
P1
U8
I/O
I/O
W3
U9
WD, I/O
VCCA
VCCI
I/O
WD, I/O
GND
GND
W4
TMS, I/O
I/O
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U18
W5
I/O
W6
I/O
I/O
W7
I/O
P2
I/O
I/O
W8
WD, I/O
WD, I/O
I/O
P3
I/O
QCLKB, I/O
I/O
W9
P4
VCCA
I/O
W10
W11
W12
P17
P18
P19
VCCI
I/O
I/O
I/O
I/O
I/O
GND
2-36
v6.0
FPGA Families 40MX and 42MX
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version Changes in current version (v6.0)
Page
1-i
v5.1
The "Ease of Integration" section was updated.
The "Temperature Grade Offerings" section is new.
The "Speed Grade Offerings" section is new.
1-iii
1-iii
1-1
The "General Description" section was updated.
The "MultiPlex I/O Modules" section was updated.
The "User Security" section was updated.
1-6
1-6
Table 1 • Voltage Support of MX Devices was updated.
The "Power Dissipation" section was updated.
1-7
1-8
The "Static Power Component" section was updated.
The "Equivalent Capacitance" section was updated.
Figure 1-13 • Silicon Explorer II Setup with 42MX was updated.
Table 4 • Supported BST Public Instructions was updated.
Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry was updated.
Table 5 • Boundary Scan Pin Configuration and Functionality was updated.
The "Development Tool Support" section was updated.
1-8
1-8
1-10
1-11
1-11
1-12
1-13
The Table 7 • Absolute Maximum Ratings for 42MX Devices* and the Table 6 • Absolute 1-14
Maximum Ratings for 40MX Devices* were updated.
The Table 9 • 5V TTL Electrical Specifications was updated.
The Table 13 • 3.3V LVTTL Electrical Specifications was updated.
1-15
1-17
In the "Mixed 5.0V/3.3V Electrical Specifications" section, Table 14 • Absolute Maximum 1-18
Ratings*, Table 15 • Recommended Operating Conditions, and Table 16 • Mixed 5.0V/3.3V
Electrical Specificationswere updated.
The Table 17 • DC Specification (5.0V PCI Signaling)1 was updated.
The Table 19 • DC Specification (3.3V PCI Signaling)1 was updated.
1-19
1-20
The <zBlue>Junction Temperature (TJ) section, "Package Thermal Characteristics" section, and the 1-22
tables were updated.
Figure 1-17 • 40MX Timing Model* was updated.
1-23
1-24
1-24
1-27
1-31
1-32
1-77
2-7
Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
The Figure 1-20 • 42MX Timing Model (SRAM Functions) was updated.
The Figure 1-27 • Output Buffer Latches was updated.
The Table 22 • 42MX Temperature and Voltage Derating Factors is new.
The Table 23 • 40MX Temperature and Voltage Derating Factors is new.
The "Pin Descriptions" section was updated.
In the 100-Pin PQFP table, the following pins changed:
Pin 64 (42MX09 and 42MX16) has changed to LP
v6.0
3-1
FPGA Families 40MX and 42MX
Previous version Changes in current version (v6.0)
Page
5.1
In the 160-Pin PQFP table, the following pins changed:
2-10
Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP
In the 208-Pin PQFP table, the following pins changed:
Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP
Pin 198 (42MX09) has changed to I/O
2-14
The n the 240-Pin PQFP table, the following pins changed:
Pin 91 (42MX36) has changed to LP
2-18
2-23
2-25
2-35
In the 100-Pin VQFP Package table, the following pins changed:
Pin 62 (42MX09 and 42MX16) has changed to LP
In the 176-Pin TQFP table, the following pins changed:
Pin 109 (42MX09 and 42MX16) has changed to LP
In the 272-Pin PBGA table, the following pins changed:
Pin K20 (42MX36) has changed to LP
v5.0
The "Low Power Mode" section was updated.
1-7
Footnote 8 in the Table 9 • 5V TTL Electrical Specifications was updated.
Footnote 8 in the Table 13 • 3.3V LVTTL Electrical Specifications was updated.
1-15
1-17
v4.0.1
Because the changes in this data sheet are extensive and technical in nature, this should be viewed ALL
as a new document. Please read it as you would a data sheet that is published for the first time.
Note that the “Package Characteristics and Mechanical Drawings” section has been eliminated
from the data sheet. The mechanical drawings are now contained in a separate document,
“Package Characteristics and Mechanical Drawings,” available on the Actel web site.
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
3-2
v6.0
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
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