A42U2604SERIES [ETC]
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE ; 与EDO页模式4M X 4 CMOS动态RAM\n
| 型号： | A42U2604SERIES |
| 厂家： | 
ETC |
| 描述： | 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
|
| 文件： | 总25页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A42U2604 Series
Preliminary
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
June 13, 2001
Preliminary
Preliminary (June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U2604 Series
Preliminary
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
nOrganization: 4,194,304 words X 4 bits
nPart Identification
- A42U2604 (2K Ref.)
nSingle 2.5V power supply/built-in VBB generator
nLow power consumption
- Operating: 120mA (-50 max)
- Standby: 1mA (TTL), 0.2mA (CMOS),
250µA (Self-refresh current)
nHigh speed
- 13/15/20 ns CAS access time
- 20/25/35 ns EDO Page Mode Cycle Time
nFast Page Mode with Extended Data Out
nRead-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
nTTL-compatible, three-state I/O
nJEDEC standard packages
- 300mil, 24/26-pin SOJ
- 300mil, 24/26-pin TSOP type II package
- 50/60/80 ns RAS access time
- 25/30/40 ns column address access time
General Description
This allow random access of up to 2048(2K Ref.) words
within a row at a 50/40/28 MHz EDO cycle, making the
A42U2604 ideally suited for graphics, digital signal
processing and high performance computing systems.
The A42U2604 is a new generation randomly accessed
memory for graphics, organized in a 4,194,304-word by
4-bit configuration. This product can execute Write and
Read operation via
pin.
CAS
The A42U2604 offers an accelerated Fast Page Mode
cycle with a feature called Extended Data Out (EDO).
Pin Configuration
Pin Descriptions
n SOJ
n TSOP
Symbol
A0 - A10
I/O0 - I/O3
Description
Address Inputs (2K product)
Data Input/Output
26
25
24
23
22
21
26
25
24
23
22
21
VCC
VCC
1
2
3
VSS
1
2
3
VSS
I/O
I/O
0
1
I/O
I/O
0
1
I/O
I/O
3
2
I/O
I/O
3
2
WE
RAS
NC
4
5
6
CAS
OE
A9
WE
RAS
NC
4
5
6
CAS
OE
A9
Row Address Strobe
RAS
CAS
WE
Column Address Strobe
A10
A0
8
19
18
17
16
15
14
A8
A10
A0
8
19
18
17
16
15
14
A8
9
A7
9
A7
Write Enable
A1
10
11
12
13
A6
A1
10
11
12
13
A6
A2
A5
A2
A5
Output Enable
OE
A3
A4
A3
A4
VCC
VSS
NC
2.5V Power Supply
Ground
VCC
VSS
VCC
VSS
No Connection
PRELIMINARY
(June, 2001, Version 0.0)
1
AMIC Technology, Inc.
A42U2604 Series
Selection Guide
Symbol
Description
-50
-60
-80
Unit
tRAC
50
60
80
ns
Maximum RAS Access Time
tAA
Maximum Column Address Access Time
25
13
30
15
40
20
ns
ns
tCAC
Maximum CAS Access Time
tOEA
13
15
20
ns
Maximum Output Enable ( OE) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
tRC
tPC
84
20
104
25
134
35
ns
ns
Functional Description
The A42U2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
and
are used to strobe the row address and the
CAS
RAS
column address, respectively.
A Read cycle is performed by holding the WE signal high
A memory cycle is terminated by returning both RAS and
high. Memory cell data will retain its correct state by
CAS
during RAS/
operation. A Write cycle is executed by
CAS
maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless
holding the WE signal low during RAS /
operation;
CAS
the input data is latched by the falling edge of WE or
, whichever occurs later. The data inputs and outputs
of sequence, at least once every 32ms through any RAS
CAS
are routed through 4 common I/O pins, with RAS,
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
,
CAS
WE and OE controlling the in direction.
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization
latched by RAS followed by a column address latched by
. While holding RAS low,
can be toggled to
CAS
CAS
cycles containing a RAS clock. During Power-On, the
VCC current is dependent on the input levels of RAS and
strobe changing column addresses, thus achieving shorter
cycle times.
The A42U2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
. It is recommended that RAS and
VCC or be held at a valid VIH during Power-On to avoid
current surges.
track with
CAS
CAS
keeps the output drivers on during the
precharge
goes high,
CAS
time (tcp). Since data can be output after
CAS
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
PRELIMINARY
(June, 2001, Version 0.0)
2
AMIC Technology, Inc.
A42U2604 Series
Block Diagram
Vcc
Vss
RAS
CAS
Control
Clocks
VBB Generator
WE
Row Decoder
Refresh Timer
Data in
Buffer
I/O0
to
Refresh control
Refresh Counter
I/O3
Memory Array
4,194,304 X 4
Cells
Data out
Buffer
OE
Row Address Buffer
Col. Address Buffer
A0~A10
A0~A10
Column Decoder
Recommended Operating Conditions (Ta = 0°C to +70°C)
Symbol
VCC
VSS
VIH
Description
Power Supply
Min.
2.25
0
Typ.
Max.
2.75
0
Unit
V
2.5
Input High Voltage
Input High Voltage
Input Low Voltage
0
-
V
1.8
VCC + 0.2
0.8
V
VIL
-1.0
-
V
PRELIMINARY
(June, 2001, Version 0.0)
3
AMIC Technology, Inc.
A42U2604 Series
Truth Table
Function
RAS
H
L
WE
X
OE
X
Address
X
I/Os
High-Z
CAS
Standby
H
L
L
L
L
L
Read: Word
Read
H
L
Row/Col.
Row/Col.
Row/Col.
Row/Col.
Row/Col.
Data Out
L
H
L
Data Out
Write: Word (Early)
Write (Early)
Read-Write
L
L
X
Data In
L
L
X
Data In
L
H® L
L® H
Data Out ® Data In
EDO-Page-Mode Read: Hi-Z
-First cycle
L
L
H
H
Row/Col.
Col.
Data Out
Data Out
H® L
H® L
H® L
H® L
-Subsequent Cycles
EDO-Page-Mode Write(Early)
-First cycle
L
L
L
L
X
X
Row/Col.
Col.
Data In
Data In
H® L
H® L
-Subsequent Cycles
EDO-Page-Mode Read-Write
-First cycle
L
L
Row/Col.
Col.
H® L
H® L
L
H® L
H® L
H
L® H
L® H
L
Data Out ® Data In
Data Out ® Data In
Data Out
-Subsequent Cycles
Hidden Refresh Read
Row/Col.
Row/Col.
Row
L® H® L
L® H® L
L
Hidden Refresh Write
L
L
X
Data In ® High-Z
H
X
X
High-Z
RAS-Only Refresh
CBR Refresh
Self Refresh
L
L
X
H
X
X
X
X
High-Z
High-Z
H® L
H® L
PRELIMINARY
(June, 2001, Version 0.0)
4
AMIC Technology, Inc.
A42U2604 Series
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Input Voltage (Vin) . . . . . . . . . . . . . . . -0.5V to VCC+0.5V
Output Voltage (Vout) . . . . . . . . . . . . . -0.5V to VCC+0.5V
Power Supply Voltage (VCC) . . . . . . . -0.5V to VCC+0.5V
Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
DC Electrical Characteristics (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
-50
-60
-80
Symbol
Parameter
Unit
Test Conditions
Notes
Min. Max. Min. Max. Min. Max.
IIL
Input Leakage
Current
-5
+5
-5
+5
-5
+5
mA
0V £ Vin £ Vin + 0.2V
Pins not under
Test = 0V
IOL
Output Leakage
Current
-5
-
+5
-5
-
+5
-5
-
+5
DOUT disabled,
0V £ Vout £ + VCC
mA
ICC1
Operating Power
Supply Current
120
110
100
mA
1, 2
RAS,
,
UCAS LCAS
Address cycling; tRC = min.
ICC2
ICC3
TTL Standby Power
Supply Current
-
-
1
-
-
1
-
-
1
mA
mA
RAS= =VIH
=
UCAS LCAS
Average Power
Supply Current,
120
110
100
1
1, 2
1
RAS cycling,
=
= VIH,
UCAS LCAS
RAS Refresh Mode
tRC = min.
ICC4
ICC5
EDO Page Mode
Average Power
Supply Current
-
-
100
110
-
-
90
-
-
80
90
mA
mA
RAS = VIL,
,
Address
UCAS LCAS
cycling; tPC = min.
100
CAS -before-RAS
Refresh Power
Supply Current
RAS,
,
UCAS LCAS
cycling; tRC = min.
ICC6
ICC7
CMOS Standby
Power Supply
Current
-
-
0.2
-
-
0.2
-
-
0.2
mA
µA
RAS=
=
=
UCAS LCAS
VCC - 0.2V
Self Refresh Mode
Current
250
250
250
RAS=
£ VSS+0.2V
CAS
All other input high levels
are VCC-0.2V or input
low levels are VSS +0.2V
VOH
VOL
2.0
-
-
2.0
-
-
2.0
-
-
V
V
IOUT = -2mA
IOUT = 2mA
Output Voltage
0.4
0.4
0.4
PRELIMINARY
(June, 2001, Version 0.0)
5
AMIC Technology, Inc.
A42U2604 Series
AC Characteristics (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: VIH/VIL=1.8V/0.8V
Output reference level: VOH/VOL=1.6V/0.8V
Output Load: 1TTL gate + CL (100pF)
Assumed tT=2ns
Std
-50
-60
-80
#
Symbol
Parameter
Unit Notes
Min. Max. Min. Max. Min Max.
.
tT
Transition Time (Rise and Fall)
Refresh Period
1
-
50
32
1
-
50
32
1
-
50
32
ns
4, 5
3
2K
Self-REF
Random Read or Write Cycle Time
ms
tREF
-
128
-
128
-
128
ms
ns
ns
3
1
2
tRC
tRP
84
30
-
-
104
40
-
-
134
50
-
-
RAS Precharge Time
RAS Pulse Width
3
4
5
6
7
8
9
tRAS
tCAS
tRCD
tRAD
tRSH
tCSH
tCRP
50
7
10K
10K
37
25
-
60
10
14
12
10
40
5
10K
10K
45
30
-
80
15
20
15
10
50
5
10K
10K
60
40
-
ns
ns
ns
ns
ns
ns
ns
CAS Pulse Width
11
9
6
7
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Hold Time
CAS Hold Time
7
37
5
-
-
-
-
-
-
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
10
11
12
tASR
tRAH
tCLZ
0
7
0
-
-
-
0
10
0
-
-
-
0
10
0
-
-
-
ns
ns
ns
8
CAS to Output in Low Z
Access Time from RAS
13
14
tRAC
tCAC
-
-
50
13
-
-
60
15
-
-
80
20
ns
ns
6,7
6, 12
7, 12
Access Time from CAS
15
16
tAA
tAR
Access Time from Column Address
-
25
-
-
30
-
-
40
-
ns
ns
44
55
70
Column Address Hold Time from RAS
Read Command Setup Time
17
18
tRCS
tRCH
0
0
-
-
0
0
-
-
0
0
-
-
ns
ns
Read Command Hold Time
9
PRELIMINARY
(June, 2001, Version 0.0)
6
AMIC Technology, Inc.
A42U2604 Series
AC Characteristics (continued) (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: VIH/VIL=1.8V/0.8V
Output reference level: VOH/VOL=1.6V/0.8V
Output Load: 1TTL gate + CL (100pF)
Assumed tT=2ns
Std
-50
-60
-80
#
Symbol
Parameter
Unit
Notes
Min. Max. Min. Max. Min Max.
.
Read Command Hold Time Reference
to RAS
19
tRRH
0
-
0
-
0
-
ns
9
20
21
tRAL
tCOH
25
5
-
-
30
5
-
-
40
3
-
-
ns
ns
Column Address to RAS Lead Time
Output Hold After CAS Low
Output Disable Setup Time
Output Buffer Turn-Off Delay Time
Column Address Setup Time
Column Address Hold Time
22
23
24
25
26
tODS
tOFF
tASC
tCAH
tOES
0
0
0
7
5
-
13
-
0
0
-
15
-
0
0
-
20
-
ns
ns
ns
ns
ns
8, 10
0
0
-
10
5
-
10
10
-
-
-
-
Low to CAS High Set Up
OE
27
28
29
tWCS
tWCH
tWCR
Write Command Setup Time
Write Command Hold Time
0
7
-
-
-
0
-
-
-
0
-
-
-
ns
ns
ns
11
11
10
55
10
70
44
Write Command Hold Time to RAS
Write Command Pulse Width
30
31
tWP
7
-
-
10
15
-
-
10
20
-
-
ns
ns
tRWL
13
Write Command to RAS Lead Time
32
tCWL
7
-
10
-
10
-
ns
Write Command to CAS Lead Time
Data-in setup Time
33
34
35
tDS
tDH
0
7
-
-
-
0
-
-
-
0
-
-
-
ns
ns
ns
Data-in Hold Time
10
55
15
70
tDHR
44
Data-in Hold Time to RAS
36
37
tRWC
tRWD
Read-Modify-Write Cycle Time
110
67
-
-
135
79
-
-
180
107
-
-
ns
ns
RAS to WE Delay Time (Read-Modify-
Write)
11
11
CAS to WE Delay Time (Read-
Modify-Write)
38
tCWD
30
-
34
-
47
-
ns
PRELIMINARY
(June, 2001, Version 0.0)
7
AMIC Technology, Inc.
A42U2604 Series
AC Characteristics (continued) (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: VIH/VIL=1.8V/0.8V
Output reference level: VOH/VOL=1.6V/0.8V
Output Load: 1TTL gate + CL (100pF)
Assumed tT=2ns
Std
-50
-60
-80
#
Symbol
Parameter
Unit Notes
Min. Max. Min. Max. Min. Max.
Column Address to WE Delay Time
(Read-Modify-Write)
39
tAWD
42
-
49
-
67
-
ns
11
40
41
42
tOEH
tOEP
tPC
7
2
-
-
-
10
2
-
-
-
20
5
-
-
-
ns
ns
ns
OE Hold Time from WE
OE High Pulse Width
Read or Write Cycle Time (EDO Page)
20
25
35
13
12
Access Time from CAS Precharge
(EDO Page)
43
tCPA
-
28
-
33
-
45
ns
44
45
tCP
7
-
-
10
68
-
-
10
80
-
-
ns
ns
CAS Precharge Time (EDO Page)
EDO Page Mode RMW Cycle Time
tPCM
58
EDO Page Mode CAS Pulse Width
(RMW)
46
tCRW
34
-
38
-
42
-
ns
47
48
49
tRASP
tCSR
tCHR
50
5
100K
60
5
100K
80
5
100K
ns
ns
ns
RAS Pulse Width (EDO Page)
-
-
-
-
-
-
3
3
CAS Setup Time ( CAS -before-RAS)
CAS Hold Time ( CAS -before-RAS)
10
10
15
RAS to CAS Precharge Time
( CAS -before-RAS)
50
tRPC
5
-
5
-
5
-
ns
51
52
53
54
55
tROH
tOEA
tOED
tOEZ
5
-
-
13
-
5
-
-
15
-
5
-
-
20
-
ns
ns
ns
ns
ms
RAS Hold Time Reference to OE
OE Access Time
13
0
15
0
20
0
OE to Data Delay
13
-
15
-
20
-
8
Output Buffer Turn-off Delay from OE
tRASS
100
100
100
RAS pulse width ( -B- self-refresh)
R
C
RAS precharge time
56
57
tRPS
tCHS
84
-
-
104
-
-
134
-
-
ns
ns
(
-B- self-refresh)
R
C
50
50
50
CAS hold time ( -B- self-refresh)
R
C
PRELIMINARY
(June, 2001, Version 0.0)
8
AMIC Technology, Inc.
A42U2604 Series
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200ms is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to one TTL load and
100pF, VIL (min.) ³ GND and VIH (max.) £ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500W Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ³ tWCS (min.) and tWCH ³ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ³ tRWD (min.) , tCWD ³
tCWD (min.) and tAWD ³ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. Access time is determined by the longer of tAA or tCAC or tCPA.
13. tASC ³ tCP to achieve tPC (min.) and tCPA (max.) values.
PRELIMINARY
(June, 2001, Version 0.0)
9
AMIC Technology, Inc.
A42U2604 Series
Word Read Cycle
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
tCAS(4)
tCRP(9)
CAS
tRAD(6)
tRAL(20)
tCAH(25)
tASR(10)
tRAH(11)
tASC(24)
Address
Row Address
Column Address
tAR(16)
tRCS(17)
tRCH(18)
tRRH(19)
WE
OE
tROH(51)
tOEA(52)
tCAC(14)
tAA(15)
tOFF(23)
tRAC(13)
tOEZ(54)
I/O
I/O
0
~
3
High-Z
Valid Data-out
tCLZ(12)
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
10
AMIC Technology, Inc.
A42U2604 Series
Word Write Cycle (Early Write)
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
tCRP(9)
tCAS(4)
CAS
tAR(16)
tRAD(6)
tRAL(20)
tASR(10)
tRAH(11)
tCAH(25)
tASC(24)
Row Address
Column Address
Address
tWCR(29)
tCWL(32)
tRWL(31)
tWP(30)
WE
OE
tWCS(27)
tWCH(28)
tDHR(35)
tDS(33)
tDH(34)
I/O
I/O
0
~
3
Valid Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
11
AMIC Technology, Inc.
A42U2604 Series
Word Write Cycle (Late Write)
t
RC(1)
t
RAS(3)
t
RP(2)
RAS
CAS
t
CSH(8)
t
CRP(9)
t
RCD(5)
t
RSH(7)
tCRP(9)
t
CAS(4)
t
AR(16)
t
RAD(6)
t
RAL(20)
t
ASR(10)
tRAH(11)
t
CAH(25)
t
ASC(24)
Row Address
Column Address
Address
t
CWL(32)
RWL(31)
t
t
WCR(29)
t
WP(30)
WE
OE
t
OEH(40)
t
OED(53)
t
DHR(35)
t
DS(33)
t
DH(34)
High-Z
I/O
0
~
Vaild Data-in
I/O
3
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
12
AMIC Technology, Inc.
A42U2604 Series
Word Read-Modify-Write Cycle
tRWC(36)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
tCAS(4)
tCRP(9)
CAS
tAR(16)
tRAD(6)
tRAH(11)
tASR(10)
tASC(24)
tCAH(25)
Address
WE
Row Address
Column Address
tAWD(39)
tCWD38)
tCWL(32)
tRWL(31)
tRCS(17)
tRWD(37)
tWP(30)
tOED(53)
tOEA(52)
tOEZ(54)
OE
tOEH(40)
tDH(34)
tCAC(14)
tAA(15)
tDS(33)
tRAC(13)
High-Z
I/O
I/O
0
~
3
Data-out
Data-in
tCLZ(12)
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
13
AMIC Technology, Inc.
A42U2604 Series
EDO Page Mode Word Read Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8)
tPC(42)
tRSH(7)
tCRP(9)
tCRP(9)
tRCD(5)
tCP(44)
tCAS(4)
tCAS(4)
tCAS(4)
CAS
tCSH(8)
tAR(16)
tRAL(20)
tCAH(25)
tRAD(6)
tRAH(11)
tCAH(25)
tASR(10)
tASC(24)
tASC(24)
Row
Column
Column
Column
Address
WE
tCAH(25)
tRCS(17)
tRCH(25)
tRCS(17)
tRCH(25)
tRCS(17)
tAA(15)
tAA(15)
tRRH(19)
tCPA(43)
tOEA(52)
tOEA(52)
tOES(26)
OE
tCAC(14)
tCOH(21)
tRAC(13)
tOEP(41)
tOFF(23)
tOEZ(54)
tCAC(14)
tCAC(14)
tCLZ(12)
tOEZ(54)
I/O
I/O
0
~
3
Data-out
Data-out
Data-out
tCLZ(12)
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
14
AMIC Technology, Inc.
A42U2604 Series
EDO Page Mode Early Word Write Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8)
tRCD(5)
tPC(42)
tRSH(7)
tCRP(9)
tCRP(9)
tCAS(4)
tCP(44)
tCAS(4)
tCP(44)
tCAS(4)
CAS
tRAL(20)
tCAH(25)
tRAD(6)
tRAH(11)
tASC(24)
tCAH(25)
tASC(24)
tCAH(25)
tASC(24)
tASR(10)
Address
Row
Column
Column
Column
tCWL(32)
tCWL(32)
tCWL(32)
tRWL(31)
tWCS(27)
tWCS(27)
tWCH(28)
tWCS(27)
tWCH(28)
tWCH(28)
WE
OE
tWP(30)
tWP(30)
tWP(30)
tDH(34)
tDS(33)
tDH(34)
tDS(33)
tDH(34)
tDS(33)
I/O0 ~
I/O3
Data-in
Data-in
Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
15
AMIC Technology, Inc.
A42U2604 Series
EDO Page Mode Word Read-Modify-Write Cycle
t
RP(2)
t
RASP(47)
RAS
t
CSH(8)
t
PCM(45)
tRSH(7)
t
CRP(9)
t
CRP(9)
t
RCD(5)
t
CP(44)
tCAS(4)
t
CAS(4)
t
CP(44)
tCAS(4)
CAS
t
RAL(20)
CAH(25)
ASC(24)
t
RAD(6)
t
t
CAH(25)
t
CAH(25)
t
RAH(11)
t
ASR(10)
t
ASC(24)
t
ASC(24)
t
Address
Row
Column
Column
Column
t
CWL(32)
t
CWL(32)
tCWL(32)
t
RWD(37)
t
RWL(31)
t
CWD(38)
t
RCS(17)
t
CWD(38)
tCWD(38)
WE
OE
t
WP(30)
AWD(39)
t
WP(30)
AWD(39)
tWP(30)
t
AWD(39)
t
t
t
ROH(51)
t
t
OEA(52)
t
OEA(52)
t
OEA(52)
t
OEH(40)
t
OED(53)
t
OED(53)
CPA(43)
AA(15)
t
OED(53)
CAC(14)
t
CPA(43)
AA(15)
t
t
AA(15)
t
t
t
OEZ(54)
tOEZ(54)
t
OEZ(54)
t
DH(34)
t
DH(34)
tDH(34)
t
RAC(13)
t
DS(33)
t
DS(33)
t
DS(33)
I/O
I/O
0
~
3
High-Z
t
CLZ(12)
t
CLZ(12)
tCLZ(12)
Data-in
Data-in
Data-in
Data-out
Data-out
Data-out
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
16
AMIC Technology, Inc.
A42U2604 Series
RAS Only Refresh Cycle
t
RC(1)
t
RAS(3)
t
RP(2)
RAS
t
RPC(50)
t
CRP(9)
CAS
t
ASR(10)
tRAH(11)
Row
Address
Note: WE, OE = Don't care.
: High or Low
CAS Before RAS Refresh Cycle
tRC(1)
tRP(2)
tRAS(3)
tRP(2)
RAS
tRPC(50)
tCHR(49)
tCSR(48)
tPC(42)
CAS
tOFF(23)
High-Z
I/O0 ~
I/O3
Note: WE, OE, Address = Don't care.
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
17
AMIC Technology, Inc.
A42U2604 Series
Hidden Refresh Cycle (Word Read)
t
RC(1)
t
RC(1)
t
RAS(3)
t
RP(2)
t
RAS(3)
tRP(2)
RAS
t
AR(16)
t
CRP(9)
t
RSH(7)
tCHR(49)
t
RCD(5)
tCRP(9)
CAS
t
RAD(6)
tRAL(20)
t
ASR(10)
t
CAH(25)
t
t
RAH(11)
ASC(24)
Row
Column
Address
t
RCS(17)
tRRH(19)
WE
OE
t
AA(15)
t
CAC(14)
t
OFF(23)
t
CLZ(12)
t
RAC(13)
High-Z
I/O0 ~
I/O3
Valid Data-out
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
18
AMIC Technology, Inc.
A42U2604 Series
Hidden Refresh Cycle (Early Word Write)
tRC(1)
t
RC(1)
tRAS(3)
tRP(2)
tRAS(3)
tRP(2)
RAS
tAR(16)
t
CRP(9)
tRCD(5)
t
RSH(7)
t
CHR(49)
tCRP(9)
CAS
t
RAD(6)
tRAL(20)
tASR(10)
t
CAH(25)
tRAH(11)
tASC(24)
Row
Column
Address
WE
tWCS(27)
tWCH(28)
t
WP(30)
OE
t
DS(33)
tDH(34)
I/O0 ~
Valid Data-in
I/O
3
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
19
AMIC Technology, Inc.
A42U2604 Series
EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
t
RP(2)
t
RASP(47)
RAS
CAS
t
CSH(8)
t
PC(42)
t
PC(42)
t
RSH(7)
t
RCD(5)
t
CAS(4)
t
CP(44)
t
CAS(4)
t
CP(44)
t
CAS(4)
tCPR(9)
t
CRP(9)
t
RAD(6)
t
RAL(20)
t
RAD(6)
t
ASC(24)
tCAH(25)
t
ASC(24)
tCAH(25)
t
RAH(11)
t
ASC(24)
t
CAH(25)
t
ASR(10)
Row
Column
Column
Column
Address
t
RCH(18)
t
RCS(17)
t
WCS(27)
tWCH(28)
WE
t
AA(15)
t
AA(15)
t
CAP(43)
t
DS(33)
t
DH(34)
t
RAC(13)
t
CAC(14)
tCAC(14)
t
OEA(52)
OE
t
COH(21)
I/O
I/O
0
~
3
Data-out
Data-out
Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
20
AMIC Technology, Inc.
A42U2604 Series
Self Refresh Mode
tRP(2)
tRASS(55)
tRPS(56)
RAS
tCHS(57)
tCRP(9)
tCSR(48)
tRPC(50)
UCAS
LCAS
tCPN(42)
tASR(10)
ROW
COL
A0 ~ A10
tOFF(23)
High-Z
I/O0 ~ I/O3
: High or Low
Note: WE, OE = Don't care.
nSelf Refresh Mode.
a. Entering the Self Refresh Mode:
The A42U2604 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal
"low" longer than 100ms.
b. Continuing the Self Refresh Mode:
The Self Refresh Mode is continued by holding RAS "low" after entering the Self Refresh Mode.
It does not depend on CAS being "high" or "low" after entering the Self Refresh Mode continue the Self Refresh Mode.
c. Exiting the Self Refresh Mode:
The A42U2604 exits the Self Refresh Mode when the RAS signal is brought "high".
PRELIMINARY
(June, 2001, Version 0.0)
21
AMIC Technology, Inc.
A42U2604 Series
Capacitance (Ta = Room Temperature, VCC = 2.5V ± 10%)
Symbol
CIN1
Signals
A0 - A10
Parameter
Max.
Unit
pF
Test Conditions
Vin = 0V
5
7
CIN2
Input Capacitance
pF
Vin = 0V
RAS,
,
CAS
WE , OE
CI/O
I/O0 - I/O3
I/O Capacitance
10
pF
Vin = Vout = 0V
Ordering Codes
50ns
60ns
80ns
Refresh
Cycle
Self-
Refresh
Package\ RAS Access Time
24/26L SOJ (300mil)
A42U2604S-50
A42U2604V-50
A42U2604S-60
A42U2604V-60
A42U2604S-80
A42U2604V-80
2K
2K
Yes
Yes
24/26L TSOP type II (300mil)
PRELIMINARY
(June, 2001, Version 0.0)
22
AMIC Technology, Inc.
A42U2604 Series
Package Information
SOJ 24L/26L (300mil) Outline Dimensions
unit: inches/mm
D
24
19
18
13
1
6
7
12
Pin 1 Identifier
A
A
b
b
- y -
q
e
S
2
E2
Seating Plane
0.004
y
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
Min
-
Nom
-
Max
3.56
2.29
2.67
0.56
0.81
0.36
17.42
8.81
7.75
7.24
1.42
1.22
A
A1
A2
b
0.140
0.090
0.105
0.022
0.032
0.014
0.686
0.347
0.305
0.285
0.056
0.048
0.070
0.095
0.016
0.026
0.008
-
0.080
0.100
0.018
0.028
0.010
0.675
0.337
0.300
0.265
0.050
-
1.78
2.41
0.41
0.66
0.20
-
2.03
2.54
0.46
0.71
0.25
17.15
8.56
7.62
6.73
1.27
-
b2
C
D
E
0.327
0.295
0.245
0.044
-
8.31
7.49
6.22
1.12
-
E1
E2
e
S
-
-
q
0°
10°
0°
10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension E2 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY
(June, 2001, Version 0.0)
23
AMIC Technology, Inc.
A42U2604 Series
Package Information
TSOP 24/26L (TYPE II) Outline Dimensions
unit: inches/mm
24
13
q
L1
1
12
D
e
S
B
L1
L
y
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
0.047
-
Min
Nom
-
Max
A
A1
A2
B
-
1.20
-
0.002
-
0.05
0.95
0.30
-
-
0.037
0.039
0.016
0.005
0.675
0.300
0.050
0.363
0.031
0.020
0.037
-
0.041
0.020
-
1.00
0.40
0.127
17.14
7.62
1.27
9.22
0.80
0.50
0.95
-
1.05
0.50
-
0.012
c
-
D
E
0.671
0.679
0.302
-
17.04
7.57
-
17.24
7.67
-
0.298
e
-
HE
L
0.359
0.367
-
9.12
-
9.32
-
-
L1
S
0.016
0.024
-
0.40
-
0.60
-
-
-
y
0.004
5°
-
0.10
5°
-
-
q
0°
0°
Notes:
1. Dimension D&E do not included interiead flash.
2. Dimension B does not included dambar protrusion / intrusion.
3. Dimension S includes end flash.
PRELIMINARY
(June, 2001, Version 0.0)
24
AMIC Technology, Inc.
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