A54SX08-1PL84_技术文档

v3.0.1

54SX Family FPGAs

Leading Edge Performance

Features

• 320 MHz Internal Performance

• 66 MHz PCI

• 3.7 ns Clock-to-Out (Pin-to-Pin)

• 0.1 ns Input Set-Up

• CPLD and FPGA Integration

• Single Chip Solution

• 0.25 ns Clock Skew

• 100% Resource Utilization with 100% Pin Locking

• 3.3V Operation with 5.0V Input Tolerance

• Very Low Power Consumption

Specifications

• 12,000 to 48,000 System Gates

• Up to 249 User-Programmable I/O Pins

• Up to 1080 Flip-Flops

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Debug capability with

Silicon Explorer II

• 0.35µ CMOS

• Boundary Scan Testing in Compliance with IEEE Standard

1149.1 (JTAG)

• Secure Programming Technology Prevents Reverse

Engineering and Design Theft

SX Product Profile

A54SX08

A54SX16

A54SX16P

A54SX32

Capacity

Typical Gates

System Gates

8,000

12,000

16,000

24,000

16,000

24,000

32,000

48,000

Logic Modules

Combinatorial Cells

768

512

1,452

924

1,452

924

2,880

1800

Register Cells (Dedicated Flip-Flops)

Maximum User I/Os

Clocks

256

130

528

175

528

175

1,080

249

3

JTAG

Yes

PCI

—

Yes

—

Clock-to-Out

3.7 ns

0.8 ns

Std, –1, –2, –3

C, I, M

3.9 ns

0.5 ns

Std, –1, –2, –3

C, I, M

4.4 ns

0.5 ns

Std, –1, –2, –3

C, I, M

4.6 ns

0.1 ns

Std, –1, –2, –3

C, I, M

Input Set-Up (External)

Speed Grades

Temperature Grades

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

PBGA

FBGA

84

208

100

—

208

100

176

—

208

100

144, 176

—

208

—

144, 176

—

144, 176

313, 329

—

144

—

May 2000

1

General Description

Actel’s SX family of FPGAs features a sea-of-modules

architecture that delivers device performance and

integration levels not currently achieved by any other FPGA

architecture. SX devices greatly simplify design time, enable

dramatic reductions in design costs and power

consumption, and further decrease time to market for

performance-intensive applications.

machines, and datapath logic. The general system of

segmented routing tracks allows any logic module in the

array to be connected to any other logic or I/O module.

Within this system, propagation delay is minimized by

limiting the number of antifuse interconnect elements to

five (90 percent of connections typically use only three

antifuses). The unique local and general routing structure

featured in SX devices gives fast and predictable

performance, allows 100 percent pin-locking with full logic

utilization, enables concurrent PCB development, reduces

design time, and allows designers to achieve performance

goals with minimum effort.

Actel’s SX architecture features two types of logic modules,

the combinatorial cell (C-cell) and the register cell (R-cell),

each optimized for fast and efficient mapping of synthesized

logic functions. The routing and interconnect resources are

in the metal layers above the logic modules, providing

optimal use of silicon. This enables the entire floor of the

device to be spanned with an uninterrupted grid of

fine-grained, synthesis-friendly logic modules (or

“sea-of-modules”), which reduces the distance signals have

to travel between logic modules. To minimize signal

propagation delay, SX devices employ both local and general

routing resources. The high-speed local routing resources

(DirectConnect and FastConnect) enable very fast local

signal propagation that is optimal for fast counters, state

Further complementing SX’s flexible routing structure is a

hard-wired, constantly loaded clock network that has been

tuned to provide fast clock propagation with minimal clock

skew. Additionally, the high performance of the internal

logic has eliminated the need to embed latches or flip-flops

in the I/O cells to achieve fast clock-to-out or fast input

set-up times. SX devices have easy-to-use I/O cells that do

not require HDL instantiation, facilitating design re-use and

reducing design and verification time.

Ordering Information

A54SX16

P

–

2

PQ

208

Application (Temperature Range)

Blank = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

PP = Pre-production

Package Lead Count

Package Type

BG = Ball Grid Array

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flat Pack

TQ = Thin (1.4 mm) Quad Flat Pack

VQ = Very Thin (1.0 mm) Quad Flat Pack

FG = Fine Pitch Ball Grid Array (1.0 mm)

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% Faster than Standard

–2 = Approximately 25% Faster than Standard

–3 = Approximately 35% Faster than Standard

Blank = Not PCI Compliant

P = PCI Compliant

Part Number

A54SX08 = 12,000 System Gates

A54SX16 = 24,000 System Gates

A54SX16P = 24,000 System Gates

A54SX32 = 48,000 System Gates

2

54SX Family FPGAs

Product Plan

Speed Grade*

Application

Std

–1

–2

–3

C

I^†

M^•

A54SX08 Device

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

144-Pin Thin Quad Flat Pack (TQFP)

144-Pin Fine Pitch Ball Grid Array (FBGA)

176-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

A54SX16 Device

✔

—

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

176-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

A54SX16P Device

✔

P

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

144-Pin Thin Quad Flat Pack (TQFP)

176-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

A54SX32 Device

✔

—

144-Pin Thin Quad Flat Pack (TQFP)

176-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

313-Pin Plastic Ball Grid Array (PBGA)

329-Pin Plastic Ball Grid Array (PBGA)

✔

P

—

Contact your Actel sales representative for product availability.

Applications: C = Commercial Availability: ✔ = Available

= Industrial = Planned

— = Not Planned

*Speed Grade: –1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

–3 = Approx. 35% faster than Standard

† Only Std, –1, –2 Speed Grade

I

P

M = Military

• Only Std, –1 Speed Grade

Plastic Device Resources

User I/Os (including clock buffers)

PLCC

VQFP

PQFP

TQFP

PBGA

FBGA

Device

A54SX08

84-Pin

100-Pin

208-Pin

144-Pin

176-Pin

313-Pin

329-Pin

144-Pin

69

—

81

—

130

175

174

113

—

128

147

—

111

—

A54SX16

A54SX16P

A54SX32

113

—

249

—

Package Definitions (Consult your local Actel sales representative for product availability.)

PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,

PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch (1.0 mm) Ball Grid Array

3

SX Family Architecture

The SX family architecture was designed to satisfy

next-generation performance and integration requirements

for production-volume designs in a broad range of

applications.

antifuse interconnect elements, which are embedded

between the M2 and M3 layers. The antifuses are normally

open circuit and, when programmed, form a permanent

low-impedance connection.

The extremely small size of these interconnect elements

gives the SX family abundant routing resources and provides

excellent protection against design pirating. Reverse

engineering is virtually impossible because it is extremely

difficult to distinguish between programmed and

unprogrammed antifuses, and there is no configuration

bitstream to intercept.

Programmable Interconnect Element

The SX family provides efficient use of silicon by locating the

routing interconnect resources between the Metal 2 (M2)

and Metal 3 (M3) layers (Figure 1). This completely

eliminates the channels of routing and interconnect

resources between logic modules (as implemented on SRAM

FPGAs and previous generations of antifuse FPGAs), and

enables the entire floor of the device to be spanned with an

uninterrupted grid of logic modules.

Additionally, the interconnect (i.e., the antifuses and metal

tracks) have lower capacitance and lower resistance than

any other device of similar capacity, leading to the fastest

signal propagation in the industry.

Interconnection between these logic modules is achieved

using Actel’s patented metal-to-metal programmable

Routing Tracks

Metal 3

Amorphous Silicon/

Dielectric Antifuse

Tungsten Plug Via

Metal 2

Metal 1

Tungsten Plug

Contact

Silicon Substrate

Figure 1 • SX Family Interconnect Elements

Logic Module Design

The R-cell contains a flip-flop featuring asynchronous clear,

asynchronous preset, and clock enable (using the S0 and S1

lines) control signals (Figure 2 on page 5). The R-cell

registers feature programmable clock polarity selectable on

a register-by-register basis. This provides additional

flexibility while allowing mapping of synthesized functions

into the SX FPGA. The clock source for the R-cell can be

chosen from either the hard-wired clock or the routed clock.

The SX family architecture is described as

a

“sea-of-modules” architecture because the entire floor of

the device is covered with a grid of logic modules with

virtually no chip area lost to interconnect elements or

routing. Actel’s SX family provides two types of logic

modules, the register cell (R-cell) and the combinatorial

cell (C-cell).

4

54SX Family FPGAs

The C-cell implements a range of combinatorial functions

up to 5-inputs (Figure 3). Inclusion of the DB input and its

associated inverter function dramatically increases the

number of combinatorial functions that can be

implemented in a single module from 800 options in

previous architectures to more than 4,000 in the SX

architecture. An example of the improved flexibility

enabled by the inversion capability is the ability to integrate

a 3-input exclusive-OR function into a single C-cell. This

facilitates construction of 9-bit parity-tree functions with 2

ns propagation delays. At the same time, the C-cell

structure is extremely synthesis friendly, simplifying the

overall design and reducing synthesis time.

Routed

Data Input

S1

S0

PSETB

Direct

Connect

Input

D

Q

Y

HCLK

CLKA,

CLKB,

CLRB

Internal Logic

CKS

CKP

Figure 2 • R-Cell

D0

D1

Y

D2

D3

Sa

Sb

DB

A0 B0

A1 B1

Figure 3 • C-Cell

Chip Architecture

To increase design efficiency and device performance, Actel

The SX family’s chip architecture provides a unique

approach to module organization and chip routing that

delivers the best register/logic mix for a wide variety of new

and emerging applications.

has further organized these modules into SuperClusters

(Figure 4 on page 6). SuperCluster 1 is a two-wide grouping

of Type 1 clusters. SuperCluster 2 is a two-wide group

containing one Type 1 cluster and one Type 2 cluster. SX

devices feature more SuperCluster 1 modules than

SuperCluster 2 modules because designers typically require

significantly more combinatorial logic than flip-flops.

Module Organization

Actel has arranged all C-cell and R-cell logic modules into

horizontal banks called Clusters. There are two types of

Clusters: Type 1 contains two C-cells and one R-cell, while

Type 2 contains one C-cell and two R-cells.

5

R-Cell

C-Cell

D0

D1

Routed

Data Input

S1

S0

PSETB

Y

D2

D3

Direct

Connect

Input

D

Q

Y

Sa

Sb

HCLK

CLKA,

CLKB,

Internal Logic

CLRB

DB

CKS

CKP

A0 B0

A1 B1

Cluster 1

Cluster 2

Cluster 1

Type 1 SuperCluster

Figure 4 • Cluster Organization

Type 2 SuperCluster

Routing Resources

Clusters and SuperClusters can be connected through the

use of two innovative local routing resources called

FastConnect and DirectConnect, which enable extremely

fast and predictable interconnection of modules within

Clusters and SuperClusters (Figure 5 and Figure 6 on

page 7). This routing architecture also dramatically reduces

the number of antifuses required to complete a circuit,

ensuring the highest possible performance.

automatic place and route software to minimize signal

propagation delays.

Actel’s high-drive routing structure provides three clock

networks. The first clock, called HCLK, is hard wired from the

HCLK buffer to the clock select MUX in each R-cell. This

provides a fast propagation path for the clock signal, enabling

the 3.7 ns clock-to-out (pin-to-pin) performance of the SX

devices. The hard-wired clock is tuned to provide clock skew

as low as 0.25 ns. The remaining two clocks (CLKA, CLKB) are

global clocks that can be sourced from external pins or from

internal logic signals within the SX device.

DirectConnect is a horizontal routing resource that provides

connections from a C-cell to its neighboring R-cell in a given

SuperCluster. DirectConnect uses a hard-wired signal path

requiring no programmable interconnection to achieve its

fast signal propagation time of less than 0.1 ns.

FastConnect enables horizontal routing between any two

logic modules within a given SuperCluster and vertical

routing with the SuperCluster immediately below it. Only

one programmable connection is used in a FastConnect

path, delivering maximum pin-to-pin propagation of 0.4 ns.

In addition to DirectConnect and FastConnect, the

architecture makes use of two globally oriented routing

resources known as segmented routing and high-drive

routing. Actel’s segmented routing structure provides a

variety of track lengths for extremely fast routing between

SuperClusters. The exact combination of track lengths and

antifuses within each path is chosen by the 100 percent

6

54SX Family FPGAs

Other Architectural Features

Technology

and dielectric material with barrier metals and has a

programmed (“on” state) resistance of 25Ω with

capacitance of 1.0 fF for low signal impedance.

Actel’s SX family is implemented on a high-voltage twin-well

CMOS process using 0.35µ design rules. The metal-to-metal

antifuse is made up of a combination of amorphous silicon

Direct Connect

• No antifuses

• 0.1 ns routing delay

Fast Connect

• One antifuse

• 0.4 ns routing delay

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Type 1 SuperClusters

Figure 5 • DirectConnect and FastConnect for Type 1 SuperClusters

Direct Connect

• No antifuses

• 0.1 ns routing delay

Fast Connect

• One antifuse

• 0.4 ns routing delay

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Type 2 SuperClusters

Figure 6 • DirectConnect and FastConnect for Type 2 SuperClusters

7

Performance

Boundary Scan Testing (BST)

The combination of architectural features described above

enables SX devices to operate with internal clock

frequencies exceeding 300 MHz, enabling very fast

execution of even complex logic functions. Thus, the SX

family is an optimal platform upon which to integrate the

functionality previously contained in multiple CPLDs. In

addition, designs that previously would have required a gate

array to meet performance goals can now be integrated into

an SX device with dramatic improvements in cost and time

to market. Using timing-driven place and route tools,

designers can achieve highly deterministic device

performance. With SX devices, designers do not need to use

complicated performance-enhancing design techniques

such as the use of redundant logic to reduce fanout on

critical nets or the instantiation of macros in HDL code to

achieve high performance.

All SX devices are IEEE 1149.1 compliant. SX devices offer

superior diagnostic and testing capabilities by providing

Boundary Scan Testing (BST) and probing capabilities.

These functions are controlled through the special test pins

in conjunction with the program fuse. The functionality of

each pin is described in Table 2.In the dedicated test mode,

TCK, TDI and TDO are dedicated pins and cannot be used as

regular I/Os. In flexible mode, TMS should be set HIGH

through a pull-up resistor of 10kΩ. TMS can be pulled LOW

to initiate the test sequence.

The program fuse determines whether the device is in

dedicated or flexible mode. The default (fuse not blown) is

flexible mode. .

Table 2 • Boundary Scan Pin Functionality

Program Fuse Blown

(Dedicated Test Mode)

Program Fuse Not Blown

(Flexible Mode)

I/O Modules

TCK, TDI, TDO are dedi-

cated BST pins

TCK, TDI, TDO are flexible

and may be used as I/Os

Each I/O on an SX device can be configured as an input, an

output, a tristate output, or a bidirectional pin. Even without

the inclusion of dedicated I/O registers, these I/Os, in

combination with array registers, can achieve clock-to-out

(pad-to-pad) timing as fast as 3.7 ns. I/O cells that have

embedded latches and flip-flops require instantiation in HDL

code; this is a design complication not encountered in SX

FPGAs. Fast pin-to-pin timing ensures that the device will

have little trouble interfacing with any other device in the

system, which in turn enables parallel design of system

components and reduces overall design time.

No need for pull-up resistor Use a pull-up resistor of 10k

for TMS Ω on TMS

Development Tool Support

The SX devices are fully supported by Actel’s line of FPGA

development tools, including the Actel DeskTOP series and

Designer Advantage tools. The Actel DeskTOP series is an

integrated design environment for PCs that includes design

entry, simulation, synthesis, and place and route tools.

Designer Advantage, Actel’s suite of FPGA development

point tools for PCs and Workstations, includes the ACTgen

Macro Builder, Designer with DirectTime timing driven

place and route and analysis tools, and device programming

software.

Power Requirements

The SX family supports 3.3V operation and is designed to

tolerate 5.0V inputs. (Table 1). Power consumption is

extremely low due to the very short distances signals are

required to travel to complete a circuit. Power requirements

are further reduced because of the small number of

low-resistance antifuses in the path. The antifuse

architecture does not require active circuitry to hold a

charge (as do SRAM or EPROM), making it the lowest-power

architecture on the market.

In addition, the SX devices contain ActionProbe circuitry

that provides built-in access to every node in a design,

enabling 100-percent real-time observation and analysis of a

device's internal logic nodes without design iteration. The

probe circuitry is accessed by Silicon Explorer II, an

easy-to-use integrated verification and logic analysis tool

that can sample data at 100 MHz (asynchronous) or 66 MHz

(synchronous). Silicon Explorer II attaches to a PC’s

standard COM port, turning the PC into a fully functional

18-channel logic analyzer. Silicon Explorer II allows

designers to complete the design verification process at

their desks and reduces verification time from several hours

per cycle to only a few seconds.

Table 1 • Supply Voltages

Input

Output

V_CCAV_CCIV_CCRTolerance Drive

3.3V

5.0V

3.3V

5.0V

3.3V

A54SX08

A54SX16

A54SX32

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

3.3V

5.0V

SX Probe Circuit Control Pins

A54SX16P

The Silicon Explorer II tool uses the boundary scan ports

(TDI, TCK, TMS and TDO) to select the desired nets for

verification. The selected internal nets are assigned to the

PRA/PRB pins for observation. Figure 7 illustrates the

8

54SX Family FPGAs

Design Considerations

interconnection between Silicon Explorer II and the FPGA

to perform in-circuit verification. The TRST pin is equipped

with a pull-up resistor. To remove the boundary scan state

machine from the reset state during probing, it is

recommended that the TRST pin be left floating.

The TDI, TCK, TDO, PRA, and PRB pins should not be used

as input or bidirectional ports. Because these pins are

active during probing, critical signals input through these

pins are not available while probing. In addition, the

Security Fuse should not be programmed because doing so

disables the Probe Circuitry.

SX FPGA

TDI

TCK

TMS

Serial Connection

Silicon Explorer II

TDO

PRA

PRB

Figure 7 • Probe Setup

9

3.3V/5V Operating Conditions

Absolute Maximum Ratings¹

Recommended Operating Conditions

Symbol

Parameter

Limits

Units

Parameter

Commercial Industrial Military Units

2

V_CCR

DC Supply Voltage³

DC Supply Voltage

(A54SX08,A54SX16, –0.3 to +4.0

A54SX32)

–0.3 to +6.0

–0.3 to +4.0

V

Temperature

Range¹

–40 to

+85

–55 to

+125

0 to+70

10

°C

2

V_CCA

3.3V Power

Supply

Tolerance

10

%V_CC

2

V_CCI

V

5.0V Power

Supply

Tolerance

DC Supply Voltage

–0.3 to +6.0

2

V_CCI

5

%V_CC

(A54SX16P)

V_I

Input Voltage

–0.5 to +5.5

–0.5 to +3.6

V

Note:

V_O

Output Voltage

1. Ambient temperature (T_A) is used for commercial and

industrial; case temperature (T_C) is used for military.

I/O Source Sink

Current³

I_IO

–30 to +5.0

–40 to +125

mA

T_STG

Storage Temperature

°C

Notes:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended

periods may affect device reliability. Device should not be

operated outside the Recommended Operating Conditions.

2. V_CCRin the A54SX16P must be greater than or equal to V_CCI

during power-up and power-down sequences and during

normal operation.

3. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V_CC+ 0.5V or less than GND – 0.5V, the internal protection

diodes will forward-bias and can draw excessive current.

Electrical Specifications

Commercial

Industrial

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

(I_OH= -20uA) (CMOS)

(I_OH= -8mA) (TTL)

(I_OH= -6mA) (TTL)

(V_CCI– 0.1)

V_CCI

(V_CCI– 0.1)

V_CCI

V_OH

2.4

V

2.4

V_CCI

(I_OL= 20uA) (CMOS)

(I_OL= 12mA) (TTL)

(I_OL= 8mA) (TTL)

0.10

0.50

V_OL

V

0.50

0.8

V_IL

0.8

V

V_IH

2.0

t_R, t_F

C_IO

Input Transition Time t_R, t_F

C_IOI/O Capacitance

50

10

50

10

ns

pF

mA

I_CC

Standby Current, I_CC

4.0

I_CC(D)

I_{CC(D) Dynamic}

I

V_CCSupply Current

See “Evaluating Power in 54SX Devices” on page 18.

10

54SX Family FPGAs

PCI Compliance for the 54SX Family

The 54SX family supports 3.3V and 5V PCI and is compliant

with the PCI Local Bus Specification Rev. 2.1.

A54SX16P DC Specifications (5.0V PCI Operation)

Symbol

Parameter

Condition

Min.

Max.

Units

V_CCA

V_CCR

V_CCI

V_IH

Supply Voltage for Array

Supply Voltage required for Internal Biasing

Supply Voltage for IOs

Input High Voltage¹

3.0

4.75

2.0

3.6

5.25

V

5.25

V

V_CC+ 0.5

0.8

V

V_IL

Input Low Voltage¹

–0.5

V

I_IH

Input High Leakage Current

Input Low Leakage Current

Output High Voltage

Output Low Voltage²

Input Pin Capacitance³

V_IN= 2.7

70

µA

V

I_IL

V_IN= 0.5

–70

V_OH

V_OL

I_OUT= –2 mA

I_OUT= 3 mA, 6 mA

2.4

5

0.55

10

12

8

V

C_IN

pF

C_CLK

C_IDSEL

Notes:

CLK Pin Capacitance

IDSEL Pin Capacitance⁴

1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include,

FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).

4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].

11

A54SX16P AC Specifications for (PCI Operation)

Symbol

Parameter

Condition

Min.

Max.

Units

0 < V_OUT≤ 1.4¹

1.4 ≤ V_OUT< 2.4^{1, 2}

–44

mA

I_OH(AC)

Switching Current High

(Test Point)

–44 + (V_OUT– 1.4)/0.024

1, 3

3.1 < V_OUT< V_CC

V_OUT= 3.1³

Equation A: on page 13

–142

mA

V_OUT≥ 2.2¹

95

I_OL(AC)

Switching Current High

2.2 > V_OUT> 0.55¹

0.71 > V_OUT> 0^{1, 3}

V_OUT= 0.71³

V_OUT/0.023

Equation B: on page 13

mA

(Test Point)

206

I_CL

Low Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–5 < V_IN≤ –1

0.4V to 2.4V load⁴

2.4V to 0.4V load⁴

–25 + (V_IN+ 1)/0.015

mA

slew_R

slew_F

Notes:

1

5

V/ns

1. Refer to the V/I curves in Figure 8. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here;

i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs.

“Switching Current High” specification are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs.

2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward

the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.

3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)

are provided with the respective diagrams in Figure 8. The equation defined maxima should be met by design. In order to facilitate

component testing, a maximum current test point is defined for each side of the output driver.

4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point

within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an

unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is

now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to

revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard

designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity

modeling accounts for this. Rise slew rate does not apply to open drain outputs.

1/2 in. max.

output

buffer

V_CC

10 pF

1kΩ

12

54SX Family FPGAs

Figure 8 shows the 5.0V PCI V/I curve and the minimum and

maximum PCI drive characteristics of the A54SX16P

family.

0.50

0.45

0.40

PCI I

Maximum

OL

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

SX PCI I

OL

PCI I

4

Minimum

OL

1

2

3

5

6

–0.05

–0.10

–0.15

–0.20

PCI I

OH

Minimum

SX PCI I

OH

PCI I

OH

Maximum

Voltage Out

Figure 8 • 5.0V PCI Curve for A54SX16P Family

Equation A:

Equation B:

I

_OH= 11.9 * (V_OUT– 5.25) * (V_OUT+ 2.45)

I_OL= 78.5 * V_OUT* (4.4 – V_OUT)

for V_CC> V_OUT> 3.1V

for 0V < V_OUT< 0.71V

13

A54SX16P DC Specifications (3.3V PCI Operation)

Symbol

Parameter

Condition

Min.

Max.

Units

V_CCA

V_CCR

V_CCI

V_IH

Supply Voltage for Array

Supply Voltage required for Internal Biasing

Supply Voltage for IOs

Input High Voltage

3.0

3.6

V

0.5V_CCV_CC+ 0.5

V

V_IL

Input Low Voltage

–0.5

0.3V_CC

V

I_IPU

Input Pull-up Voltage¹

Input Leakage Current²

Output High Voltage

0.7V_CC

V

I_IL

0 < V_IN< V_CC

I_OUT= –500 µA

I_OUT= 1500 µA

10

µA

V

V_OH

V_OL

0.9V_CC

Output Low Voltage

0.1V_CC

V

C_IN

Input Pin Capacitance³

CLK Pin Capacitance

IDSEL Pin Capacitance⁴

10

12

8

pF

C_CLK

C_IDSEL

Notes:

5

1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated

network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this

input voltage.

2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

3. Absolute maximum pin capacitance for a PCI input is 10pF (except for CLK).

4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].

14

54SX Family FPGAs

A 54SX16P AC Specifications (3.3V PCI Operation)

Symbol Parameter

Condition

Min.

Max.

Units

1

0 < V_OUT≤ 0.3V_CC

mA

1

Switching Current High 0.3V_CC≤ V_OUT< 0.9V_CC

–12V_CC

1, 2

I_OH(AC)

0.7V_CC< V_OUT< V_CC

–17.1 + (V_CC– V_OUT

)

Equation C: on page 16

2

(Test Point)

V_OUT= 0.7V_CC

–32V_CC

mA

1

V_CC> V_OUT≥ 0.6V_CC

Switching Current High 0.6V_CC> V_OUT> 0.1V_CC

16V_CC

I_OL(AC)

0.18V_CC> V_OUT> 0^{1, 2}

26.7V_OUT

on page 16

2

(Test Point)

V_OUT= 0.18V_CC

–3 < V_IN≤ –1

38V_CC

I_CL

Low Clamp Current

–25 + (V_IN+ 1)/0.015

mA

I_CH

High Clamp Current

25 + (V_IN– V_OUT– 1)/0.015

slew_R

slew_F

Notes:

Output Rise Slew Rate³0.2V_CCto 0.6V_CCload

1

4

V/ns

Output Fall Slew Rate³

0.6V_CCto 0.2V_CCload

1. Refer to the V/I curves in Figure 9. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here;

i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs.

“Switching Current High” specification are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs.

2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)

are provided with the respective diagrams in Figure 9. The equation defined maxima should be met by design. In order to facilitate

component testing, a maximum current test point is defined for each side of the output driver.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point

within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an

unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum

parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.

1/2 in. max.

output

buffer

V_CC

10 pF

1kΩ

15

Figure 9 shows the 3.3V PCI V/I curve and the minimum and

maximum PCI drive characteristics of the A54SX16P family.

0.50

0.45

0.40

PCI I

OL

Maximum

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

SX PCI I

OL

PCI I

OL

Minimum

SX PCI I

OH

5

1

2

3

4

6

–0.05

–0.10

–0.15

–0.20

PCI I

OH

Minimum

PCI I

OH

Maximum

Voltage Out

Figure 9 • 3.3V PCI Curve for A54SX16P Family

Equation C:

Equation D:

I_OH= (98.0/V_CC) * (V_OUT– V_CC) * (V_OUT+ 0.4V_CC)

I_OL= (256/V_CC) * V_OUT* (V_CC– V_OUT)

for V_CC> V_OUT> 0.7 V_CC

for 0V < V_OUT< 0.18 V_CC

16

54SX Family FPGAs

Power-Up Sequencing

V_CCA

V_CCR

V_CCI

Power-Up Sequence

Comments

A54SX08, A54SX16, A54SX32

5.0V First

3.3V Second

No possible damage to device.

Possible damage to device.

3.3V

5.0V

3.3V

3.3V First

5.0V Second

A54SX16P

3.3V

5.0V

3.3V

3.3V Only

No possible damage to device.

5.0V First

3.3V Second

3.3V First

5.0V Second

Possible damage to device.

No possible damage to device.

5.0V First

3.3V Second

3.3V

5.0V

3.3V First

5.0V Second

Power-Down Sequencing

V_CCA

V_CCR

V_CCI

Power-Down Sequence

Comments

A54SX08, A54SX16, A54SX32

5.0V First

3.3V Second

Possible damage to device.

3.3V

5.0V

3.3V

3.3V First

No possible damage to device.

5.0V Second

A54SX16P

3.3V

5.0V

3.3V

3.3V Only

No possible damage to device.

Possible damage to device.

5.0V First

3.3V Second

3.3V First

5.0V Second

No possible damage to device.

5.0V First

3.3V Second

3.3V

5.0V

3.3V First

5.0V Second

17

Evaluating Power in 54SX Devices

A critical element of system reliability is the ability of

electronic devices to safely dissipate the heat generated

during operation. The thermal characteristics of a circuit

depend on the device and package used, the operating

temperature, the operating current, and the system’s ability

to dissipate heat.

(0.5 * (q₁* C_EQCR* f_q1) + (r₁* f_q1))_RCLKA

(0.5 * (q₂* C_EQCR* f_q2)+ (r₂* f_q2))_RCLKB

(0.5 * (s₁* C_EQHV* f_s1) + (C_EQHF* f_s1))_HCLK

+

]

(4)

Definition of Terms Used in Formula

m

n

p

= Number of logic modules switching at f_m

= Number of input buffers switching at f_n

= Number of output buffers switching at f_p

You should complete a power evaluation early in the design

process to help identify potential heat-related problems in the

system and to prevent the system from exceeding the device’s

maximum allowed junction temperature.

q₁

= Number of clock loads on the first routed array

clock

q₂

= Number of clock loads on the second routed

array clock

The actual power dissipated by most applications is

significantly lower than the power the package can dissipate.

However, a thermal analysis should be performed for all

projects. To perform a power evaluation, follow these steps:

x

= Number of I/Os at logic low

y

= Number of I/Os at logic high

r₁

r₂

= Fixed capacitance due to first routed array clock

= Fixed capacitance due to second routed array

clock

• Estimate the power consumption of the application.

• Calculate the maximum power allowed for the device and

s₁

= Number of clock loads on the dedicated array

clock

package.

• Compare the estimated power and maximum power

C_EQM= Equivalent capacitance of logic modules in pF

values.

C_EQI

C_EQO

= Equivalent capacitance of input buffers in pF

= Equivalent capacitance of output buffers in pF

Estimating Power Consumption

C_EQCR= Equivalent capacitance of routed array clock in

pF

C_EQHV= Variable capacitance of dedicated array clock

C_EQHF= Fixed capacitance of dedicated array clock

The total power dissipation for the 54SX family is the sum of

the DC power dissipation and the AC power dissipation. Use

Equation 1 to calculate the estimated power consumption of

your application.

C_L

f_m

f_n

= Output lead capacitance in pF

P_Total= P_DC+ P_AC

(1)

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

= Average second routed array clock rate in MHz

= Average dedicated array clock rate in MHz

DC Power Dissipation

The power due to standby current is typically a small

component of the overall power. The Standby power is shown

below for commercial, worst case conditions (70°C).

f_p

f_q1

f_q2

f_s1

Table 3 •

I_CC

V_CC

Power

A54SX08 A54SX16 A54SX16P A54SX32

4mA

3.6V

14.4mW

C

_EQM(pF) 4.0

4.0

3.4

4.7

1.6

0.615

140

171

_EQI(pF) 3.4

_EQO(pF) 4.7

_EQCR(pF) 1.6

3.4

The DC power dissipation is defined in Equation 2 as follows:

P_DC= (I_standby)*V_CCA+ (I_standby)*V_CCR

(I_standby)*V_CCI+ x*V_OL*I_OL+ y*(V_CCI– V_OH)*V_OH

4.7

+

1.6

(2)

C_EQHV

C_EQHF

r₁(pF)

r₂(pF)

0.615

60

0.615

96

0.615

96

AC Power Dissipation

The power dissipation of the 54SX Family is usually

dominated by the dynamic power dissipation. Dynamic power

dissipation is a function of frequency, equivalent capacitance

and power supply voltage. The AC power dissipation is defined

as follows:

87

138

P

_AC= P_Module+ P_{RCLKA Net}+ P_{RCLKB Net}+ P_{HCLK Net}

_{Output Buffer}+ P_{Input Buffer}

+

(3)

P_AC= V_CCA²* [(m * C_EQM* f_m)_Module

+

(n * C_EQI* f_n)_{Input Buffer}+ (p * (C_EQO+ C_L) * f_p)_{Output Buffer}

+

18

54SX Family FPGAs

Guidelines for Calculating Power

Consumption

+

Buffer

(0.5 * (q₁* C_EQCR* f_q1) + (r₁* f_q1))_RCLKA

(0.5 * (q₂* C_EQCR* f_q2)+ (r₂* f_q2))_RCLKB

(0.5 * (s₁* C_EQHV* f_s1) + (C_EQHF* f_s1))_HCLK

+

The following guidelines are meant to represent worst-case

scenarios so that they can be generally used to predict the

upper limits of power dissipation. These guidelines are as

follow:

]

(7)

Step #1: Define Terms Used in Formula

V_CCA

3.3

Logic Modules (m)

Inputs Switching (n)

= 20% of modules

= # inputs/4

Module

Number of logic modules switching at f_m

(Used 50%)

m

264

20

Outputs Switching (p)

= # output/4

First Routed Array Clock Loads (q₁)

= 20% of register

cells

Average logic modules switching rate

f_m(MHz) (Guidelines: f/10)

f_m

Second Routed Array Clock Loads (q₂) = 20% of register

cells

Module capacitance C_EQM(pF)

Input Buffer

Number of input buffers switching at f_n

Average input switching rate f_n(MHz)

(Guidelines: f/5)

Input buffer capacitance C_EQI(pF)

Output Buffer

Number of output buffers switching at f_p

Average output buffers switching rate

f_p(MHz) (Guidelines: f/10)

Output buffers buffer Capacitance C_EQO(pF) C_EQO4.7

Output Load capacitance C_L(pF)

RCLKA

Number of Clock loads q₁

Capacitance of routed array clock (pF)

Average clock rate (MHz)

Fixed capacitance (pF)

RCLKB

Number of Clock loads q₂

Capacitance of routed array clock (pF)

Average clock rate (MHz)

Fixed capacitance (pF)

HCLK

Number of Clock loads

Variable capacitance of dedicated

array clock (pF)

Fixed capacitance of dedicated

array clock (pF)

C_EQM4.0

Load Capacitance (C_L)

= 35 pF

n

1

Average Logic Module Switching Rate = f/10

(f_m)

f_n

40

Average Input Switching Rate (f_n)

Average Output Switching Rate (f_p)

= f/5

= f/10

C_EQI3.4

Average First Routed Array Clock Rate = f/2

(f_q1)

Average Second Routed Array Clock = f/2

Rate (f_q2)

p

1

f_p

20

Average Dedicated Array Clock Rate

(f_s1)

= f

C_L

35

Dedicated Clock Array clock loads (s₁) = 20% of regular

modules

q₁

528

C_EQCR1.6

f_q1

r₁

200

138

Sample Power Calculation

One of the designs used to characterize the A54SX family was

a 528 bit serial in serial out shift register. The design utilized

100% of the dedicated flip-flops of an A54SX16P device. A

pattern of 0101… was clocked into the device at frequencies

ranging from 1 MHz to 200 MHz. Shifting in a series of 0101…

caused 50% of the flip-flops to toggle from low to high at every

clock cycle.

q₂

0

C_EQCR1.6

f_q2

r₂

0

138

Follow the steps below to estimate power consumption. The

values provided for the sample calculation below are for the

shift register design above. This method for estimating power

consumption is conservative and the actual power

consumption of your design may be less than the estimated

power consumption.

s₁

0

C_EQHV0.615

C_EQHF96

Average clock rate (MHz)

f_s1

0

The total power dissipation for the 54SX family is the sum of

the AC power dissipation and the DC power dissipation.

P_Total= P_AC(dynamic power) + P_DC(static power)

(5)

AC Power Dissipation

P_AC= P_Module+ P_{RCLKA Net}+ P_{RCLKB Net}+ P_{HCLK Net}

+

P

_{Output Buffer}+ P_{Input Buffer}

P_AC= V_CCA²* [(m * C_EQM* f_m)_Module

(n * C_EQI* f_n)_{Input Buffer}+ (p * (C_EQO+ C_L) * f_p)_Output

(6)

+

19

Step #2: Calculate Dynamic Power Consumption

_CCA*V_CCA

m*f_m*C_EQM

n*f_n*C_EQI

p*f_p*(C_EQO+C_L)

0.5*(q₁*C_EQCR*f_q1)+(r₁*f_q1)

0.5*(q₂*C_EQCR*f_q2)+(r₂*f_q2)

0.5 *(s₁* C_EQHV* f_s1)+(C_EQHF*f_s1)

P_AC= 1.461W

P

_DC= (I_standby)*V_CCA

V

10.89

0.02112

0.000136

0.000794

0.11208

0

P_DC= .55mA*3.3V

P_DC= 0.001815W

Step #4: Calculate Total Power Consumption

P_Total= P_AC+ P_DC

P_Total= 1.461 + 0.001815

P_Total= 1.4628W

0

Step #5: Compare Estimated Power Consumption against

Characterized Power Consumption

Step #3: Calculate DC Power Dissipation

DC Power Dissipation

The estimated total power consumption for this design is

1.46W. The characterized power consumption for this design

at 200 MHz is 1.0164W. Figure 10 shows the characterized

power dissipation numbers for the shift register design using

frequencies ranging from 1 MHz to 200 MHz.

P_DC= (I_standby)*V_CCA+ (I_standby)*V_CCR+ (I_standby)*V_CCI

+

X*V_OL*I_OL+ Y*(V_CCI– V_OH)*V_OH

(8)

For a rough estimate of DC Power Dissipation, only use

_DC= (I_standby)*V_CCA. The rest of the formula provides a very

P

small number that can be considered negligible.

1200

1000

800

600

400

200

0

20

40

60

80

100

120

140

160

180

200

Frequency MHz

Figure 10 • Power Dissipation

20

54SX Family FPGAs

Junction Temperature (T_J)

P = Power calculated from Estimating Power Consumption

section

The temperature that you select in Designer Series software

is the junction temperature, not ambient temperature. This is

an important distinction because the heat generated from

dynamic power consumption is usually hotter than the

ambient temperature. Use the equation below to calculate

junction temperature.

θ = Junction to ambient of package. θ numbers are located

ja

in Package Thermal Characteristics section.

Package Thermal Characteristics

The device junction to case thermal characteristic is θ_jc, and

the junction to ambient air characteristic is θ_ja. The thermal

characteristics for θ_jaare shown with two different air flow

rates.

Junction Temperature = ∆T + T_a

Where:

T_a= Ambient Temperature

The maximum junction temperature is 150°C.

∆T = Temperature gradient between junction (silicon) and

ambient

A sample calculation of the absolute maximum power

dissipation allowed for a TQFP 176-pin package at

commercial temperature and still air is as follows:

∆T = θ * P

ja

Max. junction temp. (°C) – Max. ambient temp. (°C)

150°C – 70°C

Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 2 . 8 6 W

θ_ja(°C/W)

28°C/W

θ_ja

Package Type

Pin Count

θ_jc

Still Air

300 ft/min

Units

Plastic Leaded Chip Carrier (PLCC)

Thin Quad Flat Pack (TQFP)

84

12

11

10

8

32

22

24

°C/W

144

176

100

208

272

313

329

144

Thin Quad Flat Pack (TQFP)

28

21

Very Thin Quad Flatpack (VQFP)

Plastic Quad Flat Pack (PQFP) without Heat Spreader

Plastic Quad Flat Pack (PQFP) with Heat Spreader

Plastic Ball Grid Array (PBGA)

38

32

30

23

3.8

3

20

17

20

14.5

17

Plastic Ball Grid Array (PBGA)

3

23

Plastic Ball Grid Array (PBGA)

3

18

13.5

26.7

Fine Pitch Ball Grid Array (FBGA)

3.8

38.8

Note:

SX08 does not have a heat spreader.

21

54SX Timing Model*

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

Combinatorial

Cell

I/O Module

t_INY= 1.5 ns

t

_IRD2= 0.6 ns

t_DHL= 1.6 ns

t_RD1= 0.3 ns

t_RD4= 1.0 ns

t_PD=0.6 ns

I/O Module

t

_RD8= 1.9 ns

t_DHL= 1.6 ns

Register

Cell

Register

Cell

D

Q

t_RD1= 0.3 ns

t

_ENZH= 2.3 ns

t_SUD= 0.5 ns

_HD= 0.0 ns

t

t_RCO= 0.8 ns

Routed

Clock

t_RCKH= 1.5 ns (100% Load)

F_MAX= 250 MHz

Hard-Wired

Clock

t_HCKH= 1.0 ns

F_HMAX= 320 MHz

*Values shown for A54SX08-3, worst-case commercial conditions.

Hard-Wired Clock

Routed Clock

External Set-Up = t_INY+ t_IRD1+ t_SUD– t_HCKH

External Set-Up = t_INY+ t_IRD1+ t_SUD– t_RCKH

= 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns

Clock-to-Out (Pin-to-Pin)

= 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns

Clock-to-Out (Pin-to-Pin)

= t_HCKH+ t_RCO+ t_RD1+ t_DHL

= t_RCKH+ t_RCO+ t_RD1+ t_DHL

= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns

= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns

22

54SX Family FPGAs

Output Buffer Delays

E

D

To AC test loads (shown below)

PAD

TRIBUFF

V_CC

In

GND

1.5V

50%

V_OH

En

Out

GND

10%

50%

En

GND

90%

50%

V_CC

50%

V_OH

50%

1.5V

V_OL

Out

V_OL

Out

GND

1.5V

t_DLH

t_DHL

t_ENZL

t_ENLZ

t_ENZH

t_ENHZ

AC Test Loads

Load 3

Load 2

(Used to measure enable delays)

Load 1

(Used to measure disable delays)

(Used to measure

propagation delay)

V_CC

GND

To the output

under test

35 pF

R to V_CCfor t_PZL

R to GND for t_PZH

R = 1 kΩ

R to V_CCfor t_PLZ

R to GND for t_PHZ

R = 1 kΩ

To the output

under test

To the output

under test

35 pF

5 pF

Input Buffer Delays

C-Cell Delays

S

A

B

Y

PAD

INBUF

V_CC

GND

S, A or B

50% 50%

V_CC

3V

In

0V

1.5V

V_CC

1.5V

50%

Out

50%

GND

t_PD

50%

Out

GND

50%

V_CC

50%

Out

GND

t_PD

50%

t_PD

t_INY

23

Register Cell Timing Characteristics

Flip-Flops

D

Q

PRESET

CLR

CLK

(Positiveedgetriggered)

t_HD

D

t_HP

t_HPWH

,

t_SUD

t_RPWH

CLK

t_HPWL

,

t_RPWL

t_RCO

Q

CLR

t_CLR

t_PRESET

t_WASYN

PRESET

Long Tracks

Timing Characteristics

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows, columns, or

modules. Long tracks employ three and sometimes five

antifuse connections. This increases capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically up to 6% of nets in a fully

utilized device require long tracks. Long tracks contribute

approximately 4 ns to 8.4 ns delay. This additional delay is

represented statistically in higher fanout (FO=24) routing

delays in the data sheet specifications section.

Timing characteristics for 54SX devices fall into three

categories: family-dependent, device-dependent, and

design-dependent. The input and output buffer

characteristics are common to all 54SX family members.

Internal routing delays are device dependent. Design

dependency means actual delays are not determined until

after placement and routing of the user’s design is complete.

Delay values may then be determined by using the DirectTime

Analyzer utility or performing simulation with post-layout

delays.

Timing Derating

Critical Nets and Typical Nets

54SX devices are manufactured in a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process variations. Minimum

timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case processing.

Maximum timing parameters reflect minimum operating

voltage, maximum operating temperature, and worst-case

processing.

Propagation delays are expressed only for typical nets, which

are used for initial design performance evaluation. Critical

net delays can then be applied to the most time-critical paths.

Critical nets are determined by net property assignment prior

to placement and routing. Up to 6% of the nets in a design may

be designated as critical, while 90% of the nets in a design are

typical.

Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, V_CCA= 3.0V)

Junction Temperature (T_J)

V_CCA

3.0

–55

0.75

0.70

0.66

–40

0.78

0.73

0.69

0

25

70

85

125

1.16

1.08

1.02

0.87

0.82

0.77

0.89

0.83

0.78

1.00

0.93

0.87

1.04

0.97

0.92

3.3

3.6

24

54SX Family FPGAs

A54SX08 Timing Characteristics

(Worst-Case Commercial Conditions, V_CCR= 4.75V, V_CCA,V_CCI= 3.0V, T_J= 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

C-Cell Propagation Delays¹

Min. Max. Min. Max. Min. Max. Min. Max. Units

t_PD

Internal Array Module

0.6

0.7

0.8

0.9

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.6

0.8

1.0

1.9

2.8

0.1

0.4

0.7

0.9

1.2

2.2

3.2

0.1

0.4

0.8

1.0

1.4

2.5

3.7

0.1

0.5

0.9

1.2

1.6

2.9

4.3

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

FO=2 Routing Delay

t_RD3

FO=3 Routing Delay

t_RD4

FO=4 Routing Delay

t_RD8

FO=8 Routing Delay

t_RD12

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.8

0.5

0.7

1.1

0.6

0.8

1.2

0.7

0.9

1.4

0.8

1.0

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_PRESET

t_SUD

0.5

0.0

1.4

0.5

0.0

1.6

0.7

0.0

1.8

0.8

0.0

2.1

t_HD

t_WASYN

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

1.5

1.7

1.9

2.2

ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.6

0.8

1.0

1.9

2.8

0.4

0.7

0.9

1.2

2.2

3.2

0.4

0.8

1.0

1.4

2.5

3.7

0.5

0.9

1.2

1.6

2.9

4.3

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is

based on actual routing delay measurements performed on the device prior to shipment.

25

A54SX08 Timing Characteristics (continued)

(Worst-Case Commercial Conditions)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hard-Wired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.0

1.1

1.2

1.3

1.4

1.5

1.6

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

ns

0.1

0.2

ns

Minimum Period

2.7

3.1

3.6

4.2

ns

f_HMAX

Maximum Frequency

350

320

280

240

MHz

Routed Array Clock Networks

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

1.3

1.4

1.5

1.6

1.7

1.8

1.7

1.8

1.9

2.0

1.9

2.0

2.1

2.2

2.3

2.2

2.3

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

2.1

2.4

2.7

3.2

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.1

0.3

0.2

0.3

0.2

0.4

0.2

0.4

TTL Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

1.6

2.1

2.3

1.4

1.3

1.9

2.4

2.7

1.7

1.5

2.1

2.8

3.1

1.9

1.7

2.5

3.2

3.6

2.2

2.0

ns

t_DHL

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

Note:

1. Delays based on 35 pF loading, except t_ENZLand t_ENZH. For t_ENZLand t_ENZHthe loading is 5 pF.

26

54SX Family FPGAs

A54SX16 Timing Characteristics

(Worst-Case Commercial Conditions, V_CCR= 4.75V, V_CCA,V_CCI= 3.0V, T_J= 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

C-Cell Propagation Delays¹

Min. Max. Min. Max. Min. Max. Min. Max. Units

t_PD

Internal Array Module

0.6

0.7

0.8

0.9

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.6

0.8

1.0

1.9

2.8

0.1

0.4

0.7

0.9

1.2

2.2

3.2

0.1

0.4

0.8

1.0

1.4

2.5

3.7

0.1

0.5

0.9

1.2

1.6

2.9

4.3

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

FO=2 Routing Delay

t_RD3

FO=3 Routing Delay

t_RD4

FO=4 Routing Delay

t_RD8

FO=8 Routing Delay

t_RD12

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.8

0.5

0.7

1.1

0.6

0.8

1.2

0.7

0.9

1.4

0.8

1.0

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_PRESET

t_SUD

0.5

0.0

1.4

0.5

0.0

1.6

0.7

0.0

1.8

0.8

0.0

2.1

t_HD

t_WASYN

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

1.5

1.7

1.9

2.2

ns

Predicted Input Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.6

0.8

1.0

1.9

2.8

0.4

0.7

0.9

1.2

2.2

3.2

0.4

0.8

1.0

1.4

2.5

3.7

0.5

0.9

1.2

1.6

2.9

4.3

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is

based on actual routing delay measurements performed on the device prior to shipment.

27

A54SX16 Timing Characteristics (continued)

(Worst-Case Commercial Conditions)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hard-Wired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.2

1.4

1.5

1.6

1.8

1.9

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

ns

0.2

0.3

ns

Minimum Period

2.7

3.1

3.6

4.2

ns

f_HMAX

Maximum Frequency

350

320

280

240

MHz

Routed Array Clock Networks

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

1.6

1.8

2.0

1.8

2.0

1.8

2.0

2.1

2.2

2.1

2.2

2.1

2.3

2.5

2.4

2.5

2.7

2.8

3.0

2.8

3.0

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

2.1

2.4

2.7

3.2

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.5

0.6

0.5

0.7

0.8

TTL Output ModuleTiming¹

t_DLH

Data-to-Pad LOW to HIGH

1.6

2.1

2.3

1.4

1.3

1.9

2.4

2.7

1.7

1.5

2.1

2.8

3.1

1.9

1.7

2.5

3.2

3.6

2.2

2.0

ns

t_DHL

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

Note:

1. Delays based on 35 pF loading, except t_ENZLand t_ENZH. For t_ENZLand t_ENZHthe loading is 5 pF.

28

54SX Family FPGAs

A54SX16P Timing Characteristics

(Worst-Case Commercial Conditions, V_CCR= 4.75V, V_CCA,V_CCI= 3.0V, T_J= 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

C-Cell Propagation Delays¹

Min. Max. Min. Max. Min. Max. Min. Max. Units

t_PD

Internal Array Module

0.6

0.7

0.8

0.9

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.6

0.8

1.0

1.9

2.8

0.1

0.4

0.7

0.9

1.2

2.2

3.2

0.1

0.4

0.8

1.0

1.4

2.5

3.7

0.1

0.5

0.9

1.2

1.6

2.9

4.3

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

FO=2 Routing Delay

t_RD3

FO=3 Routing Delay

t_RD4

FO=4 Routing Delay

t_RD8

FO=8 Routing Delay

t_RD12

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.9

0.5

0.7

1.1

0.6

0.8

1.3

0.7

0.9

1.4

0.8

1.0

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_PRESET

t_SUD

0.5

0.0

1.4

0.5

0.0

1.6

0.7

0.0

1.8

0.8

0.0

2.1

t_HD

t_WASYN

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

1.5

1.7

1.9

2.2

ns

Predicted Input Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.6

0.8

1.0

1.9

2.8

0.4

0.7

0.9

1.2

2.2

3.2

0.4

0.8

1.0

1.4

2.5

3.7

0.5

0.9

1.2

1.6

2.9

4.3

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is

based on actual routing delay measurements performed on the device prior to shipment.

29

A54SX16P Timing Characteristics (continued)

(Worst-Case Commercial Conditions, V_CCR= 4.75V, V_CCA,V_CCI= 3.0V, T_J= 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hard-Wired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.2

1.4

1.5

1.6

1.8

1.9

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

ns

0.2

0.3

ns

Minimum Period

2.7

3.1

3.6

4.2

ns

f_HMAX

Maximum Frequency

350

320

280

240

MHz

Routed Array Clock Networks

Input LOW to HIGH (Light Load)

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

1.6

1.8

2.0

1.8

2.0

1.8

2.0

2.1

2.2

2.1

2.2

2.1

2.3

2.5

2.4

2.5

2.7

2.8

3.0

2.8

3.0

ns

(Pad to R-Cell Input)

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

2.1

2.4

2.7

3.2

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.5

0.6

0.5

0.7

0.8

TTL Output Module Timing

t_DLH

Data-to-Pad LOW to HIGH

2.4

2.3

3.0

3.3

2.3

2.8

2.9

3.4

3.8

2.7

3.2

3.1

3.2

3.9

4.3

3.0

3.7

3.8

4.6

5.0

3.5

4.3

ns

t_DHL

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

TTL/PCI Output Module Timing

t_DLH

Data-to-Pad LOW to HIGH

1.5

1.9

2.3

1.5

2.7

2.9

1.7

2.2

2.6

1.7

3.1

3.3

2.0

2.4

3.0

1.9

3.5

3.7

2.3

2.9

3.5

2.3

4.1

4.4

ns

t_DHL

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

30

54SX Family FPGAs

A54SX16P Timing Characteristics (continued)

(Worst-Case Commercial Conditions V_CCR= 3.0V, V_CCA, V_CCI= 3.0V, T_J= 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

PCI Output Module Timing¹

Min. Max. Min. Max. Min. Max. Min. Max. Units

t_DLH

Data-to-Pad LOW to HIGH

1.8

1.7

0.8

1.2

1.0

1.1

2.0

1.0

1.2

1.1

1.3

2.3

2.2

1.1

1.5

1.3

1.5

2.7

2.6

1.3

1.8

1.5

1.7

ns

t_DHL

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

TTL Output Module Timing

t_DLH

Data-to-Pad LOW to HIGH

2.1

2.0

2.5

3.0

2.3

2.9

2.5

2.3

2.9

3.5

2.7

3.3

2.8

2.6

3.2

3.9

3.1

3.7

3.3

3.1

3.8

4.6

3.6

4.4

ns

t_DHL

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

Note:

1. Delays based on 10 pF loading.

31

A54SX32 Timing Characteristics

(Worst-Case Commercial Conditions, V_CCR= 4.75V, V_CCA,V_CCI= 3.0V, T_J= 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

C-Cell Propagation Delays¹

Min. Max. Min. Max. Min. Max. Min. Max. Units

t_PD

Internal Array Module

0.6

0.7

0.8

0.9

ns

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, Direct Connect

0.1

0.3

0.7

1.0

1.4

2.7

4.0

0.1

0.4

0.8

1.2

1.6

3.1

4.7

0.1

0.4

0.9

1.4

1.8

3.5

5.3

0.1

0.5

1.0

1.6

2.1

4.1

6.2

ns

t_FC

FO=1 Routing Delay, Fast Connect

FO=1 Routing Delay

t_RD1

t_RD2

FO=2 Routing Delay

t_RD3

FO=3 Routing Delay

t_RD4

FO=4 Routing Delay

t_RD8

FO=8 Routing Delay

t_RD12

FO=12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.8

0.5

0.7

1.1

0.6

0.8

1.3

0.7

0.9

1.4

0.8

1.0

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_PRESET

t_SUD

0.5

0.0

1.4

0.6

0.0

1.6

0.7

0.0

1.8

0.8

0.0

2.1

t_HD

t_WASYN

Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

1.5

1.7

1.9

2.2

ns

Predicted Input Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.7

1.0

1.4

2.7

4.0

0.4

0.8

1.2

1.6

3.1

4.7

0.4

0.9

1.4

1.8

3.5

5.3

0.5

1.0

1.6

2.1

4.1

6.2

ns

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is

based on actual routing delay measurements performed on the device prior to shipment.

32

54SX Family FPGAs

A54SX32 Timing Characteristics (continued)

(Worst-Case Commercial Conditions)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hard-Wired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.9

2.1

2.4

2.8

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

1.6

1.8

2.1

ns

0.3

0.4

0.5

ns

Minimum Period

2.7

3.1

3.6

4.2

ns

f_HMAX

Maximum Frequency

350

320

280

240

MHz

Routed Array Clock Networks

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

2.4

2.7

2.8

2.7

3.0

3.1

3.2

3.0

3.1

3.5

3.6

3.5

3.6

3.5

3.6

4.1

4.2

4.1

4.3

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Min. Pulse Width HIGH

2.1

2.4

2.7

3.2

ns

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.85

1.23

1.30

0.98

1.4

1.1

1.6

1.7

1.3

1.9

2.0

1.5

TTL Output Module Timing¹

t_DLH

Data-to-Pad LOW to HIGH

1.6

2.1

2.3

1.4

1.3

1.9

2.4

2.7

1.7

1.5

2.1

2.8

3.1

1.9

1.7

2.5

3.2

3.6

2.2

2.0

ns

t_DHL

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

Note:

1. Delays based on 35pF loading, except t_ENZLand t_ENZH. For t_ENZLand t_ENZHthe loading is 5pF.

33

Pin Description

CLKA/B

Clock A and B

TDI

Test Data Input

These pins are 3.3V/5.0V PCI/TTL clock inputs for clock

distribution networks. The clock input is buffered prior to

clocking the R-cells. If not used, this pin must be set LOW or

HIGH on the board. It must not be left floating. (For

A54SX72A, these clocks can be configured as bidirectional.)

Serial input for boundary scan testing and diagnostic probe.

In flexible mode, TDI is active when the TMS pin is set LOW

(refer to Table 2 on page 8). This pin functions as an I/O

when the boundary scan state machine reaches the “logic

reset” state.

GND

Ground

TDO

Test Data Output

LOW supply voltage.

Serial output for boundary scan testing. In flexible mode, TDO

is active when the TMS pin is set LOW (refer to Table 2 on

page 8). This pin functions as an I/O when the boundary scan

state machine reaches the “logic reset” state.

HCLK

Dedicated (Hard-wired)

Array Clock

This pin is the 3.3V/5.0V PCI/TTL clock input for sequential

modules. This input is directly wired to each R-cell and offers

clock speeds independent of the number of R-cells being

driven. If not used, this pin must be set LOW or HIGH on the

board. It must not be left floating.

TMS

Test Mode Select

The TMS pin controls the use of the IEEE 1149.1 Boundary

Scan pins (TCK, TDI, TDO). In flexible mode when the TMS

pin is set LOW, the TCK, TDI, and TDO pins are boundary scan

pins (refer to Table 2 on page 8). Once the boundary scan

pins are in test mode, they will remain in that mode until the

internal boundary scan state machine reaches the “logic

reset” state. At this point, the boundary scan pins will be

released and will function as regular I/O pins. The “logic

reset” state is reached 5 TCK cycles after the TMS pin is set

HIGH. In dedicated test mode, TMS functions as specified in

the IEEE 1149.1 specifications.

I/O

Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Based on certain configurations, input

and output levels are compatible with standard TTL, LVTTL,

3.3V PCI or 5.0V PCI specifications. Unused I/O pins are

automatically tristated by the Designer Series software.

NC

No Connection

This pin is not connected to circuitry within the device.

V_CCI

Supply Voltage

PRA, I/O

Probe A

Supply voltage for I/Os. See Table 1 on page 8.

The Probe A pin is used to output data from any user-defined

design node within the device. This independent diagnostic

pin can be used in conjunction with the Probe B pin to allow

real-time diagnostic output of any signal path within the

device. The Probe A pin can be used as a user-defined I/O

when verification has been completed. The pin’s probe

capabilities can be permanently disabled to protect

programmed design confidentiality.

V_CCA

Supply Voltage

Supply voltage for Array. See Table 1 on page 8.

V_CCR

Supply Voltage

Supply voltage for input tolerance (required for internal

biasing) See Table 1 on page 8.

PRB, I/O

Probe B

The Probe B pin is used to output data from any node within

the device. This diagnostic pin can be used in conjunction

with the Probe A pin to allow real-time diagnostic output of

any signal path within the device. The Probe B pin can be

used as a user-defined I/O when verification has been

completed. The pin’s probe capabilities can be permanently

disabled to protect programmed design confidentiality.

TCK

Test Clock

Test clock input for diagnostic probe and device

programming. In flexible mode, TCK becomes active when the

TMS pin is set LOW (refer to Table 2 on page 8). This pin

functions as an I/O when the boundary scan state machine

reaches the “logic reset” state.

34

54SX Family FPGAs

Package Pin Assignments

84-Pin PLCC (Top View)

1

84

84-Pin

PLCC

35

84-Pin PLCC Package

Number

A54SX08

Function

Number

A54SX08

Function

1

V_CCR

GND

V_CCA

PRA, I/O

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

V_CCR

I/O

2

3

HCLK

I/O

4

5

I/O

6

I/O

7

V_CCI

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

I/O

TDO, I/O

I/O

TCK, I/O

TDI, I/O

I/O

TMS

I/O

V_CCA

V_CCI

GND

I/O

V_CCA

GND

I/O

GND

V_CCI

I/O

PRB, I/O

V_CCA

GND

I/O

CLKA

CLKB

36

54SX Family FPGAs

Package Pin Assignments (continued)

208-Pin PQFP (Top View)

208

1

208-Pin PQFP

37

208-Pin PQFP

A54SX16,

A54SX16P

Function

A54SX16,

A54SX16P

Function

A54SX08

Function

A54SX32

Function

A54SX08

Function

A54SX32

Function

Pin Number

1

2

3

4

5

6

7

8

GND

TDI, I/O

I/O

NC

I/O

NC

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

54

55

56

57

58

59

60

61

62

63

64

65*

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

I/O

V_CCI

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

NC*

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

I/O

TMS

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCR

GND

V_CCA

GND

I/O

NC

I/O

NC

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

NC

I/O

NC

I/O

PRB, I/O

GND

V_CCA

GND

V_CCR

I/O

HCLK

I/O

PRB, I/O

GND

V_CCA

GND

V_CCR

I/O

HCLK

I/O

PRB, I/O

GND

V_CCA

GND

V_CCR

I/O

HCLK

I/O

V_CCR

GND

V_CCA

GND

I/O

V_CCR

GND

V_CCA

GND

I/O

NC

I/O

NC

I/O

NC

I/O

NC

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

GND

I/O

TDO, I/O

I/O

GND

NC

TDO, I/O

I/O

GND

I/O

TDO, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

* Please note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).

38

54SX Family FPGAs

208-Pin PQFP (Continued)

A54SX16,

A54SX16P

Function

A54SX16,

A54SX16P

Function

A54SX08

Function

A54SX32

Function

A54SX08

Function

A54SX32

Function

Pin Number

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

I/O

NC

I/O

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCA

V_CCI

NC

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

V_CCA

GND

V_CCR

I/O

GND

V_CCA

GND

V_CCR

I/O

GND

V_CCA

GND

V_CCR

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

GND

PRA, I/O

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

GND

PRA, I/O

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

GND

PRA, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCA

GND

I/O

NC

I/O

V_CCA

GND

I/O

V_CCI

I/O

V_CCA

GND

I/O

V_CCI

I/O

NC

I/O

V_CCI

I/O

V_CCI

NC

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

NC

GND

I/O

GND

I/O

GND

I/O

TCK, I/O

I/O

TCK, I/O

I/O

TCK, I/O

* Please note that Pin 65 in the A54SX32—PQ208 is a no connect (NC).

39

Package Pin Assignments (continued)

144-Pin TQFP (Top View)

144

1

144-Pin

TQFP

40

54SX Family FPGAs

144-Pin TQFP

A54SX08

Function

A54SX16P

Function

A54SX32

Function

A54SX08

Function

A54SX16P

Function

A54SX32

Function

Pin Number

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I/O

2

3

I/O

4

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

V_CCA

GND

V_CCR

I/O

V_CCA

GND

V_CCR

I/O

V_CCA

GND

V_CCR

I/O

V_CCR

V_CCA

I/O

V_CCR

V_CCA

I/O

V_CCR

V_CCA

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCA

V_CCI

V_CCA

V_CCI

V_CCA

V_CCI

I/O

41

144-Pin TQFP (Continued)

A54SX08

Function

A54SX16P

Function

A54SX32

Function

A54SX08

Function

A54SX16P

Function

A54SX32

Function

Pin Number

81

82

GND

I/O

GND

I/O

GND

I/O

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

I/O

83

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

84

I/O

85

I/O

86

I/O

87

I/O

88

I/O

89

V_CCA

V_CCR

I/O

V_CCA

V_CCR

I/O

V_CCA

V_CCR

I/O

90

I/O

91

I/O

92

I/O

93

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

I/O

94

I/O

95

I/O

96

I/O

97

I/O

98

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

99

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

TCK, I/O

I/O

42

54SX Family FPGAs

Package Pin Assignments (continued)

176-Pin TQFP (Top View)

176

1

176-Pin

TQFP

43

176-Pin TQFP

A54SX16,

A54SX16P

Function

A54SX16,

A54SX16P

Function

A54SX08

Function

A54SX32

Function

A54SX08

Function

A54SX32

Function

Pin Number

1

GND

TDI, I/O

NC

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

TMS

V_CCI

NC

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

NC

I/O

NC

I/O

PRB, I/O

GND

V_CCA

V_CCR

I/O

PRB, I/O

GND

V_CCA

V_CCR

I/O

PRB, I/O

GND

V_CCA

V_CCR

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

GND

44

54SX Family FPGAs

176-Pin TQFP (Continued)

A54SX16,

A54SX16P

Function

A54SX16,

A54SX16P

Function

A54SX08

Function

A54SX32

Function

A54SX08

Function

A54SX32

Function

Pin Number

89

GND

NC

I/O

GND

I/O

GND

I/O

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

GND

I/O

GND

I/O

GND

I/O

90

91

I/O

92

I/O

93

I/O

94

I/O

95

I/O

96

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

97

I/O

98

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

PRA, I/O

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

PRA, I/O

I/O

CLKA

CLKB

V_CCR

GND

V_CCA

PRA, I/O

I/O

NC

I/O

NC

V_CCA

GND

V_CCI

I/O

V_CCA

GND

V_CCI

I/O

V_CCA

GND

V_CCI

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

TCK, I/O

45

Package Pin Assignments (continued)

100-Pin VQFP (Top View)

100

1

100-Pin

VQFP

46

54SX Family FPGAs

100-VQFP

A54SX16,

A54SX16P

Function

A54SX16

A54SX16P

Function

A54SX08

Function

A54SX08

Function

Pin Number

1

2

3

4

5

6

7

8

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

GND

I/O

GND

I/O

TMS

V_CCI

GND

I/O

V_CCI

I/O

PRB, I/O

V_CCA

GND

V_CCR

I/O

HCLK

I/O

V_CCI

I/O

TMS

V_CCI

GND

I/O

V_CCI

I/O

PRB, I/O

V_CCA

GND

V_CCR

I/O

HCLK

I/O

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

I/O

V_CCA

GND

I/O

V_CCI

I/O

V_CCA

GND

I/O

V_CCI

I/O

CLKA

CLKB

V_CCR

V_CCA

GND

PRA, I/O

I/O

CLKA

CLKB

V_CCR

V_CCA

GND

PRA, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TCK, I/O

47

Package Pin Assignments (continued)

313-Pin PBGA (Top View)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

H

J

K

L

K

L

M

N

P

R

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AB

AC

AD

AE

AD

AE

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

48

54SX Family FPGAs

313-Pin PBGA

A54SX32

Pin Number Function

A54SX32

Pin Number Function

A54SX32

Pin Number Function

A1

GND

NC

I/O

V_CCR

I/O

NC

GND

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

NC

I/O

V_CCR

AC15

AC17

AC19

AC21

AC23

AC25

AD2

AD4

AD6

AD8

AD10

AD12

AD14

AD16

AD18

AD20

AD22

AD24

AE1

I/O

C5

C7

NC

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

F20

F22

F24

G1

I/O

A3

A5

I/O

C9

I/O

A7

I/O

C11

C13

C15

C17

C19

C21

C23

C25

D2

I/O

A9

I/O

G3

TMS

I/O

A11

NC

G5

A13

GND

I/O

G7

I/O

A15

G9

V_CCI

I/O

A17

V_CCI

I/O

G11

G13

G15

G17

G19

G21

G23

G25

H2

A19

CLKB

I/O

A21

I/O

A23

PRB, I/O

I/O

A25

D4

I/O

AA1

AA3

AA5

AA7

AA9

AA11

AA13

AA15

AA17

AA19

AA21

AA23

AA25

AB2

AB4

AB6

AB8

AB10

AB12

AB14

AB16

AB18

AB20

AB22

AB24

AC1

AC3

AC5

AC7

AC9

AC11

AC13

I/O

D6

I/O

D8

I/O

D10

D12

D14

D16

D18

D20

D22

D24

E1

I/O

NC

I/O

H4

I/O

NC

H6

I/O

AE3

I/O

H8

I/O

AE5

I/O

H10

H12

H14

H16

H18

H20

H22

H24

J1

I/O

AE7

I/O

PRA, I/O

I/O

AE9

I/O

AE11

AE13

AE15

AE17

AE19

AE21

AE23

AE25

B2

I/O

V_CCA

I/O

E3

NC

I/O

E5

I/O

E7

V_CCI

I/O

E9

I/O

E11

E13

E15

E17

E19

E21

E23

E25

F2

I/O

TDO, I/O

GND

TCK, I/O

I/O

J3

I/O

J5

I/O

J7

NC

I/O

B4

J9

B6

I/O

J11

J13

J15

J17

J19

J21

J23

J25

K2

I/O

B8

I/O

CLKA

I/O

B10

I/O

B12

I/O

B14

I/O

F4

I/O

B16

I/O

F6

GND

I/O

B18

I/O

F8

B20

I/O

F10

F12

F14

F16

F18

I/O

B22

I/O

B24

I/O

K4

I/O

C1

TDI, I/O

I/O

K6

I/O

C3

K8

V_CCI

49

313-Pin PBGA (Continued)

A54SX32

Pin Number Function

A54SX32

Pin Number Function

A54SX32

Pin Number Function

A54SX32

Pin Number Function

K10

K12

K14

K16

K18

K20

K22

K24

L1

I/O

N3

N5

V_CCA

V_CCR

I/O

R21

R23

R25

T2

I/O

HCLK

I/O

V_CCI

I/O

V_CCA

I/O

NC

V18

V20

V22

V24

W1

I/O

V_CCA

V_CCI

I/O

NC

I/O

V_CCI

I/O

NC

I/O

NC

I/O

N7

I/O

N9

V_CCI

GND

I/O

N11

N13

N15

N17

N19

N21

N23

N25

P2

T4

V_CCA

I/O

T6

W3

T8

W5

I/O

T10

T12

T14

T16

T18

T20

T22

T24

U1

W7

I/O

W9

L3

I/O

W11

W13

W15

W17

W19

W21

W23

W25

Y2

L5

I/O

V_CCR

V_CCA

I/O

L7

I/O

L9

I/O

L11

L13

L15

L17

L19

L21

L23

L25

M2

I/O

P4

I/O

GND

I/O

P6

I/O

P8

I/O

P10

P12

P14

P16

P18

P20

P22

P24

R1

I/O

U3

I/O

GND

I/O

U5

I/O

U7

Y4

I/O

U9

Y6

I/O

U15

U17

U19

U21

U23

U25

V2

Y8

I/O

NC

Y10

Y12

Y14

Y16

Y18

Y20

Y22

Y24

M4

I/O

M6

I/O

M8

I/O

M10

M12

M14

M16

M18

M20

M22

M24

N1

I/O

R3

I/O

GND

V_CCI

I/O

R5

I/O

R7

I/O

V4

R9

I/O

V6

R11

R13

R15

R17

R19

I/O

V8

I/O

GND

I/O

V10

V12

V14

V16

I/O

50

54SX Family FPGAs

Package Pin Assignments (continued)

329-Pin PBGA (Top View)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

51

329-Pin PBGA

A54SX32

Pin Number Function

A54SX32

Pin Number Function

A54SX32

Pin Number Function

A1

A2

GND

V_CCI

NC

AA23

AB1

V_CCI

I/O

AC22

AC23

B1

V_CCI

GND

V_CCI

GND

I/O

C21

C22

C23

D1

V_CCI

GND

NC

I/O

A3

AB2

GND

I/O

A4

AB3

B2

A5

I/O

AB4

I/O

B3

D2

I/O

A6

I/O

AB5

I/O

B4

I/O

D3

I/O

A7

V_CCI

NC

AB6

I/O

B5

I/O

D4

TCK, I/O

I/O

A8

AB7

I/O

B6

I/O

D5

A9

I/O

AB8

I/O

B7

I/O

D6

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

I/O

AB9

I/O

B8

I/O

D7

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

I/O

B9

I/O

D8

I/O

PRB, I/O

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

C1

I/O

D9

I/O

CLKB

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

E1

I/O

HCLK

I/O

PRA, I/O

CLKA

I/O

V_CCA

V_CCR

I/O

NC

I/O

V_CCI

GND

V_CCI

I/O

GND

I/O

GND

V_CCI

NC

I/O

GND

V_CCI

NC

I/O

GND

I/O

AC2

I/O

AC3

C2

TDI, I/O

GND

I/O

V_CCI

I/O

AC4

C3

E2

I/O

AC5

I/O

C4

E3

I/O

AC6

I/O

C5

I/O

E4

I/O

AC7

I/O

C6

I/O

E20

E21

E22

E23

F1

I/O

AC8

I/O

C7

I/O

AC9

V_CCI

I/O

C8

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

C9

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

I/O

F2

TMS

I/O

F3

I/O

F4

I/O

NC

I/O

F20

F21

F22

F23

G1

I/O

TDO, I/O

V_CCI

I/O

G2

I/O

NC

I/O

G3

I/O

52

54SX Family FPGAs

329-Pin PBGA

A54SX32

Pin Number Function

A54SX32

Pin Number Function

A54SX32

Pin Number Function

G4

G20

G21

G22

G23

H1

I/O

L22

L23

M1

I/O

NC

R20

R21

R22

R23

T1

I/O

V_CCA

I/O

V_CCA

I/O

V_CCI

I/O

NC

I/O

GND

I/O

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

I/O

V_CCA

V_CCR

I/O

M2

I/O

GND

I/O

M3

I/O

M4

V_CCA

GND

V_CCA

I/O

T2

I/O

H2

I/O

M10

M11

M12

M13

M14

M20

M21

M22

M23

N1

T3

I/O

H3

I/O

T4

I/O

H4

I/O

T20

T21

T22

T23

U1

I/O

H20

H21

H22

H23

J1

V_CCA

I/O

GND

I/O

NC

I/O

U2

I/O

J2

I/O

V_CCI

I/O

U3

J3

I/O

U4

J4

I/O

N2

I/O

U20

U21

U22

U23

V1

J20

J21

J22

J23

K1

I/O

N3

I/O

N4

I/O

N10

N11

N12

N13

N14

N20

N21

N22

N23

P1

GND

NC

I/O

V2

K2

I/O

V3

K3

I/O

V4

K4

I/O

V20

V21

V22

V23

W1

W2

W3

W4

W20

W21

W22

W23

Y1

K10

K11

K12

K13

K14

K20

K21

K22

K23

L1

GND

I/O

P2

I/O

P3

I/O

P4

I/O

P10

P11

P12

P13

P14

P20

P21

P22

P23

R1

GND

I/O

L2

I/O

L3

I/O

L4

V_CCR

GND

V_CCR

I/O

Y2

L10

L11

L12

L13

L14

L20

L21

I/O

Y3

I/O

Y4

I/O

Y5

I/O

Y6

R2

I/O

Y7

R3

I/O

Y8

R4

I/O

Y9

53

Package Pin Assignments (Continued)

144-Pin FBGA (Top View)

4

1

2

3

5

6

7

8

10 11 12

9

A

B

C

D

E

F

G

H

J

K

L

M

54

54SX Family FPGAs

144-Pin FBGA

A54SX08

Function

A54SX08

Function

A54SX08

Function

Pin Number

A1

A2

I/O

E1

E2

I/O

J1

J2

I/O

A3

I/O

E3

I/O

J3

I/O

A4

I/O

E4

I/O

J4

I/O

A5

V_CCA

GND

CLKA

I/O

E5

TMS

V_CCI

V_CCA

I/O

J5

I/O

A6

E6

J6

PRB, I/O

I/O

A7

E7

J7

A8

E8

J8

I/O

A9

I/O

E9

J9

I/O

A10

A11

A12

B1

I/O

E10

E11

E12

F1

J10

J11

J12

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

K12

L1

I/O

GND

I/O

V_CCA

I/O

B2

GND

I/O

F2

I/O

B3

F3

V_CCR

I/O

B4

I/O

F4

I/O

B5

I/O

F5

GND

V_CCI

I/O

B6

I/O

F6

I/O

B7

CLKB

I/O

F7

GND

I/O

B8

F8

B9

I/O

F9

I/O

B10

B11

B12

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

I/O

F10

F11

F12

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

L2

TCK, I/O

I/O

L3

I/O

L4

I/O

GND

V_CCI

I/O

L5

I/O

PRA, I/O

I/O

L6

I/O

L7

HCLK

I/O

L8

I/O

L9

I/O

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

I/O

V_CCI

TDI, I/O

I/O

V_CCA

V_CCI

V_CCA

I/O

V_CCA

I/O

TDO, I/O

I/O

V_CCR

55

Package Mechanical Drawings

Plastic Leaded Chip Carrier (PLCC)

.048 (1.219)

.042 (1.067)

D3 D1

D

E3

E1

E

.049 (1.244)

A

A1

0.006

e1

D2/E2

.075 (1.905)

B2

.032 (0.812)

C

MAX

.005 (0.127)

After Lead

Finish

Base Line

B

.035 RAD

(0.889)

.020 (0.508)

MIN

.044

(1.117)

56

54SX Family FPGAs

Plastic Leaded Chip Carrier Packages (PLCC)

PLCC 84

JEDEC Equiv

Dimension

MS007 AE VAR

Min.

Max

A

A1

3.94

2.29

4.45

3.30

B

0.33

0.69

B2

0.66

0.81

C

0.13

0.28

D/E

D1/E1

D2/E2

D3/E3

e1

29.72

28.96

27.69

30.73

29.46

28.70

25.4 nominal

1.27 BSC

Notes:

1. All dimensions are in millimeters.

2. BSC—Basic Spacing between Centers.

57

Package Mechanical Drawings (continued)

Plastic Quad Flat Pack (PQFP, TQFP, VQFP)

E1

E

D1

D

See Detail A

A1

A2

A

ccc

C

L

Detail A

10 Typ

0.20 RAD Typ

Theta

b

e

0.20 RAD Typ

58

54SX Family FPGAs

Package Mechanical Drawings (continued)

Plastic Quad Flat Pack

Rectangular Package (PQFP)

E1

E

D1

D

See Detail A

A1

A2

A

ccc

C

L

Detail A

10 Typ

0.20 RAD Typ

Theta

b

e

0.20 RAD Typ

59

Plastic Quad Flat Packs (PQFP)

PQFP 208

JEDEC Equiv

Dimension

MO-143

Min.

Nom

Max

A

3.70

0.38

3.40

4.10

A1

0.25

3.20

A2

3.60

0.27

0.20

b

c

0.17

0.09

D/E

D1/E1

e

30.25

27.90

30.60

28.00

30.85

28.10

0.50 BSC

0.60

L

0.50

0.75

ccc

0.10

7 deg

20.82

Theta

Diameter

0

19.82

20.32

Thin Quad Flat Packs (TQFP)

TQFP 144

TQFP 176

MO-136

JEDEC Equiv

Dimension

MO-136

Min.

Nom

Max

Min

Nom

Max

A

A1

1.60

0.15

1.60

0.15

0.05

1.35

0.10

1.40

0.05

1.35

0.10

1.40

A2

1.45

b

0.17

0.27

0.17

0.27

c

0.09

0.20

0.09

0.20

D/E

D1/E1

e

21.75

19.90

22.00

20.00

22.25

20.10

25.75

23.90

26.00

24.00

26.25

24.10

0.50 BSC

0.60

0.50 BSC

0.60

L

0.45

0

0.75

0.10

0.45

0

0.75

0.10

ccc

Theta

Notes:

7 deg

1. All dimensions are in millimeters.

2. BSC—Basic Spacing between Centers.

60

54SX Family FPGAs

Thin Quad Flat Packs (VQFP)

VQFP 100

JEDEC Equiv

Dimension

MO-136

Min

Nom

Max

A

A1

1.20

0.15

0.05

0.95

0.10

1.00

A2

1.05

b

0.17

0.27

c

0.09

0.20

D/E

D1/E1

e

15.75

13.90

16.00

14.00

16.25

14.10

0.50 BSC

0.60

L

0.45

0

0.75

0.10

ccc

Theta

Notes:

7 deg

1. All dimensions are in millimeters.

2. BSC—Basic Spacing between Centers.

61

Package Mechanical Drawings (continued)

144-Pin FBGA

Bottom View

Top View

Pin One Corner

D/D2

2

12 11 10

9

8

7

6

5

4

3

1

A

B

C

D

E

F

e

E/E2

E1

G

H

J

K

L

M

D1

Side View

Detail A

D1/E1 SQ

Detail A

// ccc C

// bbb C

A2

A

C

c

aaa C

∅b

A1

62

54SX Family FPGAs

Fine Pitch Ball Grid Array (FBGA)

FBGA 144

Dimension

Min.

Nom.

Max.

A

A1

A2

aaa

b

1.35

0.35

0.65

1.45

0.40

0.70

1.55

0.45

0.75

0.15

0.55

0.20

0.45

0.50

0.35

bbb

c

ccc

D

0.25

12.80

13.00

11.00 BSC

13.00

13.20

D1

D2

E

12.80

13.20

13.00

E1

E2

e

11.00 BSC

13.00

12.80

0.9

13.20

1.10

1.00

Notes:

1. All dimensions are in millimeters.

2. BSC—Basic Spacing between Centers.

63

Package Mechanical Drawings (continued)

Plastic Ball Grid Array (PBGA313)

Bottom View

Top View

D

Pin One

Corner

Pin One Corner

D2

25242322 2120 19181716151413121110 9 8 7

6 5 4 3 2 1

A

B

C

D

E

e

F

G

H

J

K

L

M

N

P

R

T

E E2

E1

U

V

W

Y

AA

AB

AC

AD

AE

r (dia.)

D1

Side View

Detail A

D1/E1 SQ

Detail A

R0.025 Typ.

// ccc C

A2

30

A

// bbb C

C

c

aaa C

∅b

A1

64

54SX Family FPGAs

Package Mechanical Drawings (continued)

Plastic Ball Grid Array (PBGA329)

Bottom View

Top View

D

Pin One

Corner

Pin One Corner

D2

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

e

F

G

H

J

K

L

E E2

M

N

P

E1

R

T

U

V

W

Y

AA

AB

AC

D1

Side View

Detail A

D1/E1 SQ

Detail A

R0.025 Typ.

// ccc C

A2

30

A

// bbb C

C

c

aaa C

∅b

A1

65

Plastic Ball Grid Array (PBGA)

JEDEC

Equivalent

PBGA313

Nom.

PBGA329

Nom.

Dimension

Min.

Max.

Min.

Max.

A

A1

A2

D

2.12

0.50

2.33

0.60

2.52

0.70

2.17

0.50

2.33

0.60

2.70

0.70

1.12

1.17

1.22

1.10

1.20

1.30

34.80

35.00

35.20

30.80

31.00

31.20

D1

D2

E

30.48 BSC

30.00

27.94 BSC

28.00

29.50

34.80

30.70

35.20

27.90

30.80

28.10

31.20

35.00

31.00

E1

E2

b

30.48 BSC

30.00

27.94 BSC

28.00

29.50

0.60

0.53

30.70

0.90

0.61

0.15

N/A

27.90

0.60

0.53

28.10

0.90

0.70

0.20

0.25

0.76

c

0.56

0.60

aaa

bbb

ccc

e

0.35

1.27 typ.

Notes:

1. All dimensions are in millimeters.

2. BSC—Basic Spacing between Centers.

66

54SX Family FPGAs

67

68

54SX Family FPGAs

69

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Europe Ltd.

Actel Corporation

955 East Arques Avenue

Sunnyvale, California 94086

USA

Actel Asia-Pacific

Daneshill House, Lutyens Close

Basingstoke, Hampshire RG24 8AG

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Tel: +44-(0)125-630-5600

Fax: +44-(0)125-635-5420

Tel: (408) 739-1010

Fax: (408) 739-1540

Tel: +81-(0)3-3445-7671

Fax: +81-(0)3-3445-7668

5172137-3/5.00


型号：	A54SX08-1PL84
厂家：	ETC
描述：	Field Programmable Gate Array (FPGA) 现场可编程门阵列（FPGA）的\n 现场可编程门阵列栅
文件：	总70页 (文件大小：1515K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A54SX08-1PL84 [ETC]

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