A6150A1XDL8A [ETC]
High Efficiency Linear Power Supply with Power Surveillance and Software Monitoring; 高效率线性电源供应器与电源监控和监视软件
| 型号： | A6150A1XDL8A |
| 厂家： | 
ETC |
| 描述： | High Efficiency Linear Power Supply with Power Surveillance and Software Monitoring |
| 文件： | 总14页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM MICROELECTRONIC-MARIN SA
A6150
High Efficiency Linear Power Supply with
Power Surveillance and Software Monitoring
software clears the watchdog too quickly (incorrect
Features
cycle time) or too slowly (incorrect execution) it will
cause the system to be reset. The system enable
output prevents critical control functions being
activated until software has successfully cleared the
watchdog three times. Such a security could be used
to prevent motor controls being energized on
repeated resets of a faulty system.
Highly accurate 5 V, 100 mA guaranteed output
Low dropout voltage, typically 380 mV at 100 mA
Low quiescent current, typically 175 µA
Standby mode, maximum current 340 µA (with
100 µA load on OUTPUT)
Unregulated DC input can withstand –20 V reverse
battery and + 60 V power transients
Fully operational for unregulated DC input voltage
up to 26 V and regulated output voltage down to 3.0 V
Reset output guaranteed for regulated output voltage
down to 1.2 V
No reverse output current
Very low temperature coefficient for the regulated output
Current limiting
Applications
Automotive systems
Cellular telephones
Security systems
Battery powered products
High efficiency linear power supplies
Automotive electronics
Comparator for voltage monitoring,voltage reference
1.52 V
Programmable reset voltage monitoring
Programmable power on reset (POR ) delay
Watchdog with programmable time windows guarant-
ees a minimum time and a maximum time between
software clearing of the watchdog
Time base accuracy 10%
System enable output offers added security
TTL/CMOS compatible
Version A0:
Version A1:
Unregu-
lated
voltage
-40 to +85 °C temperature range
On request extended temperature range,-40 to +125 °C
DIP8 and SO8 packages
5 V
INPUT OUTPUT
A6150
R
VIN
TCL
RES
EN
Description
The A6150 offers a high level of integration by combining
voltage regulation, voltage monitoring and software
monitoring in an 8 lead package. The voltage regulator
has a low dropout voltage (typ. 380 mV at 100 mA) and a
low quiescent current (175 µA). The quiescent current
increases only slightly in dropout prolonging battery life.
Built-in protection includes a positive transient absorber for
up to 60 V (load dump) and the ability to survive an
unregulated input voltage of –20 V (reverse battery). The
input may be connected to ground or a reverse voltage
without reverse current flow from the output to the input. A
comparator monitors the voltage applied at the VIN input
comparing it with an internal 1.52 V reference. The power-
on reset function is initialized after VIN reaches 1.52 V and
takes the reset output inactive after TPOR depending of
external resistance. The reset output goes active low when
the VIN voltage is less than 1.52 V. The RES and EN
outputs are guaranteed to be in a correct state for a
regulated output voltage as low as 1.2 V. The watchdog
function monitors software cycle time and execution. If
VSS
GND
Fig. 1
Typical Operating Configuration
Pin Assignment
DIP8/ SO8
EN
VIN
RES
TCL
VSS
R
A6150
OUTPUT
INPUT
Fig. 2
1
A6150
Absolute Maximum Ratings
Operating Conditions
Parameter
Symbol
Conditions
Parameter
Symbol Min. Typ. Max. Units
Operating junction
temperature 1)
Continuous voltage at INPUT
to VSS
TJ
VINPUT
VOUTPUT
-40
2.3
1.2
1.2
+125
26
°C
V
V
V
mA
VINPUT
-0.3 to + 30 V
INPUT voltage 2)
OUTPUT voltage 2) 3)
Transients on INPUT for
t < 100 ms and duty cycle 1%
Reverse supply voltage on INPUT
Max. voltage at any signal pin
Min. voltage at any signal pin
Storage temperature
Electrostatic discharge max. to
MIL-STD-883C method 3015
Max. soldering conditions
VTRANS
VREV
VMAX
VMIN
up to + 60 V
- 20 V
OUTPUT + 0.3 V
VSS – 0.3 V
RES & EN guaranteed 4) VOUTPUT
OUTPUT current 5)
Comparator input
voltage
IOUTPUT
VIN
100
VOUTPUT
1000
0
V
TSTO
-65 to + 150 °C
RC-oscillator
programming
Thermal resistance from
junction to ambient 6)
-DIP8
R
10
kΩ
VSmax
TSmax
1000 V
250 °C x 10 s
Table 1
Rth(j-a)
Rth(j-a)
105 °C/W
160 °C/W
-SO8
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure be-
yond specified operating conditions may affect device
reliability or cause malfunction.
Table 2
1) The maximum operating temperature is confirmed by
sampling at initial device qualification. In production, all
devices are tested at +85 °C. On request devices tested at
+125 °C can be supplied.
Handling Procedures
2) Full operation quaranteed. To achieve the load regulation
specified in Table 3 a 22 µF capacitor or greater is
required on the INPUT, see Fig. 18. The 22 µF must have
an effective resistance ≤ 5 Ω and a resonant frequency
above 500 kHz.
This device has built-in protection against high static
voltages or electric fields; however, anti-static precau-
tions must be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only
occur when all terminal voltages are kept within the
supply voltage range. At any time, all inputs must be tied
to a defined logic voltage level.
3) A 10 µF load capacitor and a 100 nF decoupling capacitor
are required on the regulator OUTPUT for stability. The
10 µF must have an effective series resistance of ≤ 5 Ω and
a resonant frequency above 500 kHz.
4) RES and EN (EN only for version A0) must be pulled up
externally to VOUTPUT even if they are unused. (Note: RES
and EN are used as inputs by EM test).
5) The OUTPUT current will not apply for all possible
combinations of input voltage and output current.
Combinations that would require the A6150 to work above
the maximum junction temperature (+125 °C) must be
avoided.
6) The thermal resistance specified assumes the package is
soldered to a PCB.
2
A6150
Electrical Characteristics
VINPUT = 6.0 V, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to +85 °C, unless otherwise specified
Parameter
Symbol Test Conditions
Min. Typ. Max.
Unit
Supply current in standby mode ISS
REXT = don’t care, TCL = VOUTPUT
VIN = 0 V, IL = 100 µA
REXT = 100 kΩ, I/PS at VOUTPUT,
O/PS 1 MΩ to VOUTPUT, IL = 100 µA
REXT = 100 kΩ, I/PS at VOUTPUT, VINPUT
8.0 V, O/PS 1 MΩ to VOUTPUT, IL = 100 mA
IL = 100 µA
100 µA ≤ IL ≤ 100 mA,
-40 °C ≤ TJ ≤+125 °C
,
340
400
µA
µA
Supply current 1)
Supply current 1)
ISS
ISS
175
1.7
=
4.2
5.12
mA
V
Output voltage
Output voltage
VOUTPUT
VOUTPUT
4.88
4.85
5.15
V
Output voltage temperature
coefficient 2)
Vth(coeff)
VLINE
50
180 ppm/°C
Line regulation 3)
6 V ≤ VINPUT ≤26 V, IL = 1 mA,
TJ = +125 °C
0.2
0.2
40
0.5
0.6
170
%
%
mV
mV
mV
Load regulation 3)
Dropout voltage 4)
Dropout voltage 4)
Dropout voltage 4)
Dropout supply current
VL
100 µA ≤ IL ≤ 100 mA
VDROPOUT IL = 100 µA
VDROPOUT IL = 100 mA
VDROPOUT IL = 100 mA, -40 °C ≤ TJ ≤+125 °C
ISS
380
650
VINPUT = 4.5 V, IL = 100 µA,
REXT = 100 kΩ, O/PS 1 MΩ to
VOUTPUT, I/PS at VOUTPUT
TJ = +25 °C, IL = 50 mA,
VINPUT = 26 V, T = 10 ms
OUTPUT tied to VSS
1.2
1.6
mA
Thermal regulation 5)
Current limit
Vthr
0.05 0.25
450
%/W
mA
ILmax
OUTPUT noise, 10Hz to 100kHz VNOISE
200
µVrms
RES & EN
Output Low Voltage
VOL
VOL
VOL
VOL
VOUTPUT = 4.5 V, IOL= 20 mA
VOUTPUT = 4.5 V, IOL = 8 mA
VOUTPUT = 2.0 V, IOL = 4 mA
VOUTPUT = 1.2 V, IOL = 0.5 mA
0.4
0.2
0.2
V
V
V
V
0.4
0.4
0.2
0.06
EN (vers. A1)
Output High Voltage
VOH
VOH
VOH
VOUTPUT = 4.5 V, IOH= -1 mA
VOUTPUT = 2.0 V, IOH= -100 µA
VOUTPUT = 1.2 V, IOH= -30 µA
3.5
1.8
1.0
4.1
1.9
1.1
V
V
V
TCL and VIN
TCL Input Low Level
TCL Input High Level
Leakage current
VIN input resistance
VIL
VIH
ILI
RVIN
VREF
VREF
VREF
VHY
VSS
2.0
0.8
VOUTPUT
1
V
V
µA
MΩ
V
V
V
VSS ≤ VTCL ≤ VOUTPUT
TJ = +25 °C
0.05
100
1.474 1.52 1.566
1.436
1.420
Comparator reference 6)7)
Comparator hysteresis 7)
1.620
1.620
-40 °C ≤TJ ≤+125 °C
2
mV
Table 3
1) If INPUT is connected to VSS, no reverse current will flow from the OUTPUT to the INPUT, however the supply current specified will
be sank by the OUTPUT to supply the A6150.
2) The OUTPUT voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.
3) Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in OUTPUT voltage
due to heating effects are covered in the specification for thermal regulation.
4) The dropout voltage is defined as the INPUT to OUTPUT differential, measured with the input voltage equal to 5.0 V.
5) Thermal regulation is defined as the change in OUTPUT voltage at a time T after a change in power dissipation is applied,
excluding load or line regulation effects.
6) The comparator and the voltage regulator have separate voltage references (see “ Block Diagram” Fig. 7).
7) The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference
voltage plus the comparator hysteresis (see Fig. 4).
3
A6150
Timing Characteristics
V INPUT = 6.0 V, IL = 100 µA, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to + 85 °C, unless otherwise specified
Parameter
Symbol Test Conditions
Min.
Typ.
Max.
Units
Propagation delays:
TCL to Output Pins
VIN sensitivity
Logic Transition Times on all Output Pins TTR
Power-on Reset delay
Watchdog Time
TDIDO
TSEN
250
5
30
100
100
500
20
100
110
110
ns
µs
1
Load 10 kΩ, 50 pF
REXT = 123 kΩ 1%
REXT = 123 kΩ 1%
ns
TPOR
TWD
90
90
ms
ms
Open Window Percentage
Closed Window Time
OWP
TCW
TCW
TOW
TOW
TWDR
TWDR
TTCL
0.2 TWD
0.8 TWD
80
0.4 TWD
40
TWD/40
2.5
REXT = 123 kΩ 1%
REXT = 123 kΩ 1%
REXT = 123 kΩ 1%
72
36
88
44
ms
ms
Open Window Time
Watchdog Reset Pulse
TCL Input Pulse Width
ms
ns
150
Table 4
Timing Waveforms
Watchdog Timeout Period
TWD = TPOR
Condition:
REXT = 123 kΩ
+ OWP
+ 20%
−
−
OWP
20%
TCW – closed window
TOW – open window
100
Watchdog
timer reset
t [ms]
Fig. 3
80
120
Voltage Monitoring
VHY
Conditions:
VOUTPUT ≥ 3 V
No timeout
VIN
VREF
TSEN
TSEN
TSEN
TSEN
TPOR
TPOR
RES
Fig. 4
4
A6150
Timer Reaction
Conditions: VIN > VREF after power-up sequence
TOW
TCW
TCW
TCW+TOW
TCW
TCW+TOW
TCW+TOW
TOW
TCL
RES
TTCL
TWDR
EN
1
2
3
3 correct TCL services
EN goes active low
Timeout
- Watchdog timer reset
Fig.5
Combined Voltage and Timer Reaction
Condition:
VOUTPUT ≥ 3 V
VIN
VREF
TPOR=TWD
TOW
TCW
TCL
TCW+TOW
RES
EN
1
2
3
TCL
too early
3 correct TCL service
EN goes active low
- Watchdog timer reset
Fig. 6
Block Diagram
Voltage
OUTPUT
EN
Regulator
INPUT
Enable
Logic
Voltage
Reference
Vers. A0
Vers. A1
VREF
Comparator
Voltage
Reference
Reset
Control
RES
VIN
Open drain
output RES
Current
Controlled
Oscillator
Timer
R
Fig. 7
TCL
5
A6150
Pin Description
The maximum continuous power dissipation at a given
temperature can be calculated using the formula:
Pin Name
Function
1
EN
Vers. A0:
P
MAX = ( 125 °C – TA) / Rth(j-a)
Open drain active low enable output.
EN must be pulled to VOUTPUT
even if unused
where Rth(j-a) is the termal resistance from the junction to
the ambient and is specified in Table 2. Note the Rth(j-a)
given in Table 2 assumes that the package is soldered
to a PCB. The above formula for maximum power dissi-
pation assumes a constant load (ie.≥100 s). The
transient thermal resistance for a single pulse is much
lower than the continuous value. For example the A6150
in DIP8 package will have an effective thermal resistance
from the junction to the ambient of about 10 °C/W for a
single 100 ms pulse.
Vers. A1:
Push-pull active low reset output
Open drain active low reset output.
RES must be pulled up to VOUTPUT
even if unused
Watchdog timer clear input signal
GND terminal
2
RES
3
4
5
6
7
8
TCL
VSS
INPUT
Voltage regulator input
OUTPUT Voltage regulator output
R
VIN
VIN Monitoring
REXT input for RC oscillator tuning
Voltage comparator input
The power-on reset and the power-down reset are
generated as a response to the external voltage level
applied on the VIN input. The VDD voltage at which reset is
asserted or released is determined by the external
voltage divider between VDD and VSS, as shown on Fig.
18. A part of VDD is compared to the internal voltage
reference. To determine the values of the divider, the
leakage current at VIN must be taken into account as well
as the current consumption of the divider itself. Low
resistor values will need more current, but high resistor
values will make the reset threshold less accurate at
high temperature, due to a possible leakage current at
the VIN input. The sum of the two resistors should stay
below 300 kΩ. The formula is: VRESET = VREF *(1 + R1/R2).
Example: choosing R1 = 100 kΩ and R2 = 51 kΩ will
result in a VDD reset threshold of 4.5 V (typ.).
Table 5
Functional Description
Voltage Regulator
The A6150 has a 5 V
2%, 100 mA, low dropout volt-
age regulator. The low supply current (typ.155 µA) mak-
es the A6150 particularly suited to automotive systems
then remain energized 24 hours a day. The input voltage
range is 2.3 V to 26 V for operation and the input protec-
tion includes both reverse battery (20 V below ground)
and load dump (positive transients up to 60 V). There is
no reverse current flow from the OUTPUT to the INPUT
when the INPUT equals VSS. This feature is important for
systems which need to implement (with capacitance) a
minimum power supply hold-up time in the event of
power failure. To achieve good load regulation a 22 µF
capacitor (or greater ) is needed on the INPUT (see
Fig. 18). Tantalum or aluminium electrolytics are adequate
for the 22 µF capacitor; film types will work but are relati-
vely expensive. Many aluminium electrolytics have
electrolytes that freeze at about –30 °C, so tantalums are
recommended for operation below –25 °C. The impor-
tant parameters of the 22 µF capacitor are an effective series
At power-up the reset output (RES) is held low (see
Fig. 4). After INPUT reaches 3.36 V (and so OUTPUT
reaches at least 3 V) and VIN becomes greater than VREF
,
the RES output is held low for an additional power-on-
reset (POR) delay which is equal to the watchdog time
TWD (typically 100 ms with an external resistor of 123 kΩ
connected at R pin). The POR delay prevents repeated
toggling of RES even if VIN and the INPUT voltage drops
out and recovers. The POR delay allows the micropro-
cessor’s crystal oscillator time to start and stabilize and
ensures correct recognition of the reset signal to the
microprocessor.
The RES output goes active low generating the power-
down reset whenever VIN falls below VREF. The sensiti-
vity or reaction time of the internal comparator to the vol-
tage level on VIN is typically 5 µs.
resistance of ≤ 5 Ω and a resonant frequency
500 kHz.
A 10 µF capacitor (or greater) and a 100 nF capacitor are
required on the OUTPUT to prevent oscillations due to
instability. The specification of the 10 µF capacitor is as
per the 22 µF capacitor on the INPUT (see previous
paragraph).
above
Timer Programming
The A6150 will remain stable and in regulation with no
external load and the dropout voltage is typically con-
stant as the input voltage fall to below its minimum level
(see Table 2). These features are especially important in
CMOS RAM keep-alive applications.
Care must be taken not to exceed the maximum junction
temperature (+ 125 °C). The power dissipation within
the A 6150 is given by the formula:
The on-chip oscillator with an external resistor REXT con-
nected between the R pin and VSS (see Fig. 18) allows
the user to adjust the power-on reset (POR) delay,
watchdog time TWD and with this also the closed and
open time windows as well as the watchdog reset pulse
width (TWD/40).
With REXT = 123 kΩ typical values are:
-Power-on reset delay: TPOR is 100 ms
-Watchdog time:
TWD is 100 ms
PTOTAL = (VINPUT – VOUTPUT) * IOUTPUT + (VINPUT) * ISS
6
A6150
-Closed window:
-Open window:
-Watchdog reset:
Note the current consumption increases as the fre-
quency increases.
TCW is 80 ms
TOW is 40 ms
4.
26 ms at +25 °C
T
WDR is 2.5 ms
a) (26 − 10% = 23.4 ms) (26 + 10% = 28.6 ms) a)
Watchdog Timeout Period Description
b) (23.4 − 5% = 22.2 ms)
(28.6 + 5% = 30.0 ms) b)
The watchdog timeout period is divided into two parts, a
“closed” window and an “open” window (see Fig. 3) and
is defined by two parameters, TWD and the Open Window
Percentage (OWP).
min.: (30.0 − 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
The closed window starts just after the watchdog timer
resets and is defined by TCW = TWD – OWP(TWD).
The open window starts after the closed time window
finishes and lasts till TWD + OWP(TWD).The open window
Typical TCL period of
(24.0 + 26.7) / 2 = 25.4 ms
The ratio between TWD = 26 ms and the (TCL period)
= 25.4 ms is 0.975.
time is defined by TOW = 2 x OWP (TWD
)
Then the relation over the production and the full
temperature range is, TCL period = 0.975 x TWDor
0.975 x REXT
For example if TWD = 100 ms (actual value) and OWP =
20% this means the closed window lasts during first
the 80 ms (TCW = 80 ms = 100ms – 0.2 (100 ms)) and
the open window the next 40 ms (TOW = 2 x 0.2 (100 ms)
= 40 ms). The watchdog can be serviced between
80 ms and 120 ms after the timer reset. However as the
TCL period =
, as typical value.
a) While PRODUCTION value unknown for the custo-
mer when REXT ≠ 123 kΩ.
b) While operating TEMPERATURE range
-40 °C ≤ TJ ≤ +85 °C.
time base is
10% accurate, software must use the
5. If you fixed a TCL period = 26 ms
following calculation as the limits for servicing signal TCL
during the open window:
Related to curves (Fig. 10 to Fig. 20), especially Fig. 19
and Fig. 20, the relation between TWD and REXT could
easily be defined. Let us take an example describing the
variations due to production and temperature:
1.Choice, TWD = 26 ms.
26 x 1.155
⇒ REXT
=
= 30.8 kΩ.
0.975
If during your production the TWD time can be mea-
sured at TJ = + 25 °C and the µC can adjust the TCL
period, then the TCL period range will be much larger
for the full operating temperature.
2.Related to Fig. 20, the coefficient (TWD to REXT
1.155 where REXT is in kΩ and TWD in ms.
3.REXT (typ.) = 26 x 1.155 = 30.0 kΩ.
)
is
TWD versus VOUTPUT at TJ = +25 °C
TWD versus R at TJ = +25 °C
10’000
R = 1 MΩ
1000
1000
100
R = 100 kΩ
100
R = 10 k
3 V
4.8 V
10
5 V
5.2 V
6 V
R = 1 kΩ
1
1
100
1000
10’000
Fig. 9
10
0.1
1
6
VOUTPUT [V]
R[kΩ]
Fig. 8
7
A6150
TWD versus R at TJ = +25 °C
10’000
1000
100
3 V
10
4.8 V
5 V
5.2 V
6 V
1
100
1000
10’000
10
0.1
1
R[kΩ]
Fig. 10
8
A6150
TWD versus VOUTPUT at TJ = +85 °C
R = 10 MΩ
TWD versus R at TJ = +85 °C
10’000
10’000
1000
100
R = 1 MΩ
1000
100
R = 100 kΩ
R = 10 kΩ
R = 1 kΩ
5
10
1
10
1
3 V
4.8 V
5 V
5.2 V
6 V
0.1
1
10’000
1000
10
100
6
3
4
R[kΩ]
Fig. 12
VOUTPUT [V]
Fig. 11
TWD versus VOUTPUT at TJ = -40 °C
TWD versus R at TJ = -40 °C
R = 10 MΩ
10’000
R = 1 MΩ
1000
100
1000
R = 100 kΩ
100
10
1
10
R = 10 kΩ
R = 1 kΩ
5
1
3 V
4.8 V
5 V
5.2 V
6 V
0.1
6
3
4
1
10
100
1000 10’000
Fig. 14
0.1
R[kΩ]
VOUTPUT [V]
Fig. 13
9
A6150
TWD versus temperature at 5 V
T WD versus R at 5 V
R = 10 MΩ
R = 1 MΩ
10’000
10’000
1000
100
1000
100
R = 100 kΩ
R = 10 kΩ
R = 1 kΩ
-40 °C
-20 °C
+25 °C
+70 °C
+85 °C
10
1
10
1
1000 10’000
Fig. 16
100
R[kΩ]
0.1
1
10
+80
+60
-20
+20 +40
-40
0
TJ [°C]
Fig. 15
OUTPUT Current versus INPUT Voltage
SO8 package
soldered to PC board
80
T
Jmax = + 125 °C
60
TA=+50 °C
TA=+25 °C
TA=+85 °C
20
0
5
10
15
20
25
30
INPUT voltage [V]
Fig.17
10
A6150
TPOR, a pull-up to VDD is required on that pin. After the
POR delay has elapsed, RES goes inactive and the
watchdog timer starts acting. If no TCL pulse occurs,
RES goes active low for a short time TWDR after each
closed and open window period. A TCL pulse coming
during the open window clears the watchdog timer.
When the TCL pulse occurs too early (during the closed
window), RES goes active and a new timeout sequence
starts. A voltage drop below the VREF level for longer than
typically 5µs overrides the timer and immediately forces
RES active and EN inactive. Any further TCL pulse
has no effect until the next power-up sequence has
completed.
Timer Clearing and RES Action
The watchdog circuit monitore the activity of the proces-
sor. If the user’s software does not send a pulse to the
TCL input within the programmed open window timeout
period a short watchdog RES pulse is generated which
is equal to TWD /40 = 2.5 ms typically (see Fig. 5).
With the open window constraint new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution) it will cause the system to be reset.
If software is stuck in a loop which includes the routine
to clear the watchdog then a conventional watchdog
would not make a system reset even though software is
malfunctioning; the A6150 would make a system reset
because the watchdog would be cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves
of period (TCW + TOW + TWDR). The watchdog will remain
in this state until the next TCL falling edge appears
during an open window, or until a fresh power-up se-
quence. The system enable output, EN , can be used to
prevent critical control functions being activated in the
event of the system going into this failure mode (see
section “Enable-EN Output”).
Enable - EN Output
The system enable output, EN ,is inactive always when
RES is active and remains inactive after a RES pulse
until the watchdog is serviced correctly 3 consecutive
times (ie. the TCL pulse must come in the open win-
dow). After three consecutive services of the watchdog
with TCL during the open window, the EN goes active
low.
A malfunctioning system would be repeatedly reset by
the watchdog. In a conventional system critical motor
controls could be energized each time reset goes inac-
tive (time allowed for the system to restart) and in this
way the electrical motors driven by the system could
function out of control. The A6150 prevents the above
failure mode by using the EN output to disable the motor
controls until software has successfully cleared the
watchdog three times (ie. the system has correctly re-
started after a reset condition).
The RES output must be pulled up to VOUTPUT even if the
output is not used by the system (see Fig 18).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrat-
ed by the sequence of events shown in Fig. 6. On pow-
er-up, when the voltage at VIN reaches VREF, the power-
on-reset, POR, delay is initialized and holds RES active
for the time of the POR delay. A TCL pulse will have no
effect until this power-on-reset delay is completed. When
the risk exists that TCL temporarily floats, e.g. during
For the version A0 the EN output must be pulled up to
V
OUTPUT even if the output is not used by the system (see
Fig. 18.
Typical Application
Version A0:
Version A1:
Regulated voltage
Unregulated voltage
INPUT
OUTPUT
100 nF
+
R1
Address
decoder
10 µF
A6150
VIN
R
22 µF
+
100 kΩ
TCL
RES
EN
Microprocessor
RES
VSS
Motor
EN
controls
R2
GND
Fig.18
11
A6150
TWD Coefficient versus REXT at TJ = + 25 °C
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
0.80
0.78
0.76
10
100
1000
REXT [kΩ]
Fig. 19
REXT Coefficient versus TWD at TJ = + 25 °C
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
10
1000
100
TWD [ms]
Fig. 20
12
A6150
Package Information
Dimensions of 8-Pin SOIC Package
E
D
C
0 - 8°
A
A1
B
L
e
H
Dimensions in mm
Min Nom Max
1.35 1.63 1.75
A
A1 0.10 0.15 0.25
4
5
3
2
7
B
C
D
E
e
0.33 0.41 0.51
0.19 0.20 0.25
4.80 4.93 5.00
3.80 3.94 4.00
1.27
6
8
H
5.80 5.99 6.20
L
0.40 0.64 1.27
Fig. 21
Dimensions of 8-Pin Plastic DIP Package
A1 A2
A
C
L
eA
eB
b3
e
b2
b
Dimensions in mm
Min. Nom. Max.
5.33
Min. Nom. Max.
A
D
E
9.01 9.27 10.16
7.62 7.87 8.25
A1 0.38
A2 2.92 3.30 4.95
0.35 0.45 0.56
b2 1.14 1.52 1.78
b3 0.76 0.99 1.14
E1 6.09 6.35 7.11
4
3
2
1
b
e
2.54
7.62
eA
eB
L
E1
E
10.92
C
0.20 0.25 0.35
2.92 3.30 3.81
5
6
7
8
Fig.22
13
A6150
Ordering Information
When ordering, please specify complete Part Number
Part Number
Output EN Temperature Range
Package
Delivery Form Package Marking
(first line)
A6150A1SO8A
A6150A1SO8B
A6150A1DL8A*
A6150A0SO8A*
A6150A0SO8B* Open drain
A6150A0DL8A*
A6150A1XSO8A*
A6150A1XSO8B* Push-pull
A6150A1XDL8A*
8-pin SOIC
8-pin SOIC
8-pin plastic DIP Stick
8-pin SOIC
8-pin SOIC
8-pin plastic DIP Stick
Stick
Tape & Reel
6150A1
6150A1
A6150A1
6150A0
6150A0
A6150A0
6150A1X
6150A1X
A61501X
6150A0X
6150A0X
A61500X
Push-pull
-40 °C to +85 °C
Stick
Tape & Reel
8-pin SOIC
8-pin SOIC
-40 °C to +125 °C 8-pin plastic DIP Stick
Stick
Tape & Reel
A6150A0XSO8A*
A6150A0XSO8B* Open drain
A6150A0XDL8A*
8-pin SOIC
8-pin SOIC
8-pin plastic DIP Stick
Stick
Tape & Reel
* = non stock item. Might be available on request and upon minimum order quantity (please contact EM Microelectronic).
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely
embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the
circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given
has not been superseded by a more up-to-date version.
© 2002 EM Microelectronic-Marin SA, 03/02, Rev. N/344
14
EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. +41 – (0)32 75 55 111, Fax +41 – (0)32 75 55 403
相关型号：
A6150A1XSO8A
High Efficiency Linear Power Supply with Power Surveillance and Software Monitoring
ETC
A6150A1XSO8B
High Efficiency Linear Power Supply with Power Surveillance and Software Monitoring
ETC
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