概述
数据手册ACE1101BEN14 概述
8-Bit Microcontroller
8位微控制器\n
ACE1101BEN14 数据手册
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August 2001
ACE1101 Product Family
Arithmetic Controller Engine (ACEx™)
for Low Power Applications
General Description
I On-chip oscillator
— No external components
— 1µs instruction cycle time
The ACE1101 (Arithmetic Controller Engine) family of
microcontrollers is a dedicated programmable monolithic inte-
grated circuit for applications requiring high performance, low
power, and small size. It is a fully static part fabricated using
I On-chip Power-on Reset
I Brown-out Reset
CMOS technology.
I Programmable read and write disable functions
I Memory mapped I/O
The ACE1101 product family has an 8-bit microcontroller core, 64
bytes of RAM, 64 bytes of data EEPROM and 1K bytes of code
EEPROM. Its on-chip peripherals include a multi-function 16-bit
timer, watchdog/idle timer, and programmable under-voltage
detection circuitry. On-chip clock and reset functions reduce the
number of required external components. The ACE1101 product
family is available in 8-pin TSSOP, 8-pin DIP and 14-pin DIP
packages.
I Multi-level Low Voltage Detection
I Fully static CMOS
— Low power HALT mode (100nA @ 3.3V)
— Power saving IDLE mode
I Single supply operation
— 1.8-5.5V (ACE1101L)
— 2.2-5.5V (ACE1101)
— 2.7-5.5V (ACE1101B)
Features
I Software selectable I/O options
— Push-pull outputs with tri-state option
— Weak pull-up or high impedance inputs
I Arithmetic Controller Engine
I 1K bytes on-board code EEPROM
I 64 bytes data EEPROM
I 64 bytes RAM
I 40 years data retention
I 1,000,000 writes
I Watchdog
I 8-pin TSSOP, 8 and 14-pin DIP packages. (SOIC and CSP
packages available upon request)
I Multi-input wake-up on all I/O pins
I 16-bit multifunction timer
I In-circuit programming
Block and Connection Diagram
1
V
CC
GND1
Power-on
Reset
Internal
Oscillator
RESET2
Low Battery/Brown-out
Detect
Watchdog/
12-Bit Timer 0
16-Bit Timer 1
G0 (CKO)
G1 (CKI)
G2 (T1)
G3(Input only)
G4
G port
general
purpose
I/O
with
multi-
input
ACE1101
Control
Unit
HALT/IDLE
Power saving
Modes
Programming
Interface
RAM block
64 bytes
G5
G62
wakeup
1K bytes of CODE
EEPROM
64 bytes of DATA
EEPROM
G72
1. 100nf Decoupling capacitor recommended
2. Available only in the 14-pin package option.
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1
© 2001 Fairchild Semiconductor Corporation
ACE1101 Product Family Rev. B.2
Figure 2: ACE1101 Application Example (Remote Keyless Entry)
V
CC
Optional
LED
G4
V
G3
CC
RF Interface
G0
G1
G5
G2
RF Stage
GND
Figure 3: ACE1101 TSSOP/DIP 8-pin Device
a) Normal Mode Operation
b) Programming Mode Operation
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
G3
G4
G5
G0
VCC
GND
G2
LOAD
SFT_IN
NC/VCC
NC
VCC
GND
SFT_OUT
CKI
G1
Figure 4: ACE1101 DIP 14-pin Device
a) Normal Mode Operation
b) Programming Mode Operation
1
2
3
4
5
6
7
14
13
12
11
10
9
G3
G4
NC
G6
G7
G5
G0
VCC
GND
RESET
G2
1
2
3
4
5
6
7
14
13
12
11
10
9
LOAD
SFT_IN
NC
VCC
GND
RESET
SFT_OUT
NC
NC
NC
NC
NC
NC/VCC
NC
NC
8
G1
8
CKI
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2
ACE1101 Product Family Rev. B.2
2.0 Electrical Characteristics
Absolute Maximum Ratings
Operating Conditions
Relative Humidity (non-condensing)
EEPROM write limits
Ambient Storage Temperature
-65°C to +150°C
95%
Input Voltage not including G3
G3 Input Voltage
-0.3V to VCC+0.3V
0.3V to 13V
+300°C
See DC Electrical
Characteristics
Lead Temperature (10s max)
Electrostatic Discharge on all pins
2000V min
Device
ACE1101
Operating Voltage Ambient Operating Temperature
2.2 to 5.5V
2.2 to 5.5V
2.2 to 5.5V
2.7 to 5.5V
2.7 to 5.5V
2.7 to 5.5V
1.8 to 5.5V
0°C to 70°C
-40°C to +85°C
-40°C to +125°C
0°C to 70°C
ACE1101E
ACE1101V
ACE1101B
ACE1101BE
ACE1101BV
ACE1101L
-40°C to +85°C
-40°C to +125°C
0°C to 70°C
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3
ACE1101 Product Family Rev. B.2
Preliminary ACE1101/1101B/1101L DC Electrical Characteristics
VCC = 2.2/2.7/1.8 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
Parameter
ConditionsMIN
TYP
MAX
Units
3
ICC
Supply Current –
no data EEPROM write in
progress
1.8V
2.2V
2.7V
3.3V
5.5V
0.2
0.4
0.7
1.2
3.7
0.5
1.0
1.2
2.0
5.5
mA
mA
mA
mA
mA
ICCH
HALT Mode current
3.3V @ -40°C to +25°C
5.5V @ -40°C to +25°C
3.3V @ +85°C
5.5V @ +85°C
3.3V @ +125°C
10
60
75
400
600
1550
100
nA
nA
nA
nA
nA
nA
1000
1000
2500
5000
8000
5.5V @+125°C
4
ICCL
IDLE Mode Current
3.3V
5.5V
150
200
200
300
µA
µA
VCCW
EEPROM Write Voltage
Code EEPROM in
Programming Mode
4.5
2.4
5.0
5.5
V
Data EEPROM in
Operating Mode
5.5
V
SVCC
VIL
Power Supply Slope
1µs/V
10ms/V
0.2VCC
Input Low with Schmitt
Trigger Buffer
VCC = 1.8 -5.5V
VCC = 1.8 - 5.5V
V
V
VIH
Input High with Schmitt
Trigger Buffer
0.8VCC
30
IIP
Input Pull-up Current
TRI-STATE Leakage
Output Low Voltage
G0, G1, G2, G4, G6, G7
G5
VCC =5.5V, VIN =0V
VCC =5.5V
65
2
350
200
µA
ITL
nA
VOL
VCC = 1.8 - 2.2V
0.8 mA sink
0.2VCC
0.2VCC
V
V
1.0 mA sink
Output Low Voltage
G0, G1, G2, G4, G6, G7
G5
VCC = 2.2V – 3.3V
3.0 mA sink
0.2VCC
0.2VCC
V
V
5.0 mA sink
Output Low Voltage
G0, G1, G2, G4, G6, G7
G5
VCC = 3.3V – 5.5V
5.0 mA sink
0.2VCC
0.2VCC
V
V
10.0 mA sink
VOH
Output High Voltage
G0, G1, G2, G4, G6, G7
G5
VCC = 1.8 - 2.2V
0.1 mA source
0.2 mA source
VCC = 3.3V – 5.5V
0.4 mA source
0.8 mA source
VCC = 3.3V – 5.5V
0.4 mA source
1.0 mA source
0.8VCC
0.8VCC
V
V
Output High Voltage
G0, G1, G2, G4, G6, G7
G5
0.8VCC
0.8VCC
V
V
Output High Voltage
G0, G1, G2, G4, G6, G7
G5
0.8VCC
0.8VCC
V
V
3 ICC active current is dependent on the program code.
4 Based on a continuous IDLE looping program.
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4
ACE1101 Product Family Rev. B.2
Preliminary ACE1101/1101B/1101L AC Electrical Characteristics
CC = 2.2/2.7/1.8 to 5.5V
V
All measurements valid for ambient operating temperature range unless otherwise stated.
Parameter
ConditionsMIN
TYP
MAX
Units
Instruction cycle time from
internal clock - setpoint
5.0V at +25°C
0.9
1.0
1.1
µs
%
%
%
Internal clock voltage dependent 3.0V to 5.5V,
frequency variation
+5
+10
+2
constant temperature
Internal clock temperature
dependent frequency variation
3.0V to 5.5V,
full temperature range
Internal clock frequency
deviation for 0.5V drop
3.0V to 4.5V,
constant temperature
Crystal oscillator frequency
External clock frequency
EEPROM write time
(Note 5)
(Note 6)
4
4
MHz
MHz
ms
3
10
2
Internal clock start up time
Oscillator start up time
(Note 6)
(Note 6)
ms
2400
cycles
5 The maximum permissible frequency is guaranteed by design but not 100% tested.
6 The parameter is guaranteed by design but not 100% tested.
Preliminary ACE1101/1101B/1101L Electrical Characteristics for programming
All data following is valid between 4.5V and 5.5V at ambient temperature. The following charac-
teristics are guaranteed by design but are not 100% tested. See "EEPROM write time" in the AC
Electrical Characteristics for definition of the programming ready time.
Parameter
Description
MIN
500
500
100
100
100
900
50
MAX
DC
Units
ns
tHI
CLOCK high time
tLO
CLOCK low time
DC
ns
tDIS
SHIFT_IN setup time
SHIFT_IN hold time
SHIFT_OUT setup time
SHIFT_OUT hold time
LOAD supervoltage timing
LOAD timing
ns
tDIH
ns
tDOS
tDOH
tSV1, tSV2
ns
ns
µs
tLOAD1, tLOAD2, tLOAD3, tLOAD4
VSUPERVOLTAGE
5
µs
Supervoltage level
11.5
12.5
V
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5
ACE1101 Product Family Rev. B.2
Preliminary ACE1101/1101L Low Battery Detect (LBD) Characteristics
VCC = 2.2/1.8 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
ConditionsMIN
TYP
MAX
2.84
2.02
2.98
2.05
3.08
2.12
3.31
2.27
3.36
2.40
Units
LBD Voltage Threshold
Level 1 @ -40°C
V
V
V
V
V
V
V
V
V
V
Level 8 @ -40°C
Level 1 @ 0°C
Level 8 @ 0°C
Level 1 @ +25°C
Level 8 @ +25°C
Level 1 @ +85°C
Level 8 @ +85°C
Level 1 @ +125°C
Level 8 @ +125°C
Preliminary ACE1101 Brown-out Reset (BOR) Characteristics
VCC = 2.2 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
ConditionsMIN
-40°C
TYP
MAX
1.98
2.06
2.12
2.27
2.37
Units
BOR Trigger Threshold
V
V
V
V
V
0°C
+25°C
+85°C
+125°C
Preliminary ACE1101L Brown-out Reset (BOR) Characteristics
VCC = 1.8 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
ConditionsMIN
TYP
MAX
1.78
Units
BOR Trigger Threshold
0°C
V
V
V
+25°C
+70°C
1.82
1.96
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ACE1101 Product Family Rev. B.2
3.0 AC & DC Electrical Characteristic Graphs
Figure 5: RC Oscillator Frequency vs. Temperature (VCC=5.0V)
2.600
2.400
2.200
2.000
1.800
1.600
1.400
1.200
1.000
Avg
Min
Max
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Figure 6: RC Oscillator Frequency vs. Temperature (VCC=2.5V)
1.600
1.400
1.200
1.000
0.800
0.600
Avg
Min
Max
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Figure 7: Internal Oscillator Frequency
Temperature [°C]
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7
ACE1101 Product Family Rev. B.2
Figure 8: Power Supply Rise Time
VCC
VBATT
1V
tS min
tS actual
tS max
time
Name
Parameter
Unit
VCC
Supply Voltage
[V]
[V]
VBATT
tS min
tS actual
tS max
SVCC
Battery Voltage (Nominal Operating Voltage)
Minimum Time for VCC to Rise by 1V
Actual Time for VCC to Rise by 1V
Maximum Time for VCC to Rise by 1V
Power Supply Slope
[ms]
[ms]
[ms]
[ms/V]
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ACE1101 Product Family Rev. B.2
Figure 9: ICC Active
ICC Active (no data EEPROM writes) vs. Temperature
Temperature [°C]
ICC Active (data EEPROM writes) vs. Temperature
Temperature [°C]
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9
ACE1101 Product Family Rev. B.2
Figure 10: HALT Mode Currents
HALT current vs. Temperature
Temperature [°C]
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10
ACE1101 Product Family Rev. B.2
Figure 11: IDLE Mode Currents
IDLE current vs. Temperature
Temperature [°C]
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11
ACE1101 Product Family Rev. B.2
segment of the memory map. This modification improves the
overall code efficiency of the ACEx microcontroller and takes
advantage of the flexibility found on Von Neumann style ma-
chines.
4.0 Arithmetic Controller Core
The ACEx microcontroller core is specifically designed for low
cost applications involving bit manipulation, shifting block encryp-
tion. It is based on a modified Harvard architecture meaning
peripheral,I/O, andRAMlocationsareaddressedseparatelyfrom
instruction data.
4.1 CPU Registers
The ACEx microcontroller has five general-purpose registers.
These registers are the Accumulator (A), X-Pointer (X), Program
Counter (PC), Stack Pointer (SP), and Status Register (SR). The
X, SP, and SR registers are all memory-mapped.
The core differs from the traditional Harvard architecture by
aligningthedataandinstructionmemorysequentially. Thisallows
the X-pointer (11-bits) to point to any memory location in either
Figure 12: Programming Model
7
0
0
0
0
A
8-bit accumulator register
11-bit X pointer register
10-bit program counter
4-bit stack pointer
10
9
X
PC
SP
SR
3
8-bit status register
R 0 0 G Z C H N
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag
GLOBAL Interrupt Mask
READY flag (from EEPROM)
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12
ACE1101 Product Family Rev. B.2
instruction, the address of the instruction is automatically pushed
onto the stack least significant byte first. When the subroutine is
finished, a return from subroutine (RET) instruction is executed.
The RET instruction pulls the previously stacked return address
from the stack and loads it into the program counter. Execution
then continues at the recovered return address.
4.1.1 Accumulator (A)
The Accumulator is a general-purpose 8-bit register that is used
to hold data and results of arithmetic calculations or data manipu-
lations.
4.1.2 X-Pointer (X)
4.1.5 Status Register (SR)
The X-Pointer register allows for an 11-bit indexing value to be
added to an 8-bit offset creating an effective address used for
reading and writing between the entire memory space. (Software
canonlyreadfromcodeEEPROM.)Thisprovidessoftwarewiththe
flexibility of storing lookup tables in the code EEPROM memory
space for the core’s accessibility during normal operation.
This 8-bit register contains four condition code indicators (C, H, Z,
and N), one interrupt masking bit (G), and an EEPROM write flag
(R). In the ACEx microcontroller, condition codes are automati-
cally updated by most instructions. (See Table 10)
Carry/Borrow (C)
The ACEx core allows software to access the entire 11-bit X-
PointerregisterusingthespecialX-pointerinstructions(e.g. LDX,
#000H). (See Table 9) However, software may also access the
registerthroughanyofthememory-mappedinstructionsusingthe
XHI (X[10:8]) and XLO (X[7:0]) variables located at 0xBE and
0xBF, respectively. (See Table 11)
The carry flag is set if the arithmetic logic unit (ALU) performs a carry
or borrow during an arithmetic operation and by its dedicated
instructions. The rotate instruction operates with and through the
carry bit to facilitate multiple-word shift operations. The LDC and
INVCinstructionsfacilitatedirectbitmanipulationusingthecarryflag.
The X register is divided into two sections. The 10 least significant
bits (LSB) of the register is the address of the program or data
memory space. The most significant bit (MSB) of the register is
write only and selects between the data (0x000 to 0x0FF) or
program (0xC00 to 0xFFF) memory space.
Half Carry (H)
Thehalfcarryflagindicateswhetheranoverflowhastakenplaceonthe
boundary between the two nibbles in the accumulator. It is primarily
used for Binary Coded Decimal (BCD) arithmetic calculation.
Zero (Z)
Example: If Bit 10 = 0, then the LD A, [00,X] instruction will take a
value from address range 0x000 to 0x0FF and load it into A. If Bit
10 = 1, then the LD A, [00,X] instruction will take a value from
address range 0xC00 to 0xFFF and load it into A.
The zero flag is set if the result of an arithmetic, logic, or data
manipulation operation is zero. Otherwise, it is cleared.
Negative (N)
The X register can also serve as a counter or temporary storage
register. However, this is true only for the 10-LSBs since the 11th
bit is dedicated for memory space selection.
The negative flag is set if the MSB of the result from an arithmetic,
logic, or data manipulation operation is set to one. Otherwise, the
flag is cleared. A result is said to be negative if its MSB is a one.
4.1.3 Program Counter (PC)
Interrupt Mask (G)
The 10-bit program counter register contains the address of the
next instructionto beexecuted. Afterareset, ifinnormal modethe
program counter is initialized to 0xC00.
The interrupt request mask (G) is a global mask that disables all
maskable interrupt sources. If the G Bit is cleared, interrupts can
become pending, but the operation of the core continues uninter-
rupted. However, if the G Bit is set an interrupt is recognized. After any
reset, the G bit is cleared by default and can only be set by a software
instruction. When an interrupt is recognized, the G bit is cleared after
thePCisstackedandtheinterruptvectorisfetched.Oncetheinterrupt
is serviced, a return from interrupt instruction is normally executed to
restore the PC to the value that was present before the interrupt
occurred. The G bit is reset to one after a return from interrupt is
executed. Although the G bit can be set within an interrupt service
routine,“nesting”interruptsinthiswayshouldonlybedonewhenthere
is a clear understanding of latency and of the arbitration mechanism.
4.1.4 Stack Pointer (SP)
The ACEx microcontroller has an automatic program stack with a 4-
bit stack pointer. The stack can be initialized to any location between
addresses0x30-0x3F.Normally,thestackpointerisinitializedbyone
of the first instructions in an application program. After a reset, the
stack pointer is defaulted to 0xF pointing to address 0x3F.
Thestackisconfiguredasadatastructurewhichdecrementsfrom
high to low memory. Each time a new address is pushed onto the
stack, the core decrements the stack pointer by two. Each time an
address is pulled from the stack, the core increments the stack
pointer is by two. At any given time, the stack pointer points to the
next free location in the stack.
4.2 Interrupt handling
When an interrupt is recognized, the current instruction com-
pletes its execution. The return address (the current value in the
program counter) is pushed onto the stack and execution contin-
When a subroutine is called by a jump to subroutine (JSR)
Table 8: Interrupt Priority Sequence
Priority (4 highest, 1 lowest)
Interrupt
4
3
2
1
MIW
(EDGEI)
(TMRI0)
(TMRI1)
(INTR)
Timer0
Timer1
Software
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13
ACE1101 Product Family Rev. B.2
ues at the address specified by the unique interrupt vector (see
Table 11). This process takes five instruction cycles. At the end
of the interrupt service routine, a return from interrupt (RETI)
instruction is executed. The RETI instruction causes the saved
address to be pulled off the stack in reverse order. The G bit is
set and instruction execution resumes at the return address.
modecanbeusedtoaddresseitherdataorprogrammemoryspace.
Indirect
TheinstructionallowstheX-pointertoaddressanylocationwithin
the data memory space.
Direct
The ACEx microcontroller is capable of supporting four interrupts.
Three are maskable through the G bit of the SR and the fourth
(softwareinterrupt)isnotinhibitedbytheGbit(seeFigure13).The
software interrupt instruction is generated by the execution of the
INTR instruction. once the INTR instruction is executed, the ACEx
corewillinterruptwhethertheGbitissetornot. TheINTRinterrupt
is executed in the same manner as the other maskable interrupts
where the program counter register is stacked and the G bit is
cleared. This means, if the G bit was enabled prior to the software
interrupt the RETI instruction must be used to return from interrupt
in order to restore the G bit to its previous state. However, if the G
bit was not enabled prior to the software interrupt the RET
instruction must be used.
The instruction contains an 8-bit address field that directly points
to the data memory space as an operand.
Immediate
The instruction contains an 8-bit immediate field as an operand.
Inherent
This instruction has no operands associated with it.
Absolute
The instruction contains a 10-bit address that directly points to a
location in the program memory space. There are two operands
associated with this addressing mode. Each operand contains a
byteofanaddress.Thismodeisusedonlyforthelongjump(JMP)
and JSR instructions.
In case of multiple interrupts occurring at the same time, the ACEx
microcontroller core has prioritized the interrupts. The interrupt
priority sequence in shown in Table 8.
Relative
4.3 Addressing Modes
This mode is used for the short jump (JP) instructions where the
operand is a value relative to the current PC address. With this
instruction, software is limited to the number of bytes it can jump,
-31 or +32.
The ACEx microcontroller has seven addressing modes indexed,
indirect, direct, immediate, absolute jump, and relative jump.
Indexed
The instruction allows an 8-bit unsigned offset value to be added to
the 10-LSBs of the X-pointer yielding a new effective address. This
Figure 13: Basic Interrupt Structure
INTR
T1PND
T1
T0PND
T0
Interrupt
WKPND
MIW
Interrupt
Pending
Flags
T0INT
EN
WKINT
EN
G
T1EN
Global Interrupt
Enable
Interrupt Enable Bits
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14
ACE1101 Product Family Rev. B.2
Table 9: Instruction Addressing Modes
Instruction
Immediate
Direct
Indexed
Indirect
Inherent
Relative Absolute
ADC
ADD
AND
OR
A, #
A, M
A, M
A, M
A, M
A, M
A, M
A, [X]
A, [X]
A, [X]
A, [X]
A, [X]
A, [X]
A, #
A, #
A, #
A, #
A, #
SUBC
XOR
CLR
INC
M
M
M
A
A
A
X
X
X
DEC
IFEQ
IFGT
IFNE
IFLT
A, #
A, #
A, #
X, #
X, #
M,#
A, M
A, M
A, M
A, [X]
A, [X]
A, [X]
X, #
SC
no-op
no-op
no-op
no-op
no-op
RC
IFC
IFNC
INVC
LDC
STC
#, M
#, M
RLC
RRC
M
M
A
A
LD
ST
LD
A, #
#, A
X, #
M, #
A, M
A, M
M, M
A, [00,X]
A, [00,X]
A, [X]
A, [X]
NOP
no-op
IFBIT
SBIT
RBIT
#, M
#, M
#, M
#, [X]
#, [X]
JP
Rel
JSR
JMP
RET
RETI
INTR
M
M
no-op
no-op
no-op
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15
ACE1101 Product Family Rev. B.2
Table 10: Instruction Cycles and Bytes
Mnemonic Operand BytesCycles Flags
Mnemonic Operand BytesCycles Flags
affected
affected
ADC
ADC
ADC
ADD
ADD
ADD
AND
AND
AND
CLR
CLR
CLR
DEC
DEC
DEC
IFBIT
IFBIT
IFC
A, [X]
A, M
A, #
A, [X]
A, M
A, #
A, [X]
A, #
A, M
X
1
2
2
1
2
2
1
2
2
1
1
2
1
2
1
1
2
1
1
2
2
3
3
2
1
2
3
2
1
2
3
1
1
2
1
1
1
1
2
2
1
2
2
1
2
2
1
1
1
1
2
1
1
2
1
1
2
2
3
3
2
1
2
3
2
1
2
3
1
1
2
1
5
1
C,H,Z,N
C,H,Z,N
C,H,Z,N
Z,N
JMP
JP
M
3
1
3
2
2
1
2
3
3
2
3
1
2
1
2
1
2
1
1
1
1
2
1
2
1
2
1
2
1
2
2
2
1
2
2
1
2
4
1
5
2
3
1
2
3
3
2
3
1
2
1
2
2
2
1
5
5
1
2
1
2
2
2
1
3
1
2
2
2
1
2
2
1
2
None
None
None
None
None
None
None
None
None
C
JSR
LD
M
A, #
Z,N
LD
A, [00,X]
A, [X]
A, M
M, #
X, #
Z,N
LD
Z,N
LD
Z,N
LD
Z,N
LD
Z
LDC
LD
#, M
M, M
A
Z,N,C,H
Z,N,C,H
Z,N
None
None
Z,N
M
NOP
OR
A
A, #
M
Z,N
OR
A, [X]
A, M
#, [X]
#, M
Z,N
X
Z
OR
Z,N
#, A
#, M
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,N
RBIT
RBIT
RC
Z,N
Z,N
C,H
IFEQ
IFEQ
IFEQ
IFEQ
IFEQ
IFGT
IFGT
IFGT
IFGT
IFNE
IFNE
IFNE
IFLT
IFNC
INC
A, [X]
A, #
RET
RETI
RLC
RLC
RRC
RRC
SBIT
SBIT
SC
None
None
C,Z,N
C,Z,N
C,Z,N
C,Z,N
Z,N
A, M
M, #
X, #
A
M
A
A, #
M
A, [X]
A, M
X, #
#, [X]
#, M
Z,N
C,H
A, #
ST
A, [00,X]
A, [X]
A, M
None
None
None
Z,N
A, [X]
A, M
X, #
ST
ST
STC
SUBC
SUBC
SUBC
XOR
XOR
XOR
#, M
A, #
C,H,Z,N
C,H,Z,N
C,H,Z,N
Z,N
A
M
X
A, [X]
A, M
INC
Z,N
INC
Z
A, #
INTR
INVC
None
C
A, [X]
A, M
Z,N
Z,N
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16
ACE1101 Product Family Rev. B.2
4.4 Memory Map
All I/O ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory space.
Table 11: Memory Map
Address
0x00 - 0x3F
0x40 - 0x7F
0xAA
Memory Space
Data
Block
SRAM
EEPROM
Timer1
Timer1
Timer1
Timer1
Timer1
MIW
Contents
Data RAM
Data
Data EEPROM
Data
T1RALO register
T1RAHI register
TMR1LO register
TMR1HI register
T1CNTRL register
WKEDG register
WKPND register
WKEN register
0xAB
Data
0xAC
Data
0xAD
Data
0xAE
Data
0xAF
Data
0xB0
Data
MIW
0xB1
Data
MIW
0xB2
Data
I/O
PORTGD register
PORTGC register
PORTGP register
WDSVR register
T0CNTRL register
HALT mode register
Reserved
0xB3
Data
I/O
0xB4
Data
I/O
0xB5
Data
Timer0
Timer0
Clock
0xB6
Data
0xB7
Data
0xB8 - 0xBC
0xBD
Data
Data
LBD
Core
LBD register
0xBE
XHI register
0xBF
Data
Core
XLO register
0xC0
Data
Core
Power mode clear (PMC) register
SP register
0xCE
Data
Core
0xCF
Data
Core
Status register (SR)
Code EEPROM
Timer0 Interrupt vector
Timer1 Interrupt vector
MIW Interrupt vector
Software Interrupt vector
Reserved
0xC00 - 0xFF5
0xFF6 - 0xFF7
0xFF8 - 0xFF9
0xFFA - 0xFFB
0xFFC - 0xFFD
0xFFE - 0xFFF
Program
Program
Program
Program
Program
EEPROM
Core
Core
Core
Core
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17
ACE1101 Product Family Rev. B.2
4.5 Memory
4.6 Initialization Registers
The ACEx microcontroller device has 64 bytes of SRAM and 64
bytes of EEPROM available for data storage. The device also has
1KbytesofEEPROMforprogramstorage. Softwarecanreadand
writetoSRAManddataEEPROMbutcanonlyreadfromthecode
EEPROM. While in normal mode, the code EEPROM is protected
from any writes. The code EEPROM can only be rewritten when
the device is in program mode and if the write disable (WDIS) bit
of the initialization register is not set to 1.
The ACEx microcontroller has two 8-bit wide initialization regis-
ters. These registers are read from the memory space on power-
up to initialize certain on-chip peripherals. Figure 14 provides a
detailed description of Initialization Register 1. The Initialization
Register 2 is used to trim the internal oscillator to its appropriate
frequency. This register is pre-programmed in the factory to yield
an internal instruction clock of 1MHz.
Both Initialization Registers 1 and 2 can be read from and written
to during programming mode. However, re-trimming the internal
oscillator (writing to the Initialization Register 2) once it has left the
factory is discouraged.
While in normal mode, the user can write to the data EEPROM
array by 1) polling the ready (R) flag of the SR, then 2) executing
the appropriate instruction. If the R flag is 1, the data EEPROM
block is ready to perform the next write. If the R flag is 0, the data
EEPROM is busy. The data EEPROM array will reset the R flag
after the completion of a write cycle. Attempts to read, write, or
enter HALT/IDLE mode while the data EEPROM is busy (R = 0)
can affect the current data being written.
Figure 14: Initialization Register 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMODE[0]
CMODE[1]
WDEN
BOREN
BLSEL 9
UBD 7,8
WDIS 7,8
RDIS 7,8
(0) RDIS 7,8
(1) WDIS 7,8
(2) UBD 7,8
(3) BLSEL 9
If set, disables attempts to read the contents from the memory while in programming mode
If set, disables attempts to write new contents to the memory while in programming mode
If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)
If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for the ACE1101
If not set, the BOR voltage reference level is set to its lower range for the ACE1101L
(4) BOREN
If set, allows a BOR to occur if VCC falls below the voltage reference level
If set, enables the on-chip processor watchdog circuit
Clock mode select bit 1 (See Table 17)
(5) WDEN
(6) CMODE[1]
(7) CMODE[0]
Clock mode select bit 0 (See Table 17)
7 If both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode.
8 If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.
9 The BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain BLSEL set value.
www.fairchildsemi.com
18
ACE1101 Product Family Rev. B.2
The timer can be started or stopped through the T1CNTRL
register bit T1C0. When running, the timer counts down (decre-
ments) every clock cycle. Depending on the operating mode, the
timer’s clock is either the instruction clock or a transition on the T1
input. In addition, occurrences of timer underflow (transitions from
0x0000 to 0xFFFF/T1RA value) can either generate an interrupt
and/or toggle the T1 output pin.
5.0 Timer 1
Timer 1 is a versatile 16-bit timer that can operate in one of three
modes:
• Pulse Width Modulation (PWM) mode, which generates
pulses of a specified width and duty cycle
• External Event Counter mode, which counts occurrences
of an external event
Timer 1’s interrupt (TMRI1) can be enabled by interrupt enable
(T1EN) bit in the T1CNTRL register. When the timer interrupt is
enabled, depending on the operating mode, the source of the
interrupt is a timer underflow and/or a timer capture.
• Standard Input Capture mode, which measures the
elapsed time between occurrences of external events
Timer 1 contains a 16-bit timer/counter register (TMR1), a 16-bit
auto-reload/capture register (T1RA), and an 8-bit control register
(T1CNTRL). All register are memory-mapped for simple access
through the core with both the 16-bit registers organized as a pair
of8-bitregisterbytes{TMR1HI,TMR1LO}and{T1RAHI,T1RALO}.
Depending on the operating mode, the timer contains an external
input or output (T1) that is multiplexed with the I/O pin G2. By
default, the TMR1 is reset to 0xFFFF, T1RA is reset to 0x0000,
and T1CNTRL is reset to 0x00.
5.1 Timer control bits
Reading and writing to the T1CNTRL register controls the timer’s
operation. By writing to the control bits, the user can enable or
disable the timer interrupts, set the mode of operation, and start or
stop the timer. The T1CNTRL register bits are described in Tables
12 and 13.
Table 12: TIMER1 Control Register Definition (T1CNTRL)
T1CNTRL Register
Name
T1C3
T1C2
T1C1
T1C0
Function
Bit 7
Bit 6
Bit 5
Bit 4
Timer TIMER1 control bit 3 (see Table 13)
Timer TIMER1 control bit 2 (see Table 13)
Timer TIMER1 control bit 1 (see Table 13)
Timer TIMER1 run: 1 = Start timer, 0 = Stop timer;
or Timer TIMER1 underflow interrupt pending flag
in input capture mode
Bit 3
Bit 2
T1PND
T1EN
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Bit 1
Bit 0
-----------
-----------
Reserved
Reserved
Table 13: TIMER1 Operating Mode Selection
T1
C3
T1
C2
T1
C1
Timer Mode
Interrupt A
Source
Timer Counts On
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
0
1
MODE 2
MODE 2
TIMER1 Underflow
TIMER1 Underflow
Autoreload T1RA
Autoreload T1RA
Pos. T1 Edge
T1 Pos. Edge
T1 Neg. Edge
MODE 1 T1 Toggle
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
MODE 1 No T1 Toggle
MODE 3 Captures: T1 Pos. edge
MODE 3 Captures: T1 Neg. Edge
Neg. T1 Edge
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19
ACE1101 Product Family Rev. B.2
1. Configure T1 as an output by setting bit 2 of PORTGC.
SBIT 2, PORTGC ; Configure G2 as an output
5.2 Mode1:PulseWidthModulation(PWM)Mode
-
In the PWM mode, the timer counts down at the instruction clock
rate. When an underflow occurs, the timer register is reloaded from
T1RAandthecountdownproceedsfromtheloadedvalue.Atevery
underflow, a pending flag (T1PND) located in the T1CNTRL regis-
ter is set. Software must then clear the T1PND flag and load the
T1RA register with an alternate PWM value. In addition, the timer
can be configured to toggle the T1 output bit upon underflow.
Configuring the timer to toggle T1 results in the generation of a
signal outputted from port G2 with the width and duty cycle
controlled by the values stored in the T1RA. A block diagram of the
timer’s PWM mode of operation is shown in Figure 15.
2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of
PORTGD.
-
SBIT 2, PORTGD
; Set G2 high
3. Load the initial PWM high (low) time into the timer register.
-
-
LD TMR1LO, #6FH
LD TMR1HI, #05H
; High (Low) for 1.391ms
(1MHz clock)
4. Load the PWM low (high) time into the T1RA register.
-
LD T1RALO, #2FH
; Low (High) for .303ms
(1MHz clock)
-
LD T1RAHI, #01H
The timer has one interrupt (TMRI1) that is maskable through the
T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit of
the SR is set. If interrupts are enabled, the timer will generate an
interrupt each time T1PND flags is set (whenever the timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
5. Write the appropriate control value to the T1CNTRL
register to select PWM mode with T1 toggle, to clear the
enable bit and pending flag, and to start the timer. (See
Table 12 and Table 13)
-
LD T1CNTRL, #0B0H
; Setting the T1C0 bit starts
the timer
6. After every underflow, load T1RA with alternate values. If
the user wishes to generate an interrupt on a T1 output
transition, reset the pending flags and then enable the
interrupt using T1EN. The G bit must also be set. The
interrupt service routine must reset the pending flag and
perform whatever processing is desired.
The interrupt will be synchronous with every rising and falling edge
oftheT1outputsignal.Generatinginterruptsonlyonrisingorfalling
edgesofT1isachievablethroughappropriatehandlingoftheT1EN
bit or T1PND flag through software.
The following steps show how to properly configure Timer 1 to
operate in the PWM mode. For this example, the T1 output signal
is toggled with every timer underflow and the “high” and “low” times
for the T1 output can be set to different values. The T1 output signal
can start out either high or low depending on the configuration of
G2; the instructions below are for starting with the T1 output high.
Follow the instructions in parentheses to start the T1 output low.
-
-
RBIT T1PND, T1CNTRL
LD T1RALO, #6FH
; T1PND equals 3
; High (Low) for 1.391ms
(1MHz clock)
-
LD T1RAHI, #05H
Figure 15: Pulse Width Modulation Mode Block Diagram
16-bit Auto-Reload
Register (T1RA)
Underflow
Interrupt
Data
Bus
Data
Latch
16-bit Timer (TMR1)
T1
Instruction
Clock
www.fairchildsemi.com
20
ACE1101 Product Family Rev. B.2
the instructions in parentheses to clock the counter every rising
edge.
5.3 Mode 2: External Event Counter Mode
The External Event Counter mode operates similarly to the PWM
mode; however, the timer is not clocked by the instruction clock
but by transitions of the T1 input signal. The edge is selectable
through the T1C1 bit of the T1CNTRL register. A block diagram of
the timer’s External Event Counter mode of operation is shown in
Figure 16.
1. Configure T1 as an input by clearing bit 2 of PORTGC.
-
RBIT 2, PORTGC
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
SBIT 2, PORTGD ; Set G2 high
3. Enable the global interrupt enable bit.
SBIT 4, STATUS
; Configure G2 as an input
-
-
The T1 input should be connected to an external device that
generates a positive/negative-going pulse for each event. By
clocking the timer through T1, the number of positive/negative
transitions can be counted therefore allowing software to capture
the number of events that occur. The input signal on T1 must have
a pulse width equal to or greater than one instruction clock cycle.
4. Load the initial count into the TMR1 and T1RA registers.
When the number of external events is detected, the counter
will reach zero; however, it will not underflow until the next
event is detected. To count N pulses, load the value N-1 into
the registers. If it is only necessary to count the number of
occurrences and no action needs to be taken at a particular
count, load the value 0xFFFF into the registers.
The counter can be configured to sense either positive-going or
negative-goingtransitionsontheT1pin. Themaximumfrequency
at which transitions can be sensed is one-half the frequency of the
instruction clock.
-
-
-
-
LD TMR1LO, #0FFH
LD TMR1HI, #00H
LD T1RALO, #0FFH
LD T1RAHI, #00H
As with the PWM mode, when the counter underflows the counter
is reloaded from the T1RA register and the count down
proceedsfrom the loaded value. At every underflow, a pending
flag (T1PND) located in the T1CNTRL register is set. Software
must then clear the T1PND flag and can then load the T1RA
register with an alternate value.
5. Write the appropriate control value to the T1CNTRL register
to select External Event Counter mode, to clock every falling
edge, to set the enable bit, to clear the pending flag, and to
start the counter. (See Table 12 and Table 13)
-
LD T1CNTRL, #34H (#00h) ; Setting the T1C0 bit
starts the timer
The counter has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit
of the SR is set. If interrupts are enabled, the counter will generate
an interrupt each time the T1PND flag is set (whenever timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
6. When the counter underflows, the interrupt service routine
must clear the T1PND flag and take whatever action is
required once the number of events occurs. If the software
wishes to merely count the number of events and the
anticipated number may exceed 65,536, the interrupt service
routine should record the number of underflows by
incrementing a counter in memory. Software can then
calculate the correct event count.
The following steps show how to properly configure Timer 1 to
operateintheExternalEventCountermode.Forthisexample,the
counter is clocked every falling edge of the T1 input signal. Follow
-
RBIT T1PND, T1CNTRL
; T1PND equals 3
Figure 16: External Event Counter Mode Block Diagram
16-bit Auto-Reload
Register (T1RA)
Data
Bus
Underflow
Interrupt
16-bit Counter (TMR1)
T1
Edge Selector
Logic
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21
ACE1101 Product Family Rev. B.2
input capture mode even while the timer is running. This feature
allows you to measure the width of a pulse received on an input pin.
5.4 Mode 3: Input Capture Mode
IntheInputCapturemode,thetimerisusedtomeasureelapsedtime
betweenedgesofaninputsignal.Oncethetimerisconfiguredforthis
mode, the timer starts counting down immediately at the instruction
clockrate.TheTimer1willthentransferthecurrentvalueoftheTMR1
register into the T1RA register as soon as the selected edge of T1 is
sensed. The input signal on T1 must have a pulse width equal to or
greater than one instruction clock cycle. At every T1RA capture,
software can then store the values into RAM to calculate the elapsed
time between edges on T1. At any given time (with proper consider-
ation of the state of T1) the timer can be configured to capture on
positive-going or negative-going edges. A block diagram of the
timer’s Input Capture mode of operation is shown in Figure 17.
For example, the T1 pin can be programmed to be sensitive to a
positive-going edge. When the positive edge is sensed, the TMR1
register contents is transferred to the T1RA register and a Timer 1
interrupt is generated. The Timer 1 interrupt service routine records
the contents of the T1RA register, changes the edge sensitivity from
positivetonegative-goingedge,andclearstheT1PNDflag.Whenthe
negative-goingedgeissensedanotherTimer1interruptisgenerated.
The interrupt service routine reads the T1RA register again. The
difference between the previous reading and the current reading
reflects the elapsed time between the positive edge and negative
edge of the T1 input signal i.e. the width of the positive-going pulse.
The timer has one interrupt (TMRI1) that is maskable through the
T1EN bit of the T1CNTRL register. However, the core is only
interruptediftheT1ENbitandtheG(GlobalInterruptenable)bitofthe
SR is set. The Input Capture mode contains two interrupt pending
flags 1) the TMR1 register capture in T1RA (T1PND) and 2) timer
underflow (T1C0). If interrupts are enabled, the timer will generate an
interrupteachtimeapendingflagisset(providedthatthependingflag
was previously cleared.) The interrupt service routine is responsible
for proper handling of the T1PND flag, T1C0 flag, and the T1EN bit.
Remember that the Timer1 interrupt service routine must test the
T1C0andT1PNDflagstodeterminethecauseoftheinterrupt.Ifthe
T1C0 flag caused the interrupt, the interrupt service routine should
record the occurrence of an underflow by incrementing a counter in
memory or by some other means. The software that calculates the
elapsed time between captures should take into account the
number of underflow that occurred when making its calculation.
The following steps show how to properly configure Timer 1 to
operate in the Input Capture mode.
For this operating mode, the T1C0 control bit serves as the timer
underflow interrupt pending flag. The Timer 1 interrupt service
routine must read both the T1PND and T1C0 flags to determine the
causeoftheinterrupt. AsetT1C0flagmeansthatatimerunderflow
occurred whereas a set T1PND flag means that a capture occurred
in T1RA. It is possible that both flags will be found set, meaning that
botheventsoccurredatthesametime.Theinterruptserviceroutine
should take this possibility into consideration.
1. Configure T1 as an input by clearing bit 2 of PORTGC.
-
RBIT 2, PORTGC
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
SBIT 2, PORTGD ; Set G2 high
3. Enable the global interrupt enable bit.
SBIT 4, STATUS
; Configure G2 as an input
-
-
4. With the timer stopped, load the initial time into the TMR1
register (typically the value is 0xFFFF.)
Because the T1C0 bit is used as the underflow interrupt pending
flag,itisnotavailableforuseasastart/stopbitasintheothermodes.
-
-
LD TMR1LO, #0FFH
LD TMR1HI, #00H
The TMR1 register counts down continuously at the instruction
clock rate starting from the time that the input capture mode is
selected. (See Table 12and Table 13) To stop the timer from
running, you must change the mode to an alternate mode (PWM
or External Event Counter) while resetting the T1C0 bit.
5. Write the appropriate control value to the T1CNTRL register
to select Input Capture mode, to sense the appropriate edge,
to set the enable bit, and to clear the pending flags. (See
Table 12 and Table 13)
-
LD T1CNTRL, #64H
; T1C1 is the edge select bit
The input pins can be independently configured to sense positive-
going or negative-going transitions. The edge sensitivity of pin T1
is controlled by bit T1C1 as indicated in Table 13.
6. As soon as the input capture mode is enabled, the timer
starts counting. When the selected edge is sensed on T1,
the T1RA register is loaded and a Timer 1 interrupt is
triggered.
The edge sensitivity of a pin can be changed without leaving the
Figure 17: Input Capture Mode Block Diagram
Capture
Interrupt
16-bit Input Capture
Register (T1RA)
T1
Edge Selector
Logic
Data
Bus
Underflow
Interrupt
16-bit Timer (TMR1)
Instruction
Clock
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22
ACE1101 Product Family Rev. B.2
reset by software or system reset.
6.0 Timer 0
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt
block. See Section 8 for details.
Timer 0 is a 12-bit free running idle timer. Upon power-up or any
reset, the timer is reset to 0x000 and then counts up continuously
based on the instruction clock of 1MHz (1 µs). Software cannot
read from or write to this timer. However, software can monitor the
timer’s pending (T0PND) bit that is set every 8192 cycles (initially
4096 cycles after a reset). The T0PND flag is set every other time
the timer overflows (transitions from 0xFFF to 0x000) through a
divide-by-2circuit.Afteranoverflow,thetimerwillresetandrestart
its counting sequence.
7.0 Watchdog
The Watchdogtimerisused to resetthedevice and safelyrecover
in the rare event of a processor “runaway condition.” The 12-bit
Timer0isusedasapre-scalerforWatchdogtimer.TheWatchdog
timer must be serviced before every 61,440 cycles but no sooner
than 4096 cycles since the last Watchdog reset. The Watchdog is
serviced through software by writing the value 0x1B to the
Watchdog Service (WDSVR) register (see Figure 19). The part
resets automatically if the Watchdog is serviced too frequent, or
not frequent enough.
Software can either poll the T0PND bit or vector to an interrupt
subroutine. In order to interrupt on a T0PND, software must be
sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the
Timer 0 control (T0CNTRL) register and also make sure the G bit
is set in SR. Once the timer interrupt is serviced, software should
reset the T0PND bit before exiting the routine. Timer 0 supports
the following functions:
The Watchdog timer must be enabled through the Watchdog
enable bit (WDEN) in the initialization register. The WDEN bit can
onlybesetwhilethedeviceisinprogrammingmode.Onceset,the
Watchdog will always be powered-up enabled. Software cannot
disable the Watchdog. The Watchdog timer can only be disabled
in programming mode by resetting the WDEN bit as long as the
memory write protect (WDIS) feature is not enabled.
1. Exiting from IDLE mode (See Section 16.0 for details.)
2. Start up delay from HALT mode
3. Watchdog pre-scaler (See Section 7.0 for details.)
The T0INTEN bit is a read/write bit. If set to 0, interrupt requests
from the Timer 0 are ignored. If set to 1, interrupt requests are
accepted. Upon reset, the T0INTEN bit is reset to 0.
WARNING
Ensure that the Watchdog timer has been serviced before enter-
ing IDLE mode because it remains operational during this time.
TheT0PNDbitisaread/writebit.Ifsetto1,itindicatesthataTimer
0 interrupt is pending. This bit is set by a Timer 0 overflow and is
Figure 18: Timer 0 Control Register Definition (T0CNTRL)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WKINTEN
x
x
x
x
x
T0PND
T0INTEN
Figure 19: Watchdog Server Register (WDSVR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
1
1
www.fairchildsemi.com
23
ACE1101 Product Family Rev. B.2
6. Set the WKEN bits associated with the pins to be used, thus
enabling those pins for the Wakeup/Interrupt function.
8.0 Multi-Input Wakeup/interrupt Block
The Multi-Input Wakeup (MIW)/Interrupt contains three memory-
mapped registers associated with this circuit: WKEDG (Wakeup
Edge), WKEN (Wakeup Enable), and WKPND (Wakeup Pending).
Eachregisterhas8-bitswitheachbitcorrespondingtoaninputpinsas
showninFigure20.Allthreeregistersareinitializedtozerouponreset.
-
LD WKEN, #10H
; Enabling G4
Once the Multi-Input Wakeup/Interrupt function has been config-
ured, a transition sensed on any of the I/O pins will set the
corresponding bit in the WKPND register. The WKPND bits , where
thecorrespondingenable(WKEN)bitsareset, willbringthedevice
out of the HALT/IDLE mode and can also trigger an interrupt if
interrupts are enabled. The interrupt service routine can read the
WKPND register to determine which pin sensed the interrupt.
TheWKEDGregisterestablishestheedgesensitivityforeachofthewake-
up input pin: either positive going-edge (0) or negative-going edge (1).
The WKEN register enables (1) or disables (0) each of the port
pins for the Wakeup/Interrupt function. The wakeup I/Os used for
theWakeup/Interruptfunctionmustalsobeconfiguredasaninput
pin in its associated port configuration register. However, an
interrupt of thecore willnot occurunlessinterruptsareenabled for
the blockviabit 7ofthe T0CNTRLregister(seeFigure18) andthe
G (global interrupt enable) bit of the SR is set.
The interrupt service routine or other software should clear the
pending bit. The device will not enter HALT/IDLE mode as long as
a WKPND pending bit is pending and enabled. The user has the
responsibility of clearing the pending flags before attempting to
enter the HALT/IDLE mode.
Upon reset, the WKEDG register is configured to select positive-
going edge sensitivity for all wakeup inputs. If the user wishes to
change the edge sensitivity of a port pin, use the following proce-
dure to avoid false triggering of a Wakeup/Interrupt condition.
The WKPND register contains the pending flags corresponding to
each of the port pins (1 for wakeup/interrupt pending, 0 for
wakeup/interrupt not pending).
TousetheMulti-InputWakeup/Interruptcircuit,performthestepslisted
below. Performing the steps in the order shown will prevent false
triggering of a Wakeup/Interrupt condition. This same procedure
should be used following any type of reset because the wakeup inputs
areleftfloatingafterresetsresultinginunknowndataontheportinputs.
1. Clear the WKEN bit associated with the pin to disable that pin.
2. Write the WKEDG register to select the new type of edge
sensitivity for the pin.
3. Clear the WKPND bit associated with the pin.
4. Set the WKEN bit associated with the pin to re-enable it.
1. Clear the WKEN register.
PORTG provides the user with three fully selectable, edge sensi-
tive interrupts that are all vectored into the same service subrou-
tine. The interrupt from PORTG shares logic with the wakeup
circuitry. The WKEN register allows interrupts from PORTG to be
individually enabled or disabled. The WKEDG register specifies
the trigger condition to be either a positive or a negative edge. The
WKPND register latches in the pending trigger conditions.
-
CLR WKEN
2. If necessary, write to the port configuration register to select
the desired port pins to be configured as inputs.
-
RBIT 4, PORTGC
; G4
3. If necessary, write to the port data register to select the
desired port pins input state.
-
SBIT 4, PORTGD
; Pull-up
Since PORTG is also used for exiting the device from the HALT/IDLE
mode,theusercanelecttoexittheHALT/IDLEmodeeitherwithorwithout
the interrupt enabled. If the user elects to disable the interrupt, then the
device restarts execution from the point at which it was stopped (first
instruction cycle of the instruction following HALT/IDLE mode entrance
instruction). In the other case, the device finishes the instruction that was
being executed when the part was stopped and then branches to the
interrupt service routine. The device then reverts to normal operation.
4. Write the WKEDG register to select the desired type of edge
sensitivity for each of the pins used.
-
LD WKEDG, #0FFH
5. Clear the WKPND register to cancel any pending bits.
CLR WKPND
; All negative-going edges
-
Figure 20: Multi-input Wakeup (MIW) Register Definition
WKEDG, WKEN, WKPND
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10G7
10G6
G5
G4
G3
G2
G1
G0
10 Available only on the 14-pin package option
Figure 21: Multi-input Wakeup (MIWU) Block Diagram
Data Bus
7
0
WKEN[7:0]
0
G0
G7
WKOUT
EDGEI
7
WKINTEN11
WKEDG[0:7]
WKPND[0:7]
11 WKINTEN: Bit 7 of T0CNTRL
www.fairchildsemi.com
24
ACE1101 Product Family Rev. B.2
(PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0or as anoutputby writinga 1to itscorresponding PORTGC bit.
If a pin is configured as an output, its PORTGD bit represents the
state of the pin (1 = logic high, 0 = logic low). If the pin is configured
as an input, its PORTGD bit selects whether the pin is a weak pull-
uporahigh-impedenceinput. Table14providesdetailsoftheport
configuration options. The port configuration and data registers
can both be read from or written to. Reading PORTGP returns the
value of the port pins regardless of how the pins are configured.
Since this device supports MIW, PORTG inputs have Schmitt
triggers.
9.0 I/O Port
ThesixI/Opins(eighton14-pinpackageoption)arebi-directional
(see Figure 22) with the exception of G3 which is always an input
with weak pull-up. The bi-directional I/O pins can be individually
configured by software to operate as high-impedance inputs, as
inputs with weak pull-up, or as push-pull outputs. The operating
stateisdeterminedbythecontentsofthecorrespondingbitsinthe
dataandconfigurationregisters.Eachbi-directionalI/Opincanbe
used for general purpose I/O, or in some cases, for a specific
alternate function determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G7) have three memory-mapped port registers
associated with the I/O circuitry: a port configuration register
Figure 22: PORTG Logic Diagram
GXPULLEN
GXBUFEN
GXOUT
PADGX
GXIN
Figure 23: I/O Register bit assignments (PORTGC, PORTGD, PORTGD)
PORTGC, PORGD, PORTGD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G712
G612
G5
G4
G313
G2
G1
G0
12 Available only on the 14-pin package option
13 G3 is always an input with weak pull-up.
Table 14: I/O configuration options
Configuration Bit
Data Bit
Port Pin Configuration
0
0
1
1
0
1
0
1
High-impedence input (TRI-STATE input)
Input with pull-up (weak one input)
Push-pull zero output
Push-pull one output
www.fairchildsemi.com
25
ACE1101 Product Family Rev. B.2
10.0 In-circuit Programming Specification14, 15
The ACEx microcontroller supports in-circuit programming of the
internal data EEPROM, code EEPROM, and the initialization regis-
ters. AnexternallycontrolledfourwireinterfaceconsistingofaLOAD
control pin (G3), a serial data SHIFT-IN input pin (G4), a serial data
SHIFT-OUToutputpin(G2),andaCLOCKpin(G1)isusedtoaccess
the on-chip memory locations. Communication between the ACEx
microcontroller and the external programmer is made through a 32-
bit command and response word described in Table 15.
0V phase (if the timing specifications in Figure 24 are obeyed).
The device will set the R bit of the Status register when the write
operation has completed. The external programmer must wait for
the SHIFT_OUT pin to go high before bringing the LOAD signal to
5V to initiate a normal command cycle.
10.2 Read Sequence
Whenreadingthedeviceafterawrite,theexternalprogrammermust
set the LOAD signal to 5V before it sends the new command word.
Next, the 32-bit serial command word (for during a READ) should be
shifted into the device using the SHIFT_IN and the CLOCK signals
while the data from the previous command is serially shifted out on
the SHIFT_OUT pin. After the Read command has been shifted into
thedevice,theexternalprogrammermust,onceagain,settheLOAD
signal to 0V and apply two clock pulses as shown in Figure 24 to
complete READ cycle. Data from the selected memory location, will
be latched into the lower 8 bits of the command word shortly after the
second rising edge of the CLOCK signal.
The serial data timing for the four-wire interface is shown in Figure
25 and the programming protocol is shown in Figure 24.
10.1 Write Sequence
The external programmer brings the ACEx microcontroller into
programming mode by applying a super voltage level to the LOAD
pin. TheexternalprogrammerthenneedstosettheLOADpinto5V
beforeshiftinginthe32-bitserialcommandwordusingtheSHIFT_IN
and CLOCK signals. By definition, bit 31 of the command word is
shifted in first. At the same time, the ACEx microcontroller shifts out
the 32-bit serial response to the last command on the SHIFT_OUT
pin. It is recommended that the external programmer samples this
signal tACCESS (1µs) after the rising edge of the CLOCK signal. The
serialresponseword,sentimmediatelyafterenteringprogramming
mode, contains indeterminate data.
Writing a series of bytes to the device is achieved by sending a
series of Write command words while observing the devices
handshaking requirements.
Reading a series of bytes from the device is achieved by sending
a series of Read command words with the desired addresses in
sequence and reading the following response words to verify the
correct address and data contents.
After 32 bits have been shifted into the device, the external
programmer must set the LOAD signal to 0V, and then apply two
clock pulses as shown in Figure 24 to complete program cycle.
The SHIFT_OUT pin acts as the handshaking signal between the
device and programming hardware once the LOAD signal is
brought low. The device sets SHIFT_OUT low by the time the
programmer has sent the second rising edge during the LOAD =
The addresses of the data EEPROM and code EEPROM loca-
tions are the same as those used in normal operation.
Powering down the device will cause the part to exit programming
mode.
Table 15: 32-Bit Command and Response Word
Bit number
bits 31 – 30
bit 29
Input command word
Output response word
Must be set to 0
X
Set to 1 to read/write data EEPROM or the initial-
ization registers, otherwise 0
X
bit 28
Set to 1 to read/write code EEPROM,
otherwise 0
X
bits 27 – 25
bit 24
Must be set to 0
X
Set to 1 to read, 0 to write
X
bits 23 – 18
bits 17 – 8
bits 7 – 0
Must be set to 0
X
Address of the byte to be read or written
Data to be programm ed or zero if data is to be read
Same as Input command word
Programmed data or data read at specified address
14Ffor further information see Application Note AN-8005.
15 During in-circuit programming, G5 must be either not connected or driven high.
www.fairchildsemi.com
26
ACE1101 Product Family Rev. B.2
Figure 24- Programming Protocol15
A
A
tSV1 tSV2
tload1 tload2
tready
tload3 tload4
enter prog.
mode
LOAD (G3)
32 clock pulses
CLOCK (G1)
bit 31
bit 30
bit 0
bit 31
SHIFT_IN (G4)
BUSY low by
2nd clock pulse
READY
SHIFT_OUT (G2)
(in write mode)
BUSY
SHIFT_OUT (G2)
(in read mode)
A: start of programming cycle
Figure 25- Serial Data Timing
tHI
tLO
CLOCK (G1)
tDIS
tDIH
Valid
SHIFT_IN (G4)
tDOS
tDOH
Valid
SHIFT_OUT (G2)
tACCESS
www.fairchildsemi.com
27
ACE1101 Product Family Rev. B.2
can be thoughtofas asupplement function tothePower-on Reset
when VCC does not fall below ~1.5V. The Power-on Reset circuit
works best when VCC starts from zero and rises sharply. So in
applications where VCC is not constant, the BOR will give added
device stability.
11.0 Brown-out/Low Battery Detect Circuit
The Brown-out Reset (BOR) and Low Battery Detect (LBD)
circuits on the ACEx microcontroller have been designed to offer
two types of voltage reference comparators. The sections below
will describe the functionality of both circuits.
The BOR circuit must be enabled through the BOR enable bit
(BOREN) in the initialization register. The BOREN bit can only be
set while the device is in programming mode. Once set, the BOR
will always be powered-up enabled. Software cannot disable the
BOR. The BOR can only be disabled in programming mode by
resettingtheBORENbitaslongastheglobalwriteprotect(WDIS)
feature is not enabled.
Figure 26: BOR/LBD Block Diagram
Vcc
0
1.8V
_
1
2.2V
BOR
LBD
2
to RESET logic
S
+
BLSEL16
11.2 Low Battery Detect
_
+
The Low Battery Detect (LBD) circuit allows software to monitor
the VCC level at the lower voltage ranges. LBD has an eight level
software programmable voltage reference threshold that can be
changed on the fly. Once VCC falls below the selected threshold,
the LBD flag in the LBD control register is set. The LBD flag will
hold its value until VCC rises above the threshold. (See Table 16)
Adjust Reference Voltage
LBD
Control
Register
7
6
5
4
3
1
0
The LBD bit is read only. If LBD is 0, it indicates that the VCC level
is higher than the selected threshold. If LBD is 1, it indicates that
the VCC level is below the selected threshold. The threshold level
can be adjusted up to eight levels using the three trim bits
(Bat_trim[2:0]) of the LBD control register. The LBD flag does not
cause any hardware actions or an interruption of the processor. It
is for software monitoring only.
11.1 Brown-out Reset 17
The Brown-out Reset (BOR) function is used to hold the device in
reset when VCC drops below a fixed threshold. (See BOR Electri-
cal Characteristics for threshold voltage.) While in reset, the
device is held in its initial condition until VCC rises above the
threshold value. Shortly after VCC rises above the thresholdvalue,
aninternalresetsequenceisstarted.Aftertheresetsequence,the
core fetches the first instruction and starts normal operation.
The LBD function is disabled during HALT/IDLE mode. After
exiting HALT/IDLE, software must wait at lease 10 µs before
reading the LBD bit to ensure that the internal circuit has stabi-
lized.
16 See Figure 14 for information on BLSEL.
17 BOR is not available on the ACE1101B device.
On the devices, the BOR should be used in situations when VCC
rises and falls slowly and in situations when VCC does not fall to
zero before rising back to operating range. The Brown-out Reset
Table 16: LBD Control Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bat_trim[2:0]
X
X
X
X
LBD
Voltage
Reference
Bat_trim[0] Range ( 20%)
Level
Bat_trim[2]
Bat_trim[1]
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2.9 - 3.0
2.8 - 2.9
2.7 - 2.8
2.6 - 2.7
2.5 - 2.6
2.4 - 2.5
2.3 - 2.4
2.2 - 2.3
www.fairchildsemi.com
28
ACE1101 Product Family Rev. B.2
The external reset provides a way to properly reset the ACEx
microcontroller if POR cannot be used in the application. The
external reset pin contains an internal pull-up resistor. Therefore,
to reset the device the reset pin should be held low for at least 2ms
so that the internal clock has enough time to stabilize.
12.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset
setting all I/Os to high-impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is gener-
ated by any one of the following three conditions:
14.0 CLOCK
• Power-on Reset (as described in Section 13.0)
• Brown-out Reset (as described in Section 11.1)
• Watchdog Reset (as described in Section 7.0)
• External Reset18 (as described in Section 13.0)
The ACEx microcontroller has an on-board oscillator trimmed to
a frequency of 2MHz who is divided down by two yielding a 1MHz
frequency. (See AC Electrical Characteristics.) Upon power-up,
the on-chip oscillator runs continuously unless entering HALT
mode or using an external clock source.
13.0 Power-On-Reset
Ifrequired,anexternaloscillatorcircuitmaybeuseddependingon
the states of the CMODE bits of the initialization register. (See
Table 17) When the device is driven using an external clock, the
clock input to the device (G1/CKI) can range between DC to
4MHz. For external crystal configuration, the output clock (CKO)
is on the G0 pin. (See Figure 28) If an external crystal or RC is
used, internally the input frequency (CKI) is divided-down by four
to yield the corresponding instruction clock. If the device is
configured for an external square clock, it will not be divided.
The Power-On Reset (POR) circuit is guaranteed to work if the
rate of rise of VCC is no slower than 10ms/1volt. The POR circuit
wasdesignedtorespondtofastlowtohightransitionsbetween0V
and VCC. The circuit will not work if VCC does not drop to 0V before
thenextpower-upsequence. Inapplicationswhere1)the VCC rise
is slower than 10ms/1 volt or 2) VCC does not drop to 0v before the
nextpower-upsequencetheexternalresetoptionshouldbeused.
Table 17: CMODEx Bit Definition
CMODE[1]
CMODE[0]
Clock Type
Internal 1 MHz clock
0
0
1
1
0
1
0
1
External square clock
External crystal/resonator
External RC clock
Figure 27: BOR and POR Circuit Relationship Diagram
V
(Pin 8)
CC
BOR
output
V
CC
V
CC
1.75
0
V
CC
0
Reset
circuit
output
Global Reset
to Logic
Time
BOR Output
A
POR
output
External
Reset
B
The Reset circuit will trigger
when inputs A or B transition
from High to Low. At that time
the Global Reset signal will go
high which will reset all controller
logic. The Global Reset will go
high and stay high for around 1µs.
Pin
V
CC
(14-Pin Only)
5.0V
1.8V
0
(Pin 7)
V
CC
POR Output
Pulse
POR
output
0
18 Available only on the 14-pin package option.
www.fairchildsemi.com
29
ACE1101 Product Family Rev. B.2
Figure 28: Crystal (a) and RC (b) Oscillator Diagrams
a)
b)
CKI
(G1)
CKO
(G0)
CKI
(G1)
CKO
(G0)
1M
R
V
CC
C
33pF
33pF
15.0 HALT Mode
16.0 IDLE Mode
The HALT mode is a power saving feature that almost completely
shuts down the device for current conservation. The device is
placed into HALT mode by setting the HALT enable bit (EHALT)
of the HALT register through software using only the “LD M, #”
instruction. EHALT is a write only bit and is automatically cleared
upon exiting HALT. When entering HALT, the internal oscillator
and all the on-chip systems including the LBD and the BOR
circuits are shut down.
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed into
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT
register through software using only the “LD M, #” instruction.
EIDLE is a write only bit and is automatically cleared upon exiting
IDLE. The IDLE mode operation is similar to HALT except the
internal oscillator, the Watchdog, and the Timer 0 remain active
while the other on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit HALT mode only by the MIW circuit. There-
fore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 8) After a wakeup from
HALT, a 1ms start-up delay is initiated to allow the internal
oscillator to stabilize before normal execution resumes. Immedi-
ately after exiting HALT, software must clear the Power Mode
Clear (PMC) register by only using the “LD M, #” instruction. (See
Figure 30)
The device can exit IDLE by a Timer 0 overflow every 8192 cycles
or/and by the MIW circuit. If exiting IDLE mode with the MIW, prior
to entering, software must configure the MIW circuit accordingly.
(See Section 8) Once a wake from IDLE mode is triggered, the
core will begin normal operation by the next clock cycle. Immedi-
ately after exiting IDLE mode, software must clear the Power
Mode Clear (PMC) register by using only the “LD M, #” instruction.
(See Figure 31)
Figure 29: HALT Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
undefined
undefined
undefined
undefined
undefined
undefined
EIDLE
EHALT
Figure 30: Recommended HALT Flow
Figure 31: Recommended IDLE Flow
Normal Mode
Normal Mode
LD
HALT, #01H
LD HALT, #01h
Timer0
Underflow
IDLE Mode
Multi-Input
Wakeup
Multi-Input
Halt
Wakeup
LD PMC, #00H
Resume Normal
Mode
LD PMC, #00h
Resume
Normal Mode
www.fairchildsemi.com
30
ACE1101 Product Family Rev. B.2
Ordering Information
Part Numbe
Core Type
Max. #
I/Os
Program
Memory Size
Operating Voltage Range
Temperature Range
Package
Tape
and
0
1
2
8
1K
2K
1.8 –
5.5V
2.2 –
5.5V
2.7 –
5.5V
0 to
70°C
-40 to
+85C
-40 to
+125°C
8-pin
TSSOP
8-pin
DIP
14-pin
DIP
Reel
ACE1101MT8
ACE1101MT8X
ACE1101N
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101N14
X
X
X
X
X
X
X
X
ACE1101EMT8
ACE1101EMT8X
ACE1101EN
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101EN14
ACE1101VMT8
ACE1101VMT8X
ACE1101VN
X
X
X
X
X
X
ACE1101VN14
ACE1101BMT8
ACE1101BMT8X
ACE1101BN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101BN14
ACE1101BEMT8
ACE1101BEMT8X
ACE1101BEN
ACE1101BEN14
ACE1101BVMT8
ACE1101BVMT8X
ACE1101BVN
ACE1101BVN14
ACE1101LMT8
ACE1101LMT8X
ACE1101LN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1101LN14
www.fairchildsemi.com
31
ACE1101 Product Family Rev. B.2
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0118
(0.19 - 0.30)
0°-8°
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP (MT8)
Order Number ACE1101(1101L)MT8/ACE1101EMT8/ACE1101VMT8
ACE1101BMT8/ACE1101BEMT8/ACE1101BVMT8
Package Number MTC08
www.fairchildsemi.com
32
ACE1101 Product Family Rev. B.2
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95° 5°
0.009 - 0.015
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
(0.508)
Min
(0.229 - 0.381)
0.018 0.003
(0.457 0.076)
NOM
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
8-Pin DIP (N)
Order Number ACE1101(1101L)N/ACE1101EN/ACE1101VN
ACE1101BN/ACE1101BEN/ACE1101BVN
Package Number N08E
www.fairchildsemi.com
33
ACE1101 Product Family Rev. B.2
Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin DIP (N14)
Order Number ACE1101(1101L)N14/ACE1101EN14/ACE1101VN14
ACE1101BN14/ACE1101BEN14/ACE1101BVNT14
Package Number N014A
www.fairchildsemi.com
34
ACE1101 Product Family Rev. B.2
ACEx Emulator Kit: Fairchild also offers a low cost real-time in-
circuit emulator kit that includes:
ACEx Development Tools
General Information
Emulator board
Emulator software
Assembler and Manuals
Power supply
Fairchild Semiconductor offers different possibilities to evaluate
and emulate software written for ACEx.
ACEx Starter Kit includes:
Programmer Board
DIP14 target cable
PC cable
Simulator Software
Programmer Software
Assembler and Manuals
Cables and samples devices
DIP programming sockets
The ACEx emulator allows for debugging the program code in a
symbolic format. It is possible to place one breakpoint and watch
various data locations. It also has built-in programming capability.
Prototype Board Kits: Fairchild offer two solutions for the simpli-
fication of the breadboard operation so that ACEx Applications
can be quickly tested.
Programmer board: Interfaces with a PC through a Windows
program using the serial communication port. This board is
intended for engineering prototype and can be used for small
volume production. Fairchild offers factory pre-programming and
serialization (for justified quantities) for a small additional cost.
Please refer to your local distributor for details regarding factory
programming.
1) ACEDEMO is can be used for general purpose applications
2) ACETXRX for transmitting / receiving (RF, IR, RS232,
RS485) applications.
ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator,
buzzer, and a lamp with a small breadboard area.
Simulator: Is a Windows program able to load, assemble, and
debugACExprograms.Itispossibletoplaceasmanybreakpoints
as needed, trace the program execution in symbolic format, and
program a device with the proper options. The ACEx Simulator is
available free-of-charge and can be downloaded from Fairchild’s
web site at www.fairchildsemi.com/products/memory/ace
Ordering P/Ns
Starter Kit:
ACESTART1101
ACESTART1202
Programming Adapters:
DIP8 - ACESDIP8
DIP14 - ACESDIP14
TSSOP8 - ACESTSSOP8
SO8 - ACESSOP8
SO14 - ACESSOP15
Emulator Kit: ACEICE (110Vac)
ACEICE_EU (220Vac)
Prototype Boards:
ACEDEMO
ACETXRX (specify RF freq. 433 or 315MHz)
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
AmericasEurope
Fairchild Semiconductor
Fairchild Semiconductor
Kong
Fairchild Semiconductor
Japan
Hong
Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
Tel:
Tel:
Tel:
+44 (0) 1793-856858
+49 (0) 8141-6102-0
+44 (0) 1793-856856
+33 (0) 1-6930-3696
+39 (0) 2-249111-1
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
4F, Natsume Bldg.
Deutsch
English
Français
Italiano
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
www.fairchildsemi.com
35
ACE1101 Product Family Rev. B.2
ACE1101BEN14 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ACE1101BMT8 | FAIRCHILD | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications | 获取价格 |
|
| ACE1101BMT8X | FAIRCHILD | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications | 获取价格 |
|
| ACE1101BN | ETC | 8-Bit Microcontroller | 获取价格 |
|
| ACE1101BN14 | ETC | 8-Bit Microcontroller | 获取价格 |
|
| ACE1101BV | FAIRCHILD | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications | 获取价格 |
|
| ACE1101BVMT8 | FAIRCHILD | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications | 获取价格 |
|
| ACE1101BVMT8X | FAIRCHILD | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications | 获取价格 |
|
| ACE1101BVN | ETC | 8-Bit Microcontroller | 获取价格 |
|
| ACE1101BVN14 | ETC | 8-Bit Microcontroller | 获取价格 |
|
| ACE1101E | FAIRCHILD | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications | 获取价格 |
|
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