AD402M186RCB-5 [ETC]
Low voltage operation is more suitable to be used on battery backup, portable electronic; 低电压工作，以对电池备份用更合适的，便携式电子
| 型号： | AD402M186RCB-5 |
| 厂家： | 
ETC |
| 描述： | Low voltage operation is more suitable to be used on battery backup, portable electronic |
| 文件： | 总28页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASCEND
Semiconductor
4Mx4 EDO
Data sheet
Rev.1
Page1
AD 40 4M 4 2 V S A – 5
Ascend
Semiconductor
EDO/FPM
D-RAMBUS
DDRSDRAM
DDRSGRAM
SGRAM
: 40
: 41
: 42
: 43
: 46
: 48
SDRAM
Density
16M : 16 Mega Bits
8M : 8 Mega Bits
4M : 4 Mega Bits
2M : 2 Mega Bits
1M : 1 Mega Bit
Min Cycle Time ( Max Freq.)
-5 : 5ns ( 200MHz )
-6 : 6ns ( 167MHz )
-7 : 7ns ( 143MHz )
-75 : 7.5ns ( 133MHz )
-8 : 8ns ( 125MHz )
-10 : 10ns ( 100MHz )
Organization
4: x4
8 : x8
9 : x9
16 : x16
18 : x18
EDO : -5 (50 ns)
-6 (60 ns)
32 : x32
Refresh
1
8
: 1K : 8K
2 : 2K 6 :16K
4 : 4K
Revision
A : 1st B : 2nd
C : 3rd D :4th
Interface
V: 3.3V
R: 2.5V
Package
C: CSP B: uBGA
T: TSOP Q: TQFP
P: PQFP ( QFP )
L: LQFP S: SOJ
Rev.1
Page2
Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-
tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).
Features
• Single 3.3V(±10 %) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
- Active mode : 432/396 mW (Mas)
- Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Rev.1
Page3
Pin Configuration
26/24-PIN 300mil Plastic TSOP (ll)
26/24-PIN 300mil Plastic SOJ
1
2
3
4
VSS
VCC
DQ1
DQ2
WE
1
2
3
4
VSS
VCC
DQ1
DQ2
WE
26
25
24
26
25
24
DQ4
DQ3
DQ4
DQ3
CAS
OE
A9
CAS
OE
A9
23
22
23
22
RAS
NC
5
6
RAS
NC
5
6
21
21
8
8
19
19
A10
A8
A10
A8
9
9
18
17
16
15
14
A0
A1
18
17
16
15
14
A0
A1
A7
A6
A7
10
11
10
11
A6
A2
A3
A2
A3
A5
A5
12
13
12
13
A4
A4
VCC
VCC
VSS
VSS
Pin Description
Pin Name
Function
Address inputs
A0-A10
- Row address
A0-A10
- Column address
- Refresh address
A0-A10
A0-A10
DQ1~DQ4
RAS
CAS
WE
Data-in / data-out
Row address strobe
Column address strobe
Write enable
OE
Output enable
Power (+ 3.3V)
Ground
Vcc
Vss
Rev.1
Page4
Block Diagram
WE
CONTROL
LOGIC
DATA-IN BUFFER
CAS
DQ1
.
.
DQ4
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
OE
COLUMN
COLUMN
DECODER
ADDRESS
BUFFERS (11)
A0
A1
A2
2048
REFRESH
CONTROLLER
A3
A4
A5
A6
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
2048x4
A7
A8
A9
2048x2048x4
MEMORY
ARRAY
ROW
A10
ADDRESS
BUFFERS (11)
Vcc
Vss
NO. 1 CLOCK
GENERATOR
RAS
Rev.1
Page5
TRUTH TABLE
ADDRESSES
FUNCTION
ROW
X
COL
X
DQS
RAS
H
CAS
WE
X
OE
X
Notes
STANDBY
High-Z
H ® X
READ
L
L
L
L
L
L
H
L
L
ROW
ROW
ROW
COL Data-Out
COL Data-ln
WRITE: (EARLY WRITE )
READ WRITE
X
COL Data-Out,Data-ln
COL Data-Out
H ® L
L ® H
EDO-PAGE-
MODE READ
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
L
L
L
L
L
H
L
ROW
n/a
H ® L
H ® L
H ® L
H ® L
H ® L
H
L
L
L
X
X
COL Data-Out
EDO-PAGE
MODE WRITE
ROW
n/a
COL Data-In
COL Data-In
EDO-
PAGE-MODE
READ-WRITE
ROW
COL Data-Out, Data-In
H ® L
L ® H
2nd Cycle
READ
L
n/a
COL Data-Out, Data-In
COL Data-Out
H ® L
H ® L
L ® H
HIDDEN
REFRESH
L
L
H
L
L
ROW
ROW
L ® H ® L
WRITE
X
COL Data-In
1
L ® H ® L
L
RAS-ONLY REFRESH
CBR REFRESH
H
L
X
H
X
X
ROW
X
n/a
X
High-Z
High-Z
H ® L
Notes: 1. EARLY WRITE only.
Rev.1
Page6
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to Vss
Supply voltage relative to Vss
Short circuit output current
Power dissipation
-0.5 to + 4.6
VCC
IOUT
PD
-0.5 to + 4.6
50
V
mA
W
1.0
Operating temperature
TOPT
TSTG
0 to + 70
-55 to + 125
°C
°C
Storage temperature
Recommended DC Operating Conditions
Parameter/Condition
Symbol
3.3 Volt Version
Unit
Min
3.0
Typ
3.3
Max
Supply Voltage
VCC
VIH
VIL
3.6
VCC + 0.3
0.8
V
V
V
Input High Voltage, all inputs
Input Low Voltage, all inputs
2.0
-
-
-0.3
Capacitance
Ta = 25°C, V = 3.3V ±10 %, f = 1MHz
CC
Parameter
Symbol
CI1
Typ
-
Max
Unit
pF
Note
Input capacitance (Address)
5
7
7
1
1
Input capacitance (RAS, CAS, OE, WE)
CI2
-
-
pF
pF
Output capacitance
(Data-in, Data-out)
CI/O
1, 2
Note: 1. Capacitance measured with effective capacitance measuring method.
2. RAS, CAS = V to disable Dout.
IH
Rev.1
Page7
DC Characteristics :
(T = 0 to 70°C, VCC = + 3.3V ±10 %, V = 0V)
a
SS
Parameter
Symbol
Test Conditions
AD404M42V
-6
Unit Notes
-5
Min Max Min Max
Operating current
Low
ICC1
RAS cycling
CAS, cycling
tRC = min
-
-
-
120
-
-
-
110
mA
mA
mA
1, 2
ICC2
LVTTL interface
RAS, CAS = VIH
0.5
0.5
power
S-version
Dout = High-Z
CMOS interface
0.15
0.15
RAS, CAS ³ VCC -0.2V
Dout = High-Z
Standby
Current
Standard
power
LVTTL interface
RAS, CAS = VIH
-
-
2
-
-
2
mA
mA
version
Dout = High-Z
CMOS interface
RAS,CAS ³ VCC -0.2V
Dout = High-Z
0.5
0.5
RAS- only refresh current
EDO page mode current
ICC3
RAS cycling, CAS = VIH
-
120
-
110
mA
1, 2
t
RC = min
ICC4
ICC5
tPC = min
-
-
90
-
-
80
mA
mA
1, 3
1, 2
CAS- before- RAS refresh
current
tRC = min
120
110
RAS, CAS cycling
Self- refresh current
(S-Version)
ICC8
-
550
-
550
tRASS ³ 100ms
mA
Rev.1
Page8
DC Characteristics :
(T = 0 to 70°C, V = +3.3V ±10 %, V = 0V)
a
SS
CC
AD404M42V
Unit
Notes
-5
-6
Parameter
Symbol
ILI
Test Conditions
Min
-5
Max
Min
-5
Max
Input leakage current
5
5
0V £ Vin £ VCC + 0.3V
mA
mA
Output leakage current
ILO
-5
5
-5
5
0V £ Vout £ VCC + 0.3V
Dout = Disable
Output high Voltage
Output low voltage
VOH
VOL
IOH = -2mA
2.4
-
-
2.4
-
-
V
V
IOL = +2mA
0.4
0.4
Notes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the
device is selected. ICC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
Rev.1
Page9
AC Characteristics
(Ta = 0 to + 70°C, Vcc = 3.3V ±10 %, Vss = 0V) *1, *2, *3, *4
Test conditions
• Output load: one TTL Load and 100pF (VCC = 3.3V ±10 %)
• Input timing reference levels:
VIH = 2.0V, VIL = 0.8V (VCC = 3.3V ±10 %)
• Output timing reference levels:
VOH = 2.0V, VOL = 0.8V
Read, Write, Read- Modify- Write and Refresh Cycles
(Common Parameters)
AD404M42V
Unit
Notes
-5
-6
Parameter
Symbol
tRC
Min
84
Max
Min
104
Max
Random read or write cycle time
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
RAS precharge time
tRP
tCPN
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRAL
tRSH
tCSH
tCRP
tOED
tT
30
10
40
10
CAS precharge time in normal mode
RAS pulse width
50 10000
60 10000
10 10000
5
6
CAS pulse width
8
0
10000
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
Column address to RAS lead time
RAS hold time
-
0
10
0
-
8
-
-
0
-
-
7
8
-
10
14
12
30
10
40
5
-
12
10
25
8
37
45
8
9
25
30
-
-
-
-
CAS hold time
38
5
-
-
CAS to RAS precharge time
OE to Din delay time
-
-
10
11
12
1
-
50
32
128
-
15
1
-
50
32
128
-
Transition time (rise and fall)
Refresh period
tREF
tREF
tCLZ
tDZC
tDZO
-
-
Refresh period (S- Version)
CAS to output in Low- Z
CAS delay time from Din
OE delay time from Din
-
-
0
0
0
-
0
-
0
-
0
-
Rev.1
Page10
Read Cycle
AD404M42V
Unit
Notes
-5
-6
Min
Max
50
Min
Max
60
Parameter
Symbol
tRAC
Access time from RAS
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
Access time from CAS
tCAC
tAA
14
25
12
-
15
30
15
-
13, 14
14, 15
Access time from column address
Access time from OE
tOEA
tRCS
tRCH
tRRH
tOFF
tOEZ
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Output buffer turn-off time
Output buffer turn-off time from OE
0
0
0
0
0
0
0
0
0
0
7
10, 16
16
-
-
-
-
12
12
15
15
17
17
Write Cycle
AD404M42V
Unit
Notes
7, 18
-5
-6
Min
Max
Min
Max
Parameter
Symbol
tWCS
Write command setup time
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCH
tWP
8
8
10
10
15
10
0
tRWL
tCWL
tDS
13
8
0
19
19
Data-in hold time
tDH
8
10
10
WE to Data-in delay
tWED
10
Rev.1
Page11
Read- Modify- Write Cycle
AD404M42V
Unit
Notes
-5
-6
Min
108
Max
Min
133
Max
Parameter
Symbol
tRWC
Read-modify- write cycle time
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
RAS to WE delay time
tRWD
tCWD
tAWD
tOEH
64
26
39
8
77
32
47
10
18
18
18
CAS to WE dealy time
Column address to WE delay time
OE hold time from WE
Refresh Cycle
AD404M42V
-5
-6
Min
Max
Min
Max
Parameter
Symbol
tCSR
Unit
ns
Notes
CAS setup time (CBR refresh)
5
-
-
-
-
5
-
CAS hold time (CBR refresh)
RAS precharge to CAS hold time
RAS pulse width (self refresh)
tCHR
tRPC
8
5
10
5
-
-
-
ns
ns
10
7
tRASS
100
90
-50
0
100
ms
ns
ns
ns
ns
RAS precharge time (self refresh)
CAS hold time (CBR self refresh)
WE setup time
tRPS
tCHS
tWSR
tWHR
-
-
-
-
110
-50
0
-
-
-
-
WE hold time
10
10
Rev.1
Page12
EDO Page Mode Cycle
AD404M42V
-6
-5
Min
20
10
50
-
Max
Min
25
10
60
-
Max
Parameter
Symbol
tPC
Unit
ns
Notes
EDO page mode cycle time
-
-
EDO page mode CAS precharge time
EDO page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
OE high hold time from CAS high
OE high pulse width
tCP
tRASP
tCPA
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
105
30
105
35
20
10, 14
tCPRH
tOEHC
tOEP
30
5
-
-
35
5
-
-
10
5
-
10
5
-
Data output hold time after CAS low
Output disable delay from WE
tCOH
tWHZ
tWPZ
-
-
3
10
-
3
10
-
WE pulse width for output disable when
CAS high
7
7
EDO Page Mode Read Modify Write Cycle
AD404M42V
-5
-6
Min
45
Max
Min
55
Max
-
Parameter
Symbol
tCPW
Unit
ns
Notes
10
EDO page mode read- modify- write cycle
CAS precharge to WE delay time
-
EDO page mode read- modify- write cycle
time
tPRWC
56
-
68
-
ns
Rev.1
Page13
Notes :
1. AC measurements assume tT = 2ns.
2. An initial pause of 100 ms is required after power up, and it followed by a minimum of eight
initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal
refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the VCC and VSS pins shall be supplied with the same voltages.
5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.
6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.
7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .
8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.
Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.
9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.
Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.
10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .
11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between VIH and VIL.
12. Assumes that tRCD £ tRCD(max) and tRAD £ tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
13. Assumes that tRCD ³ tRCD (max) andtRAD £ tRAD (max).
14. Access time is determined by the maximum of tAA, tCAC, tCPA
.
15. Assumes that tRCD £ tRCD (max) and tRAD ³ tRAD (max).
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high
impedance). tOFF is determined by the later rising edge of RAS or CAS.
18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ³ tWCS (min), the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD ³ tRWD (min),
tCWD ³ tCWD (min), tAWD ³ tAWD (min) and tCPW ³ tCPW (min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a
delayed write or a read-modify-write cycle.
20. tRASP defines RAS pulse width in EDO page mode cycles.
Rev.1
Page14
Timing Waveforms
• Read Cycle
t
RC
t
t
RAS
RP
RAS
t
CRP
t
CSH
t
t
RCD
RSH
t
T
t
t
CPN
CAS
CAS
t
t
RAL
RAD
t
t
t
t
ASC
CAH
ASR
RAH
ADDRESS
Column
Row
t
RRH
t
t
RCH
RCS
WE
OE
t
t
OEA
CAC
OEZ
t
t
OFF
t
AA
t
OFF
t
RAC
D
DQ1~DQ4
OUT
t
CLZ
Note :
= don’t care
= Invalid Dout
Rev.1
Page15
•Early Write Cycle
t
RC
t
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
RCD
RSH
t
CPN
t
T
t
CAS
CAS
t
t
RAD
RAL
t
t
t
t
ASC
CAH
ASR
RAH
ADDRESS
Row
Column
t
t
WCH
WCS
WE
t
t
DS
DH
D
IN
DQ1~DQ4
Rev.1
Page16
• Delayed Write Cycle
t
RC
t
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
RCD
RSH
t
t
T
t
CPN
CAS
CAS
t
t
t
t
CAH
RAH
ASC
ASR
ADDRESS
Row
Column
t
CWL
t
RCS
t
t
RWL
WP
WE
OE
t
t
OED
OEH
t
t
DS
DH
OPEN
DQ1~DQ4
DIN
Rev.1
Page17
• Read - Modify - Write Cycle
t
RWC
t
t
RAS
RP
RAS
t
T
t
t
t
RCD
CAS
CRP
t
CPN
CAS
t
RAD
t
t
t
t
RAH
ASC
ASR
CAH
Row
Column
RCS
ADDRESS
t
t
t
CWL
CWD
t
t
AWD
RWL
t
RWD
t
WP
WE
t
t
DZC
DH
t
DS
OPEN
DIN
DQ1~DQ4
t
DZO
t
t
OED
OEH
OE
t
t
t
OEA
CAC
AA
t
OEZ
t
RAC
DQ1~DQ4
DOUT
Rev.1
Page18
• EDO Page Mode Read Cycle
t
t
RP
RASP
t
CPRH
RAS
t
CRP
t
t
t
PC
CSH
RSH
t
t
t
t
t
t
t
t
CRP
RCD
CAS
CAS
CAS
CPN
CP
CP
CAS
t
RAD
t
RAL
t
t
t
t
ASC
t
t
t
t
ASR
CAH
ASC
ASC
CAH
RAH
CAH
ADDRESS
Column N
Row
Column 2
Row
Column 1
t
RRH
t
RCH
t
RCS
WE
OE
t
OEHC
t
OEA
t
OEP
t
OEA
t
t
t
t
OEZ
RAC
CPA
CPA
t
t
t
AA
AA
AA
t
t
OFF
OEZ
t
t
t
CAC
CAC
CAC
t
OFF
t
COH
OPEN
DOUT
1
DQ1~DQ4
DOUT N
DOUT
2
Rev.1
Page19
• EDO Page Mode Early Write Cycle
t
t
RP
RASP
RAS
t
T
t
t
t
CRP
t
PC
CSH
RSH
t
t
t
t
t
t
t
RCD
CAS
CAS
CAS
CPN
CP
CP
CAS
t
t
t
t
ASC
t
ASC
t
t
t
ASC
ASR
CAH
CAH
RAH
CAH
ADDRESS
Column N
Row
Column 1
Column 2
t
t
t
t
t
t
WCS
WCS
WCH
WCS
WCH
WCH
WE
t
t
t
t
t
t
DS
DS
DH
DS
DH
DH
DIN
N
DIN
2
DIN
1
DQ1~DQ4
Rev.1
Page20
• EDO Page Mode Read-Early-Write Cycle
t
t
RASP
RP
t
CPRH
RAS
t
CRP
t
PC
t
t
CSH
RSH
t
t
t
t
t
t
t
t
CRP
RCD
CAS
CAS
CAS
CPN
CP
CP
CAS
t
t
CAL
CSH
RAD
RAH
t
t
RAL
t
t
t
t
ASC
t
t
t
t
ASR
CAH
ASC
ASC
RAH
CAH
ADDRESS
Column N
Row
Column 2
Row
Column 1
t
WCS
t
RCH
t
t
RCS
WCH
WE
OE
t
OEA
t
WED
t
t
RAC
CPA
t
t
AA
AA
t
WHZ
t
t
CAC
CAC
t
DH
t
DS
t
COH
Data
Data
Doutput 1
OPEN
DQ1~DQ4
Doutput 2
Data
Input N
Rev.1
Page21
• EDO Page Mode Read-Modify-Write Cycle
t
RASP
t
CPRH
t
RP
RAS
t
t
T
t
PRWC
t
CRP
t
t
CP
CP
t
t
t
RCD
CAS
CAS
CAS
CAS
t
t
RAD
t
RAL
ASC
t
t
ASR
t
ASC
ASC
t
t
t
t
RAH
CAH
CAH
CAH
ADDRESS
Column 1
1
Column 2
t
Column N
t
Row
t
t
t
t
CWL
CWL
CWL
RWD
CPW
CPW
t
t
t
t
AWD
AWD
RWL
AWD
t
t
t
t
CWD
CWD
CWD
RCS
t
RCS
WE
t
t
t
RCS
WP
t
WP
WP
t
DZC
t
DZC
t
t
t
DS
DS
DS
t
DZC
t
t
DH
DH
t
DH
OPEN
OPEN
OPEN
DIN
N
DIN
2
DIN
1
DQ1~DQ4
t
DZO
t
DZO
t
DZO
t
t
t
OED
OED
OED
t
t
OEH
t
OEH
OEH
OE
t
t
OEA
OEA
t
OEA
CAC
t
t
t
CAC
CAC
t
t
AA
AA
t
AA
t
t
t
CPA
RAC
CPA
t
t
t
OEZ
OEZ
OEZ
DQ1~DQ4
D
N
D
2
DOUT
1
OUT
OUT
Rev.1
Page22
• Read Cycle with WE Controlled Disable
RAS
t
CSH
t
RCD
t
t
CAS
T
CAS
t
RAD
t
t
t
t
CAH
ASC
RAH
ASR
Row
Column
ADDRESS
t
t
RCH
WPZ
t
RCS
WE
t
WHZ
OE
t
OEA
t
OEZ
t
CAC
t
AA
t
RAC
D
OUT
DQ1~DQ4
t
CLZ
Rev.1
Page23
RAS-Only Refresh Cycle
t
t
RC
t
RP
RAS
RAS
t
T
t
t
RPC
CRP
t
CRP
CAS
t
ASR
t
RAH
ADDRESS
ROW
t
OFF
OPEN
DQ1~DQ4
CAS-Before-RAS Refresh Cycle
t
RC
t
RC
t
t
t
RP
t
t
RP
RAS
RAS
RP
RAS
CAS
t
T
t
t
CRP
t
RPC
RPC
t
t
t
t
t
CSR
CHR
CSR
CHR
t
t
WSR
WHR
t
WHR
WSR
WE
t
OFF
OPEN
DQ1~DQ4
Rev.1
Page24
CBR Self-Refesh Cycle
t
t
RPS
RASS
RAS
t
RPC
t
CSR
t
CHS
CAS
t
OFF
High lmpedance
DQ1~DQ4
t
t
WSR
WHR
WE
Rev.1
Page25
• Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RP
RAS
(REFRESH)
RAS
RAS
(READ)
RP
(REFRESH)
RAS
t
T
t
CRP
t
CHR
t
t
RSH
t
t
RCD
CAS
CAS
t
RAL
RAD
t
t
t
ASC
ASR
RAH
t
CAH
ADDRESS
COlumn
ROW
t
RRH
t
RCS
t
RCH
WE
OE
t
t
OEZ
OEA
t
CAC
t
OFF
t
AA
t
OFF
t
RAC
D
DQ1~DQ4
OUT
Rev.1
Page26
Ordering information
Part Number
Access time
50 ns
Package
AD404M42VSA-5
AD404M42VSA-6
AD404M42VTA-5
AD404M42VTA-6
60 ns
50 ns
60 ns
300mil 26/24-Pin
Plastic SOJ
TSOP II
AD404M42VSA-5
• AD
• 40
• 4M4
• 2
• Ascend Memory Product
• Device Type
• Density and Organization
• Refresh Rate, 2: 2K Refresh
• T: 5V, V: 3.3V
• V
• S
• Package Type (S : SOJ, T : TSOP II)
• Version
• A
• 5
• Speed (5: 50 ns, 6: 60 ns)
Packaging information
• 300 mil, 26/24-Pin Plastic SOJ
D
b
MILLIMETERS
INCHES
DIM
A
26
21
19
14
b1
MIN. NOM. MAX. MIN.
NOM. MAX.
3.25
3.51
---
3.76 0.128 0.138 0.148
---
A1 2.08
0.082
---
---
c1
c
A2
2.54 REF.
0.100 REF.
E1
E
b
0.41 ---
0.51 0.016
---
0.020
BASE METAL
b1
b2
c
0.41
0.66
0.18
0.18
0.46
---
0.48 0.016 0.018 0.019
WITH PLATING
0.81 0.026
0.30 0.007
0.28 0.007
---
---
---
0.032
---
0.012
0.011
1
6
8
13
SECTION B-B
c1
D
E
---
17.02 17.15 17.27 0.670 0.675 0.680
8.51 BASIC
0.335 BASIC
7.75 0.295 0.300 0.305
0.267 BASIC
E1
E2
e
7.49 7.62
C
L
6.78 BASIC
1.27 BASIC
---
0.050 BASIC
R1 0.76
1.02 0.030
---
0.040
0.025" MIN.
A2
B
A
B
A1
NOTE:
1. CONTROLLING DIMENSION : INCHES
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
E2
RAD R1
e
0.004"
SEATING PLANE
b2
4-e
b
M
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE.
0.007"
3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR
INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm)
DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH
TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN.
Rev.1
Page27
• 300 mil, 26/24-Pin TSOP II
MILLIMETERS
DIM
INCHES
NOM.
---
RAD R1
RAD R
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.52
0.45
0.21
0.16
17.27
MIN.
---
MAX.
0.047
0.006
0.041
0.020
0.018
0.008
(0.006)
0.680
26
21
19
14
A
A1
A2
b
A2
A1
c
0.05
0.95
0.30
0.30
0.12
0.12
17.01
---
0.002
0.037
0.012
0.012
0.005
0.005
0.670
---
B
1.00
---
0.039
---
B
E1
E
0.016
---
L
b1
c
0.40
---
DETAIL A
0 ~5
0.006
c1
D
0.15
17.14
0.95 REF.
b
0.675
SECTION B-B
b1
1
6
8
13
ZD
0.0374 BASIC
0.050 BASIC
e
1.27 BASIC
D
c
c1
E
9.02
7.49
0.40
0.12
0.12
9.22
7.62
0.50
---
9.42
7.75
0.60
0.25
---
0.355
0.295
0.016
0.005
0.005
0.363
0.300
0.020
---
0.371
E1
L
0.305
0.024
0.010
---
BASE METAL
R
WITH PLATING
R1
---
---
DETAIL A
(ZD)
NOTE:
1. CONTROLLING DIMENSION : MILLIMETERS
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
A
MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE.
4-1.27
REF.
e
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
SEATING PLANE
b
0.200(0.008")
M
0.100(0.004")
Rev.1
Page28
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