ADC82124_技术文档

Advanced

Communication

Devices

aShet:ACD8124

Y

OR

Data Sheet: ACD82124

24 Ports 10/100 Fast Ethernet Switch Controller

Rev.1.1.1.F

INRODUCT

Last Update: November 5, 1998

Subject to Change

Please check ACD’s website for

update information before starting a design

Web site: http://www.acdcorp.com

or Contact ACD at:

Email: support@acdcorp.com

Tel: 408-433-9898x115

Fax: 408-545-0930

ACD Confidential Material

For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission.

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aShet:ACD8124

Table of Contents

Section

Page

Y

1

2

3

4

5

6

7

8

9

General Description

Main Features

3

4

10

16

27

32

38

39

OR

System Block Diagram

System Description

Functional Description

Interface Description

Register Description

Pin Description

Timing Description

10 Electrical Specifications

11 Packaging

INRODUCT

Appendix

A1 Address Resolution Logic

(The built-in ARL)

40

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1. GENERAL DESCRIPTION

2. FEATURES

•

24 ports 10/100 auto-sensing with MII interface

The ACD82124 is a single chip implementation of a 24

port 10/100 Ethernet switch system intended for IEEE

802.3 and 802.3u compatible networks. The device

includes 24 independent 10/100 MACs. Each MAC

interfaces with an external PMD/PHY device through a

standard MII interface. Speed can be automatically

configured through the MDIO port. Each port can op-

erate at either 10Mbps or 100Mbps. The core logic of

the ACD82124, implemented with patent pending

BASIQ (Bandwidth Assured Switching with Intelligent

Queuing) technology, can simultaneously process 24

asynchronous 10/100Mbps port traffic. The Queue

Manager inside the ACD82124 provides the capability

of routing traffic with the same order of sequence,

without any packet loss.

Half-duplex operation, with optional full-duplex con-

figuration by combining 2 adjacent ports

2.4 Gbps aggregated throughput

True non-blocking switch architecture

Flexible port configuration (up to 12 full duplex 10/

100 ports, up to 24 half duplex 10/100 ports)

Built-in storage of 2,000 MAC address

Automatic source address learning

Zero-Packet Loss back-pressure flow control

Store-and-forward switch mode

•

aShet:ACD8124

•

Port based V-LAN support

UART type CPU management interface

Supports up to 11K MAC addresses with the

ACD80800

Y

•

RMON and SNMP support with ACD80900

Status LEDs: Link, Speed, Full Duplex, Transmit,

Receive, Collision and Frame Error

Reversible MII option for CPU and expansion port

interface

Wire speed forwarding rate

576 pin BGA package

3.3V power supply, 3.3V I/O with 5V tolerance

OR

A complete 24 port 10/100 switch can be built with the

use of the ACD82124, 10/100 PHY and ASRAM. The

MAC addresses can be expanded from the built-in 2K

to 11K by the use of ACD’s external ARL chip

(ACD80800 Address Resolution Logic). Advanced net-

work management features can be supported with the

use of ACD’s MIB (ACD80900 Management Informa-

tion Base) chip.

•

INRODUCT

3. SYSTEM BLOCK DIAGRAM

FIFO

Buffer

PMD/

PHY-0

MAC-0

MAC-1

Lookup Engine

(2K MAC Addr.)

BIST Handler

LED Controller

FIFO

Buffer

PMD/

PHY-1

MX

Queue Manager

DMX

FIFO

Buffer

PMD/

PHY-22

MAC-22

MAC-23

FIFO

Buffer

ARL Interface

SRAM Interface

MIB Interface

PMD/

PHY-23

ACD82124

ARL

ACD80800

(11K MAC Addr.)

(optional)

MIB

ACD80900

(optional)

SRAM

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4. SYSTEM DESCRIPTION

The MAC address space can be expanded from 2,000

to 8,000 per system by using the ACD80800. The

ACD82124 has a proprietary ARL interface that allows

direct connection with ACD80800. System designers

can also use this ARL interface to implement a ven-

dor-specific address resolution algorithm.

The ACD82124 is a single chip implementation of a

24-port Fast Ethernet switch. Together with external

ASRAM and transceiver devices, it can be used to

build a complete desktop class Fast Ethernet switch.

Each individual port can be either auto-sensed or manu-

ally selected to run at 10 Mbps or 100 Mbps speed

rate, under Half Duplex mode.

The ACD82124 provides management support through

its MIB (Management Information Base) interface. The

MIB interface can be used to monitor all traffic activi-

ties of the switch system. ACD’s supporting chip (the

ACD80900) provides a full set of statistical counters to

support both SNMP and RMON network management.

The MIB interface can also be used by system de-

signers to implement vendor-specific network manage-

ment functionality.

aShet:ACD8124

The ACD82124 Ethernet switch contains three major

functional blocks: the Media Access Controller (MAC),

the Queue Manager, and the Lookup Engine.

There are 24 independent MACs within the ACD82124.

The MAC controls the receiving, transmitting, and de-

ferring process of each individual port, in accordance

to IEEE 802.3 and 802.3u standard. The MAC logic

also provides framing, FCS checking, error handling,

status indication and back-pressure flow control func-

tions. Each MAC interfaces with an external transceiver

through standard MII interface.

Y

Among the 24 MII interfaces, 10 of them can be con-

figured as reversed MII, to connect directly with stand-

alone MAC controller devices. A MAC in the ACD82124

can be viewed logically as a PHY device if it is config-

ured as a reversed MII interface. The reversed MII is

intended for a CPU network interface, or expansion

port interface.

OR

The device utilizes ACD’s proprietary BASIQ (Band-

width Assured Switching with Intelligent Queuing) tech-

nology. It is a technology to enforce the first-in-first-

out rule of Ethernet Bridge-type devices in a very effi-

cient way. The technology enables a true non-block-

ing frame switching operation at wire speed for a high

throughput and high port density Ethernet switch.

A system CPU can access various registers inside

the ACD82124 through a serial CPU management

interface. The CPU can configure the switch by

writing into the appropriate registers, or retrieve the

status of the switch by reading the corresponding

registers. The CPU can also access the registers of

external transceiver (PHY) devices through the CPU

management interface.

INRODUCT

The on-chip 2,000 MAC addresses Lookup Engine

maps each destination address into a destination port.

Each port’s MAC address is automatically learned by

the Lookup Engine when it receives a frame with no

error. Therefore, the ACD82124 alone can be used to

build a desktop class Fast Ethernet switch without any

additional switching devices.

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5. FUNCTIONAL DESCRIPTION

Start of Frame Detection

The MAC controller performs transmit, receive, and

defer functions, in accordance to IEEE 802.3 and

802.3u standard specification. The MAC logic also

handles frame detection, frame generation, error de-

tection, error handling, status indication and flow con-

trol functions.

When a port’s MAC is idle, assertion of the RXDV in

the MII interface will cause the port to go into the re-

ceive state. The MII presents the received data in 4-bit

nibbles that are synchronous to the receive clock

(25Mhz or 2.5MHz). The ACD82124 will convert this

data into a serial bit stream, and attempt to detect the

occurrence of the SFD (10101011) pattern. All data

prior to the detection of SFD are discarded. Once SFD

is detected, the following frame data are forwarded

and stored in the buffer of the switch.

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Frame Format

The ACD82124 assumes that the received data packet

will have the following format:

Frame Reception

Y

Preamble SFD DA SA Type/Len Data FCS

Under normal operating conditions, the ACD82124

expects a received frame to have a minimum inter frame

gap (IFG). The minimum IFG required by the device is

80 BT (Bit Time).

OR

Where,

•

Preamble is a repetitive pattern of ‘1010….’ of

any length with nibble alignment.

In the event the ACD82124 receives a packet with IFG

less than 80BT, the ACD82124 does not guarantee to

be able to receive the frame. The packet will be dropped

if the ACD82124 cannot receive the frame.

SFD (Start Frame Delimiter) is defined as an oc-

tet pattern of 10101011.

DA (Destination Address) is a 48-bit field that speci-

fies the MAC address of the destined DTE. If the

first bit of DA is 1, the ACD82124 will treat the

frame as a broadcast/multicast frame and will for-

ward the frame to all ports within the source port’s

VLAN except the source port itself or BPDU ad-

dress.

The device will check all received frames for errors

such as symbol error, FCS error, short event, runt,

long event, jabber etc. Frames with any kind of error

will not be forwarded to any port.

INRODUCT

Preamble Bit Processing

•

SA (Source Address) is a 48-bit field that con-

tains the MAC address of the source DTE that is

transmitting the frame to the ACD82124. After a

frame is received with no error, the SA is learned

as the port’s MAC address.

The preamble bit in the header of each frame will be

used to synchronize the MAC logic with the incoming

bit stream. The minimum length of the preamble is 0

bits and there is no limitation on the maximum length of

preamble. After the receive data valid signal RXDV is

asserted by the external PHY device, the port will wait

for the occurrence of the SFD pattern (10101011) and

then start a frame receiving process.

Type/Len field is a 2-byte field that specifies the

type (DIX Ethernet frame) or length (IEEE 802.3

frame) of the frame. The ACD82124 does not pro-

cess this information.

Source Address and Destination Address

•

Data is the encapsulated information within the

Ethernet Packet. The ACD82124 does not pro-

cess any of the data information in this field.

After a frame is received by the ACD82124, the em-

bedded destination address and source address are

retrieved. The destination address is passed to the

lookup table to find the destination port. The source

address is automatically stored into the address lookup

table. For applications that use an external ARL, the

ACD82124 will disable the internal lookup table and

pass the DA and SA to the external ARL for address

lookup and learning.

FCS (Frame Check Sequence) is a 32-bit field of

a CRC (Cyclic Redundancy Check) value based

on the destination address, the source address,

the type/length and the data field. The ACD82124

will verify the FCS field for each frame. The pro-

cedure of computing FCS is described in section

of “FCS Calculation.”

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5

A port’s MAC address register is cleared on power-

up, hardware reset, or when the port enters into Link

Fail state. If the SA aging option is enabled (Register-

16 bit 4), the learned SA will be cleared if it does not

reappear within five minutes.

is less then 64 bytes, the frame is flagged with runt

error.

In order to support an application where extra byte

length is required, an Extra-Long-Frame option is pro-

vided. When the Extra long frame option is enabled

(Table 12: CFG7), only frames longer than 1530 bytes

are marked with a long event error. Frame length is

measured from the first byte of DA to the last byte of

FCS.

During the receive process, the Lookup Engine will

attempt to match the destination address with the ad-

dresses stored in the address table. If a match is found,

a link between the source port and the destination port

is established. If an external ARL is used, the ACD82124

indicates the presence of a 48-bit DA through the sta-

tus line of the ARL interface. The external ARL will use

the value of DA for address comparison and return a

result of the lookup to the ACD82124.

aShet:ACD8124

Frame Filtering

Frames with any kind of error will be filtered. Types of

error include code error (indicated by assertion of

RXER signal), FCS error, alignment error, short event,

runt, and long event.

Y

Frame Data

OR

Frame data are transparent to the ACD82124. The

ACD82124 will forward the data to the destination

port(s) without interpreting the content of the frame

data field.

Any frame heading to its own source port will be fil-

tered. If external ARL is used, the ACD82124 will filter

the frame as directed by the external ARL.

If the Spanning Tree Support option is enabled, frames

containing DA equal to any reserved Bridge Manage-

ment Group Address specified in Table 3.5 of IEEE

802.1d will not be forwarded to any ports, except the

Port-23, which may receive BPDU frames. If span-

ning tree support is not enabled, frames with DA equal

to the reserved Group Address for PBDU will be broad-

casted to all ports in the same VLAN of the source

port.

FCS Calculation

Each port of the ACD82124 has CRC checking logic

to verify if the received frame has a correct FCS value.

A wrong FCS value is an indication of a fragmented

frame or a frame with frame bit error. The method of

calculating the CRC value is using the following poly-

nomial,

INRODUCT

32

26

23

7

22

5

16

4

12

11

G(x) = x + x + x + x + x + x + x

Jabber Lockup Protection

10

8

2

+ x + x + x + x + x + x + x + 1

If a receiving port is active continuously for more than

50,000 BT, the port is considered to be jabbering. A

jabbering port will automatically be partitioned from the

switch system in order to prevent it from impairing the

performance of the network. The partitioned port will

be re-activated as soon as the offending signal dis-

continues.

as a divider to divide the bit sequence of the incoming

frame, beginning with the first bit of the destination

address field, to the end of the data field. The result of

the calculation, which is the residue after the polyno-

mial division, is the value of the frame check sequence.

This value should be equal to the FCS field appended

at the end of the frame. If the value does not match the

FCS field of the frame, the Frame Bit Error LED of the

port will be turned on once and the packet will be

dropped.

Excessive Collision

In the event that there are more than 16 consecutive

collision, the ACD82124 will reset the counter to zero

and retransmit the packet. This implementation insures

there is no packet loss even under channel capture

situation. However, ACD82124 has an option to drop

the packet on excessive collision. When this option is

enabled (Table 12: CG11), the frame will be dropped

after 16 consecutive collisions.

Frame Length

During the receiving process, the MAC will monitor the

length of the received frame. Legal Ethernet frames

should have a length of not less than 64 bytes and no

more than 1518 bytes. If the carrier sense signal of a

frame is asserted for less than 76 BT, the frame is

flagged with short event error. If the length of a frame

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False Carrier Events

tional 32 BT before starting the transmit process. In

the event that the carrier sense signal is asserted by

the MII during the wait period, the MAC logic will gen-

erate a JAM signal to cause a forced collision.

If the RXER signal in the MII interface is asserted when

the receive data valid (RXDV) signal is not asserted,

the port is considered to have a false carrier event. If

a port has more than two consecutive false carrier

events, the port will automatically be partitioned from

the switch system. The partitioned port will be re-acti-

vated if it has been idling for 33,000 BT or it has re-

ceived a valid frame.

The MAC logic will abort the transmit process if a colli-

sion is detected through the assertion of the Col signal

of the MII. Re-transmission of the frame is scheduled

in accordance to IEEE 802.3’s truncated binary expo-

nential backoff algorithm. If the transmit process has

encountered 16 consecutive collisions, an excessive

collision error is reported, and the ACD82124 will try

to re-transmit the frame, unless the drop-on-exces-

sive-collision option of the port is enabled. It will first

reset the number of collisions to zero and then start

the transmission after 96 BT of interframe gap. If drop-

on-excessive-collision is enabled, the ACD82124 will

not try to re-transmit the frame after 16 consecutive

collisions. If a collision is detected after 512 BT of the

transmission, a late collision error will be reported, but

the frame will still be retransmitted after proper backoff

time.

aShet:ACD8124

Frame Forwarding

If the first bit of the destination address is 0, the frame

is handled as a unicast frame. The destination ad-

dress is passed to the Address Resolution Logic, which

returns a destination port number to identify which port

the frame should be forwarded to. If Address Resolu-

tion Logic cannot find any match for the destination

address, the frame will be treated as a frame with un-

known DA. The frame will be processed in one of two

ways. If the option flood-to-all-port is enabled, the

switch will forward the frame to all ports within the same

VLAN of the source port, except the source port itself.

If the option is not enabled, the frame will be forwarded

to the ‘dumping port’ of the source port VLAN only.

The dumping port is determined by the VLAN ID of the

source port. If the source port belongs to multiple

VLANs, a frame with unknown DA will then be for-

warded to multiple dumping ports of the VLANs.

Y

OR

Frame Generation

During a transmit process, frame data is read out from

the memory buffer and is forwarded to the destination

port’s PHY device in nibbles. 7 bytes of preamble sig-

nal (10101010) will be generated first followed by the

SFD (10101011), and then the frame data and 4 bytes

of FCS are sent out last.

INRODUCT

If the first bit of the destination address is a 1, the

frame is handled as a multicast or broadcast frame.

The ACD82124 does not differentiate a multicast packet

from a broadcast packet except the reserved bridge

management group address, as specified in table 3.5

of the IEEE 802.1d standard. The destination ports of

the broadcast frame is all ports within the same VLAN

except the source port itself.

Frame Buffer

All ports of the ACD82124 work in Store-And-Forward

mode so that all ports can support both 10Mbps and

100Mbps data speed. The ACD82124 utilizes a global

memory buffer pool, which is shared by all ports. The

device has a unique architecture that inherits the ad-

vantage of both output buffer-based and input buffer-

based switches. An output buffer-based switch stores

the received data only once into the memory, and hence

has a short latency. Whereas an input buffer-based

switch typically has more efficient flow control.

The order of all broadcast frames with respect to the

unicast frames is strictly enforced by the ACD82124.

Frame Transmission

The ACD82124 transmits all frames in accordance to

IEEE 802.3 standard. The ACD82124 will send the

frames with a guaranteed minimum interframe gap of

96 BT, even if the received frames have an IFG less

than the minimum requirement. Before the transmit

process is started, the MAC logic will check if the chan-

nel has been silent for more than 64 BT. Within the 64

BT silent window, the transmission process will defer

on any receiving process. If the channel has been

silent for more than 64 BT, the MAC will wait an addi-

Flow Control

Under half duplex mode of operation, when the switch

cannot handle the receiving of an incoming frame, a

collision is generated by sending a jam pattern to the

sending party to force it to back off and re-transmit the

frame later. Back pressure flow control is applied to a

port when its reserved-buffer is full and no more shared

buffer is available, or when starvation control is active.

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7

This process is used to ensure that there are no

dropped frames. Backpressure flow control can be

disabled by setting the corresponding bit of the regis-

ter-21.

802.3 standard. The ACD82124 will direct the follow-

ing frames to the dumping port:

•

frame with unicast destination address that does

not match with any port’s source address within

the VLAN of the source port

VLAN Support (register 23 & 24)

frame with broadcast/multicast destination address*

The ACD82124 can support up to 4 port-based secu-

rity VLANs. Each port of the ACD82124 can be as-

signed up to four VLAN. On power up, every port is

assigned to VLAN-0 as default VLAN. Frames from

the source port will only be forwarded to destination

ports within the same VLAN domain. A broadcast/

multicast frame will be forwarded to all ports within the

VLAN(s) of the source port. A unicast frame will be

forwarded to the destination port only if the destination

port is in the same VLAN as the source port. Other-

wise, the frame will be treated as a frame with un-

known DA. Each VLAN can be assigned with a dedi-

cated dumping port. Multiple VLANs can also share a

dumping port. Unicast frames with unknown destina-

tion addresses will be forwarded to the dumping port

of the source port VLAN.

* See Spanning Tree Support

aShet:ACD8124

If the device is configured to work under Flood-to-All-

Port mode (Register 25, bit 8), frames listed above will

be forwarded to all the ports in the VLAN(s) of the

source port except the source port itself.

Y

Mode of Operation

OR

By default, all ports of the ACD82124 work in half du-

plex mode. A full-duplex port can be configured by

combining two half-duplex ports. In this case, the op-

eration mode of the port is determined by the port’s

PHY device through auto-negotiation. The mode of a

port can also be assigned by the duplex mode indica-

tion/assignment register (Register 27).

Security VLAN can be disabled by setting the corre-

sponding bit in the system configuration register (bit 8

of Register 16). When security VLAN is disabled, each

VLAN becomes a leaky VLAN and is equivalent to a

broadcast domain. Four dumping ports of four differ-

ent virtual VLAN can be grouped together to form a fat

pipe uplink (For example, if port 0&1, port 2&3, port

3&4, port 5&6 are combined to form 4 full duplex ports

with 200Mbps per port throughput, these 4 full duplex

ports can be grouped to form an 800 Mbps uplink port).

When multiple dumping ports are grouped as a single

pipe, each port has to be assigned to one and only

one VLAN. A unicast frame with a matched DA will be

forwarded to any destination, even if the VLAN ID is

different. All unmatched DA packets will be forwarded

to the designated dumping port of the source port

VLAN. The broadcast and multicast packets will only

be forwarded to the ports in the same VLAN of the

source port. Therefore, a 200 to 800 Mbps pipe can

be established by carefully grouping the dumping ports,

and connects directly with the segmentation switches.

Spanning Tree Support

The ACD82124 supports Spanning Tree protocol.

When Spanning Tree Support is enabled (Register 16

bit 1), frames from the CPU port (port 23) having a DA

equal to the reserved Bridge Management Group Ad-

dress for BPDU will be forwarded to the port specified

by the CPU. Frames from all other ports with a DA

equal to the Reserved Group Address for BPDU will be

forwarded to the CPU port if the port is in the same

VLAN of the CPU port. Port 23 is designed as the

default CPU port. When Spanning Tree Support is dis-

abled, all reserved group addresses for Bridge Man-

agement is treated as broadcast address.

INRODUCT

Every port of the ACD82124 can be set to block-and-

listen mode through the CPU interface. In this mode,

incoming frames with DA equal to the reserved Group

Address for BPDU will be forwarded to the CPU port.

Incoming frames with all other DA value will be dropped.

Outgoing frames with DA value equal to the Group Ad-

dress for BPDU will be forwarded to the attached PHY

device; all other outgoing frames will be filtered.

Dumping Port

Each VLAN can be assigned with a dedicated dump-

ing port. Multiple VLANs can share a dumping port.

Each dumping port can be used for up-link connec-

tion or for DTE connection. That is, the dumping port

can be used to connect the switch with a computer

repeater hub, a workgroup switch, a router, or any

type of interconnecting device compliant with the IEEE

Queue Management

Each port of the ACD82124 has its own individual

transmission queue. All frames coming into the

ACD82124 are stored into the shared memory buffer,

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8

and are lined up in the transmission queues of the

corresponding destination port. The order of all frames,

unicast or broadcast, is strictly enforced by the

ACD82124. The ACD82124 is designed with a non-

blocking switching architecture. It is capable of achiev-

ing wire-speed frame forwarding rate and handling

maximum traffic load.

CPU Interface

The ACD82124 does not require a microprocessor for

operation. Initialization and most configurations can

be done with the use of external hardware pins. How-

ever, the ACD82124 provides a CPU interface for a

microprocessor to access some of its control regis-

ters and status registers. The microprocessor can send

a read command to retrieve the status of the switch, or

send a write command to configure the switch through

a serial interface. This interface is a commonly used

UART type interface. The CPU interface can also be

used to access the registers inside each PHY device

connected with the ACD82124.

aShet:ACD8124

MII Interface

The MAC of each port of the ACD82124 interfaces

with the port’s PHY device through the standard MII

interface. For reception, the received data (RXD) can

be sampled by the rising edge (default) or the falling

edge of the receive clock (RXCLK). Assertion of the

receive data valid (RXDV) signal will cause the MAC to

look for start of Frame Delimiter (SFD). For transmis-

sion, the transmit data enable (TXEN) signal is as-

serted when the first preamble nibble is sent on the

transmit data (TXD) lines. The transmit data are clocked

out by the falling edge of the transmit clock (TXCLK).

Y

ARL Interface

OR

The ACD82124 has a built-in ARL that can store up to

2,000 MAC addresses. It is actually a subset of the full

ACD80800 ARL IC. For detailed description, please

refer to the ACD80800 Data Sheet. The UARTID for

this built-in ARL is shared with the ACD82124 (CFG16

& 17).

The ACD82124 supports PHY device management

through the serial MDIO and MDC signal lines. The

ACD82124 can continuously poll the status of the PHY

devices through the serial management interface, with-

out CPU intervention. The ACD82124 will also config-

ures the PHY capability field to ensure proper opera-

tion of the link. The ACD82124 also enables the CPU

to access any registers in the PHY devices through

the CPU interface.

The ACD82124 also provides an ARL interface (Table

12: CFG9) for supporting additional MAC addresses.

Through the ARL interface, the external ARL

(ACD80800) device can tap the value of DA out from

the data bus in the ASRAM interface, and execute a

lookup process to map the value of DA into a port

number. The external ARL device also learns the SA

values embedded in the received frames via the ARL

interface. The value of SA is used to build up the ad-

dress lookup table.

INRODUCT

Reversed MII Interface

Ten ports of the ACD82124 can be configured as re-

versed MII interface. Reversed MII behaves as a PHY

MII, that the TXCLK, COL, RXD<3:0>, RXCLK, RXDV,

CRS signals (names specified by IEEE 802.3u) be-

come output signals of the ACD82124, and the TXER,

TXD<3:0>, TXEN, RXER, signals (names specified by

IEEE 802.3u) become input signals of the ACD82124.

Reversed MII interface enables an external MAC de-

vice to be connected directly with the ACD82124.

MIB Interface

Traffic activities on all ports of the ACD82124 can be

monitored through the MIB interface. Through the MIB

interface, a MIB device can view what the source port

is receiving, or what the destination port is transmit-

ting. Therefore, the MIB device can maintain a record

of traffic statistics for each port to support network

management. Since all received data are stored into

the memory buffer, and all transmitted data are re-

trieved from the memory buffer, the data of the activi-

ties can also be captured from the data bus of ASRAM

interface. The status of each data transaction between

the ACD82124 and the ASRAM is displayed by some

dedicated status signal pins of the ACD82124.

ASRAM Interface

The ACD82124 requires the use of asynchronous

SRAM as a memory buffer. Each read or write cycle

takes up to 20 ns. An ASRAM chip with access speed

at 12 ns or faster should be used. The ASRAM inter-

face contains a 52-bit data bus, a 17-bit address bus

and 4 chip-select signals.

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9

LED Interface

The ACD82124 provides a wide variety of LED indica-

tors for simple system management. The update of the

LED is completely autonomous and merely requires

low speed TTL or CMOS devices as LED drivers. The

status display is designed to be flexible to allow the

system designer to choose those indicators appropri-

ate for the specification of the equipment.

aShet:ACD8124

There are two LED control signals, LEDVLD0 and

LEDVLD1, used to indicate the start and end of the

LED data signal. LEDCLK signal is a 2.5MHz clock

signal. The rising edge of LEDCLK should be used to

latch the LED data signal into the LED driver circuitry.

Y

The LED data signals contain Lnk, Xmt, Rcv, Col, Err,

Adr, Fdx and Spd, which represent Link status, Trans-

mit status, Receive status, Collision indication, Frame

error indication, Port Address learning status, Full du-

plex operation and Operational Speed status respec-

tively. These status signals are sent out sequentially

from port 23 to port 0, once every 50ms. For details

about the timing diagrams of the LED signals, refer to

the chapter of “Timing Description ”

OR

Life Pulse

The ACD82124 continuously sends out life pulses to

the WCHDOG pin when it is operating properly. In a

catastrophic event, the ACD82124 will not send the

life pulse to cause the external watchdog circuitry to

time-up and reset the switch system.

INRODUCT

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10

6. INTERFACE DESCRIPTION

Table-6.2: Reversed MII Interface Signals

Name

Type

Description

MII Interface (MII)

PxCRSR

O

I

Carrier sense

PxRXDVR

PxRXCLKR

PxRXERR

PxRXD0R

PxRXD1R

PxRXD2R

PxRXD3R

Transmit data valid

Transmit clock (25/2.5 MHz)

Not-Ready (Input)

The ACD82124 communicates with the external 10/

100 Ethernet transceivers through standard MII inter-

face. The signals of MII interface are described in

table-6.1:

O

I

Transmit data bit 0

Transmit data bit 1

Transmit data bit 2

I

aShet:ACD8124

I

Table-6.1: MII Interface Signals

I

Transmit data bit 3

Collision Indication/

Not-Ready (Output)

Receive data valid

Name

Type

Description

Carrier sense

Receive data valid

Receive clock (25/2.5 MHz)

Receive error

Receive data bit 0

Receive data bit 1

Receive data bit 2

Receive data bit 3

Collision indication

Transmit data valid

Transmit clock (25/2.5 MHz)

Transmit data bit 0

Transmit data bit 1

Transmit data bit 2

Transmit data bit 3

PxCOLR

O

PxCRS

I

PxRXDV

PxRXCLK

PxRXERR

PxRXD0

PxRXD1

PxRXD2

PxRXD3

PxCOL

PxTXENR

PxTXCLKR

PxTXD0R

PxTXD1R

PxTXD2R

PxTXD3R

O

Receive clock (25/2.5 MHz)

Receive data bit 0

Y

Receive data bit 1

OR

Receive data bit 2

Receive data bit 3

PxTXEN

PxTXCLK

PxTXD0

PxTXD1

PxTXD2

PxTXD3

O

I

O

For reversed MII interface, signal PxRXDVR, and

PxRXD0R through PxRXD3R are clocked out by the

falling edge of PxRXCLKR. Signal PxTXENR, and

PxTXD0R through PxTXD3R can be sampled by the

falling edge or rising edge of PxTXCLKR, depends on

the setting of bit 9 of Register 16. The timing behavior

is described in the chapter of “Timing Description.“

INRODUCT

For MII interface, signal PxRXDV, PxRXER and

PxRXD0 through PxRXD3 are sampled by the rising

edge of PxRXCLK. Signal PxTXEN, and PxTXD0

through PxTXD3 are clocked out by the falling edge of

PxTXCLK. The detailed timing requirement is described

in the chapter of “Timing Description”

PHY Management Interface

All control and status registers of the PHY devices are

accessible through the PHY management interface.

The interface consists of two signals: MDC and MDIO,

which are described in Table-6.3.

Ports 0,1, 2, 3, 4, 5, 6, 7, 22 and 23 can be config-

ured as reversed MII ports (Register 28, the Reversed

MII Enable register). These ports, when configured as

“normal” MII, have the same characteristics as all other

MII ports. However, when configured as reversed MII

interface, they will behave logically like a PHY device,

and can interface directly with a MAC device. The

signal of reversed MII interface are described by table-

6.2:

Table-6.3: PHY Management Interface Signals

Name Type

Description

MDC

MDIO

O

I/O

PHY management clock (1.25MHz)

PHY management data

Frames transmitted on MDIO has the following format

(Table-6.4):

Note: * Collision Indication for half-duplex mode.

Not-Ready (output) for full duplex mode.

Table-6.4: MDIO Format

Operation

PRE

1…1

ST

01

OP

01

10

PHY-ID

aaaaa

REG-AD

rrrrr

TA

10

Z0

DATA

d…d

IDLE

Z

Write

Read

rrrrr

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11

A command sent by CPU comes through the CPUDI

line. The command consists of 9 octets. Command

frames transmitted on CPUDI have the following for-

mat (Table-6.6):

Prior to any transaction, the ACD82124 will output

thirty-two bits of ‘1’ as a preamble signal. After the

preamble, a ‘01’ signal is used to indicate the start of

the frame.

Table-6.6: CPU Command Format

Operation Command Register Index Data Checksum

For a write operation, the device will send a ‘01’ to

signal a write operation. Following the ‘01’ write signal

will be the 5 bit ID address of the PHY device and the

5 bit register address. A ‘10’ turn around signal is then

followed. After the turn around, the 16 bit of data will

be written into the register. After the completion of the

write transaction, the line will be left in a high imped-

ance state.

Write

Read

0010XX11

0010XX01

8-bit

8-bit 24-bit

8-bit

aShet:ACD8124

The byte order of data in all fields follows the big-endian

convention, i.e. most significant octet first. The bit or-

der is least significant order first. The Command octet

specifies the type of the operation. Bit 2 and bit 3 of

the command octet is used to specify the device ID of

the chip. They are set by bit 16 and bit 17 of the Reg-

ister 25 at power on strobing. The address octet speci-

fies the type of the register. The index octet specifies

the ID of the register in a register array. For write

operation, the Data field is a 4-octet value to specify

what to write into the register. For read operation, the

Data field is a 4-octet 0 as padded data. The checksum

value is an 8-bit value of exclusive-OR of all octets in

the frame, starting from the Command octet.

For a read operation, the ACD82124 will output a ‘10’

to indicate read operation after the start of frame indi-

cator. Following the ‘10’ read signal will be the 5-bit ID

address of the PHY device and the 5-bit register ad-

dress. Then, the ACD82124 will cease driving the MDIO

line, and wait for one BT. During this time, the MDIO

should be in a high impedance state. The ACD82124

will then synchronize with the next bit of ‘0’ driven by

the PHY device, and continue on to read 16 bits of

data from the PHY device.

Y

OR

The system designer should set the ID of the PHY

devices as ‘1’ for port-0, ‘2’ for port-1, … and ‘24’ for

port-23. The detail timing requirement on PHY man-

agement signals are described in the chapter of “Tim-

ing Description.”

The ACD82124 will respond to each valid command

received by sending a response frame through the

CPUDO line. The response frames have the following

format (Table-6.7):

INRODUCT

CPU Interface

Table-6.7: Response Format

Response Command Result Data Checksum

The ACD82124 includes a CPU interface to enable an

external CPU to access the internal registers of the

ACD82124. The protocol used in the CPU is the asyn-

chronous serial signal (UART). The baud rate can be

from 1200 bps to 76800 bps. The ACD82124 auto-

matically detects the baud rate for each command,

and returns the result at the same baud rate. The sig-

nals in CPU interface are described in Table-6.5.

Write

Read

00100011

00100001

8-bit

24-bit

8-bit

The command octet specifies the type of the response.

The result octet specifies the result of the execution.

The Result field in a response frame is defined as:

Table-6.5: CPU Interface Signals

Name

CPUDI

CPUDO

CPUIRQ

Type

I

O

Description

CPU data input

CPU data output

CPU interrupt request

•

00 for no error

01 for Checksum

10 for address incorrect

11 for MDIO waiting time-out

For response to a read operation, the Data field is a 3-

octet value to indicate the content of the register. For

response to a write operation, the Data field is 24 bits

of 0. The checksum value is an 8-bit value of exclu-

sive-OR of all octets in the response frame, starting

from the Command octet.

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12

the ACD82124. The timing requirement on ARL sig-

nals is described in Chapter-9 “Timing Description.”

Table-6.9 shows the associated signals in ARL inter-

face.

CPUIRQ is used to inform the CPU of some special

status has been encountered by the ACD82124, like

port partition, fatal system error, etc. By clearing the

appropriate bit in the interrupt mask register, one can

stop the specific source from generating an interrupt

request. Reading the interrupt source register retrieves

the source of the interrupt and clears the interrupt

source register.

Table-6.9: ARL Interface Signals

Name

Type

Description

ARLDO0-RLDO51

O

ARL data output, shared with

DATA 0 - DATA 51

aShet:ACD8124

ARLDIR1-ARLDIR0

O

ARL data direction indicator

ASRAM Interface

00 for idle

01 for receive

All received frames are stored into the shared memory

buffer through the ASRAM interface. When the desti-

nation port is ready to transmit the frame, data is read

from the shared memory buffer through the ASRAM

interface. The signals in ASRAM interface are de-

scribed in Table-6.8.

10 for transmit

11 for control

Y

ARLSYNC

O

ARL port synchronization

ARL data state indicator

ARLSTAT0-

ARLSTAT3

ARLCLK

OR

O

I

ARL clock

ARLDI0 - ARLDI3

ARLDIV

ARL data input

ARL input data valid

Table-6.8: ASRAM Interface

I

Name

DATA0-DATA51

ADDR0-ADDR16

nOE

Type

Description

I/O memory data bus

O

memory address bus

output enable, low active

write enable, low active

chip select signals, low active.

The data signal is tapped from the DATA bus of ASRAM

interface. Since all data of the received frames will be

written into the shared memory through the DATA bus,

the bus can be used to monitor occurrences of DA

and SA values, indicated by the status signal of

ARLSTAT. Therefore, ARLD0 through ARLD51 are the

same signals of DATA0 through DATA47.

nWE

nCS0 - nCS3

INRODUCT

Data is written into the ASRAM or read from the ASRAM

in 52-bit wide words. The data is a 48-bit wide value

and the control is a 4 bit-wide value. ADDR specifies

the address of the word, and DATA contains the con-

tent of the word. Bit 0 ~ 47 of DATA bus are used to

pass 48-bit frame data. Bit 48 are used to indicate the

start and end of a frame. Bit 49 ~ 51 are used to

indicate the length of actual data presented on DATA0

~ DATA47.

ARLDIR1 and ARLDIR0 are used to indicate the di-

rection of data on the ARLDO bus:

•

00: Idle

01: for receiving data

10: for transmitting data

11: Header

ARLSYNC is used to indicate port 0 is driving the DATA

bus. Since the bus is pre-allocated in time division

multiplexing manner, the ARL device can determine

which port is driving the DATA bus.

nOE and nWE are used to control the timing of read

or write operation respectively. nCSx selects the

ASRAM chip corresponding to the word address. The

timing requirement on ASRAM access is described in

the chapter-9 “Timing Description”.

ARLSTAT are used to indicate the status of the data

shown on the first 48 bits of DATA bus. The 4-bit status

is defined as:

ARL Interface

•

0000 - Idle

0001 - First word (DA)

0010 - Second word (SA)

0011 - Third through last word

0100 - Filter Event

0101 - Drop Event

0110 - Jabber

0111 - False Carrier/Deferred Transmission*

1000 - Alignment error/Single Collision*

ARL interface provides a communication path between

the ACD82124 and an ARL device, which can provide

up to 8K of additional address lookup function. As the

ACD82124 receives a frame, the destination address

and source address of the frame are displayed on the

ARLDO data lines for the external ARL device. After

the external ARL finds the corresponding destination

port, it returns the result through the ARLDIx lines to

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13

Table-11: LED Interface Signals

Name

LEDVLD0

LEDVLD1

nLEDCLK

nLED0

nLED1

nLED2

nLED3

Type

O

Description

Signal Group 1

Signal Group 2

LED signal valid #0

LED signal valid #1

2.5 MHz LED clock

Dual purpose indicator

1

0

-

0

1

-

address learning status

full duplex indication

port speed (1=10Mbps,0=100Mbps)

Link status

frame error indicator

collision indication

receiving activity

transmit activity

aShet:ACD8124

•

1001 - Flow Control/Multiple Collision*

1010 - Short Event/Excessive Collision

1011 - Runt/Late Collision

1100 - Symbol Error

1101 - FCS Error

1110 - Long Event

1111 - Reserved

LED Interface

*

The signals in the LED interface is described in table-

6.10:

Y

The status of each port is displayed on the LED inter-

face for every 50ms. LEDVLD0 and LEDVLD1 are

used to indicate the start and end of the LED data.

LED data is clocked out by the falling edge of LEDCLK,

and should be sampled by the rising edge of LEDCLK.

LED data of port 23 are clocked out first, followed by

port 22 down to port 0. All LED signals are low active.

OR

*

Note: error type depends on whether the port is re-

ceiving or transmitting.

ARLDIx is used to receive the lookup result from the

external ARL. Result is returned by external ARL de-

vice through the ARLDIx lines. Returned data is sampled

by the rising edge of ARLCLK. The ARL result has the

following format:

SID

RSLT

DID

INRODUCT

Where

•

SID is a 5-bit ID of the source port (0 - 23)

RSLT is a 2-bit result, defined as:

00 - reserved

01 - matched

10 - not matched

11 - forced discard

•

DID is a 5-bit ID of the destination port (0 - 23)

The start of each ARL result is indicated by assertion

of ARLDIV signal.

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14

Configuration Interface

Other Interface (Table-6.12)

There are 20 pins whose pull-up or pull-down state will

be used as Power-On-Strobing configuration data (Reg-

ister 25, & CFG0 - CFG19) to specify various working

modes of the ACD82124. The CFG pins are shared

with other functional pins of the ACD82124. The pull-

high or pull-low status of the CFG pins are used to

indicate specific configuration settings, described in

Table-6.11. The register description section will pro-

vide more details about the POS Configuration regis-

ter.

Table-6.12: Other Interface

Name

Type

Description

CLK50

I

50 MHz clock input

nRESET

WCHDOG

VDD

hardware reset

watch dog life pulse signal

3.3 V power

O

-

aShet:ACD8124

VSS

-

ground

CLK50 should come from a clock oscillator, with 0.01%

(100 ppm) accuracy.

Table-6.11: Configuration Interface

Y

Pin Name

P7TXD0

P7TXD1

P7TXD2

P7TXD3

P6TXD0

P6TXD1

P6TXD2

P6TXD3

LEDCLK

LEDVLD0

LEDVLD1

nLED3

Register #

Bit #

Setting

Assertion of the nRESET pin will cause the ACD82124

to go through the power-up initialization process. All

registers are set to their default value after reset.

0

1

2

3

4

5

6

7

8

OR

When the ACD82124 is working properly, it will gener-

ate pulses from the WCHDOG pin continuously. It is

used as a safeguard, so that in case something unex-

pected happens, the external watchdog circuit will re-

set the switch system.

See Table-

7.25

25

9

VDD is 3.3V power supply. VSS is power ground.

10

11

12

13

14

15

16

17

18

0

1

2

3

4

5

6

7

8

nLED2

nLED1

nLED0

INRODUCT

P5TXD0

P5TXD1

P5TXD2

P5TXD3

P2TxD0

P2TxD1

P2TxD2

P2TxD3

P3TxD0

P3TxD1

P3TxD2

P3TxD3

P4TxD0

P4TxD1

P4TxD2

P4TxD3

P0TXD0

P0TXD1

P0TXD2

P0TXD3

P1TXD0

P1TXD1

P1TXD2

P1TXD3

P23TXD0R

P23TXD1R

P23TXD2R

P23TXD3R

See Table-

7.26

26

9

10

11

0

1

2

3

4

5

6

7

0

1

2

See Table-

7.30

30

See Appendix-

A1

20, inside the

Internal ARL

0

3

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15

7. REGISTER DESCRIPTION

Table-7.1: INTSRC Register

Bit

0

1

2

3

4

5

6

Description

System initialization completed

System error occurred

Port partition occurred

ARL Interrupt

Default

Registers in the ACD82124 are used to define the op-

eration mode of various function modules of the switch

controller and the peripheral devices. Default values at

power-on are defined by the factory. The manage-

ment CPU (optional) can read the content of all regis-

ters and modify some of the registers to change the

operation mode. Table-7.0 lists all the registers inside

the switch controller.

0

Reserved

aShet:ACD8124

7

tem errors. It is automatically cleared after each read.

Table-7.2 lists all kind of system error.

INTSRC register (register 1)

The INTSRC register indicates the source of the inter-

rupt request. Before the CPU starts to respond to an

interrupt request, it should read this register to find out

the interrupt source. This register is automatically

cleared after each read. Table-7.1 lists all the bits of

this register.

Y

Table-7.2: SYSERR Register

Bit

0

1

Description

BIST failure indication

Reserved

Default

0

OR

2

Reserved

3

Reserved

4

Reserved

5

Reserved

SYSERR register (register 2)

6

Reserved

7

Reserved

The SYSERR register indicates the presence of sys-

8

Reserved

Table-7.0: Register List

INRODUCT

Address

Name

Type

Size

8 Bit

24 Bit

Depth

Reserved

Description

0

1

2

3

4

5

INTSRC

SYSERR

PAR

PMERR

ACT

R

1

Interrupt Source

System Error

Port Partition Indication

PHY Management Error

Port Avtivity

R

6-15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32-63

Reserved

SYSCFG

INTMSK

SPEED

LINK

nFWD

nBP

nPORT

PVID

VPID

POSCFG

nPAUSE

DPLX

RVSMII

nPM

ERRMSK

CLKADJ

PHYREG

R/W

16 Bit

8 Bit

1

System Configuration

Interrupt Mask

24 Bit

4 Bit

1

Port Speed

1

Port Link

1

Port Forward Disable

Port Back Pressure Disable

Port Disable

24

4

1

Port VLAN ID

5 Bit

VLAN Dumping Port

Power-On-Strobe Configuration

Port Pause Frame Disable

Port Duplex Mode

19 Bit

24 Bit

5 Bit

24 Bit

8 Bit

1

Reversed MII Selection

Port PHY Management Disable

Error Mask

4 Bit

16 Bit

1

24

ARL Clock Delay Adjustment

Registers in PHY device, (REG# - 32)

CfaRpUdN-DicsuAgrmetonly.

16

PAR register (register 3)

PMERR register (register 4)

The PAR register indicates the presence of the parti-

tioned ports and the port ID. A port can be automati-

cally partitioned if there is a consecutive false carrier

event, an excessive collision or a jabber. This register

is automatically cleared after each read. Table-7.3 lists

all the bits of this register.

The PMERR register indicates the presence of PHYs

that have failed to respond to the PHY Management

command issued through the MDIO line. This register

is automatically cleared after each read. Table-7.4

describes all the bit of this register.

aShet:ACD8124

Table-7.3: PAR Register

Table-7.4: PMERR Register

Bit

Description

Default

Bit

Description

Default

0 - Port 0 not partitioned.

1 - Port 0 partitioned.

0 - Port 1 not partitioned.

1 - Port 1 partitioned.

0 - Port 2 not partitioned.

1 - Port 2 partitioned.

0 - Port 3 not partitioned.

1 - Port 3 partitioned.

0 - Port 4 not partitioned.

1 - Port 4 partitioned.

0 - Port 5 not partitioned.

1 - Port 5 partitioned.

0 - Port 6 not partitioned.

1 - Port 6 partitioned.

0 - Port 7 not partitioned.

1 - Port 7 partitioned.

0 - Port 8 not partitioned.

1 - Port 8 partitioned.

0 - Port 9 not partitioned.

1 - Port 9 partitioned.

0 - Port 10 not partitioned.

1 - Port 10 partitioned.

0 - Port 11 not partitioned.

1 - Port 11 partitioned.

0 - Port 12 not partitioned.

1 - Port 12 partitioned.

0 - Port 13 not partitioned.

1 - Port 13 partitioned.

0 - Port 14 not partitioned.

1 - Port 14 partitioned.

0 - Port 15 not partitioned.

1 - Port 15 partitioned.

0 - Port 16 not partitioned.

1 - Port 16 partitioned.

0 - Port 17 not partitioned.

1 - Port 17 partitioned.

0 - Port 18 not partitioned.

1 - Port 18 partitioned.

0 - Port 19 not partitioned.

1 - Port 19 partitioned.

0 - Port 20 not partitioned.

1 - Port 20 partitioned.

0 - Port 21 not partitioned.

1 - Port 21 partitioned.

0 - Port 22 not partitioned.

1 - Port 22 partitioned.

0 - Port 23 not partitioned.

1 - Port 23 partitioned.

0 - Port 0 PHY responded

1 - Port 0 PHY failed to respond

0 - Port 1 PHY responded

1 - Port 1 PHY failed to respond

0 - Port 2 PHY responded

1 - Port 2 PHY failed to respond

0 - Port 3 PHY responded

1 - Port 3 PHY failed to respond

0 - Port 4 PHY responded

1 - Port 4 PHY failed to respond

0 - Port 5 PHY responded

1 - Port 5 PHY failed to respond

0 - Port 6 PHY responded

1 - Port 6 PHY failed to respond

0 - Port 7 PHY responded

1 - Port 7 PHY failed to respond

0 - Port 8 PHY responded

1 - Port 8 PHY failed to respond

0 - Port 9 PHY responded

1 - Port 9 PHY failed to respond

0 - Port 10 PHY responded

1 - Port 10 PHY failed to respond

0 - Port 11 PHY responded

1 - Port 11 PHY failed to respond

0 - Port 12 PHY responded

1 - Port 12 PHY failed to respond

0 - Port 13 PHY responded

1 - Port 13 PHY failed to respond

0 - Port 14 PHY responded

1 - Port 14 PHY failed to respond

0 - Port 15 PHY responded

1 - Port 15 PHY failed to respond

0 - Port 16 PHY responded

1 - Port 16 PHY failed to respond

0 - Port 17 PHY responded

1 - Port 17 PHY failed to respond

0 - Port 18 PHY responded

1 - Port 18 PHY failed to respond

0 - Port 19 PHY responded

1 - Port 19 PHY failed to respond

0 - Port 20 PHY responded

1 - Port 20 PHY failed to respond

0 - Port 21 PHY responded

1 - Port 21 PHY failed to respond

0 - Port 22 PHY responded

1 - Port 22 PHY failed to respond

0 - Port 23 PHY responded

1 - Port 23 PHY failed to respond

0

1

2

1

2

Y

OR

3

4

5

6

7

8

9

INRODUCT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

CfaRpUdN-DicsuAgrmetonly.

17

ACT register (register 5)

SYSCFG register (register 16)

The ACT register indicates the presence of transmit or

receive activities of each port since the register was

last read. This register is automatically cleared after

each read. Table-7.5 describes all the bits of this reg-

ister.

The SYSCFG register specifies certain system con-

figurations. The system options are described in the

chapter of “Function Description.” Table-7.16 describes

all the bit of this register.

aShet:ACD8124

Table-7.16: SYSCFG Register

Table-7.5: ACT Register

Bit

Description

Default

Bit

Description

Default

0 - Port 0 no activity

1 - Port 0 has activity

0 - Port 1 no activity

1 - Port 1 has activity

0 - Port 2 no activity

1 - Port 2 has activity

0 - Port 3 no activity

1 - Port 3 has activity

0 - Port 4 no activity

1 - Port 4 has activity

0 - Port 5 no activity

1 - Port 5 has activity

0 - Port 6 no activity

1 - Port 6 has activity

0 - Port 7 no activity

1 - Port 7 has activity

0 - Port 8 no activity

1 - Port 8 has activity

0 - Port 9 no activity

1 - Port 9 has activity

0 - Port 10 no activity

1 - Port 10 has activity

0 - Port 11 no activity

1 - Port 11 has activity

0 - Port 12 no activity

1 - Port 12 has activity

0 - Port 13 no activity

1 - Port 13 has activity

0 - Port 14 no activity

1 - Port 14 has activity

0 - Port 15 no activity

1 - Port 15 has activity

0 - Port 16 no activity

1 - Port 16 has activity

0 - Port 17 no activity

1 - Port 17 has activity

0 - Port 18 no activity

1 - Port 18 has activity

0 - Port 19 no activity

1 - Port 19 has activity

0 - Port 20 no activity

1 - Port 20 has activity

0 - Port 21 no activity

1 - Port 21 has activity

0 - Port 22 no activity

1 - Port 22 has activity

0 - Port 23 no activity

1 - Port 23 has activity

0

0 - BIST enabled;

1 - BIST disabled.

0 - Spanning Tree support disabled;

1 - Spanning Tree support enabled

Reserved.

0 - wait for CPU.

1 - system ready to start

*This bit is used by the CPU when bit-15 of

register-25 is set as "0" (for system with

control CPU). The system will wait for CPU

to set this bit.

0 - PHY Management not completed

1 - PHY Management completed.

*This bit is used by the CPU when bit-15 of

register-25 is set as "0" (for system with a

control CPU). The MAC will not start until this

bit is set sy the CPU.

0 - Watchdog function enabled.

1 - Watchdog function disabled.

0 - Secure VLAN checking rule enforced.

1 - Leaky VLAN checking rule enforced.

0 - Rising edge of RXCLK to latch data.

1 - Falling edge of RXCLK to latch data.

*For Reversed MII port only.

0

1

0

1

2

Y

2

3

4

5

0

OR

3

4

5

6

0

7

8

9

INRODUCT

7

8

9

0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

10 0 - Late Back-Pressure scheme disabled

1 - Late Back-Pressure scheme enabled

*When enabled, the MAC will generate back-

pressure only after reading the first bit of DA

0

0 - special handling of broadcast frames

disabled

11

1 - special handling of broadcast frames

enabled

*When enabled, all broadcast frames from

non-CPU port are forwarded to the CPU port

only, and all broadcast frames from the CPU

port are forwarded to all other ports.

Software Reset: "1" to start a system reset to

innitialize all state machines.

Hardware Reset: "1" to stop the life pulse on

the watchdog pin, which in turn will trigger the

12

0

13

external watchdog circuitry to reset the whole

system.

14 Reserved

15 Reserved

0

CfaRpUdN-DicsuAgrmetonly.

18

INTMSK register (register 17)

Table-7.18: SPEED Register

Bit

Description

Default

The INTMSK register defines the valid interrupt sources

allowed to assert interrupt request pin. Table-7.17 lists

all the bits of this register.

0 - Port 0 at 10 Mbps

1 - Port 0 at 100 Mbps

0 - Port 1 at 10 Mbps

1 - Port 1 at 100 Mbps

0 - Port 2 at 10 Mbps

1 - Port 2 at 100 Mbps

0 - Port 3 at 10 Mbps

1 - Port 3 at 100 Mbps

0 - Port 4 at 10 Mbps

1 - Port 4 at 100 Mbps

0 - Port 5 at 10 Mbps

1 - Port 5 at 100 Mbps

0 - Port 6 at 10 Mbps

1 - Port 6 at 100 Mbps

0 - Port 7 at 10 Mbps

1 - Port 7 at 100 Mbps

0 - Port 8 at 10 Mbps

1 - Port 8 at 100 Mbps

0 - Port 9 at 10 Mbps

1 - Port 9 at 100 Mbps

0 - Port 10 at 10 Mbps

1 - Port 10 at 100 Mbps

0 - Port 11 at 10 Mbps

1 - Port 11 at 100 Mbps

0 - Port 12 at 10 Mbps

1 - Port 12 at 100 Mbps

0 - Port 13 at 10 Mbps

1 - Port 13 at 100 Mbps

0 - Port 14 at 10 Mbps

1 - Port 14 at 100 Mbps

0 - Port 15 at 10 Mbps

1 - Port 15 at 100 Mbps

0 - Port 16 at 10 Mbps

1 - Port 16 at 100 Mbps

0 - Port 17 at 10 Mbps

1 - Port 17 at 100 Mbps

0 - Port 18 at 10 Mbps

1 - Port 18 at 100 Mbps

0 - Port 19 at 10 Mbps

1 - Port 19 at 100 Mbps

0 - Port 20 at 10 Mbps

1 - Port 20 at 100 Mbps

0 - Port 21 at 10 Mbps

1 - Port 21 at 100 Mbps

0 - Port 22 at 10 Mbps

1 - Port 22 at 100 Mbps

0 - Port 23 at 10 Mbps

1 - Port 23 at 100 Mbps

0

1

2

Table-7.17: INTMSK Register

aShet:ACD8124

3

Bit

Description

Enable "system initialization

completion" to interrupt

Enable "internal system error"

to interrupt

Default

0

1

4

1

2

1

5

Enable "port partition event"

to interrupt

6

Y

3

4

5

6

7

Reserved

1

7

OR

8

Reserved

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

SPEED register (register 18)

0

The SPEED register specifies or indicates the speed

rate of each port. It is read-only, unless the bit-12 of

register-25 is set (through POS to disable automatic

PHY management). At read-only mode, it indicates

the speed achieved through PHY management. At the

write-able mode, the control CPU will be able to assign

speed rate for each port. Table-7.18 describes all the

bit of this register.

INRODUCT

LINK register (register 19)

The LINK register specifies or indicates the link status

of each port. It is read-only, unless bit-12 of register-

25 is set (through POS, to disable automatic PHY man-

agement). At read-only mode, it indicates the result

achieved by PHY management. At write-able mode,

CfaRpUdN-DicsuAgrmetonly.

19

the control CPU can assign link status for each port.

Table-7.19 describes all the bit of this register.

all frames. Under block-and-listen mode, a port will

not forward regular frames, except BPDU frames. If

the spanning tree algorithm discovers redundant links,

the control CPU will allow only one link remaining in

forwarding mode and force all other links into block-

and-listen mode. Setting the associated bit in this reg-

ister will put the port into block-and-listen mode. Table-

7.20 describes all the bit of this register.

nFWD register (register 20)

The nFWD register defines the forwarding mode of

each port. Under forwarding mode, a port can forward

aShet:ACD8124

Table-7.19: LINK Register

Table-7.20: nFWD Register

Bit

Description

Default

Bit

Description

Default

0 - Port 0 link not established

1 - Port 0 link established

0 - Port 1 link not established

1 - Port 1 link established

0 - Port 2 link not established

1 - Port 2 link established

0 - Port 3 link not established

1 - Port 3 link established

0 - Port 4 link not established

1 - Port 4 link established

0 - Port 5 link not established

1 - Port 5 link established

0 - Port 6 link not established

1 - Port 6 link established

0 - Port 7 link not established

1 - Port 7 link established

0 - Port 8 link not established

1 - Port 8 link established

0 - Port 9 link not established

1 - Port 9 link established

0 - Port 10 link not established

1 - Port 10 link established

0 - Port 11 link not established

1 - Port 11 link established

0 - Port 12 link not established

1 - Port 12 link established

0 - Port 13 link not established

1 - Port 13 link established

0 - Port 14 link not established

1 - Port 14 link established

0 - Port 15 link not established

1 - Port 15 link established

0 - Port 16 link not established

1 - Port 16 link established

0 - Port 17 link not established

1 - Port 17 link established

0 - Port 18 link not established

1 - Port 18 link established

0 - Port 19 link not established

1 - Port 19 link established

0 - Port 20 link not established

1 - Port 20 link established

0 - Port 21 link not established

1 - Port 21 link established

0 - Port 22 link not established

1 - Port 22 link established

0 - Port 23 link not established

1 - Port 23 link established

0 - Port 0 in forwarding state

1 - Port 0 in block-and-listen state

0 - Port 1 in forwarding state

1 - Port 1 in block-and-listen state

0 - Port 2 in forwarding state

1 - Port 2 in block-and-listen state

0 - Port 3 in forwarding state

1 - Port 3 in block-and-listen state

0 - Port 4 in forwarding state

1 - Port 4 in block-and-listen state

0 - Port 5 in forwarding state

1 - Port 5 in block-and-listen state

0 - Port 6 in forwarding state

1 - Port 6 in block-and-listen state

0 - Port 7 in forwarding state

1 - Port 7 in block-and-listen state

0 - Port 8 in forwarding state

1 - Port 8 in block-and-listen state

0 - Port 9 in forwarding state

1 - Port 9 in block-and-listen state

0 - Port 10 in forwarding state

1 - Port 10 in block-and-listen state

0 - Port 11 in forwarding state

1 - Port 11 in block-and-listen state

0 - Port 12 in forwarding state

1 - Port 12 in block-and-listen state

0 - Port 13 in forwarding state

1 - Port 13 in block-and-listen state

0 - Port 14 in forwarding state

1 - Port 14 in block-and-listen state

0 - Port 15 in forwarding state

1 - Port 15 in block-and-listen state

0 - Port 16 in forwarding state

1 - Port 16 in block-and-listen state

0 - Port 17 in forwarding state

1 - Port 17 in block-and-listen state

0 - Port 18 in forwarding state

1 - Port 18 in block-and-listen state

0 - Port 19 in forwarding state

1 - Port 19 in block-and-listen state

0 - Port 20 in forwarding state

1 - Port 20 in block-and-listen state

0 - Port 21 in forwarding state

1 - Port 21 in block-and-listen state

0 - Port 22 in forwarding state

1 - Port 22 in block-and-listen state

0 - Port 23 in forwarding state

1 - Port 23 in block-and-listen state

0

1

2

1

2

Y

OR

3

4

5

6

7

8

9

INRODUCT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

CfaRpUdN-DicsuAgrmetonly.

20

nPORT register (register 22)

nBP register (register 21)

The nPORT register is used to isolate ports from the

network. Setting the associated bit in this register will

stop a port from receiving or transmitting any frame.

Table-7.22 describes all the bits of this register.

The nBP register defines back-pressure flow control

capability for each port. Table-7.21 describes all the

bit of this register.

aShet:ACD8124

Table-7.21: nBP Register

Table-7.22: nPort Register

Bit

Description

Default

Bit

Description

Default

0 - Port 0 back-pressure scheme enabled

1 - Port 0 back-pressure scheme disabled

0 - Port 1 back-pressure scheme enabled

1 - Port 1 back-pressure scheme disabled

0 - Port 2 back-pressure scheme enabled

1 - Port 2 back-pressure scheme disabled

0 - Port 3 back-pressure scheme enabled

1 - Port 3 back-pressure scheme disabled

0 - Port 4 back-pressure scheme enabled

1 - Port 4 back-pressure scheme disabled

0 - Port 5 back-pressure scheme enabled

1 - Port 5 back-pressure scheme disabled

0 - Port 6 back-pressure scheme enabled

1 - Port 6 back-pressure scheme disabled

0 - Port 7 back-pressure scheme enabled

1 - Port 7 back-pressure scheme disabled

0 - Port 8 back-pressure scheme enabled

1 - Port 8 back-pressure scheme disabled

0 - Port 9 back-pressure scheme enabled

1 - Port 9 back-pressure scheme disabled

0 - Port 10 back-pressure scheme enabled

1 - Port 10 back-pressure scheme disabled

0 - Port 11 back-pressure scheme enabled

1 - Port 11 back-pressure scheme disabled

0 - Port 12 back-pressure scheme enabled

1 - Port 12 back-pressure scheme disabled

0 - Port 13 back-pressure scheme enabled

1 - Port 13 back-pressure scheme disabled

0 - Port 14 back-pressure scheme enabled

1 - Port 14 back-pressure scheme disabled

0 - Port 15 back-pressure scheme enabled

1 - Port 15 back-pressure scheme disabled

0 - Port 16 back-pressure scheme enabled

1 - Port 16 back-pressure scheme disabled

0 - Port 17 back-pressure scheme enabled

1 - Port 17 back-pressure scheme disabled

0 - Port 18 back-pressure scheme enabled

1 - Port 18 back-pressure scheme disabled

0 - Port 19 back-pressure scheme enabled

1 - Port 19 back-pressure scheme disabled

0 - Port 20 back-pressure scheme enabled

1 - Port 20 back-pressure scheme disabled

0 - Port 21 back-pressure scheme enabled

1 - Port 21 back-pressure scheme disabled

0 - Port 22 back-pressure scheme enabled

1 - Port 22 back-pressure scheme disabled

0 - Port 23 back-pressure scheme enabled

1 - Port 23 back-pressure scheme disabled

0 - Port 0 enabled

1 - Port 0 disabled

0 - Port 1 enabled

1 - Port 1 disabled

0 - Port 2 enabled

1 - Port 2 disabled

0 - Port 3 enabled

1 - Port 3 disabled

0 - Port 4 enabled

1 - Port 4 disabled

0 - Port 5 enabled

1 - Port 5 disabled

0 - Port 6 enabled

1 - Port 6 disabled

0 - Port 7 enabled

1 - Port 7 disabled

0 - Port 8 enabled

1 - Port 8 disabled

0 - Port 9 enabled

1 - Port 9 disabled

0 - Port 10 enabled

1 - Port 10 disabled

0 - Port 11 enabled

1 - Port 11 disabled

0 - Port 12 enabled

1 - Port 12 disabled

0 - Port 13 enabled

1 - Port 13 disabled

0 - Port 14 enabled

1 - Port 14 disabled

0 - Port 15 enabled

1 - Port 15 disabled

0 - Port 16 enabled

1 - Port 16 disabled

0 - Port 17 enabled

1 - Port 17 disabled

0 - Port 18 enabled

1 - Port 18 disabled

0 - Port 19 enabled

1 - Port 19 disabled

0 - Port 20 enabled

1 - Port 20 disabled

0 - Port 21 enabled

1 - Port 21 disabled

0 - Port 22 enabled

1 - Port 22 disabled

0 - Port 23 enabled

1 - Port 23 disabled

0

1

2

1

2

Y

OR

3

4

5

6

7

8

9

INRODUCT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

CfaRpUdN-DicsuAgrmetonly.

21

PVID registers (register 23)

The PVID registers assign VLAN IDs for each port.

There are 24 PVID registers, one for each port. A

PVID consists of 4 bits, each corresponding to one of

the 4 VLANs. A port can belong to more than one

VLAN at the same time. Table-7.23 describes the bits

of one of the registers.

aShet:ACD8124

(24 registers)

Table-7.23: PVID Registers

Bit

Description

Default

0

0 - port not in VLAN-I.

1 - port in VLAN-I.

1

Y

1

2

3

0 - port not in VLAN-II.

1 - port in VLAN-II.

0 - port not in VLAN-III.

1 - port in VLAN-III.

0 - port not in VLAN-IV.

1 - port in VLAN-IV.

0

OR

VPID registers (register 24)

The VPID registers specify the dumping port for each

VLAN. There are 4 VPID 5-bit registers, one for each

VLAN. A valid VPID are “0” through “23” (other values

are reserved and should not used). Table-7.24 de-

scribes the bits one of the registers.

INRODUCT

(4 registers)

Table-7.24: VPID Registers

Bit

4:0

Description

Default

"00000"

"11111"

Dumping port ID for VLAN-1

Dumping port ID for VLAN-2

Dumping port ID for VLAN-3

Dumping port ID for VLAN-4

dumping port

not defined

CfaRpUdN-DicsuAgrmetonly.

22

Table-7.25: POSCFG Register

Bit

Description

Default

3:0

8 timing adjustment levels for SRAM Read data latching:

0000 - no delay

0000

0001 - level 1 delay

0011 - level 2 delay

0101 - level 3 delay

0111 - level 4 delay

1001 - level 5 delay

aShet:ACD8124

1011 - level 6 delay

1101 - level 7 delay

1111 - level 8 delay

4

0 - Absolute address mode: 1 row of 512K words, nCS2=ADDR17, nCS3=ADDR18

1 - Chip-Select address mode: 4 rows of 128K words, nCS[3:0] to select 4 rows of memory

SRAM size selection:

0

6:5

000

Y

00 - 64K words

01 - 128K words

10 - 256k words

OR

11 - 512K words

7

8

0 - Long Event defined as frame longer than 1518 byte.

1 - Long Event defined as frame longer than 1530 byte.

0 - Frames with unknown DA forwarded to the dumping port.

1 - Frames with unknown DA forwarded to all ports.

0 - Internal ARL selected (2K MAC address entry).

1 - External ARL selected (11K MAC address entry).

0 - PHY IDs start from 1, range from 1 to 24.

1 - PHY IDs start from 4, range from 4 to 27.

0 - Re-transmit after excessive collision.

1 - Drop after excessive collision.

0

9

10

11

12

0 - Automatic PHY Management enabled

1 - Automatic PHY Management disabled: the control CPU need to update the SPEED, LINK, DPLX and

nPAUSE registers

INRODUCT

13

14

15

0 - Rising edge of RxClk triggering for regular MII ports

0 - Falling edge of RxClk triggering for regular MII ports

0 - Sysem errors will trigger software reset

1 - Sysem errors will trigger hardware reset

0 - System start itself without a control CPU

1 - System start after system-ready bit in register-16 is set by the control CPU

2-bit device ID for UART communication. The device responses only to UART commands with

matching ID

0

17:16

18

00

0

0 - Rising edge of ARLCLK to latch ARLDI.

1 - Falling edge of ARLCLK to latch ARLDI.

default value of FdCfg is determined by Pull-High or

Pull-Low status of the hardware pins shown in Table-

26.

POSCFG register (register 25)

The POSCFG register specifies a certain configura-

tion setting for the switch system. The default values of

this register can be changed through pull-up/pull-down

of specific pins, as described in the “Configuration

Interface” section of the “Interface Description” chap-

ter. Table-7.25 describes all the bit of this register.

DPLX register (register 27)

The DPLX register specifies or indicates the half/full-

duplex mode of each of the 12 even-numbered ports

(port 0, 2, 4, .. 20 and 22). It is read-only, unless bit-

12 of register-25 is set (through POS, to disable auto-

matic PHY management). At read-only mode, it indi-

cates the result achieved by the PHY management. At

write-able mode, the control CPU can assign a half-

duplex or full-duplex mode for each of the 12 even-

FdEn register (register 26)

FdEn register is used to specify if an even numbered

port has been connected as a full duplex port. The

CfaRpUdN-DicsuAgrmetonly.

23

Table-7.26: FdEn Register

Bit

Description

Default

0 - Port 0 & 1 each in Half-Duplex mode

1 - Port 0 & 1 paired into ONE Full-Duplex-Capable port

0 - Port 2 & 3 each in Half-Duplex mode

1 - Port 2 & 3 paired into ONE Full-Duplex-Capable port

0 - Port 4 & 5 each in Half-Duplex mode

1 - Port 4 & 5 paired into ONE Full-Duplex-Capable port

0 - Port 6 & 7 each in Half-Duplex mode

1 - Port 6 & 7 paired into ONE Full-Duplex-Capable port

0 - Port 8 & 9 each in Half-Duplex mode

1 - Port 8 & 9 paired into ONE Full-Duplex-Capable port

0 - Port 10 & 11 each in Half-Duplex mode

1 - Port 10 & 11 paired into ONE Full-Duplex-Capable port

0 - Port 12 & 13 each in Half-Duplex mode

1 - Port 12 & 13 paired into ONE Full-Duplex-Capable port

0 - Port 14 & 15 each in Half-Duplex mode

1 - Port 14 & 15 paired into ONE Full-Duplex-Capable port

0 - Port 16 & 17 each in Half-Duplex mode

1 - Port 16 & 17 paired into ONE Full-Duplex-Capable port

0 - Port 18 & 19 each in Half-Duplex mode

1 - Port 18 & 19 paired into ONE Full-Duplex-Capable port

0 - Port 20 & 21 each in Half-Duplex mode

1 - Port 20 & 21 paired into ONE Full-Duplex-Capable port

0 - Port 22 & 23 each in Half-Duplex mode

0

1

2

aShet:ACD8124

3

4

5

0

6

Y

7

OR

8

9

10

11

1 - Port 22 & 23 paired into ONE Full-Duplex-Capable port

INRODUCT

Table-7.27: DPLX Register

Bit

Description

Default

0 - Port 0 & 1 run as TWO independant Half-Duplex ports

1 - Port 0 & 1 pair run as ONE Full-Duplex port

0 - Port 2 & 3 run as TWO independant Half-Duplex ports

1 - Port 2 & 3 pair run as ONE Full-Duplex port

0

1

0 - Port 4 & 5 run as TWO independant Half-Duplex ports

1 - Port 4 & 5 pair run as ONE Full-Duplex port

2

0 - Port 6 & 7 run as TWO independant Half-Duplex ports

1 - Port 6 & 7 pair run as ONE Full-Duplex port

3

0 - Port 8 & 9 run as TWO independant Half-Duplex ports

1 - Port 8 & 9 pair run as ONE Full-Duplex port

4

0 - Port 10 & 11 run as TWO independant Half-Duplex ports

1 - Port 10 & 11 pair run as ONE Full-Duplex port

0 - Port 12 & 13 run as TWO independant Half-Duplex ports

1 - Port 12 & 13 pair run as ONE Full-Duplex port

5

0

6

0 - Port 14 & 15 run as TWO independant Half-Duplex ports

1 - Port 14 & 15 pair run as ONE Full-Duplex port

7

0 - Port 16 & 17 run as TWO independant Half-Duplex ports

1 - Port 16 & 17 pair run as ONE Full-Duplex port

8

0 - Port 18 & 19 run as TWO independant Half-Duplex ports

1 - Port 18 & 19 pair run as ONE Full-Duplex port

9

0 - Port 20 & 21 run as TWO independant Half-Duplex ports

1 - Port 20 & 21 pair run as ONE Full-Duplex port

0 - Port 22 & 23 run as TWO independant Half-Duplex ports

1 - Port 22 & 23 pair run as ONE Full-Duplex port

10

11

CfaRpUdN-DicsuAgrmetonly.

24

number ports. Table-7.27 describes all the bits of this

register.

Table-7.29: nPM Register

Bit

Description

Default

0 - Port 0 status update enabled

1 - Port 0 status update disabled

0 - Port 1 status update enabled

1 - Port 1 status update disabled

0 - Port 2 status update enabled

1 - Port 2 status update disabled

0 - Port 3 status update enabled

1 - Port 3 status update disabled

0 - Port 4 status update enabled

1 - Port 4 status update disabled

0 - Port 5 status update enabled

1 - Port 5 status update disabled

0 - Port 6 status update enabled

1 - Port 6 status update disabled

0 - Port 7 status update enabled

1 - Port 7 status update disabled

0 - Port 8 status update enabled

1 - Port 8 status update disabled

0 - Port 9 status update enabled

1 - Port 9 status update disabled

0 - Port 10 status update enabled

1 - Port 10 status update disabled

0 - Port 11 status update enabled

1 - Port 11 status update disabled

0 - Port 12 status update enabled

1 - Port 12 status update disabled

0 - Port 13 status update enabled

1 - Port 13 status update disabled

0 - Port 14 status update enabled

1 - Port 14 status update disabled

0 - Port 15 status update enabled

1 - Port 15 status update disabled

0 - Port 16 status update enabled

1 - Port 16 status update disabled

0 - Port 17 status update enabled

1 - Port 17 status update disabled

0 - Port 18 status update enabled

1 - Port 18 status update disabled

0 - Port 19 status update enabled

1 - Port 19 status update disabled

0 - Port 20 status update enabled

1 - Port 20 status update disabled

0 - Port 21 status update enabled

1 - Port 21 status update disabled

0 - Port 22 status update enabled

1 - Port 22 status update disabled

0 - Port 23 status update enabled

1 - Port 23 status update disabled

0

RVSMII register (register 28)

1

2

The RVSMII register defines the reversed MII mode

for each port. Table-7.28 describes all the bits of this

register.

aShet:ACD8124

3

4

Table-7.28: RVSMII register

Bit

Description

Default

5

0

0 - Port 0 under normal MII mode

1 - Port 0 under reversed MII mode

0 - Port 1under normal MII mode

1 - Port 1 under reversed MII mode

0 - Port 2 under normal MII mode

1 - Port 2under reversed MII mode

0 - Port 3 under normal MII mode

1 - Port 3 under reversed MII mode

0 - Port 4 under normal MII mode

1 - Port 4 under reversed MII mode

1 - Port 5 under normal MII mode

2 - Port 5 under reversed MII mode

1 - Port 6 under normal MII mode

2 - Port 6 under reversed MII mode

1 - Port 7 under normal MII mode

2 - Port 7 under reversed MII mode

1 - Port 22 under normal MII mode

2 - Port 22 under reversed MII mode

1 - Port 23 under normal MII mode

2 - Port 23 under reversed MII mode

0

6

Y

1

2

3

4

5

6

7

8

9

0

7

OR

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

0

INRODUCT

nPM register (register 29)

The nPM register indicates the automatic PHY man-

agement capability of each port. If a bit is set in this

register, the corresponding SPEED, LINK, DPLX, and

nPAUSE status registers of a port will remain un-

changed. Table-7.29 describes all the bits of this reg-

ister.

CfaRpUdN-DicsuAgrmetonly.

25

ERRMSK register (register 30)

PHYREG registers (register 32-63)

The ERRMSK register defines certain errors as sys-

tem errors. It is reserved for factory use only. Table-

7.30 lists all the error masks specified by this register.

The PHYREG refers to the registers residing on the

PHY devices. There are 24 sets of these registers.

Each port has its own corresponding set of register

32-63. The ACD82124 merely provides an access path

for the control CPU to access the registers on the

PHYs. For detailed information about these registers,

please refer to the PHY data sheet.

Table-7.30: ERRMSK register

aShet:ACD8124

Bit

0

1

2

3

4

5

6

Description

Reserved

Setting

All "1", unless

otherwise

advised, to

ensure proper

operation.

Since the native registers ID “0” through “31” on the

PHYs have been used by the internal registers of the

ACD82124, they need to be re-mapped into “32”

through “63” by adding “32” to each original register

ID. An index is used by the ACD82124 to specify the

PHY ID. For example, register-32 with index-4 would

refer to the control register (register-0) in the PHY-4.

Y

7

0

OR

CLKADJ register (register 31)

The CLKADJ register defines the delay time of the

ARLCLK relative to the transition edge of the data sig-

nals. The ARLCLK provides reference timing for sup-

porting chips, such as the ACD80800 and the

ACD80900, which need to snoop the data bus for cer-

tain activities. Table-7.31 describes all the bits of this

register.

INRODUCT

Table-7.31: CLKADJ Register

Bit

0

Description

0 - ARLCLK not inverted

1 - ARLCLK inverted

ARLCLK delay levels:

000 - level 0 delay

001 - level 1 delay

010 - level 2 delay

011 - level 3 delay

100 - level 4 delay

101 - level 5 delay

110 - level 6 delay

111 - level 7 delay

Default

0

3:1

000

CfaRpUdN-DicsuAgrmetonly.

26

8. PIN DESCRIPTIONS

aShet:ACD8124

Pin Diagram

Bottom View

30

Y

29

28

26

27

25

23

21

19

17

15

13

11

9

OR

24

22

20

18

16

INRODUCT

14

12

10

8

7

6

5

4

2

3

1

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

AB

AC

AK

AH

AF

AD

AJ

AG

AE

AA

CfaRpUdN-DicsuAgrmetonly.

27

Pin List By Location: Part 1

Signal

Name

P23RXD0R

VDD

I/O

Type

I

Signal

Name

I/O

Type

I

O

I

O

I

O

I

O

I

O

I

O

I

O

I/O

I

Signal

Name

P16T XD1

VDD

P15RXCL K

P15T XD3

P14RXD0

P14T XE N

DAT A48

DAT A47

ARL DI3

ARL CL K

ARL S YNC

VS S

P23RXE RR

VS S

P22RXD1R

VS S

P22CRS R

VS S

P21COL

VS S

P20T XD3

VS S

P18RXD2

VS S

P18T XD3

VS S

P17T XD0

VS S

P16T XCL K

VS S

I/O

Type

O

Signal

Name

DAT A40

DAT A39

ADDR2

nCS 3

VDD

VS S

VSS

VDD

P13RXD0

P13T XCL K

P13T XD1

P13T XD2

DAT A38

DAT A37

ADDR3

nCS 2

I/O

Type

I/O

O

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B 19

B20

B 21

B22

B 23

B24

B25

B 26

B27

B28

B29

B30

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

E 01

E 02

E 03

E04

E 05

E 06

E 07

E 08

E 09

E 10

E 11

E 12

E 13

E14

E 15

E 16

E 17

E 18

E 19

E 20

E 21

E 22

E 23

E 24

P20RXCL K

P20T XD0

P19RXD3

P19RXCL K

P19T XD0

P19COL

P18RXD1

P18RXE R

P18T XD1

P17RXD2

P17RXCL K

P17T XD2

P17CRS

P16RXD0

P16T XD3

P15RXD2

P15T XD0

P15COL

S T AT 3

E 25

E 26

E 27

E 28

E 29

E 30

F 01

F 02

F 03

F 04

F 05

F 06

F 07

F 08

F 09

F 10

F 11

F 12

F 13

F 14

F 15

F 16

F 17

F 18

F 19

F 20

F 21

F 22

F 23

F 24

F 25

F 26

F 27

F 28

F 29

F 30

G01

G02

G03

G04

G05

G06

G25

G26

G27

G28

G29

G30

H01

H02

H03

H04

H05

H06

H25

H26

H27

H28

H29

H30

J01

J02

J03

J 04

J05

J06

J25

J26

J27

J28

J29

J30

K01

K 02

K03

K04

K05

K06

K25

K26

K27

K28

K29

K30

L 01

L 02

L 03

L 04

L05

L 06

L 25

L 26

L 27

L 28

L 29

L 30

M01

M02

M03

M04

M05

M06

M25

M26

M27

M28

M29

M30

N01

N02

N03

N04

N05

N06

N25

N26

N27

N28

N29

N30

P01

P02

P 03

P04

P 05

P06

P25

P 26

P27

P28

P29

P30

R01

R02

R03

R 04

R05

R06

R25

R26

R27

R28

R29

R30

P23T XD2R

P22RXD3R

P22RXE RR

P22T XD1R

P22T XD3R

P21RXD0

P21T XCL K

P21T XD0

P20RXD3

P20RXD0

P20T XCL K

P20T XD2

P19RXD1

P19RXD0

P19T XCL K

P19T XD2

VS S

P18RXDV

P18T XE N

P18CRS

P17RXD1

P17RXE R

P17T XD3

P16RXD2

P16RXE R

P16T XD0

P16CRS

O

I

O

I

O

I

O

I

O

I

O

I

O

I/O

I

O

aShet:ACD8124

I

O

I/O

O

I

Y

I/O

I

VDD

VS S

P13RXD2

P13RXD1

P13T XE N

P13T XD3

P13COL

P12RXD1

DAT A36

DAT A35

nCS 0

ADDR16

VDD

VS S

VDD

P13CRS

P12RXD0

P12RXDV

P12RXCL K

DAT A34

DAT A33

VDD

ADDR15

VDD

VS S

P12RXD3

P12RXD2

P12RXE R

P12T XCL K

P12T XE N

P12T XD0

DAT A32

DAT A31

nWE

I

O

I

O

I

O

I

O

I

O

I

I/O

O

I

I/O

O

I

DAT A51

ARL DI0

OR

O

P23RXD3R

P23RXCL KR

P23T XD0R

P23COL R

P22RXDVR

P22T XD0R

P21RXD2

P21RXE R

P21T XD3

P20RXDV

P20T XE N

P20CRS

I

I/O

O

I/O

I

O

I

O

I

O

I

O

I

O

I

O

I

O

I

I/O

O

P15RXD0

S T AT 0

P23RXD1R

P23T XCL KR

P23T XD3R

P22RXD2R

P22T XCL KR

P22T XD2R

P21RXD1

P21RXDV

P21T XE N

P21T XD2

P20RXD1

P20RXE R

P20T XD1

P19RXD2

P19RXE R

P19T XE N

P19T XD3

VDD

P18RXCL K

P 18T XD0

P17RXD3

P 17RXDV

P17T XCL K

P17COL

P 16RXD1

P16T XE N

P16COL

P15RXD1

P15T XE N

S T AT 1

STAT2

P23RXD2R

VS S

P23T XD1R

P23CRS R

P22RXCL KR

P22T XE NR

P22COL R

P21RXCL K

P21T XD1

P20RXD2

P15RXDV

P15T XD2

P14RXD2

P14T XD0

P14T XD3

DAT A46

DAT A45

ARL DIR0

ARL DIR1

VDD

I

O

I

O

I/O

O

I

I/O

P19RXDV

P19T XD1

P19CRS

INRODUCT

P18RXD0

P18T XCL K

P18COL

P17RXD0

P17T XD1

P16RXD3

P16RXCL K

P16T XD2

P15RXD3

P15T XCL K

P15CRS

P14RXD1

DAT A50

DAT A49

ARL DI2

ARLDI1

VDD

P23RXDVR

P23T XE NR

VDD

P22RXD0R

VDD

P21RXD3

VDD

P21CRS

VDD

P20COL

VDD

P18RXD3

VDD

I

O

I

O

I

O

VS S

P15RXE R

P15T XD1

P14RXD3

P14T XCL K

P14COL

P14CRS

DAT A44

DAT A43

ADDR0

ARLDIV

VDD

VS S

VDD

P14RXE R

P14T XD1

P13RXDV

P13RXCL K

DAT A42

DATA41

ADDR1

nCS 1

VDD

VS S

I

O

I

O

I/O

O

I

I/O

I

I/O

O

I

O

I

O

I

VSS

VDD

VS S

I

O

VDD

I

O

I

P12T XD1

P12T XD2

P12T XD3

P12COL

DAT A30

DAT A29

ADDR4

nOE

O

I

I/O

O

I/O

O

I /O

O

I/O

O

I/O

I

VDD

VS S

I

O

I

P14RXDV

P14RXCL K

P14T XD2

P13RXD3

P13RXE R

P13T XD0

I

O

I

O

P12CRS

P11RXD3

P11RXD2

P11RXD1

P11RXD0

P11RXDV

I

P18T XD2

VDD

P17T XE N

VDD

O

I

P16RXDV

CfaRpUdN-DicsuAgrmetonly.

28

Pin List By Location: Part 2

Signal

Name

I/O

Type

Signal

Name Type

I/O

Signal

Name

I/O

Type

Signal

Name

I/O

Type

T 01

T 02

T 03

T04

T 05

T 06

T 25

T 26

T 27

T 28

T 29

T 30

U01

U02

U03

U04

U05

U06

U25

U26

U27

U28

U29

U30

V01

V02

V03

V04

V05

V06

V25

V26

V27

DAT A28

DAT A27

ADDR5

ADDR14

VDD

VS S

VDD

P11RXE R

P11T XCL K

P11T XE N

P11RXCL K

DAT A26

DAT A25

ADDR6

ADDR13

VDD

I/O

O

AB 01

AB 02

AB03

AB04

AB05

AB 06

AB25

AB 26

AB27

AB28

AB29

AB30

AC01

AC02

AC03

AC04

AC05

AC06

AC25

AC26

AC27

AC28

AC29

AC30

AD01

AD02

AD03

AD04

AD05

AD06

AD25

AD26

AD27

AD28

AD29

AD30

AE 01

AE 02

AE 03

AE04

AE 05

AE 06

AE07

AE 08

AE 09

AE 10

AE 11

AE 12

AE 13

AE14

AE 15

AE 16

AE 17

AE18

AE 19

AE 20

AE 21

AE 22

AE 23

AE 24

AE 25

AE 26

AE 27

AE 28

AE 29

AE 30

AF 01

AF 02

AF 03

AF 04

AF 05

AF 06

DAT A16

DAT A15

VDD

LED3

VDD

VS S

VDD

P9T XCL K

P9RXCL K

P9RXDV

P9RXD0

DAT A14

DAT A13

L E D2

LED0

VDD

VS S

I/O

AF 07

AF 08

AF 09

AF 10

AF 11

AF 12

AF 13

AF 14

AF 15

AF 16

AF 17

AF 18

AF 19

AF 20

AF21

AF22

AF 23

AF 24

AF 25

AF 26

AF 27

AF 28

AF 29

AF 30

AG01

AG02

AG03

AG04

AG05

AG06

AG07

AG08

AG09

AG10

AG11

AG12

AG13

AG14

AG15

AG16

AG17

AG18

AG19

AG20

AG21

AG22

AG23

AG24

AG25

AG26

AG27

AG28

AG29

AG30

AH01

AH02

AH03

AH04

AH05

AH06

AH07

AH08

AH09

AH10

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

P0T XE NR

VDD

P1T XD3R

VDD

P1RXD3R

VDD

P2RXD1R

VDD

P3RXD3R

VDD

P4RXD2R

VDD

P5RXD1R

VDD

P6RXCLKR

VDD

P7T XD1R

P7RXE RR

VDD

O

AH19

AH20

AH21

AH22

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AJ01

AJ02

AJ03

AJ04

AJ05

AJ06

AJ07

AJ08

AJ09

AJ10

AJ11

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

AJ30

AK01

AK02

AK03

AK04

AK05

AK06

AK07

AK08

AK09

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

AK18

AK 19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

AK30

P4RXD0R

P 5T XD3R

P5TXCLKR

P 5RXD3R

P6T XD1R

P6T XCL KR

P6RXD2R

P7T XD3R

VDD

P7RXD0R

P7RXD3R

P8T XD2

DAT A2

DAT A1

I

I/O

I

I/O

I

I/O

I

O

I/O

I

aShet:ACD8124

I/O

I

O

I

I/O

O

I

O

I/O

I

I/O

I

VSS

I/O

P0T XD3R

P0RXE RR

P0RXD1R

P1T XD2R

P1T XE NR

P1RXDVR

P2COL R

P2T XD0R

P2RXCL KR

P3CRSR

P3T XD1R

P3T XENR

P3RXD0R

P4T XD3R

P4TXENR

P4RXDVR

P5COLR

P5T XD1R

P5RXE RR

P5RXDVR

P6COLR

I/O

I

I/O

O

I

I/O

O

I

I/O

O

Y

VS S

VDD

I/O

I

VDD

OR

P11T XD3

P11T XD2

P11T XD1

P11T XD0

DAT A24

DAT A23

ADDR7

ADDR12

VDD

O

P9T XD3

P9T XD0

P9T XE N

P9RXE R

DAT A12

DAT A11

L E D1

L E DVL D0

VDD

VS S

P8T XD0

P8RXE R

P8RXD1

P9COL

P9T XD2

P9T XD1

DAT A10

DAT A9

L E DVL D1

LEDCLK

VS S

P0T XD2R

VS S

P1COL R

VS S

P1RXD2R

VS S

P2RXD0R

VSS

VS S

P4CRS R

VS S

P4RXD3R

VS S

P5RXD2R

VS S

P6RXDVR

VS S

P8T XD3

P8T XCL K

P8RXD2

P8RXD3

P9CRS

DAT A8

DAT A7

CPUDI

CP UDO

VDD

O

P8COL

I

P8RXCL K

P8RXDV

P8RXD0

DAT A6

DAT A5

CPUIRQ

MDC

O

I

I/O

O

I/O

O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

O

nRE S E T

P0T XD0R

P0RXDVR

P1CRS R

P1T XCL KR

P1RXD1R

P2T XD2R

P2T XCL KR

P2RXD2R

P3T XD3R

P3RXE RR

P3RXD2R

P4T XD1R

P4RXE RR

P5CRSR

P5T XE NR

P5RXD0R

P6T XD2R

P6RXE RR

P6RXD3R

P7T XD2R

P7TXCLKR

P7RXD1R

P8CRS

VS S

P10RXD0

P10RXD1

P10RXD2

P10RXD3

P11CRS

P11COL

DAT A22

DAT A21

ADDR8

ADDR11

VDD

I

O

I

I/O

I

V28

V29

V30

I

O

I/O

I

INRODUCT

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

O

W01

W02

W03

W04

W05

W06

W25

W26

W27

W28

W29

W30

Y01

Y02

Y03

Y04

Y05

Y06

Y25

Y26

Y27

I/O

O

P6T XD0R

P6RXD0R

P7CRS R

P7T XD0R

P7RXDVR

P7RXD2R

DAT A0

VS S

VSS

VDD

I/O

I

I/O

O

I

I/O

I

CL K50

P0COL R

P10T XCL K

P10RXE R

P10RXCL K

P10RXDV

DAT A20

DAT A19

ADDR9

ADDR10

VDD

I

P0T XD1R

P0RXCL KR

P0RXD2R

P1T XD1R

P1RXERR

P1RXD0R

P2T XD3R

P2T XE NR

P2RXDVR

P3COLR

P3T XD0R

P3RXCLKR

P3RXDVR

P4COLR

P4T XD0R

P4RXCL K R

P4RXD1R

P5T XD2R

P5T XD0R

P5RXCLKR

P6CRS R

I

I/O

O

I

I/O

I

I/O

I

P8T XD1

P8T XEN

DAT A4

DAT A3

MDIO

O

I/O

O

I/O

I

VSS

I

P9RXD2

P9RXD3

P10T XD2

P10T XD1

P10T XD0

P10T XE N

DAT A18

DAT A17

VDD

VS S

VDD

VS S

I

I/O

I

I/O

I

I/O

O

I/O

Y28

Y29

Y30

WCHDOG

P0T XCL KR

P0RXD0R

P0RXD3R

P1T XD0R

P1RXCL KR

P2CRS R

P2T XD1R

P2RXE RR

P2RXD3R

P3T XD2R

P3T XCL KR

P3RXD1R

P4T XD2R

P4TXCLKR

AA01

AA02

AA03

AA04

AA05

AA06

AA25

AA26

AA27

AA28

AA29

AA30

I

O

I

I/O

I

I/O

I

P6T XD3R

P6TXENR

P6RXD1R

P7COL R

P7TXENR

P7RXCLKR

VDD

I/O

I

I/O

P9RXD1

P10CRS

P10COL

P10T XD3

I

I/O

O

I/O

O

P0CRS R

I/O

CfaRpUdN-DicsuAgrmetonly.

29

Pin List By Name (With Voltage Rating): Part 1

Signal

Name

Signal

Name

Signal

Name

Signal

Name

Pin I/O Type

ADDR0

ADDR01

ADDR02

ADDR03

ADDR04

ADDR05

ADDR06

ADDR07

ADDR08

ADDR09

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ARL CL K

ARL DI0

ARL DI1

ARL DI2

ARL DI3

ARL DIR0

ARL DIR1

ARL DIV

ARL S YNC

CLK50

H03 3.3V

J03 3.3V

K 03 3.3V

L 03 3.3V

R03 3.3V

T 03 3.3V

U03 3.3V

V03 3.3V

W03 3.3V

Y 03 3.3V

Y04 3.3V

W04 3.3V

V04 3.3V

U04 3.3V

T 04 3.3V

N04 3.3V

M04 3.3V

F 04 3.3V

D03 3.3V

E 04 3.3V

E 03 3.3V

F 03 3.3V

G03 3.3V

G04 3.3V

H04 3.3V

F 05 3.3V

AK02 3.3V

AF03 3.3V

AF 04 3.3V

AG03 3.3V

AK 01 3.3V

AJ02 3.3V

AJ01 3.3V

AH02 3.3V

AH01 3.3V

AG02 3.3V

AG01 3.3V

AF 02 3.3V

AF 01 3.3V

AE 02 3.3V

AE 01 3.3V

AD02 3.3V

AD01 3.3V

AC02 3.3V

AC01 3.3V

AB02 3.3V

AB01 3.3V

AA02 3.3V

AA01 3.3V

Y02 3.3V

Y01 3.3V

W02 3.3V

W01 3.3V

V02 3.3V

V01 3.3V

U02 3.3V

U01 3.3V

T02 3.3V

T01 3.3V

R02 3.3V

R01 3.3V

P02 3.3V

P01 3.3V

N02 3.3V

N01 3.3V

M02 3.3V

M01 3.3V

L 02 3.3V

L 01 3.3V

K 02 3.3V

K 01 3.3V

J01 3.3V

O

I

O

I

O

I

I /O

O

I/O

DAT A41

DAT A43

DAT A44

DAT A45

DAT A46

DAT A47

DAT A48

DAT A49

DAT A50

DAT A51

L E D0

J02 3.3V

H02 3.3V

H01 3.3V

G02 3.3V

G01 3.3V

F 02 3.3V

F 01 3.3V

E 02 3.3V

E 01 3.3V

D02 3.3V

AC04 3.3V

AD03 3.3V

AC03 3.3V

AB04 3.3V

I/O

O

I/O

O

I/O

I

O

I/O

I

P03CRS R AJ13 3.3V

P03RXD0R AJ16 3.3V

P03RXD1R AH16 3.3V

P03RXD2R AG16 3.3V

P03RXD3R AF 16 3.3V

P03RXDVR AK16 3.3V

P03RXE RR AG15 3.3V

P03TXCLKR AH15 3.3V

P03T XD0R AK14 3.3V

P03T XD1R AJ14 3.3V

P03T XD2R AH14 3.3V

P03T XD3R AG14 3.3V

P03T XE NR AJ15 3.3V

P04COL R AK17 3.3V

P04CRS R AE 16 3.3V

P04RXCLKR AK19 3.3V

P04RXD0R AH19 3.3V

P04RXD1R AK20 3.3V

P04RXD2R AF 18 3.3V

P04RXD3R AE 18 3.3V

P04RXDVR AJ19 3.3V

P04RXE RR AG18 3.3V

P04T XCL KR AH18 3.3V

P04T XD0R AK18 3.3V

P04T XD1R AG17 3.3V

P04T XD2R AH17 3.3V

P04T XD3R AJ17 3.3V

P04T XE NR AJ18 3.3V

P05COL R AJ20 3.3V

P05CRS R AG19 3.3V

P05RXCL KR AK23 3.3V

P05RXD0R AG21 3.3V

P05RXD1R AF 20 3.3V

P05RXD2R AE 20 3.3V

P05RXD3R AH22 3.3V

P05RXDVR AJ23 3.3V

P05RXE RR AJ22 3.3V

P05TXCLKR AH21 3.3V

P05T XD0R AK22 3.3V

P05T XD1R AJ21 3.3V

P05T XD2R AK21 3.3V

P05T XD3R AH20 3.3V

P05T XE NR AG20 3.3V

P06COL R AJ24 3.3V

P06CRS R AK24 3.3V

P06RXCL KR AF 22 3.3V

P06RXD0R AJ26 3.3V

P06RXD1R AK27 3.3V

P06RXD2R AH25 3.3V

P06RXD3R AG24 3.3V

P06RXDVR AE 22 3.3V

P06RXE RR AG23 3.3V

P06TXCLKR AH24 3.3V

P06T XD0R AJ25 3.3V

P06T XD1R AH23 3.3V

P06T XD2R AG22 3.3V

P06T XD3R AK25 3.3V

P06T XE NR AK26 3.3V

P07COL R AK28 3.3V

P07CRS R AJ27 3.3V

P07RXCL KR AK30 3.3V

P07RXD0R AH28 3.3V

P07RXD1R AG27 3.3V

P07RXD2R AJ30 3.3V

P07RXD3R AH29 3.3V

P07RXDVR AJ29 3.3V

P07RXE RR AF 25 3.3V

P07TXCLKR AG26 3.3V

P07T XD0R AJ28 3.3V

P07T XD1R AF 24 3.3V

P07T XD2R AG25 3.3V

P07T XE NR AK29 3.3V

I/O

I

P07T XD3R AH26 3.3V

P08COL AF 27 3.3V

P08CRS AG28 3.3V

P08RXCL K AF 28 3.3V

P08RXD0 AF 30 3.3V

P08RXD1 AD27 3.3V

P08RXD2 AE 28 3.3V

P08RXD3 AE 29 3.3V

P08RXDV AF 29 3.3V

P08RXE R AD26 3.3V

P08T XCL K AE 27 3.3V

P08T XD0 AD25 3.3V

P08T XD1 AG29 3.3V

P08T XD2 AH30 3.3V

P08T XD3 AE 26 3.3V

P08T XE N AG30 3.3V

P09COL AD28 3.3V

P09CRS AE 30 3.3V

P09RXCL K AB28 3.3V

P09RXD0 AB30 3.3V

P09RXD1 AA27 3.3V

P09RXD2 Y25 3.3V

P09RXD3 Y26 3.3V

P09RXDV AB29 3.3V

P09RXE R AC30 3.3V

P09T XCL K AB27 3.3V

P09T XD0 AC28 3.3V

P09T XD1 AD30 3.3V

P09T XD2 AD29 3.3V

P09T XD3 AC27 3.3V

P09T XE N AC29 3.3V

P10COL AA29 3.3V

P10CRS AA28 3.3V

P10RXCL K W29 3.3V

P10RXD0 V25 3.3V

P10RXD1 V26 3.3V

P10RXD2 V27 3.3V

P10RXD3 V28 3.3V

P10RXDV W30 3.3V

P10RXE R W28 3.3V

P10T XCL K W27 3.3V

P10T XD0 Y29 3.3V

P10T XD1 Y28 3.3V

P10T XD2 Y27 3.3V

P10T XD3 AA30 3.3V

P10T XE N Y30 3.3V

I/O

I

aShet:ACD8124

I/O

O

I/O

I

L E D1

L E D2

L E D3

O

I

L E DCL K AE 04 3.3V

L E DVL D0 AD04 3.3V

L E DVL D1 AE 03 3.3V

MDC

MDIO

nCS 0

nCS 1

nCS 2

nCS 3

nOE

Y

AG04 3.3V

AH03 3.3V

M03 3.3V

J04 3.3V

L 04 3.3V

K04 3.3V

R04 3.3V

I

OR

I

I/O

O

I/O

I

nRE S E T AG05 3.3V

nWE P03 3.3V

I

P00COLR AK03 3.3V

P00CRSR AF06 3.3V

P00RXCLKR AK05 3.3V

P00RXD0R AH06 3.3V

P00RXD1R AJ06 3.3V

P00RXD2R AK06 3.3V

P00RXD3R AH07 3.3V

P00RXDVR AG07 3.3V

P00RXE RR AJ05 3.3V

P00TXCLKR AH05 3.3V

P00T XD0R AG06 3.3V

P00T XD1R AK04 3.3V

P00T XD2R AE 07 3.3V

P00T XD3R AJ04 3.3V

P00T XE NR AF 07 3.3V

P01CRS R AG08 3.3V

P01RXCLKR AH09 3.3V

P01RXD0R AK09 3.3V

P01RXD1R AG10 3.3V

P01RXD2R AE 11 3.3V

P01RXD3R AF 11 3.3V

P01RXDVR AJ09 3.3V

P01RXE RR AK08 3.3V

P01TXCLKR AG09 3.3V

P01T XD0R AH08 3.3V

P01T XD1R AK07 3.3V

P01T XD2R AJ07 3.3V

P01T XD3R AF 09 3.3V

P01T XE NR AJ08 3.3V

P02COL R AJ10 3.3V

P02CRS R AH10 3.3V

P02RXCLKR AJ12 3.3V

P02RXD0R AE 13 3.3V

P02RXD1R AF 13 3.3V

P02RXD2R AG13 3.3V

P02RXD3R AH13 3.3V

P02RXDVR AK12 3.3V

P02RXE RR AH12 3.3V

P02TXCLKR AG12 3.3V

P02T XD0R AJ11 3.3V

P02T XD1R AH11 3.3V

P02T XD2R AG11 3.3V

P02T XD3R AK10 3.3V

P02T XE NR AK11 3.3V

P03COL R AK13 3.3V

P03RXCLKR AK15 3.3V

O

I

CPUDI

CP U DO

CPUIRQ

DAT A0

I

DAT A01

DAT A02

DAT A03

DAT A04

DAT A05

DAT A06

DAT A07

DAT A08

DAT A09

DAT A10

DAT A11

DAT A12

DAT A13

DAT A14

DAT A15

DAT A16

DAT A17

DAT A18

DAT A19

DAT A20

DAT A21

DAT A22

DAT A23

DAT A24

DAT A25

DAT A26

DATA27

DATA28

DAT A29

DAT A30

DAT A31

DAT A32

DAT A33

DAT A34

DAT A35

DAT A36

DAT A37

DAT A38

DAT A39

DAT A40

DAT A42

I

INRODUCT

I/O

O

I/O

I

I/O

O

I/O

I

O

I

P11COL

P11CRS

V30 3.3V

V29 3.3V

I

P11RXCL K T 30 3.3V

P11RXD0 R29 3.3V

P11RXD1 R28 3.3V

P11RXD2 R27 3.3V

P11RXD3 R26 3.3V

P11RXDV R30 3.3V

P11RXE R T 27 3.3V

P11T XCL K T 28 3.3V

P11T XD0 U30 3.3V

P11T XD1 U29 3.3V

P11T XD2 U28 3.3V

P11T XD3 U27 3.3V

P11T XE N T 29 3.3V

I/O

O

I/O

I

I/O

O

I/O

I

O

I

O

I

P12COL

P12CRS

P30 3.3V

R25 3.3V

I

P12RXCL K M30 3.3V

P12RXD0 M28 3.3V

P12RXD1 L 30 3.3V

P12RXD2 N26 3.3V

P12RXD3 N25 3.3V

P12RXDV M29 3.3V

P12RXE R N27 3.3V

P12T XCL K N28 3.3V

P12T XD0 N30 3.3V

I/O

O

I

I/O

O

I/O

CfaRpUdN-DicsuAgrmetonly.

30

Pin List By Name (With Voltage Rating): Part 2

Signal

Name

Signal

Name

Signal

Name

Signal

Name

Pin I/O Type

P12T XD1

P12T XD2

P12T XD3

P12T XE N

P13COL

P13CRS

P27 3.3V

P28 3.3V

P29 3.3V

N29 3.3V

L 29 3.3V

M27 3.3V

O

I

P17RXE R

P17T XCL K B24 3.3V

P17T XD0

P17T XD1

P17T XD2

P17T XD3

P17T XE N E 22 3.3V

P18COL

P18CRS

A24 3.3V

I

P22RXD1R F 09 3.3V

P22RXD2R B05 3.3V

P22RXD3R A04 3.3V

P22RXDVR D08 3.3V

P22RXE RR A05 3.3V

P22T XCL KR B06 3.3V

P22T XD0R D09 3.3V

P22T XD1R A06 3.3V

P22T XD2R B07 3.3V

P22T XD3R A07 3.3V

P22T XE NR C08 3.3V

I

I/O

O

I/O

I

VDD

VS S

VSS

VS S

Y05 3.3V Power

AB26 3.3V Power

AF 05 3.3V Power

AF 12 3.3V Power

AF 19 3.3V Power

AF 26 3.3V Power

E 05 3.3V Power

E 12 3.3V Power

E 19 3.3V Power

E 26 3.3V Power

M05 3.3V Power

M26 3.3V Power

W05 3.3V Power

W26 3.3V Power

F 22 3.3V

D23 3.3V

C24 3.3V

A25 3.3V

O

I

P13RXCL K H30 3.3V

aShet:ACD8124

P13RXD0

P13RXD1

P13RXD2

P13RXD3

P13RXDV

P13RXE R

K27 3.3V

L 26 3.3V

L 25 3.3V

J28 3.3V

H29 3.3V

J29 3.3V

D21 3.3V

A22 3.3V

P18RXCL K B20 3.3V

P18RXD0

P18RXD1

P18RXD2

P18RXD3

P18RXDV A20 3.3V

P18RXE R C20 3.3V

P18T XCL K D20 3.3V

P18T XD0

P18T XD1

P18T XD2

P18T XD3

D19 3.3V

C19 3.3V

F 18 3.3V

E 18 3.3V

P23COL R

P23CRS R

D07 3.3V

C06 3.3V

I

P13T XCL K K28 3.3V

I

P23RXCL KR D05 3.3V

P23RXD0R A01 3.3V

P23RXD1R B02 3.3V

P23RXD2R C03 3.3V

P23RXD3R D04 3.3V

P23RXDVR E 06 3.3V

P23RXE RR F 07 3.3V

P23T XCL KR B03 3.3V

P23T XD0R D06 3.3V

P23T XD1R C05 3.3V

P23T XD2R A03 3.3V

P23T XD3R B04 3.3V

P23T XE NR E 07 3.3V

P13T XD0

P13T XD1

P13T XD2

P13T XD3

P13T XE N

P14COL

P14CRS

J30 3.3V

K29 3.3V

K30 3.3V

L 28 3.3V

L 27 3.3V

G29 3.3V

G30 3.3V

O

I

A19

AA04

AA06

AA25

AB06

AB25

AC06

AC25

AD06

AE 05

AE 06

AE 08

AE 10

AE 12

AE 14

AE 15

AE 17

AE 19

AE 21

AE 23

AE 24

AE 25

AJ03

C04

Ground

Gr ound

O

I

Y

I

B21 3.3V

C21 3.3V

E 20 3.3V

F 20 3.3V

O

I

OR

I/O

O

P14RXCL K J26 3.3V

P18T XE N A21 3.3V

P19COL

P19CRS

P14RXD0

P14RXD1

P14RXD2

P14RXD3

P14RXDV

P14RXE R

E 29 3.3V

D30 3.3V

F 28 3.3V

G27 3.3V

J25 3.3V

H27 3.3V

C18 3.3V

D18 3.3V

I

P19RXCL K C16 3.3V

P19RXD0

P19RXD1

P19RXD2

P19RXD3

P19RXDV D16 3.3V

P19RXE R B16 3.3V

P19T XCL K A17 3.3V

P19T XD0

P19T XD1

P19T XD2

P19T XD3

P19T XE N B17 3.3V

P1COL R AE 09 3.3V

P20COL

P20CRS

P20RXCL K C13 3.3V

P20RXD0

P20RXD1

P20RXD2

P20RXD3

P20RXDV D13 3.3V

P20RXE R B13 3.3V

P20T XCL K A13 3.3V

A16 3.3V

A15 3.3V

B15 3.3V

C15 3.3V

S T AT 0

S T AT 1

S T AT 2

S T AT 3

VDD

B01 3.3V

C01 3.3V

C02 3.3V

D01 3.3V

I

P14T XCL K G28 3.3V

I

P14T XD0

P14T XD1

P14T XD2

P14T XD3

P14T XE N

P15COL

P15CRS

F 29 3.3V

H28 3.3V

J27 3.3V

F 30 3.3V

E 30 3.3V

C30 3.3V

D29 3.3V

O

I

A02 3.3V Power

AA03 3.3V Power

AA05 3.3V Power

AA26 3.3V Power

AB03 3.3V Power

AB05 3.3V Power

AC05 3.3V Power

AC26 3.3V Power

AD05 3.3V Power

AF 08 3.3V Power

AF 10 3.3V Power

AF 14 3.3V Power

AF 15 3.3V Power

AF 17 3.3V Power

AF 21 3.3V Power

AF 23 3.3V Power

AH27 3.3V Power

B19 3.3V Power

E 08 3.3V Power

E 10 3.3V Power

E 14 3.3V Power

E 16 3.3V Power

E 17 3.3V Power

E 21 3.3V Power

E 23 3.3V Power

G05 3.3V Power

H05 3.3V Power

H26 3.3V Power

J05 3.3V Power

K05 3.3V Power

K26 3.3V Power

L 05 3.3V Power

N03 3.3V Power

N05 3.3V Power

P05 3.3V Power

P26 3.3V Power

R05 3.3V Power

T 05 3.3V Power

T 26 3.3V P ower

U 05 3.3V P ower

U 26 3.3V P ower

I

C17 3.3V

D17 3.3V

A18 3.3V

B18 3.3V

O

I/O

I

INRODUCT

P15RXCL K E 27 3.3V

P15RXD0

P15RXD1

P15RXD2

P15RXD3

P15RXDV

P15RXE R

A30 3.3V

B29 3.3V

C28 3.3V

D27 3.3V

F 26 3.3V

G25 3.3V

E 15 3.3V

D15 3.3V

F 06

F 08

F 10

F 12

F 14

F 16

F 17

F 19

I

A12 3.3V

B12 3.3V

C12 3.3V

A11 3.3V

P15T XCL K D28 3.3V

I

P15T XD0

P15T XD1

P15T XD2

P15T XD3

P15T XE N

P16COL

P16CRS

C29 3.3V

G26 3.3V

F 27 3.3V

E 28 3.3V

B30 3.3V

B28 3.3V

A29 3.3V

O

I

F 21

F 23

F 25

G06

H06

H25

J06

K06

I

P20T XD0

P20T XD1

P20T XD2

P20T XD3

P20T XE N D14 3.3V

P21COL

P21CRS

C14 3.3V

B14 3.3V

A14 3.3V

F 15 3.3V

O

I

P16RXCL K D25 3.3V

P16RXD0

P16RXD1

P16RXD2

P16RXD3

P16RXDV

P16RXE R

C26 3.3V

B26 3.3V

A26 3.3V

D24 3.3V

E 24 3.3V

A27 3.3V

F 13 3.3V

E 13 3.3V

I

K25

L 06

M06

M25

N06

P04

P06

P25

R06

T 06

T 25

U06

U25

P21RXCL K C10 3.3V

P21RXD0

P21RXD1

P21RXD2

P21RXD3

P21RXDV B09 3.3V

P21RXE R D11 3.3V

P21T XCL K A09 3.3V

P21T XD0

P21T XD1

P21T XD2

P21T XD3

P21T XE N B10 3.3V

P22COL R

P22CRS R

P22RXCL KR C07 3.3V

P22RXD0R E 09 3.3V

A08 3.3V

B08 3.3V

D10 3.3V

E 11 3.3V

P16T XCL K F 24 3.3V

I

P16T XD0

P16T XD1

P16T XD2

P16T XD3

P16T XE N

P17COL

P17CRS

A28 3.3V

E 25 3.3V

D26 3.3V

C27 3.3V

B27 3.3V

B25 3.3V

C25 3.3V

O

I

A10 3.3V

C11 3.3V

B11 3.3V

D12 3.3V

O

I/O

I

P17RXCL K C23 3.3V

P17RXD0

P17RXD1

P17RXD2

P17RXD3

P17RXDV

D22 3.3V

A23 3.3V

C22 3.3V

B22 3.3V

B23 3.3V

V06

C09 3.3V

F 11 3.3V

W 06

W 25

Y 06

I

V05 3.3V Power WCHDOG AH04

CfaRpUdN-DicsuAgrmetonly.

31

9. TIMING DESCRIPTION

MII Receive Timing

aShet:ACD8124

RXCLK

Y

RXDV

RXD[3:0]

RXER

OR

t1

t2

T#

t1

t2

Description:

RX_DV, RXD, RX_ER setup time

RX_DV, RXD, RX_ER hold time

MIN

5

TYP

-

MAX

-

UNIT

ns

INRODUCT

MII Transmit Timing

TXCLK

t1

t2

TXEN

TXD[3:0]

T#

Desciption

Min Typ Max Unit

t1 TXEN, TXD setup time 10

t2 TXEN, TXD hold time 10

-

ns

CfaRpUdN-DicsuAgrmetonly.

32

Reversed MII Receive Timing

RXCLK

aShet:ACD8124

t1

t2

Y

RXDV

RXD[3:0]

OR

T#

t1

T2

Description:

RXDV, RXD setup time

RXDV, RXD hold time

MIN

10

TYP

-

MAX

UNIT

ns

INRODUCT

Reversed MII Transmit Timing

TXCLK

TXEN

TXD[3:0]

t1

t2

T#

Description:

MIN

TYP

MAX

UNIT

t1

T2

RXDV, RXD setup time

RXDV, RXD hold time

5

-

ns

CfaRpUdN-DicsuAgrmetonly.

33

Reversed MII Packet Timing (Start of Packet)

RXCLK

aShet:ACD8124

RXDV

Y

t1

OR

RXD[3:0]

T#

Desciption

Min Typ Max Unit

ns

t1

RXD to RXDV

0

-

INRODUCT

Reversed MII Packet Timing (End of Packet)

RXCLK

t1

RXDV

RXD[3:0]

T#

Desciption

Min Typ Max Unit

ns

t1 PXD to RXDV delay time

0

-

CfaRpUdN-DicsuAgrmetonly.

34

PHY Management Read Timing

t2

MDC

aShet:ACD8124

MDIO

Y

t1

OR

T#

Description

MIN TYP MAX UNIT

t1 MDIO setup time

0

-

300

-

ns

t2

MDC cycle

800

INRODUCT

PHY Management Write Timing

MDC

t2

t1

t5

t3

t4

MDIO

T#

t1

Description

MIN TYP MAX UNIT

MDC High time

MDC Low time

MDC period

-

400

800

-

ns

t2

t3

t4 MDIO set up time 10

t5 MDIO hold time 10

-

CfaRpUdN-DicsuAgrmetonly.

35

ASRAM Read Tim ing

t1

ADDRESS

t2

t3

aShet:ACD8124

__

OE

t4

t6

__

CE

Y

SRAM Read Tim ing

HIGH-Z

DATA

VALID DATA

t7

t8

t9

OR

t5

T#

Description

Read cycle tim e

Address access tim e

O utput hold tim e

O E access tim e

M IN

-

0

-

0

-

TYP

20

M AX

UNIT

ns

t1

t2

t3

t4

t5

t6

t7

t8

t9

-

12

-

12

-

6

-

CE access tim e

O E to Low-Z output

CE to Low-Z output

O E to High-Z output

CE to High-Z output

-

ns

INRODUCT

ASRAM W rite Timing

ADDRESS

t1

t2

t4

t3

__

CE

t5

t6

t7

___

W E

t8

DATA

VALID DATA

T#

t1

t2

t3

t4

t5

t6

t7

t8

Description

W rite cycle time

Address Setup to W rite End time

Address hold for W rite End time

CE to W rite End time

MIN

-

12

0

12

4

8

TYP

20

-

MAX

UNIT

-

ns

Address Setup time

W E pulse width

Data Setup to W rite End

Data Hold for W rite End

8

0

CfaRpUdN-DicsuAgrmetonly.

36

CPU Command Timing

t4

t1

t2

aShet:ACD8124

idle state

start

bit

stop

bit

stop

bit

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

CPUDI

t3

Y

stop

bit

bit bit

start

bit

bit0

CPUDO

6

7

OR

T #

D e s c rip t io n

CP U id le time

MIN T Y P MA X U N IT

t1

t2

t3

t4

0

1 0

0

-

u s

CP U c o mma n d b it time

Re s p o n s e time

-

2 0

ms

Co mma n d time

-

INRODUCT

ARL Result Timing

ARLCLK

ARLDO

ARLDI

DA1

DA2

t1

Result2

Result1

t2

t3

T#

t1

De s c rip t io n

MIN TYP MA X UN IT

time be twe e n DAs

time for ARL re s ult

0

-

200

-

ns

t2

t3 time be twe e n re s ults

CfaRpUdN-DicsuAgrmetonly.

37

LED Signal Timing

LEDCLK

LEDVLD0

LEDVLD1

aShet:ACD8124

ERR ERR ERR

FDX FDX FDX COL COL COL

SPD SPD SPD RCV RCV RCV

LNK LNK LNK XMT XMT XMT

ERR ERR ERR

COL COL COL

RCV RCV RCV

XMT XMT XMT

nLED0

nLED1

Y

FDX FDX FDX

SPD SPD SPD

LNK LNK LNK

OR

nLED2

nLED3

P22

P2

P0

P22

P2

P0

P23

P21

P1

P23

P21

P1

INRODUCT

10. ELECTRICAL SPECIFICATION

Absolute Maximum Ratings

Operation at absolute maximum ratings is not implied.

Exposure to stresses outside those listed could cause

permanent damage to the device.

DC Supply voltage : VDD

DC input current: Iin

-0.3V ~ +5.0V

+/-10 mA

DC input voltage: Vin

DC output voltage: Vout

-0.3 ~ VDD + 0.3V

-40 to +125^oC

Storage temperature: Tstg

Recommended Operation Conditions

Supply voltage: VDD

3.3V, +/-0.3V

Operating temperature: Ta

Maximum power consumption

0^oC -70 ^oC

3.5W

CfaRpUdN-DicsuAgrmetonly.

38

11. PACKAGING

Top View

aShet:ACD8124

Advanced

Comm.

Devices

Y

FLLLLLSMAYYWW

ACD82124

OR

Pin - A1

34.50

40.00+/-0.20

Side View

INRODUCT

o.56

0.60+/-0.05

2.33+/-0.13

Bottom View

AA AC AE AG AJ

AD AF AH AK

AB

A

B C D E F

G H J K L M N P R

T

U V W Y

Pin - A1

1

3

2

4

5

6

8

7

9

10

11

13

15

17

19

21

23

25

27

12

14

16

18

20

22

24

26

28

29

30

CfaRpUdN-DicsuAgrmetonly.

1.27

0.75+/-0.15

39

36.83

aShet:ACD8124

Y

OR

Appendix-A1

Address Resolution Logic

(The built-in ARL with 2048 MAC Addresses)

INRODUCT

CfaRpUdN-DicsuAgrmetonly.

40

1. SUMMARY

2. FEATURES

The internal Address Resolution Logic (ARL) of ACD’s

switch controllers automatically builds up an address

table and maps up to 2,048 MAC addresses into their

associated port. It can work by itself without any CPU

intervention in an UN-managed system.

•

Supports up to 2,048 MAC address lookup

Provides UART type of interface for the manage-

ment CPU

Wire speed address lookup time.

Wire speed address learning time.

Address can be automatically learned from switch

without the CPU intervention

Address can be manually added by the CPU

through the CPU interface

Each MAC address can be secured by the CPU

from being changed or aged out

Each MAC address can be marked by the CPU

from receiving any frame

Each newly learned MAC address is notified to

the CPU

Each aged out MAC address is notified to the CPU

Automatic address aging control, with configurable

aging period

•

For a managed system, the management CPU can

configure the operation mode of the ARL, learn all the

address in the address table, add new address into

the table, control security or filtering feature of each

address entry etc.

aShet:ACD8124

•

The ARL is designed with such a high performance

that it will never slow down the frame switching opera-

tion. It helps the switch controllers to reach wire speed

forwarding rate under any type of traffic load.

Y

•

OR

The address space can be expanded to 11K entries

by using the external ARL, the ACD80800.

Figure-1. ARL Block Diagram

INRODUCT

Switch Interface

CPU Interface

Address

Learning

Engine

Address

Aging

Engine

Address

Lookup

Engine

CPU Interface Engine

Address Table

(2048 Entries)

CfaRpUdN-DicsuAgrmetonly.

41

3. FUNCTIONAL DESCRIPTION

Address Lookup

The ARL provides Address Resolution service for

ACD’s switch controllers. Figure 2 is a block diagram

of the ARL.

Each destination address is passed to the Address

Lookup Engine of the ARL. The Address Lookup En-

gine checks if the destination address matches with

any existing address in the address table. If it does,

the ARL returns the associated Port ID to ACD’s switch

controller through the output data bus. Otherwise, a

no match result is passed to ACD’s switch controller

through the output data bus.

Traffic Snooping

All Ethernet frames received by ACD’s switch control-

ler have to be stored into memory buffer. As the frame

data are written into memory, the status of the data

shown on the data bus are displayed by ACD’s switch

controller through a state bus. The ARL’s Switch Con-

troller Interface contains the signals of the data bus

and the state bus. By snooping the data bus and the

state bus of ACD’s switch controller, the ARL can de-

tect the occurrence of any destination MAC address

and source MAC address embedded inside each frame.

aShet:ACD8124

CPU Interface

The CPU can access the registers of the ARL by send-

ing commands to the UART data input line. Each com-

mand is consisted by action (read or write), register

type, register index, and data. Each result of com-

mand execution is returned to the CPU through the

UART data output line.

Y

OR

Address Learning

CPU Interface Registers

Each source address caught from the data bus, to-

gether with the ID of the ingress port, is passed to the

Address Learning Engine of the ARL. The Address

Learning Engine will first determine whether the frame

is a valid frame. For a valid frame, it will first try to find

the source address from the current address table. If

that address doesn’t exist, or if it does exist but the

port ID associated with the MAC address is not the

ingress port, the address will be learned into the ad-

dress table. After an address is learned by the ad-

dress learning engine, the CPU will be notified to read

this newly learned address so that it can add it into the

CPU’s address table.

The ARL provides a bunch of registers for the control

CPU. Through the registers, the CPU can read all ad-

dress entries of the address table, delete particular

addresses from the table, add particular addresses

into the table, secure an address from being changed,

set filtering on some addresses, change the hashing

algorithm etc. Through a proper interrupt request sig-

nal, the CPU can be notified whenever it needs to

retrieve data for a newly-learned address or an aged-

out address so that the CPU can build an exact same

address table learned by the ARL.

INRODUCT

CPU Interface Engine

Address Aging

The command sent by the control CPU is executed by

the CPU Interface Engine. For example, the CPU may

send a command to learn the first newly-learned ad-

dress. The CPU Interface Engine is responsible to

find the newly-learned address from the address table,

and passes it to CPU. The CPU may request to learn

next newly-learned address. Then, it is again the re-

sponsibility of the CPU Interface Engine to search for

next newly-learned address from the address table.

After each source address is learned into the address

table, it has to be refreshed at least once within each

address aging period. Refresh means it is caught again

from the switch interface. If it has not occurred for a

pre-set aging period, the address aging engine will

remove the address from the address table. After an

address is removed by the address aging engine, the

CPU will be notified through interrupt request that it

needs to read this aged out address so that it can

remove this address from the CPU’s address table.

Address Table

The address table can hold up to 2,048 MAC ad-

dresses, together with the associated port ID, security

flag, filtering flag, new flag, aging information etc. The

address table resides in the embedded SRAM inside

the ARL.

CfaRpUdN-DicsuAgrmetonly.

42

4. INTERFACE DESCRIPTION

UARTDO is used to return the result of command ex-

ecution to the CPU. The format of the result packet is

shown as follows:

CPU Interface

The CPU can communicate with the ARL through the

UART interface of the switch IC. The management CPU

can send command to the ARL by writing into associ-

ated registers, and retrieve result from ARL by read-

ing corresponding registers. The registers are de-

scribed in the section of “Register Description.” The

CPU interface signals are described by table-1:

Header

Address

Data

Checksum

where:

aShet:ACD8124

•

Header is further defined as:

b1:b0 - read or write, 01 for read, 11

for write

b4:b2 - device number, 000 to 111 (0

to 7)

b7:b5 - device type, 010 for ARL

Address - 8-bit value for address of the

selected register

Data - 32-bit value, only the LSB is used

for read operation, all 0 for write opera-

tion

Table-1: CPU Interface

Name

UARTDI

UARTDO

I/O

I

O

Description

UART input data line.

UART output data line.

Y

•

OR

UARTDI is used by the control CPU to send command

into the ARL. The baud rate will be automatically de-

tected by the ARL. The result will be returned through

the UARTDO line with the detected baud rate. The for-

mat of the command packet is shown as follows:

•

Checksum - 8-bit value of XOR of all bytes

The ARL will always check the CMD header to see if

both the device type and the device number matches

with its setting. If not, it ignores the command and will

not generate any response to this command.

Header

Address

Data

Checksum

INRODUCT

where:

•

Header is further defined as:

b1:b0 - read or write, 01 for read, 11

for write

b4:b2 - device number, 000 to 111 (0

to 7, same as the host switch con-

troller)

b7:b5 - device type, 010 for ARL

Address - 8-bit value used to select the

register to access

Data - 32-bit value, only the LSB is used

for write operation, all 0 for read opera-

tion

•

Checksum - 8-bit value of XOR of all bytes

CfaRpUdN-DicsuAgrmetonly.

43

5. REGISTER DESCRIPTION

The DataRegX are registers used to pass the param-

eter of the command to the ACD80800, and the result

of the command to the CPU.

ACD80800 provides a bunch of registers for the CPU

to access the address table inside it. Command is sent

to ACD80800 by writing into the associated registers.

Before the CPU can pass a command to ACD80800,

it must check the result register (register 11) to see if

the command has been done. When the Result regis-

ter indicates the command has been done, the CPU

may need to retrieve the result of previous command

first. After that, the CPU has to write the associated

parameter of the command into the Data registers.

Then, the CPU can write the command type into the

command register. When a new command is written

into the command register, ACD80800 will change the

status of the Result register to 0. The Result register

will indicate the completion of the command at the end

of the execution. Before the completion of the execu-

tion, any command written into the command register

is ignored by ACD80800.

The AddrRegX are registers used to specify the ad-

dress associated with the command.

The CmdReg is used to pass the type of command to

the ACD80800. The command types are listed in table-

3. The details of each command is described in the

chapter of “Command Description.”

aShet:ACD8124

Table-3: Command List

Command

Description

Add the specified MAC address into the

address table

Y

0x09

Set a lock for the specified MAC

address

Set a filtering flag for the specified MAC

address

Delete the specified MAC address from

the address table

Assign a port ID to the specified MAC

address

OR

0x0A

0x0B

0x0C

0x0D

The registers accessible to the CPU are described by

table-2:

0x10

0x11

0x20

0x21

0x30

0x31

0x40

0x41

0x50

0x51

0x60

0x61

0x80

0x81

0xFF

Read the first entry of the address table

Table-2: Register Description


型号：	ADC82124
厂家：	ETC
描述：	24 Ports 10/100 Fast Ethernet Switch Controller 24端口10/100快速以太网交换机控制器控制器以太网局域网（LAN）标准
文件：	总48页 (文件大小：411K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC82124 [ETC]

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