概述
数据手册AK2358A 概述
Telephone Circuit (Support)
电话线路（支持）\n
AK2358A 数据手册
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1
F e a t u r e s
Built-in voice filter for cordless telephone, MSK MODEM
scrambler circuit
COMPANDOR, and
•1
Low / wide operation voltage range (1.9 V to 5.
•1
•1
•1
•1
•1
Built-in
output transient response circuit and time constant circuit
No external component is needed for
Built-in buffer amplifier for ceramic receiver driving.
Built-in electronic volume for ❑ icrophone sensitivity and modulator/demodulator
sensitivity
Receiving level
Built-in muting function for voice transmitting and receiving
External adjustment for the limiter level-
Built-in amplifier for transmission and reception gain adjustment
Low power CMOS and power-down function
Built-in
in 8 steps (-12 to
❑
•1
•1
❑
•1
❑
•1
oscillator circuit
Two inversion frequencies can be
Scrambler circuit with frequency inversion.
selected.
Bypassing the scrambler circuit available
•1
❑
•1
• 1
❑
Built-in frame detection function for the MSK demodulator
Control register and MSK MODEM data buffer controlled by serial interface
Few external component is necessary resulting cost reduction and small set size.
Package: 24 pin VSOP
B l o c k
D i a g r a m
I
microphone input
Trans mis s ion s ignal
3.
Da ta /lx Da ta
Control data
detection
Receiver
s ig n a l
output
1996
0151 E-00
- 1
o
5
4
.
I
T
I
I
TXHPF
Sc r a mbl e r
Li mi t e r
.
.
.
.
.
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9
T
TCLK
DI R
TC
-
_
Modul a t or
modul a t or
SCLK
buf f e r
—
“
“ 0 ”
.
.
.
.
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I
I
e mpha s i s
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.
.
VR4
Expa nde r
RXHPF
Sc r a mbl e r
BUFOP
.
.
.
.
.
.
.
.
.
.
.
w
Ope r a t i ng mode
.
D e s c r i p t i o n
The AK2358A, a base-band
for cordless telephone, has built-in voice filters, a
MSK MODEM for data communication, a frame detection circuit, a COMPANDOR for noise
reduction, and scrambler circuits.
The CMOS process provides low power operation. Application of 24 pin VSOP package with
the feature of significant reduction of external component provides minimum mounting area.
The time constant circuit for the
output transient response is built into the
Using a MSK MODEM for data communication has realized high data reliability and
high speed communication at the same time.
This LSI is suitable for cordless system telephones etc. which requires complicated
protocol control.
An oscillation circuit with a
crystal oscillator is built in, and no other
frequency source is required for the MSK MODEM. The oscillator also can be used for the
other DTMF generator etc.
The scrambler circuit uses the simple
method with inversion of the voice
spectrum around the carrier frequency. Two inversion frequencies can be selected.
Built-in electronic volumes provided for transmission and reception part realize automatic
adjustment of the ❑ icrophone sensitivity and the modulator/demodulator sensitivity by
external EEPROM and
❑ icroprocessor.
The transmission part is composed of high-pass filter, compressor,
circuit,
scrambler, limiter, MSK modulator, splatter filter, electronic volume control, etc.
The reception part is composed of band pass filter, de-emphasis circuit, de-scrambler,
expander, buffer amplifier, MSK demodulator, frame detection circuit, electronic volume
control, etc.
■ Pin Arrangement
24 pin VSOP
2 4
2 3
2
2 2
3
21
4
20
19
6
18
17
7
8
9
VDD
16
15
11
12
14
13
SCLK
1996
0151 00
C i r c u i t
C o n f i g u r a t i o n
Function
I
Block
AMP1
The operational amplifier for voice signal transmission gain
adjustment and for the filter to eliminate noise by the
capacitor filter) in the following stage. Use an
external resistor and capacitor to set the gain less than
the cut-off frequency to about
and
TXHPF
The SCF circuit to eliminate the low frequency component less
than
from the transmission voice signal.
Compressor
The circuit to compress the amplitude of the transmission voice
signal.
The circuit to emphasis the high-frequency component of the
transmission voice signal to improve the S/N of the modulation
signal.
Scrambler (Tx)
Limiter
The circuit to inverse the transmission voice spectrum in regard
to the carrier frequency. Carrier frequency can be selected from
two frequencies by KEY. PCONT select to use the scrambler or the
circuit.
The amplitude-limiting circuit to suppress the frequency deviation
The limitation level can be adjusted by
applying a DC voltage to the pin. If the pin is open,
the default limitation level is applied.
of the modulation signal.
Splatter filter
The SCF circuit to eliminate the high frequency component higher
than 3kHz from the limiter output signal or the MSK modulator
signal.
MSK modulator
The circuit to generate a 2400bps MSK signal according to the
received digital signal logic from the TDATA pin.
The operational amplifier to adjust the reception demodulation
AMP2
signal gain and for the filter to eliminate the
noise of
the SCF in the following stage. Set the gain to less than
and the cut-off frequency to about
capacitor.
by external resister and
RXLPF
The SCF circuit to eliminate the high frequency component higher
than
from the limiter output signal or the MSK modulator
signal.
RXHPF
The SCF circuit to eliminate the low frequency component lower
than from the reception voice signal.
De-emphasis
De scrambler (Rx)
The circuit to de-emphasis the emphasized signal by
circuit.
The circuit to re- inverse the spectrum of the scrambled receiving
voice signal respect
the carrier frequency. Carrier frequency
can be selected from two candidates by a KEY. The
or the de-emphasis circuit can be selected by
Expander
The circuit
compressor.
expand the signal amplitude compressed by the
1996/’12
0151
[AK2358AI
Function
The operational amplifier used on the smoothing filter of the
Set the gain to and the cut-off
Block
reception SCF output.
frequency to about 20kHz by external resister and capacitor.
The SCF circuit to eliminate the low frequency component lower
than 100Hz from the reception MSK signal.
The circuit to reproduce the 2400bps receiving data and the clock
from the received MSK signal in the RXIN pin.
The inverting and the non-inverting buffer amplifier to drive the
ceramic receiver.
The circuit to generate the reference voltage for the internal
analog signal.
AGND
Oscillation
circuit
The circuit to oscillate the 3.58 MHz reference clock using an
external crystal oscillator and resistor.
The volume to control the input amplitude of the transmission
voice signal. The adjustment range is
The volume to control the MOD output amplitude. The adjustment
range is to by step.
The volume to control the input amplitude of the reception
to
by
step.
VR2
VR3
demodulation signal. The adjustment range is
to
by
step.
The volume to control the receiving voice amplitude. The
VR4
adjustment range is
The control register
internal volumes of the LSI by serial data consists of 2 address
bits and 8 data bits. At the start up a power-on-reset circuit
works and the default values are set to the control register.
( s e e c o n t r o l r e g i s t e r m a p . )
to
by
step.
Control register
and data buffer
the status of internal switches and
The data buffer stores 8 bits of the MSK receiving data to smooth
the signal interface with CPU.
P i n / F u n c t i o n
I
I
Function
Analog ground input pin.
Pin No.
Pin name
1 / 0
1
Connect the capacitor to stabilize the analog
ground.
Analog ground pin for the transmission system.
Connect the capacitor to stabilize the analog
ground.
o
2
3
Transmission voice input pin.
This is the inverting input pin for
composes a microphone amplifier with a
resister and a capacitor.
It
output pin.
o
Limitation level adjustment p i n .
The limitation
to this pin. The default
is adopted if no voltage is
can be adjusted
applying a
1996
0151
[AK2358AI
Pin No.
6
Pin
MOD
1 / 0
o
Function
Output pin of the modulated transmission signal.
A load impedance larger than
Negative power supply pin.
Clock output pin for the MSK data transmission.
A 2.4kHz clock is put out by setting the internal
register TDE to “O”. If the register is set to “l”,
it goes “H” level.
can be driven.
—
Vss
7
8
TCLK
o
9
I
MSK transmission data input pin.
Data are latched synchronizing with the TCLK rising
edge.
DI/O
1 / 0 Serial data input and output pin.
1 0
o
1 1
MSK signal reception flag output and Frame detection
signal output pin.
This pin puts out two types of information,
depending on the status of the internal register
FSL. If FSL is “l”, it is MSK signal reception mode,
so the pin reaches low after 8 bits of the MSK
reception signal have been written to the data
it is the frame detection
register. If FSL is “O”,
signal output mode, so the low pulse is put out
after a frame pattern is detected.
Clock input pin for serial data 1/0.
Serial data 1/0 control pin.
I
I
1 2
1 3
1 4
DIR
XOUT
Crystal oscillator connection pin.
The reference clock
is generated by connecting a
crystal oscillator parallel to a
resistor between this pin and XIN pin. In case of
external clock operation, connect XOUT pin to
and apply the clock to XIN.
o
Crystal oscillator connection pin.
Positive power supply pin.
Expander output pin.
1 5
1 6
1 7
1 8
—
o
I
Reception voice input pin.
This is the inverting input of AMP3. It composes a
smoothing filter by external resistor and capacitor.
Reception voice output pin.
RXAF
o
1 9
This is the output pin of
A load impedance
more than
can be driven.
2 0
2 1
2 2
2 3
BUFON
o
o
o
I
Receiver amplifier output pins.
Connect the ceramic receiver between these two pins.
output pin.
BUFOP
RXIN
Demodulated receiving signal input pin.
This
the inverting input of
composes a
with external resistor and capacitor.
ground pin for the reception system.
2 4
the capacitor
stabilize analog ground.
0151 E 00
1996:12
6
[AK2358AI
A b s o l u t e
M a x i m u m
R a t i n g s
I
1
Note 1)
Parameter
Symbol
min
max
Unit
Power supply voltage:
Input current
v
“0.3
6.5
(except the power
Analog input voltage
Digital input voltage
Storage temperature
pins)
v
-0.3
-0.3
-55
3
v
“c
Tstg
130
Note 1): All voltages with respect to the
pin.
Warning: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
R e c o m m e n d e d
Note 1)
O p e r a t i n g
C o n d i t i o n s
I
Parameter
Operation temperature
Power supply voltage:
Symbol
Ta
min
-lo
1.9
typ
2.0
max
70
5.5
Unit
“c
v
Analog reference voltage
AGND
v
Current consumption
Mode O
Mode 1
Mode 2
Mode 3
0.1
0.9
1.4
5.5
0.8
1.9
2.9
10
Idd2
Idd3
Note 1): All voltages with respect to the VSS pin.
0151-E-00
1996 12
- 7
[AK2358AI
A n a l o g C h a r a c t e r i s t i c
s
to
unless otherwise specified,
OdBx=-5dBm at
Note 8)
1) TX system
I
Parameter
Standard input level
Absolute gain
typ
-lo
3.5
min
2.0
max
Unit
dBx
Note 1)
Note 1)
5.0
Limiter level
lkHz
No external R
Adjustment range by
external R
-4.5
-2.5
-2.5
-3.5
dBx
Compressor linearity
Note 1) 2)
-20
-24
-17.0
-20.0
-14
-16
Noise without input
Compressor distortion
Note 1) 3)
Note 1)
signal output
Note 1)
signal output
dBm
dBx
-36.5
-35
Transmission MSK
signal level
Transmission MSK
signal distortion
-4.5
-3.5
-2.5
-32
2) RX system
Parameter
typ
-lo
min
Unit
dBx
max
I
Standard input level
Absolute gain
-1.5
0
Note 1)
Expander linearity
Note
4)
-30.0
“40. o
-27.0
-35.0
-33.0
-45.0
Noise with no input
Expander distortion
dBm
dBx
-70
-35
Note 1) 3)
Reception MSK
signal level
-14
-7
-1
signal output
0151-E-00
1996
- 8
[AK2358AI
Unit
3) Overall characteristics
Parameter
typ
max
min
Absolute gain
+4. o
Note 5) 6)
TXINO=-10dBx KEY=”O” or “1”
o
Note 3) 5) 6)
Distortion
-50
-43
KEY=”O” or “l”
Crosstalk
Note 1) 7)
Transmission
Reception
dBx
dBx
-60
Crosstalk
Reception
Note 1) 7)
Transmission
-56.5
4) Filter characteristics
Parameter
min
typ
max
Unit
Transmission overall characteristics (See
MOD
TC=” O”
100Hz
-40
-9
-12
-10.5
Relative value with
at
gain
2. 5kHz
3kHz
8
8
6.5
6.5
9.5
9.5
-7
5kHz
Reception overall characteristics (See
O” PCONT=”l”
100Hz
-4
13.5
12
Relative value with
at
gain
9
10.5
-9
3kHz
5kHz
-10.5
-7.5
-15
Note 1) With the external circuit shown in the application circuit example.
Note 2)
Relative value with
input level
as the MOD output level at the time of input of standard
to
Note 3) With the C-message filter.
Note 4) Relative value with
standard input level
as the
BUFOP output level at the time of input of
to
With the external circuit shown in the application circuit example.
Note 5)
Further, the
connection.
gain should be
and MOD and RXIN should be in loop
Note 6)
Note 7)
Note 8)
PCONT=”O”
The dBx is standardized unit valid for various power supply voltages from 1.9 to
If the voltage is OdBx should be -5dBm. With the other voltage as X
OdBx -5 20
0151-E 00
1996 12
[AK2358AI
•l Filter characteristics
10
0
-lo
-20
-30
-40
-50
10
-
FREQUENCY
Fig.
Transmission overall characteristics
10
0
-lo
-20
-30
-40
-50
I
F R E Q UE NC Y
Fig. 2
Reception overall characteristics
“
[AK2358AI
L e v e l
D i a g r a m
I
1) TX system
Pref i I ter
TXAF
AUP
Cross point
Limiter level
-3.
level)
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
2) RX system
f-1 kHz
RXAF
10
0
-10
-25
-45 j
-50
I
Note)
The
is standardized unit valid for various power supply voltages from
to
voltage is 2V, OdBx should be
With the
as X
OdBx
5
20 log
0151-E 00
1996/’12
“
[AK2358AI
I
C h a r a c t e r i s t i c
s
I
1 . DC Characteristics
Parameter
I Pin
(1)
min
max
I
High-level input voltage 1
Low-level input voltage 1
2
Low-level input voltage 2
High-level input current
Low-level input current
v
(1)
(2)
(2)
(l)(2)
(l)(2)
(3)
v
I
I
v
10
-lo
v
I
I 0.3 I v I
Low-level
(l).
(2)
(3)
DI/O
DIR
RDF, DI/O
2. AC Characteristics
I
I
max
Unit
MHz
Parameter
Master clock frequency
MSK modulator timing
TDE Falling to TCLK Rising
TCLK period
❑ in
3.579545
208.3
416.7
T2
T3
ms
2
TDE Rising to
Falling
TS
TDATA Set up time
TH
TDATA Hold time
1
TH2
2
TDATA Hold time2
MSK demodulator timing
RCLK Period & FD pulse width
T
416.7
402.2
Serial data input timing
Clock pulse width 1
Clock pulse width 2
SDATA Set Up time
SDATA Hold time
DIR Set up time
DIR Hold time
DIR falling to SCLK falling time
input rising time
ta
tb
tc
td
te
t f
tg
ns
ns
500
500
100
100
100
100
ns
ns
S
1
S
input falling time
tj
tk
ns
ns
RDF falling to SCLK falling time
SCLK rising to RDF falling time
600
199612
0151-E 00
[AK2358AI
I
I
TX
Note)
( Internal
)
TDE
Note)
(
Internal
)
MOD
V o i c e s i g n a l
V o i c e s i g n a l
MSK modulator
ta
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
DI/O
DIR
:.....-.0.
input
Note) The timing to rewrite the internal registers
falling edge of DIR.
and TDE is synchronized with the
1
1
1
.
.
.
>
.
,
I
o
demodulator
1996/12
[AK2358AI
R e g i s t e r M a p
C o n t r o l
I
I
■ Register composition
Address
Data
D 3
D 4
FCLN
1
A l AO D 7 D 6 D 5
D 2
DO
TXAF
“ SW
RXAF
Control register 1
FSL
BS2
BS 1
TDE
0
0
Volume register
o
1
1
1
1
V R 4
Volume register
V R 2
1
0
Control register 2 +
volume register
KEY
V R 3
1
1
TC
EM
FRPT
Reception data register
MSK MODEM reception data
The-reception data register is a read only
registers.
register, and the others are write only
The reception data register has no address
information proceeding to the Data.
Set the all bits D4 to D7 of volume register address “01” to “l”. If they are set to “O”,
it changed to test mode,
■ Register map
1) Control register 1
Address
AO
Data
DO
D 7
FSL
D 6
BS2
1
D 5
BS1
0
D 4
FCLN
0
D 3
PCONT
D 2
TDE
1
o
0
(Default)
0
0
a) Transmission signal control
Transmission output
Voice signal
Mute
TDE
1
1
0
1
1
o
MSK signal
b) Reception signal control
RXAF
Mute
ON
—
1
o
o
Mute
Mute
ON
1
0
ON
c) Scrambler circuit ON/OFF
PCONT
I
(Scrambler OFF)
I
I
1
o
Scrambler works (ON)
I
I
0151-E-00
1996/12
d) Frame detection circuit ON/OFF
FCLN
1
o
The frame detection function is not us e d (OFF).
The frame detection function is used (ON).
Note) FCLN automatically changes from O to 1 when a synchronized frame is detected.
e) Power-down mode
Voice system +
Mode name
Oscillator
BS2
Reception MSK
transmission MSK
O F F
O F F
ON
ON
O F F
O F F
ON
1
o
1
o
1
0
0
m o d e l
m o d e 2
m o d e 3
O F F
O F F
ON
ON
ON
f)
selection
FSL
The MSK signal reception flag
pin.
is put out from the
1
The frame detection signal (FD) is put out from the
pin.
o
2) Control register 2
Address
Data
D3
D 5
FRPT
0
D 4
KEY
1
D 7
D 6
EM
1
AO
1
(Default)
1
1
1
0
0
0
Data name
K E Y
Function
Carrier inverting frequency
1
“:
“O”: 3.290kHz
Frame detector detection pattern “l”:
F R P T
EM
1100010011010110 (base unit)
“O”: 1001001100110110 (portable unit)
Emphasis circuit
circuit
“ “: Passage (ON)
“O”: Bypass (OFF)
1
T C
Passage (ON)
“l”:
3) Volume register
Address
Data
D 7
1
VR23
TC
D 6
1
VR22
DO
VR40
A l
o
1
AO
D 3
D 2
D 4
1
1
0
1
VR41
1
VR32
1
VR33
VR31
EM
0151-E 00
1996/12
-
[AK2358AI
a )
volume control
Volume gain (dB)
– 8 . O
– 7 . o
– 6 . O
– 5 . o
– 4 . o
– 3 . 0
– 2 . o
– 1 . 0
0
o
0
0
0
0
0
o
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
+ 1 . 0
+ 2 . o
+ 3 . 0
+ 4 . o
+ 5 . o
+ 6 . O
+ 7 . o
1
0
0
1
0
0
1
1
1
1
b)
VR3 volume control
VR23
VR33
VR22
VR32
VR20
VR30
0
Volume gain (dB)
VR31
o
0
o
0
o
o
o
o
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
– 4 . o
– 3 . 5
– 3 . o
– 2 . 5
– 2 . 0
– 1 . 5
– 1 . 0
– o . 5
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
+ 0 . 5
1
1
1
1
+ 2 . 0
0
0
1
0
1
0
1
1
1
1
1
1
1
-
17
c) VR4 volume
VR40
0
1
Volume
– 1 2
(dB)
I
I
I
o
o
o
o
1
0
0
1
– 9
– 6
– 3
0
+ 3
+ 6
+ 9
0
1
1
0
1
0
1
0
0
1
1
1
1
t he gain of all volumes are set to
and
bit is changed
Note) By reset,
to “o”.
4) MSK MODEM
reception data
Data
D 7
D 6
D 5
D 4
D 3
D 2
DO
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RDO
Data name
RDO
Function
reception data
RD7 is the first received data.
R D 7
E-00
18
[AK2358AI
M S K M o d e m
I
MSK signal transmission flow
MSK signal transmission
TDE=”O” and
:
:
MSK transmission start
are s et.
I
MSK transmission data
are trans mitted
Dur i ng MSK transmission
synchronized to TCLK.
Tr a ns mi s s i on of t he
N
:
MSK da t a t r a ns m s s i on c omp
TDE= “ 1”
:
Swi t c hi ng t o voi c e s i gna l
“ O”
I
I
Set the serial register
state is provided.
A 2400Hz clock is put out from TCLK. Synchronizing with
“O” and
to “l”, so that
transmission
(1)
( 2)
( 3)
( 4)
rising edge of
AK2358A reads the
After the transmission
register is set
transmission data from TDATA pin and put out them to MOD pin.
the necessary number
signal bit, “TDE” of
.
the serial
“l”.
before
to a voice signal transmission mode, wait at least
after “TDE” has set to “ “
MSK
bit transm
The n s e t
register to “oc”.omplete
0151-E-00
1996’ 12
- 1 9 ”
[AK2358AI
Signal Reception
s i gna l r e c e pt i on
I
:
:
Se t s o t ha t
t he
a
f r a me de t e c t i on s i gna l ( FD) i s put out f r om
FSL s e t t o “ O” .
pi n.
>
N
Sync hr oni z a t i on f r a me de t e c t i on?
Re c e pt i on voi c e mut e
:
:
:
Se t s o t ha t a n
f r om t he
s i gna l r e c e pt i on f l a g
i s put out
pi n.
N
Re c e pt i on of
Re a di ng of
8
bi t of da t a ?
8
bi t of da t a , c ha nge
“ H”
Re c e pt i on da t a r e a d
i
ng
Wa i t i ng f or t he ne xt s ync hr oni z a t i on f r a me
are fixed to
RCLK
If the internal register “FCLN” is “O”, the internal nodes
“1”.
( 1)
(2)
( 3)
After a synchronization frame is detected, FD goes to “L” during the period “T”, then
FCLN is set to “l”.
RDATA and RCLK put out the data following to the synchronized frame pattern, and these
are stored in the internal buffer.
After 8 bit of reception data have been entered to the internal buffer, RDF goes “L”.
( 4)
( 5)
it puts out 8 clock bits to
then read 8
After the CPU detect that RDF is “L”,
bit of reception data from the SDATA pin.
With input of 8 clock bits to SCLK, RDF goes “H”.
( 6)
( 7)
( 8)
Afterwards, by repeating the steps (4) and (5) the necessary data bits are
After the necessary data have been read, DIR goes “H”,
serial interface, the internal nodes and RCLK are set to “l”, then the system
waits for the next synchronization frame.
is set to “O” via the
i
1996/ 12
I
- 2 0 ”
[AK2358AI
A p p l i c a t i o n
Circuit
C i r c u i t E x a m p l e
I
1
Use as a transmitting microphone amplifier.
eliminate high frequency noise component over than
The gain should be less than 30dB. To
from input signal, 1st order
or 2nd order anti-aliasing filter is necessary.
The following drawing is one example of
the 2nd order
filter, which has
gain and
cut-off frequency.
J
.
cl
R3=330k
filter for MOD output signal
Realize low-pass filter to eliminate
output signal. The following is one example of the 1st order low-pass filter which has
clock signal component from MOD pin
of the modulator load resistor provide
signal
cut-off frequency.
attenuation.
R
MOD
‘L
(Load resistance of MOD)
The amplifier for the receiving gain adjustment and
filtering to
The gain should be less than 30dB.
eliminate high frequency noise component over
The following is an example of the 2nd order low pass filter, which has 20
40kHz cut-off frequency.
gain and
.
.
C2=27PF
.
0151 E 00
1996/12
21 -
The smoothing filter to eliminate 448kHz clock component from
signal is
Adding the
Also it works to adjust the receiving gain.
provided by this amplifier.
The following is one example of the 1st order low-pass
cut-off frequency.
other pass signal may be possible.
filter, which has
gain ,
C 2 = 0 . 0 2 2
R l = R 2 = 5 6 k
R2
c l
RXAF
+
AMP 3
L
S
I
stabilizing capacitor
To stabilize the AGND potential, connect capacitors larger than
pin and pin some capacitor is
between
Also between
ripple of the power.
pin.
pin,
pin and
necessary to reduce the
L
S I
stabilizing capacitor
To reduce the noise on VDD, connect capacitors between
and VSS.
VDD
E lect r olyt ic Ca p a cit or )
(Cer a m ic Ca pa cit or )
C2
cl
Vss
L S I
1996/12
0151 E-00
22 -
oscillator
- Crystal resonator ,
resistor and capacitors should be connected as shown Fig.3 for
on-chip oscillator operation.
- For external clock operation, if the high(H) level of the input clock signal
amplitude equals to or is greater than
and the low(L) level equals to or is
smaller than then connection should be ❑ ade as shown in Fig.4.
If the input clock signal amplitude (peak-to-peak) equals to or is smaller than
IV, and equals to or is greater than 200mV, then AC coupling should be as
illustrated in Fig.5.
Fig.4
clock signal
XOUT
fig. 5
level adjusting resistor
The limiting level can be
externally by applying DC voltage to
then the limiting level is shown as
is the voltage between and TAGND. Keeping pin open
pin.
Applied DC voltage should be larger than
while
provides default limit level. See following example.
VDD
R = 5 0 k
R
Vss
L
S
I
0151 E 00
1996/12
23
[AK2358AI
P a c k a g e
I
■ Marking
AK2358A
XXXYZ
o
[Contents of
XXX: Date of manufacture
Last digit of the year, week number of the year as 2 digits
Y: Production lot number
Z: Assembled place
■ Shape and dimensions of the package
24 pi n VSOP
0.1
o
—
_
Note:
Dimensions marked by
do not include residual res
in.
De t a i l of pa r t
A
Resin: Low
type epoxy resin
Le a d frame:
0151 E- 00
1996/’12
24
IMPORTANT NOTICE
●
These
consult the
status.
specifications
Mi c r os ys t e ms Co. . Ltd.
without notice.
application,
sales office or authorized distributor concerning their current
●
●
AKM assumes no liability f or i nf r i nge me nt of any patent, intellectual property, or other right in the application or use of
any information contained herein.
Any export of these products, or devices or systems containing
approval under the and regulations of export pertaining to customs and tariffs, currency exchange,
or materials.
are neither intended nor authorized
hazard related device and assumes no responsibility relating to any such use, except with the express
require an export license or other official
● ✌
AKM
use as
components in any safety, life support, or other
written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for
applications
medicine, aerospace, nuclear energy,
in which its failure to function or perform ma y
reasonably be expected to result in
of
or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or
directly or indirectly, in the of the
therefore meet very high standards of performance and reliability.
reasonably be expected to result, whether
or effectiveness of the device or system containing it, and which must
.
is the responsibility of the
product with a third party
and
or distributor
notify that
responsibility and liability for and
product who distributes,
the above content and conditions, and the buyer or distributor
AKM any and
otherwise
the
in
the use of said product in the absence of such notification.
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