AL1402 [ETC]
OPTOREC CONVERTER; OPTOREC转换器
| 型号： | AL1402 |
| 厂家： | 
ETC |
| 描述： | OPTOREC CONVERTER |
| 文件： | 总8页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Gen eral Descript ion
Feat u res
Com patible with ADAT Type I an d II
form ats
Th e AL1402 OptoRec in terface is designed
to decode the ADAT optical data stream
an d produ ce fou r stereo pairs of au dio
data. Alesis ADAT U.S. patent n u m ber
5,297,181.
4
stereo pairs as ou tpu ts u sin g
stan dard ADC form ats
4 u ser bit ou tpu ts to receive time-code,
MIDI data, etc.
Intern al PLL generates requ ired clocks
from optical data.
Word Clock in pu t to synch ron ize
ou tpu ts to u ser’s system .
Use of th is produ ct requ ires
a license
agreement between m anu factu rer an d
Alesis Stu dio Electron ics. Details an d
agreement in form ation are available u pon
requ est from Alesis Sem icon du ctor or
Alesis Stu dio Electron ics.
Applicat ion s
Receive in form ation
com patible devices.
from
ADAT
GND
MODE0
FMT0
VDD
LINMODE
MUTE
ERROR
FMT1
MODE1
OPDIGIN
SVCO
HOLDERR
OPDIGTHRU
DVCO
WDCLK
BCLK
USER3
USER2
OUT 1/ 2
OUT 3/ 4
OUT 5/ 6
USER1
USER0
OUT 7/ 8
Figu re A. 2 4 p in SOIC
Alesis Semicon du ctor
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
DS1402-0702
Ph one (310) 301-0780
Fax (310) 306-1551
www.alesis-semi.com
Table 1 Elect rical Ch aract erist ics an d Op erat in g Con dit ion s
Sym bol
Descript ion
Min
Typ
Max
Un it s
Recom m en d ed Op era t in g Con d it ion s
VDD
Su pply Voltage
Su pply Cu rren t, Master
Su pply Cu rren t, Slave
Grou n d
4.5
-
-
-
5.0
7.7
5.4
0.0
48
5.5
-
-
-
55
70
V
m A
m A
V
kHz
°C
IDD Master
IDD Slave
GND
Fs
Tem p
Sam ple rate
Tem peratu re
30
0
25
In pu t s (WDCLK, FMT, OPDIGIN, MODE, LINMODE, MUTE, HOLDERR)
VIH
VIL
IIH
IIL
CIN
Logical “1” in pu t voltage
Logical “0” in pu t voltage
Logical “1” in pu t cu rren t
Logical “0” in pu t cu rren t
Logic In pu t Capacitan ce
0.75 VDD
-
-
-
-
-
VDD
VDD
u A
u A
pF
-
-
-
-
0.25 VDD
1
1
-
5
Ou t pu t s (WDCLK, DVCO, OPDIGTHRU, SVCO, BCLK, ERROR)
VOH
VOL
IOH
Logical “1” ou tpu t voltage
Logical “0” ou tpu t voltage
Logical “1” ou tpu t cu rren t
Logical “0” ou tpu t cu rren t
0.9 VDD
-
-
-
-
-
VDD
VDD
m A
m A
-
-
-
0.1 VDD
-8
8
IOL
Ou t pu t s (OUT, USER)
VOH
VOL
IOH
Logical “1” ou tpu t voltage
0.9 VDD
-
-
-
-
-
VDD
VDD
m A
m A
Logical “0” ou tpu t voltage
Logical “1” ou tpu t cu rren t
Logical “0” ou tpu t cu rren t
-
-
-
0.1 VDD
-2
2
IOL
Table 2 Pin Descrip t ion s
Pin #
Nam e
Pin
Descript ion
Type
Power
In pu t
In pu t
In pu t
In pu t
In pu t
1
2
3
4
5
6
GND
MODE0
FMT0
FMT1
MODE1
OPDIGIN
Grou n d pin
Mode s elect
Form at select
Form at select
Mode s elect
In pu t from optical receiver
Derived clock from WDCLK in slave m ode; derived from DVCO in Ma ster m ode
(n om in al 12.288MHz, 256x Fs)
7
SVCO
Ou tpu t
8
9
WDCLK
BCLK
I/ O
In pu t or ou tpu t wor d clock, see Ta ble 4, Modes (n om in al 48KHz, Fs)
Bit clock (n om in al 3.072MHz, 64 x Fs)
Ch an n els 1 an d 2 data ou tpu t
Ch an n els 3 an d 4 data ou tpu t
Ch an n els 5 an d 6 data ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
Ou tpu t
10
11
12
13
14
15
16
17
18
19
OUT 1/ 2
OUT 3/ 4
OUT 5/ 6
OUT 7/ 8
USER0
USER1
USER2
USER3
DVCO
Ch an n els 7 an d 8 data ou tpu t
USER0 data bit ou tpu t. Used to receive tim ecode
USER1 data bit ou tpu t. Used to receive MIDI data.
USER2 data bit ou tpu t. Reserved.
USER3 data bit ou tpu t. Reserved.
Recovered clock from data stream (n om in al 12.288MHz, 256 x Fs)
OPDIGIN is regen erated an d clocked ou t on th is pin to allow daisy-ch ain in g
If h igh , th e ERROR pin stays h igh u n til th e cau se of th e error is rem oved AND
th e HOLDERR pin goes low.
In dicates lack of in pu t or failu re to syn ch r on ize to data strea m , m u tes data
ou tpu ts bu t n ot clock ou tpu ts
OPDIGTHRU
20
21
HOLDERR
ERROR
In pu t
Ou tpu t
22
23
24
MUTE
LINMODE
VDD
In pu t
In pu t
Power
If h igh , m u tes ou tpu ts
Tie h igh
+5V power pin
Alesis Semicon du ctor
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
DS1402-0702
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 2 -
Mast er an d Slave Modes
Use
Mast er Mode:
Th e AL1402 OptoRec in terface h as been
designed for ease of u se an d flexibility in
system s designed to in terface to the ADAT
protocol. It su pports both left an d righ t
ju stified data form ats for ease of integration
in to existin g devices as well as new devices.
Th ese form ats allow it to operate in parallel
with m an y stan dard ADC’s.
All ou tpu ts are derived from the in pu t
optical form at data stream on the OPDIGIN
(pin 6). WDCLK is an ou tpu t.
Slave Mode:
DAC ou tpu ts, USER ou tpu ts, BCLK an d
SVCO ou tpu ts are synch ron ized to WDCLK,
which is an in pu t.
Th e designer u ses the FMT0, FMT1, MODE0
an d MODE1 pins to select the desired
form at an d m ode.
In Slave mode, WDCLK m ay be at an
arbitrary ph ase with respect to the incoming
sam ples of OPDIGIN, bu t if the frequ en cies
aren ’t iden tical sam ples will be dropped,
repeated, or garbled. Generally, identical
frequ en cies are achieved by either: u sin g
DVCO (pin 18) as the sou rce from wh ich
WDCLK is generated, or creatin g OPDIGIN
from a sou rce syn ch ron ized to WDCLK.
Th e form at pins are su m m arized in Table 3,
Form ats. Th e AL1402 provides su pport for
both the ADAT Type I form at (16-bit) an d
the ADAT Type II form at (20-bit). Data
ou tpu t is 24 bit. Data in pu t len gth s u p to
24 bits is su pported.
USER0 is u sed to receive the ADAT form at
32-bit tim code; USER1 is u sed to receive
MIDI data (if the sou rce device su pports
these featu res). USER2 an d USER3 are
reserved an d shou ld not be u sed.
Table 3 Form at s
FMT1
FMT0
Form at
0
0
1
1
0
1
0
1
OUT data is righ t ju stified, BCLK falls on ch an gin g WDCLK
OUT data is left ju stified, BCLK rises on ch an gin g WDCLK
Ch ip Reset
Gated BLCK, BCLK rises on ch an gin g WDCLK
Table 4 Modes
MODE1
MODE0
Mode
0
0
Master m ode, WDCLK is an ou tpu t
Slave m ode, WDCLK is an in pu t. WDCLK MUST be derived from th e sa m e clock
su pplyin g th e s ou rce
Reserved
0
1
1
1
0
1
Reserved
Alesis Semicon du ctor
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
DS1402-0702
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 3 -
TIMING
WDCLK
LEFT CHANNEL
tDU
VALID
USER
OUT
tDS
Figu re B/ Table 5 Ou t p u t Delay
Sym bol
tDU(Master)
tDU(Slave)
tDS(Master)
tDS(Slave)
Min
-10
Typ
2
Ma x
27
Un its
n sec
-7
-10
-8
5
0
2
n sec
n sec
n sec
30
25
27
(Above specifications h old after 3900 WDCLK cycles of valid in pu t at OPDIGIN)
on e period WordClock
WDCLK
23
0
23
0
Left J u st 24
ADAT Type II
ADAT Type I
MSB
MSB
†
†
19
MSB
0
19
MSB
0
15
MSB
0
15
MSB
0
BCLK (rising)
23
0
23
0
Right J u st 24
MSB
MSB
†
19
MSB
0
19
MSB
0
ADAT Type II
ADAT Type I
†
15
MSB
0
15
MSB
0
BCLK (falling)
23
MSB
0
23
MSB
0
Left J u st 24
Gated BCLK
Master Mode
WDCLK
SVCO
2
2
124 125 126 127 128 129
124 125 126 127 128 129
132
132
252 253 254 255 256
252 253 254 255 256
1
1
3
3
4
4
5
5
130 131
130 131
133
133
Figu re C.
Ou t p u t
DVCO
Slave Mode
Tim in g
Diagram
In Slave m ode DVCO is n ot ph ase aligned with WDCLK and SVCO.
MSB bit is s ign extended to left of fram e.
†
Th ese diagra ms represent how data wou ld be fram ed from an ADAT type I
or type II device. They are not a ctu al modes of the AL1402. The Left
J u stified Mode is recom m ended for ADAT forma ts.
Alesis Semicon du ctor
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
DS1402-0702
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 4 -
Mech a n ical Specificat ion
Table 6 Pack age Dim en sion s
Dim en sion s (Typical)
In ch es
.606”
.295”
.406”
.100”
.008”
.025”
.050”
.017”
.011”
.352”
.033”
Millim eters
15.40
7.50
A
B
C
D
E
F
G
H
A
10.30
2.50
0.20
0.64
1.27
0.42
0.27
8.94
0.83
24
13
12
C
B
1
J
K
L
Notes:
1) Dimen sion “A” does not in clu de mold
flash , protru sions or gate bu rrs.
7 ° n om
K
4° n om
J
D
H
E
L
G
F
Figu re D. Mech an ical Drawin g
Alesis Semicon du ctor
DS1402-0702
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 5 -
Sam ple Applicat ion Sch em at ic
+5V
0.1u F
+5V
5
NC
4
INPUT
3
VCC
OPTOGEN
19
0.1u F
11
12
13
14
8.2k
20
VDD
2
C_LIMIT
1
IN 1/ 2
IN 3/ 4
IN 5/ 6
IN 7/ 8
IN 1/ 2
IN 3/ 4
IN 5/ 6
IN 7/ 8
GND
OPDGOUT
NC
4
5
6
TOTX173*
WDCLK
RESET
WDCLK
RESET
OPTICAL OUT
TIME CODE
MIDI DATA
15
16
17
18
7
8
9
6
USER0
USER1
USER2
USER3
FMT0
FMT1
FMT2
FMT3
WDCLKNEG
+5V
+5V
NC
NC
2
3
NC
NC
5
10
47u H
GND
+5V
1
3
1
OUTPUT
VCC
2
4
GND1
GND2
+5V
0.1u F
0.1u F
6
TORX173*
OPTOREC
6
24
VDD
19
10
11
12
13
OPDIGTHRU
OUT 1/ 2
OUT 3/ 4
OUT 5/ 6
OUT 7/ 8
OPDIGTHRU
OUT 1/ 2
OUT 3/ 4
OUT 5/ 6
OUT 7/ 8
OPDIGIN
3
FMT0
OPTICAL IN
4
FMT1
ERROR
21
20
ERROR
14
15
16
17
18
7
HOLDERR
USER0
USER1
USER2
USER3
DVCO
SVCO
WDCLK
BCLK
TIME CODE
23
LINMODE
NC
NC
MIDI DATA
2
5
MODE0
MODE1
8
9
DVCO
22
MUTE
GND
SVCO
(Master Mode, can be MCLK)
1
WDCLK (Slave Mode)
WDCLK (Master Mode)
BCLK (Master Mode)
*
Optica l I/ O pa rts sh own a re Toshiba pa rts. Th e Sh arp GP1F33RT or equ ivalen t is also com patible.
LEFTIN
LEFTOUT
RIGHTIN
RIGHTOUT
INL/ R
WDCLK
BCLK
OUTL/ R
WDCLK
BCLK
MCLK
MCLK
ADC
DAC
Figu re E. Op t oGen / Op t oRec set up
Th e OptoGen accepts inpu t from an ADC, th en ou tpu ts th e Alesis optical form at. Th e
OptoRec accepts inpu t in Alesis optical form at, th en ou tpu ts to a DAC.
Alesis Semicon du ctor
DS1402-0702
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 6 -
Applicat ion Not es
Th e clock an d data ou tpu ts of the AL1402
are u n defined after power-u p u n til a proper
data stream is well established at OPDIGIN
(pin 6). Th e clock ou tpu ts m ay be ru n ning
at an u n controlled frequ en cy. In th is case,
the ERROR pin will be high , in dicating th at
u nwan ted in the system an extern al AND
im plemen tation can be u sed to correct this.
Th e in verted error pin an d the desired
AL1402 ou tpu t clock are inpu ts to the AND
an d the desired mu table clock is ou tpu t.
Th is AND fu nction will m u te the selected
AL1402 clock when the error pin is high (i.e.
when u n stable in pu t is presen t at OpDigIn ).
Care sh ou ld be taken when ru nn in g the
AL1402 with the AL1201 DAC as the
AL1201 DAC will ou tpu t n oise if the AL1402
WDCLK is at an u n controlled VCO frequ en cy
th at is beyon d the AL1201 m aximu m
the ou tpu ts are in valid.
Th is m ay be
prevented by applying logic one to FORMAT1
(pin 4) an d logic zero to FORMAT0 (pin 3) on
power-u p. Th is resets the AL1402, stopping
the VCO clocks and m u tin g the data ou tpu t.
Th e FORMAT pin s m ay then be set to the
valu e requ ired in you r system . Nevertheless
the AL1402 will syn ch ronize an d produ ce
proper ou tpu ts when proper an d valid
in pu ts are provided, whether this reset
procedu re is u sed or not.
frequ en cy.
fu n ction can be u sed to select the AL1402
WDCLK to be mu ted when in valid
Th e
aforemen tioned
AND
OpDigIn pu t is present before proceeding as
the AL1201 WDCLK. See Figu re F. with the
AND fu n ction im plemen ted with NAND
gates. In place of th is circu it the ERROR pin
can be u sed as a m u te select for an y au dio
ou tpu t stage mu tin g circu itry th at m ay be
Th e AL1402 in Master Mode can also
produ ce
clock
ou tpu ts
ru n ning
at
u n con trolled frequ encies if the digital in pu t
becomes u n stable after stable u se, du e
m ostly to poor con nection of the optical
cable to the optical connector. If this is
present in the system.
Figu re F. AL1 4 0 2 –AL1 2 0 1 CLK MUTE CIRCUIT.
Alesis Semicon du ctor
DS1402-0702
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 7 -
NOTICE
Alesis Semicon du ctor reserves the righ t to m ake ch an ges to their produ cts or to discontinu e any
produ ct or service with ou t notice. All produ cts are sold su bject to term s an d con dition s of sale
su pplied at the time of order acknowledgemen t. Alesis Semicondu ctor assu mes n o respon sibility
for the u se of an y circu its described herein , con veys no licen se u n der any paten t or other righ t,
an d m akes no represen tation th at the circu its are free of paten t in frin gemen t. In form ation
con tained here in are on ly for illu stration pu rposes an d m ay vary depen ding u pon a u ser’s
specific application . Wh ile the in form ation in th is pu blication h as been carefu lly checked, no
respon sibility is assu med for in accu racies.
Alesis Semicon du ctor produ cts are not designed for u se in any applications which involve
poten tial risks of death , person al inju ry, or severe property or en viron men tal dam age or life
su pport application s where the failu re or m alfu nction of the produ ct can reason ably be expected
to cau se failu re of the life su pport system or to significantly affect its safety or effectiveness.
All tradem arks an d registered tradem arks are property of their respective owners.
Con tact In form ation :
Alesis Sem icon du ctor
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
Ph on e: (310) 301-0780
Fax: (310) 306-1551
Em ail: sales@alesis-sem i.com
Copyrigh t 2002 Alesis Sem icon du ctor
Datasheet J u ly 2002
Reprodu ction , in part or in whole, with ou t the prior written con sen t of Alesis Semicon du ctor is
prohibited.
Alesis Semicon du ctor
DS1402-0702
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 8 -
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