AL260_技术文档

Video Enhancement

Processor

AL260 Data Sheets

AL260

Amendments

99.10.04 Preliminary version

Preliminary version A0.1:

02.12.19

(1) Updated from Preliminary version

Version B1.0:

(1) Updated from Preliminary version A0.2

(2) Add Register Description

03.05.16

THE INFORMATION CONTAINED HEREIN IS SUBJECT TO CHANGE WIHOUT NOTICE.

Version B1.0

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Contents:

1. General Description ................................................................................................... 5

2. Function Block Diagram ............................................................................................ 6

3. Features ...................................................................................................................... 6

3.1 General Features.................................................................................................... 6

3.2 Feature Description: .............................................................................................. 7

4

5

6

7

Applications................................................................................................................ 8

Application Example .................................................................................................. 9

Pin-Out Diagram ....................................................................................................... 10

Pin Definition and Description ................................................................................ 11

7.1 Input Format Table of AL260:.............................................................................. 11

General Function Description ................................................................................. 15

8.1 Function Blocks ................................................................................................... 15

8.2 VIU (Video Input Unit)........................................................................................... 15

8

8.2.1

8.2.2

8.2.3

8.2.4

Input Data Format ......................................................................................... 15

Video Capture and Down Scale Engine ...................................................... 16

Automatic Positioning Registers................................................................. 17

PLL Programming for Memory and Display Clock..................................... 17

8.3 MIU (Memory Interface Unit)................................................................................ 17

8.3.1

8.3.2

DRAM Bandwidth Consideration................................................................. 17

DRAM Input/Output Windows ...................................................................... 18

8.3 VPU (Video Processing Unit)............................................................................... 18

8.4.1

8.4.2

8.4.3

Video De-Interlaced with Film Detection and Motion Adaptive................. 19

Up Scale Engine............................................................................................ 19

Keystone Up Scale Engine........................................................................... 20

8.4 VOU (Video Output Unit)...................................................................................... 20

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8.5.1

8.5.2

8.5.3

OSD ................................................................................................................ 22

LUT (Look up table for Gamma Correction and Color Enhancement) ..... 22

Dithering ........................................................................................................ 23

8.5 BIU (Bus Interface Unit)....................................................................................... 23

Register Definition.................................................................................................... 24

9.1 Register Set .......................................................................................................... 24

9.2 Register Description ............................................................................................ 32

9

10 Electrical Characteristics......................................................................................... 76

10.1 Absolute Maximum Ratings ............................................................................ 76

10.2 Recommended Operating Conditions............................................................ 76

10.3 DC Characteristics........................................................................................... 76

10.4 AC Characteristics........................................................................................... 77

11 Timing Diagrams ...................................................................................................... 78

12 Mechanical Drawing- PQFP-208.............................................................................. 79

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1. General Description

AL260 is a highly integration Video Enhancement Processor which supports video input

with multiple video formats then output with De-interlacing and Scaling effects. It can be

used for most video conversion and processing applications.

AL260 is equipped with a high quality scaling engine that automatically maintains full

screen output display, regardless of the resolution of the incoming signals. Applying

AverLogic’s proprietary scaling algorithm, the primary input video can be scaled up and

scaled down independently in horizontal & vertical directions. It also provides film

detection, advanced de-interlacing, filtering, and scaling which’s able to convert and

process the interlaced video to be displayed on progressive panels.

The On Screen Display (OSD) window provides overlay of a control menu, text, or caption

on the output display. It’s built-in OSD generator with 2K Bytes programmable RAM fonts

and also supports optional external OSD.

AL260 is built-in 3-channel DAC for non-interlaced analog output and also supports 24bit

digital output. It’s housed with 208-pin QFP.

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2. Function Block Diagram

3. Features

3.1General Features

z

Support Digital YUV input and Non-interlaced RGB/YPbPr Analog and Digital outputs

Film Detection with Inverse 3:2/2:2 Pull Down

Advanced De-interlacing with Motion Compensation

AverLogic’s Proprietary Cubic Scaling Algorithm for Scaling Up and Down

Built-in 2K Bytes OSD RAM and support External OSD Font ROM

Available in 208-pin PQFP

2.5V Core and 3.3V I/O power supplies with 5V input tolerant

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3.2Feature Description:

z

Input Interface

z

NTSC/PAL support

Video interface ITU-R 601/656(8/16bit), YUV422 support

z

Output Interface

z

Output resolution up to 1280x1024 @60Hz

Analog non-interlaced RGB/YPbPr output supported

z

SDRAM Interface

z

Support maximum 32bit bus width SDRAM interface, two SDRAMs configuration up to 125 MHz

supported

De-interlacing and Scan Rate Conversion

z

De-Interlacing for Interlaced Video Input

Motion Compensation De-interlacing with Spatial and Temporal Filtering support

Film Detection with Inverse 3:2 & 2:2 pull down

Frame Rate Conversion(FRC) from 50Hz up to 120Hz

z

Scaling Engine and Video Processing

z

Independent Scale Up and Down in both Horizontal and Vertical direction with 4-line, high precision

interpolation

z

Digital Brightness/Contrast/Saturation Control

Keystone Correction for Front-Projection Systems

Sharpness Control

Built-in LUT for Gamma Correction and Color Adjustment

Dithering Logic for Color Depth Enhancement

z

I2C or Parallel Port Registers Access

z

Registers can be accessed by serial I2C port or 8 bit parallel port for high speed registers data

update

On Screen Display (OSD)

2K Bytes Internal OSD RAM for fine bitmaps and text font

z

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z

Dual internal OSD windows support with Alpha Blending/Transparency effect

Support up to 64K Bytes External ROM for Font or Bitmap data

In ROM mode, Internal OSD RAM supports 1.5K Bytes for Context RAM, 0.5K Bytes for Pre-fetch

RAM

z

Pre-fetch RAM supports different speed types of Font ROMs (EE-PROM, PROM or Mask-ROM)

z

Other Features

z

Primary input stream VBI pass through support

Frame capture Mirroring support in Horizontal or Vertical direction

NTSC/PAL Video Input Auto-Detection support

Power Saving support

Slave mode support

z

Operating Power

z

2.5V core and 3.3V I/O power supplies with 5V input tolerant

Package

z

208-pin PQFP

4 Applications

z

LCD TV

DTV & Front Projection/Rear Projection/Progressive Scan TVs

TV to PC Monitor Format/Scan Rate Converter

Video Enhancer/TV Tuner box

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5 Application Example

RGB/YPbPr

SDRAM

1M X 16bit

Analog Output

Audio

Processor

AverLogic

AL260

PanelLink

Digital

16/8 bit

YUV

Analog

Video

DVI Tx.

Decoder

Output

(S-Video

Or CVBS)

SVGA/XGA

LCD Panel

LVDS Tx.

MCU

MTP/OTP

64K

OSD

Font ROM

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6 Pin-Out Diagram

PQFP-208 Package:

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7 Pin Definition and Description

7.1Input Format Table of AL260:

VIN No.

VIDEO

15~8

Y

7~0

CbCr

YCbCr

The pin-out definitions are described as follows:

Pin Name

Input Interface

VIN

Pin Number

I/O type

Description

I

Video Input Bus Bit 15-8, lower 8 bits of ITU-R 601

16bit data bus

[15:14],

[13:10],

[9:8]

49-48,

46-43,

41-40

VIN

I

Video Input Bus Bit 7-0, upper 8 bits of ITU-R 601

16bit data bus OR

[7:4],

33-30,

28-25

35

[3:0]

Video Input Bus Bit 7-0 of ITU-R 656 8bit

Reference Clock of Video Port

HDE of Video Port

VCLK

I

VHREFF

VHS

37

38

HSYNC of Video Port

VVS

39

VSYNC of Video Port

OSD ROM Interface

RDATA

I

ROM Data Bus Bit 7-0

[6:0],

[7]

22-16,

24

RA

O

ROM Address Bus Bit 15-0

[15:0]

203-188

DAC Output Interface

AVDD33

AVSS33

AVDD25

AVSS25

AVDD33R

154

136

152

153

146

AP

AG

AP

AG

AP

3.3v Analog Power for DAC

Analog GND for DAC

2.5V Analog Power for DAC

Analog GND for DAC

3.3 V Analog Power for Channel R

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Pin Name

AVSS33R

Pin Number

147

I/O type

Description

Analog GND for Channel R

AG

AP

AG

AP

AG

AP

AG

O

AVDD33G

AVSS33G

AVDD33B

AVSS33B

DVDD25

DVSS25

IOR

143

144

140

141

137

138

145

142

139

148

149

150

151

3.3 V Analog Power for Channel G

Analog GND for Channel G

3.3 V Analog Power for Channel B

Analog GND for Channel B

2.5V Digital Power for DAC

Digital GND for DAC

Channel R Current Output

Channel G Current Output

Channel B Current Output

Full-Scale Adjust Resister

Compensation Pin

IOG

O

IOB

O

RSET

I

COMP

I

VREFIN

VREFOUT

I

Voltage Reference Input

Voltage Reference Output

O

Digital Output Panel Interface

VOUT

O

Digital Video Output Bit 23-0

[23:16],

[15:5],

185-178,

168-158,

133-129

170

[4:0]

SCLK

O

I

Display Pixel Clock

PDSDEN

PHS

172

Display Data Enable

173

HSYNC Input for Slave Mode

VSYNC Input for Slave Mode

Reference Clock for Display Device

PVS

174

I

OXIN

176

I

SDRAM Interface

MDATA

[31:24],

[23-12],

[11:0]

I/O

SDRAM Data Bus Bit 31-0

113-106,

103-92,

83-72

MADDR

[10:6],

SDRAM Address Bit 10-0

128-124,

122-117

[5:0]

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Pin Name

PMXIN

Pin Number

115

I/O type

Description

SDRAM Read Data Input Sampling Clock

SDRAM Bank Address Bit 0-1

SDRAM Row Address Strobe

SDRAM Column Address Strobe

SDRAM Write Enable

I

BA[1:0]

91-90

89

O

RASB

CASB

88

WEB

87

CLK

85

SDRAM reference Clock

Host Interface

HOST_DB

[7:2],

I/O

Host Bus Bit 7-0

59-54,

51-50

63

[1:0]

HOST_WRB

HOST_RDB

HOST_DENB

HOST_MEMB

HOST_RDYB

IREQ

I

Reference Clock

64

Read/Write Strobe

Data Cycle

65

I

69

I

Memory Cycle

70

O

I/O

I

Read Data Ready Output

Interrupt Output

71

SDA

205

204

186

206

Data Bit for Serial Bus

Clock Bit for Serial Bus

I2C Enable

SCL

I2C_EN

I

INTB

O

Interrupt for Serial Protocol

PLL Interface

MXIN

15

14

2,7

3,6

5

I

Crystal Input (14.31818MHz)

Crystal Output

MXOUT

O

P1VDD25

P1VSS25

P1AVDD25

P1AVSS25

P2VDD25

P2VSS25

P2AVDD25

P2AVSS25

Others

DP

DG

AP

AG

DP

DG

AP

AG

2.5V Pad Ring Power for PLL1

Pad Ring GND for PLL1

Analog Power for PLL1

Analog GND for PLL1

4

8,12

9,13

11

10

2.5V Pad Ring Power for PLL2

Pad Ring GND for PLL2

Analog Power for PLL2

Analog GND for PLL2

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Pin Name

RSTB

NC

DIGITAL POWER / GROUND

Pin Number

207

61, 67

I/O type

Description

I

Reset

No Connection

VDD25

34, 42, 62, 86,

DP

DG

Digital Power 2.5V

Digital Ground 2.5V

116, 134, 156,

177

VSS25

36, 47, 60, 68,

84, 135, 155,

171, 187

VDD33

VSS33

1, 29, 53, 66,

105, 169, 208

23, 52, 104, 114,

123, 157, 175

DP

DG

Digital Power 3.3V

Digital Ground 3.3V

Note: For I/O type, “I”, “O”, “AP”, “AG”, “DP”, and “DG” stand for “Input”, “Output”, “Analog

Power”, “Analog Ground”, “Digital Power”, and “Digital Ground” respectively.

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8 General Function Description

8.1Function Blocks

AL260 provide a fully programmable structure allowing video stream process more flexible.

The AL260 data process is executed by parsing in the modules such as capture, down

scale, memory, up scale and mixer. In each module, data will be manipulated

corresponding to the setting of registers. Due to the lack of the number of registers, some

registers require banking to other page for access. There are 4 group registers, base

control registers, capture control registers, memory control registers and display control

registers. The value of base register 0eh determines which group of registers is taken

effect. If register 0eh is programmed to value 00, the group of base control registers is

chosen; and the register 0eh with value 01 is for capture register group, value 02 is for

memory register group and value 03 is for display register group. The register 0eh must

be set to corresponding value before that group of register can be accessed.

Register Group ID

Group register Description

Symbol Example

00 Access only base control registers

BAS#

CAP#

MEM#

DIS#

BAS#16

CAP#20

MEM#32

DIS#61

01 Access capture and base control registers

10 Access memory and base control registers

11 Access display and base control registers

<1:0>

0Eh

8.2VIU (Video Input Unit)

AL260 accepts 16/8bit YUV 4:2:2 (NTSC/PAL) video data stream with ITU-R-656/601

standards. Applying AverLogic Proprietary Scaling algorithm, the video stream can be

scaled down to accommodate required output resolutions with high quality scaling effect.

The high quality scaling engine also ensures full screen output display.

8.2.1 Input Data Format

The AL260 is an integrated video processor that automatically detects and converts

multiple video formats. The Index and Base registers provide user an expansion of the

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control registers, which implements easy control of the input and the desired output format.

The Base registers control the input type and target format.

The AL260 accepts two data formats: 8-bit ITU-R BT.656 (CCIR656) and 16-bit CCIR601

422. The clock and sync signal pins separate for RGB or YUV while the YUV data share

the same pins as RGB data. For detailed applications, please refer to AL260 Application

Notes.

8.2.2 Video Capture and Down Scale Engine

The AL260 has a high-quality scaling engine performing proprietary scaling operations

independently in both Horizontal and Vertical direction with 4-line, high precision

interpolation.

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8.2.3 Automatic Positioning Registers

The AL260 can detect and report input capture timing for Auto-adjustment function. It

detects the starting and ending positions of active video in both direction (Horizontal and

Vertical) and ensures the output fit properly into the display region. The data threshold

value defines the sensibility of valid data. The capture data will be sampled and qualified

base upon the value of data threshold, so that it can determine the starting point and

ending point of an active line or an active frame.

8.2.4 PLL Programming for Memory and Display Clock

AL260 embedded 2 independent 200MHz PLL-Based Clock Generator. One is used to

generate SDRAM clock, the other is for output clock. They are all reference input clock

from XIN (generally 14.318MHZ).

There are 3 operation modes in defined in PLL register: Power Down Mode, Bypass Mode

and Normal Mode. Power Down Mode forces FOUT to low and PLL in low power

consumption state (<10uW). Bypass Mode provides FOUT with the same frequency as

FIN. Normal Mode synthesizes FOUT by programming suitable divider values. It needs a

Tready time (Pull_in Time + Locking Time) for PLL to re-lock the FIN clock when PLL

wakes up from Power Mode to Normal Mode. In general, it should be reserved a Tread

time for re-locking when PLL is changed to Normal Mode from Power Mode or Bypass

Mode, or when any divider setting is changed.

8.3

MIU (Memory Interface Unit)

MIU supports SDRAM 32bit bus width interface. AL260 supports various SDRAM

configurations, such as 512Kx16, 2ea. It uses sequential Burst mode to control SDRAM

memory that operates at minimum 120MHz of clock frequency. For detailed operation of

SDRAM, please reference memory specifications.

8.3.1 DRAM Bandwidth Consideration

The AL260 uses external DRAMS for the purpose of frame rate conversion between the

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input video and the output video device. The frame rate conversion for video is done by

double buffering.

8.3.2 DRAM Input/Output Windows

The proceeding diagrams will describe the DRAM input control.

The DRAM input data size depends on the horizontal capture destination size.

After the input data size has been defined, the memory address of input data can be

determined by the register DRAM input stride. The DRAM input stride can be programmed

to provide extra memory space for input data.

8.3VPU (Video Processing Unit)

AL260 identifies video input sources including Progressive Film (24/25 fames/sec) and

Interlaced Video (50/60 fields/sec) and selects appropriate de-interlacing algorithm for

video enhancement. VPU supports Film Detection with Inverse 3:2 or 2:2 Pull Down and

AverLogic Proprietary De-interlacing. When AL260 detects the video source as Film, then

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progressive scan frames will be reassembled and output twice input rate such as 50/60

frame/sec. Otherwise, it will be taken as Interlaced Video Source, and processed by using

De-interlacing to reduce video artifacts. The scaling engine offers Scale-Up effect by

applying Cubic Scaling Algorithm. It supports independent Scale-Up in both Horizontal and

Vertical direction with 4-line, high precision interpolation. AL260 also offers Digital

Contrast, Brightness, and Saturation for Color adjustment. It can be adjusted in YUV data.

The Sharpness Control provides good effect for image enhancement. It also provides

Keystone function for Projector application.

8.4.1 Video De-Interlaced with Film Detection and Motion Adaptive

Video Processing unit equips a high quality de-interlacing algorithm to optimize the output

progressive scan frame by recovering film sequence and compensating motion effect

during the de-interlacing process. The motion estimation can evaluate both Y/C data or Y

data by setting register. In Motion compensation process, the sensitivity of the data

estimation can be adjusted by register for Lumina and Chroma threshold. In film video,

such as DVD movie, some duplicate fields are inserted into the interlaced video stream.

Original film sequence detection and recovery can produce a smooth progressive scan

frame transition after de-interlaced.

8.4.2 Up Scale Engine

The Up Scale Engine can scale up Primary Stream to higher resolution in high quality for

output display. The AL260 adapts FIR scaling engine that can do horizontal and vertical

up scale independently. The primary stream picture can be either down scale to smaller

size of picture or up scale to larger size of picture from original capture (input) picture for

output, but it can not do both up and down scale process at the same time. Consider to

capture full picture of input data if the output resolution of primary stream picture is going

to be enlarged.

Following block diagram illustrates the define registers of source primary stream window

and destination up scale window.

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AL260

8.4.3 Keystone Up Scale Engine

The AL260 can scale up the image in dynamic ratio which is good for LCD projector image

correction. The projected images from the LCD projector sometimes show as Figure due

to the misalignment or cheap optics. The AL260 can up scale picture in dynamic ratios

which are loaded from pre-stored at internal FIFO buffers. The keystone is designed to

compensate the distortions, such as figures following.

8.4VOU (Video Output Unit)

Two independent On-Screen-Display (OSD) windows provide overlay for a control menu,

text, or caption on the output display. The AL260’s OSD is very flexible in the way that the

font, size, and display location are all programmable. The internal 2K byte SRAM

provides storage for the OSD information. The OSD can be operated with only this

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internal SRAM or with an external ROM to store font tables or even larger bitmaps. Built-

in 8bit Programmable Gamma Look-Up Table for each input color channel for Gamma

Correction. It may be used for RGB Contrast, Brightness and Color Temperature

adjustments. Dithering is performed to retain color resolution for LCD panels that support

18-bit color depths.

AL260 provides Digital video output interface that can be directly connected to 24bit TFT

LCD Panel or DVI/LVDS Transmitters. It also provides Analog video output which can

support up to SXGA resolution.

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8.5.1 OSD

Two independent On-Screen-Display (OSD) windows provide overlay for a control menu,

text, or caption on the output display. The AL260’s OSD is very flexible in the way that the

font, size, and display location are all programmable. The internal 2K byte SRAM

provides storage for the OSD information. The OSD can be operated with only this

internal SRAM or with an external ROM to store font tables or even larger bitmaps.

Regarding the detailed usage, please refer to AL260’s OSD Application Note.

8.5.2 LUT (Look up table for Gamma Correction and Color Enhancement)

Because of the different characteristics of TV’s and PC monitors, direct color space

conversion from TV to PC may not show the same color that the human eye sees from the

original video on the TV. The contrast may not be sufficient, and the hue may not be

accurate, so to resolve these issues the AL260 has a gamma correction internal LUT

implemented.

The AL260 provides programmable registers for implementing the LUT. The directly

converted colors are sent to the LUT that then sends out the mapped, corrected colors.

The user can program the LUT based on his/her own experiments on specific types of

monitors. The typical input-output mapping curve is usually somewhat like the following:

Output

Corrected

Conversion

Direct

Conversion

Input

Figure 11 LUT Mapping

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8.5.3 Dithering

The AverLogic offers dithering technique that simulates display of colors that are not in the

current color space of a particular image. The Dithering logic provides additional color

depth enhancement to retain color resolution for LCD panels that support 18-bit color

depth.

8.5BIU (Bus Interface Unit)

It supports I²C serial and proprietary parallel programming interfaces. I²C serial interface

requires two wires to access while the proprietary parallel interface needs 11 wires. The

communication speed of proprietary parallel interface is much faster than I²C serial

interface.

Regarding to the detailed usage, please refer to AL260’s General Application Note.

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9 Register Definition

Registers are provided to setup AL260. These registers can be programmed via host

interface. The host interface protocol is illustrated in “Host Interface” paragraph. The

application notes will describe more detailed settings about these registers. Upon request,

AverLogic will provide the sample code or tool of host interface control software.

9.1Register Set

Register Name

Base Control Group Registers

COMPANYID

INTRMASK

Address

R/W Default

Function

00h

02h

03h

06h

07h

08h

09h

0Ah

0Eh

11h

12h

13h

14h

16h

17h

18h

1Bh

1Ch

1Dh

1Eh

1Fh

R

46h Company ID

00h Interrupt Mask

R/W

INTRSTATUS

CAPCTRL

00h Interrupt Vector and Mode

00h Capture Data Control

DISCTRL1

00h Display Data Control 1

DISCTRL2

00h Display Data Control 2

POLARITYCTRL

OTIMECTRL

GROUPACCESS

INSRCFORMAT

INPUTCTRL

HREFDLY

00h Display Polarity Control

00h Display Timing Control

00h Group Access ID

00h Input Video Source Format

00h Input Control

00h Horizontal Reference Delay

00h Capture control 1

CAPCTRL1

CAPCTRL2

00h Capture control 2

MEMACCR

00h Memory Access Control

00h Inverted MSB of Capture Data Format

00h PLL Setting for Memory and Display

00h LSB of NF Value for Memory PLL

00h MSB of NF/NR/NO Value for Memory PLL

00h LSB of NF Value for Display PLL

00h MSB of NF/NR/NO Value for Display PLL

INVMSB

PLLSETR

MPLLNF

MPLLNRO

OPLLNF

OPLLNRO

Capture Control Group Registers(Accessible when BAS#0E = 01h)

Capture Timing

CAPHSTART

21h & 20h

R/W

00h Horizontal Capture Start

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Register Name

CAPHSRCSIZE

Address

23h & 22h

25h & 24h

27h & 26h

29h & 28h

2Bh & 2Ah

2Eh

R/W Default

Function

R/W

00h Horizontal Capture Source Size

00h Horizontal Capture Destination Size

00h Vertical Capture Start

CAPHDESTSIZE

CAVSTART

CAPVSRCSIZE

CAPVDESTSIZE

INTERLACECTRL

HDNRATIO

00h Vertical Capture Source Size

00h Vertical Capture Destination Size

00h Interlace Control

31h & 30h

33h & 32h

00h Horizontal Scale Down Ratio

00h Vertical Scale Down Ratio

VDNRATIO

VBI Input Timing

VBIVSTART

34h

35h

36h

37h

R/W

00h VBI Vertical Capture Start

00h VBI Vertical Capture End

00h VBI Horizontal Capture Start

00h VBI Horizontal Capture Size

VBIVEND

VBIHSTART

VBIHSIZE

ITU-656 Detection

656HSTART

38h

39h

3Ah

3Bh

R/W

20h ITU656 data Horizontal sync start

A0h ITU656 data Horizontal sync end

02h ITU656 data Vertical sync start

04h ITU656 data Vertical sync end

656HEND

656VSTART

656VEND

Position Detection

POSDATATH

50h

R/W

R

00h Data Threshold for Position Detection

Horizontal Capture Active Start

Horizontal Capture Active End

Vertical Capture Active Start

POSHDESTART

POSHDEEND

POSVDESTART

POSVDEEND

Mode Detection

CAPHTOTALCNT

CAPVTOTALCNT

DBUFFLAGNUML

DBUFFLAGNUMH

TUNEINCLK

53h & 52h

55h & 54h

57h & 56h

59h & 58h

R

Vertical Capture Active End

63h & 62h

65h & 64h

70h

R

Horizontal Capture Total Counter

Vertical Capture Total Counter

R

R/W

00h Double Buffer Flag Number LSB

00h Double Buffer Flag Number MSB

00h Tune Input Clock Timing

72h

73h

Memory Control Group Registers(Accessible when reg.0Eh = 02h)

DRAM Control

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AL260

Register Name

DRAMACCESSCTRL

DRAMWRITE

Address

20h

R/W Default

Function

00h DRAM Access control

00h DRAM Write

R/W

21h

OUTFIFOCTRL

INFIFOCTRL

22h

00h Output FIFO Control

00h Input FIFO Control

00h DRAM Minimum Refresh

00h DRAM Control Register

00h DRAM Read Address

00h XY Mirror Input

23h

DRAMMINREFRESH

DRAMCTRL

28h

2Ah & 29h

2Dh ~ 2Bh

30h

DRAMRADDR

XYMIRRORIN

XYMIRROROUT

SKIPMODE

31h

00h XY Mirror Output

10h Skip Mode

32h

DRAM Input Window Control

DRAMSTART

33h

34h

35h

R/W

10h DRAM Input Start

00h DRAM Input Stride

00h DRAM Input Size

DRAMSTRIDE

DRAMISIZE

DRAM Window Copy Control

WCSRCSTART

GSDRAMINPUTSTRIDE

GSDRAMINPUTSIZE

WCSTRIDE

3Bh ~ 39h

3Ch

R/W

00h Window Copy Source Start

00h Window Copy Source Stride

00h Window Copy HSize

3Dh

3Eh

00h Direct Write Stride

WCDESTSTART

DASTART

41h ~ 3Fh

44h ~ 42h

45h

00h Window Copy Destination Start

00h Direct Read/Write Address

00h Window Copy Size

WCSIZE

WCLINETOTAL

DRAM Output Window Control

DRAMSTART

46h

00h Window Copy Line Total

47h

48h

R/W

00h DRAM Output Start

DRAMSTRIDE

00h DRAM Output Stride

DRAMSIZE

49h

00h DRAM Output Size

VBISTART

4Fh ~ 4Dh

50h

00h VBI Starting Address

FRONTMD

00h Front Motion Detect Control

00h Tune Memory Write Clock Timing

00h Tune Memory Read Clock Timing

TUNEMCLK

51h

TUNEPMCLK

52h

DRAM Data Port

Version B1.0

26

AL260

Register Name

READSTATUS

Address

60h

R/W Default

Function

R

Read Status

00h Byte 0

00h Byte 1

BYTE0

BYTE1

BYTE2

BYTE3

BYTE4

BYTE5

61h

R/W

62h

63h

00h Byte 2

00h Byte 3

00h Byte 4

00h Byte 5

64h

65h

66h

Display Control Group Registers (Accessible when reg.0Eh = 03h)

Display Timing

DISHTOTAL

21h ~ 20h

23h & 22h

25h & 24h

27h & 26h

29h & 28h

2Bh & 2Ah

2Dh & 2Ch

2Fh & 2Eh

R/W

00h Display Horizontal Total

DISHSEND

00h Display Horizontal Sync

00h Horizontal Display Start

00h Horizontal Display End

00h Display Vertical Total

00h Display Vertical Sync

00h Vertical Display Start

00h Vertical Display End

DISHDESTART

DISHDEEND

DISVTOTAL

DISVSEND

DISVDESTART

DISVDEEND

Window Output Timing

DISHDESTART

DISHDEEND

31h & 30h

33h & 32h

35h & 34h

37h & 36h

R/W

00h Horizontal Display Start

00h Horizontal Display End

00h Vertical Display Start

00h Vertical Display End

DISVDESTART

DISVDEEND

Zoom In Control Registers

DISHSRCSIZE

DISHDESTSIZE

DISVSRCSIZE

DISVDESTSIZE

ZOOMFCTRL

HUPRATIO

41h & 40h

43h & 42h

45h & 44h

47h & 46h

48h

R/W

00h Horizontal Display Source Size

00h Horizontal Display Destination Size

00h Vertical Display Source Size

00h Vertical Display Destination Size

00h Zoom In Filter Control

4Bh & 4Ah

4Dh & 4Ch

4Fh & 4Eh

00h Horizontal Scale Up Ratio

00h Delta Horizontal Scale Up Ratio

00h Vertical Scale Up Ratio

DELTAHUPRATIO

VUPRATIO

HPHASE

00h Horizontal Scale Up Initial Phase

Version B1.0

27

AL260

Register Name

VPHASE

Address

51h & 50h

54h

R/W Default

Function

R/W

00h Vertical Scale Up Initial Phase

00h Output Mode

OUTPUTMODE

LUTINDEX

55h

00h LUT Write Index

LUTRED

5Ch

00h LUT Red Color LSB

00h LUT Green Color LSB

00h LUT Blue Color LSB

LUTGREEN

5Dh

LUTBLUE

5Eh

LUTCOLOR

5Fh

00h LUT Color MSB and Read/Write Trigger

00h Pattern Generator and GPO

PATTERNGEN

OSD Color Registers

OSDRAMWADDR

OSDRAMWDATA

COLOR0RED

COLOR0GREEN

COLOR0RED

COLOR1RED

COLOR1GREEN

COLOR1BLUE

COLOR2RED

COLOR2GREEN

COLOR2BLUE

COLOR3RED

COLOR3GREEN

COLOR3BLUE

COLOR4RED

COLOR0GREEN

COLOR4BLUE

COLOR5RED

COLOR5GREEN

COLOR5BLUE

COLOR6RED

COLOR6GREEN

COLOR6BLUE

56h

59h & 58h

5Ah

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

R/W

W

00h OSD Write Address

00h OSD Write Data Port

00h Color 0 Red

00h Color 0 Green

00h Color 0 Blue

00h Color 1 Red

00h Color 1 Green

00h Color 1 Blue

00h Color 2 Red

00h Color 2 Green

00h Color 2 Blue

00h Color 3 Red

00h Color 3 Green

00h Color 3 Blue

00h Color 4 Red

00h Color 4 Green

00h Color 4 Blue

00h Color 5 Red

00h Color 5 Green

00h Color 5 Blue

00h Color 6 Red

00h Color 6 Green

00h Color 6 Blue

R/W

Version B1.0

28

AL260

Register Name

COLOR7RED

Address

75h

R/W Default

Function

R/W

00h Color 7 Red

COLOR7GREEN

COLOR7BLUE

OSD Control Registers

OSDCOLORSEL

BLINKTIME

76h

00h Color 7 Green

00h Color 7 Blue

77h

78h

79h

80h

81h

83h

82h

R/W

00h OSD Color Select

00h OSD Blink Timer

00h OSD Modes

OSDMODE

FOREOP

00h Logic Operation 1

00h Logic Operation 2

FOREOP

FADEALPHA

00h Fading Alpha Value

OSD1 Registers

OSDCONTROL1

ROMSTARTADDR1

FONTADDRUNIT1

OSDHSTART1

OSDVSTART1

RAMADDRST1

RAMSTRIDE1

BMAPHSIZE1

84h

85h

R/W

00h OSD1 Control

00h OSD1 ROM Start Address

00h OSD1 Font Address Unit

00h OSD1 Horizontal Start

86h

90h

91h

00h OSD1 Vertical Start

92h

00h OSD1 RAM Start Address

00h OSD1 RAM Horizontal Stride

00h OSD1 Bitmap Horizontal Size

00h OSD1 Bitmap Horizontal Total Pixels

00h OSD1 Bitmap Vertical Size

00h OSD1 Bitmap Vertical total Lines

00h OSD1 Icon Horizontal Total

00h OSD1 Icon Vertical Total

00h OSD1 Font Line Size

8Bh & 93h

95h & 94h

97h & 96h

99h & 98h

9Bh & 9Ah

9Ch

BMAPHTOTAL1

BMAPVSIZE1

BMAPVTOTAL1

ICONHTOTAL1

ICONVTOTAL1

FONTLINESIZE1

OSD2 Registers

OSDCONTROL2

ROMSTARTADDR2

FONTADDRUNIT2

OSDHSTART2

OSDVSTART1

RAMADDRST2

9Dh

AEh

88h

89h

8Ah

A0h

A1h

A2h

R/W

00h OSD2 Control

00h OSD2 ROM Start Address

00h OSD2 Font Address Unit

00h OSD2 Horizontal Start

00h OSD2 Vertical Start

00h OSD2 RAM Start Address

Version B1.0

29

AL260

Register Name

RAMSTRIDE2

Address

8Ch & A3h

A5h & A4h

A7h & A6h

A9h & A8h

ABh & AAh

ACh

R/W Default

Function

R/W

00h OSD2 RAM Horizontal Stride

00h OSD2 Bitmap Horizontal Size

00h OSD2 Bitmap Horizontal Total Pixels

00h OSD2 Bitmap Vertical Size

00h OSD2 Bitmap Vertical Total Lines

00h OSD2 Icon Horizontal Total

00h OSD2 Icon Vertical Total

BMAPHSIZE2

BMAPHTOTAL2

BMAPVSIZE2

BMAPVTOTAL2L

ICONHTOTAL2

ICONVTOTAL2

FONTLINESIZE2

Desktop Color Registers

DESKR

ADh

AFh

00h OSD2 Font Line Size

B3h

B4h

B5h

R/W

00h Desktop Color Component Red

00h Desktop Color Component Green

00h Desktop Color Component Blue

DESKG

DESKB

Film Detection/ Motion Compensation Registers

MOTIONCNTTH

LUMATH

C5h & C4h

C6h

R/W

R

00h Motion Counter Threshold

00h Lumina(Y) Threshold

CHROMATH

MCCTRL

C7h

00h Chroma(C) Threshold

C8h

00h De-interlacing Control Register

00h Film Detection Control Register

00h Phase Detection Control Register

00h Motion Pixel Numbers

FILMCTRL

PHASECTRL

MVCNT

C9h

CAh

CFh & CEh

Keystone/Sharpness Registers

SHPKEYCTRL

CBh

R/W

00h Sharpness/Keystone Control Register

00h Keystone Parameters Address

KEYADDR

C1h & C0h

Tri-Level Sync Registers

TRISYNCA

D0h

D1h

D2h

D3h

D4h

D7h

W

00h Tri-Level Sync Parameter Period a

00h Tri-Level Sync Parameter Period b

00h Tri-Level Sync Parameter Delta 1

00h Tri-Level Sync Parameter Delta 2

00h Tri-Level Sync Parameter Period Blank

00h Tri-Level Sync Level

TRISYNCB

TRISYNCD1

TRISYNCD2

TRISYNCBLANK

TRISYNCLEVEL

Display Parameter Registers

DISTUNEHS

C2h

R/W

Tune Display Horizontal Sync Phase

Version B1.0

30

AL260

Register Name

DISTUNESCLK

Address

CCh

R/W Default

Function

Tune Display Pixel Clock Phase

Phase Detection Control Register

Display Horizontal Total Counter

Display Vertical Total Counter

Phase Counter

R/W

R

PHASECTRL

DISHTOTAL

DISVTOTAL

PHASECNT

DISADJEN

CAh

D8h & D7h

DAh & D9h

DCh & DBh

F0h

R

R/W

00h Enable Brightness/Contrast/Saturation

80h Brightness Level

BRIGHTNESS

CONTRAST

SATURATION

F1h

F2h

40h Contrast Level

F3h

40h Saturation Level

Version B1.0

31

AL260

9.2 Register Description

Base Control Group Registers

¾

INDEX

(HEX)

Register Description

Register Name

BITS

Function Description

00

02

Company ID (R) [COMPANYID]

CompanyID <7:0> Company ID (46h)

Interrupt Mask (R/W) [INTRMASK]

DVsyncIntMask <0> Display VSYNC interrupt mask

0

1

Mask interrupt issued by VSYNC of display

Interrupt issued when display VSYNC is activated

CAPVsyncIntMask <1>

Capture VSYNC interrupt mask

0

1

Mask interrupt issued by VSYNC

Interrupt issued when VSYNC is activated

Reserved

VBlMask

<2>

<3>

Reserved

Display vertical blank interrupt mask

0

1

Mask interrupt issued by display vertical blank

Interrupt issued by display vertical blank

FilmDetMask

FullDetMask

<4>

<5>

H/W Film detected finished interrupt mask

0

1

Mask interrupt issued by film detection

Interrupt issued when HW film detected

FIFO full for directly memory write Interrupt Mask

0

Mask interrupt issued by FIFO full for directly write to

SDRAM

1

Interrupt issued by FIFO full for directly write to SDRAM

WCopyEndMask

FIFOFullMask

<6>

<7>

Window copy finished interrupt mask

0

1

Mask interrupt issued by window copy

Interrupt issued by window copy

Arbiter FIFO full interrupt mask

0

1

Mask interrupt issued by FIFO index of arbiter

Interrupt issued when FIFO is full

Version B1.0

32

AL260

03

Interrupt Vector and Mode (R)(W) [INTRSTATUS]

DVsyncInt (R)

<0>

Display VSYNC interrupt

CAPVsyncInt (R) <1>

Capture VSYNC interrupt

Reserved

<2>

<3>

<4>

<5>

<6>

<7>

<0>

Reserved

VBlInt (R)

Display vertical blank interrupt

H/W Film detected finished interrupt

FIFO full for directly memory write interrupt

Window copy finished interrupt

Arbiter FIFO full interrupt

FilmDet (R)

FullDet (R)

WCopyEnd (R)

FIFOFull (R)

IntMode(W)

0

1

0

1

Trigger mode

Level mode

<1>

High active

Low active

<7:2>

Reserved

04~05: Reserved

06

Capture Data Control (R/W) [CAPCTRL]

CapVScaleDn

<0>

Capture vertical scale down enable

0

1

Disable

Enable

Reserved

SoGo

<4:1>

<5>

Tie to “0000”

Display timing strobe by capture VSYNC

Tie to 1

Reserved

GO

<6>

<7>

Capture timing enable

0

1

Disable

Enable

07

Display Data Control 1 (R/W) [DISCTRL1]

Reserved

CscEn

<2:0> Tie to “011”

<3> Capture data color space conversion

0

1

Disable color space converter

Enable color space converter

Version B1.0

33

AL260

Reserved

<7:4> Reserved

08

Display Data Control 2 (R/W) [DISCTRL2]

UVFlip2Path

<0>

U/V flip in display data path

0

1

Disable

Enable

UVFlip2Mem

<1>

U/V flipped in capture data path

0

1

Disable

Enable

Reserved

YPbPrEn

<2>

<3>

Tie to “0”

Color space conversion, refer to BAS#07<3>

0

1

YCbCr to RGB conversion

YPbPr to RGB conversion

Reserved

<7:4> Reserved

09

Display Polarity Control (R/W) [POLARITYCTRL]

OClkSel

<0>

Output clock source selection as display clock, refer to

BAS#09<7>

0

1

Select OXIN1 as display clock

Select OXIN2 as display clock

ControlEn

<1>

Panel output data signals (clock, data, HSYNC, VSYNC and PDE)

control enable

0

Disable output data signals to panel, all output data signals

tie to low

1

Enable panel output data signals

HSyncPol

BlankPol

VSyncPol

<2>

<3>

<4>

Output horizontal sync polarity

0

1

Positive

Negative

Output horizontal blank polarity

0

1

Positive

Negative

Output vertical sync polarity

0

1

Positive

Negative

Version B1.0

34

AL260

InvertOdd

CSyncOut

OPLLSel

<5>

<6>

<7>

Invert odd field signal

0

1

Positive

Negative

Composite sync out

0

1

Separate

Composite

Display reference clock source, refer to BAS#09<0>

0

1

From external pin (OXIN1/OXIN2)

From PLL

0A

Display Timing Control (R/W) [OTIMECTRL]

WinDisable

<0>

Display window diable

0

1

Enable

Disable

Reserved

<1>

<2>

Reserved

SlaveMode

Slave mode enable, refer to BAS#0A<3>

0

1

Output timing driven by internal registers

Output timing driven by external device(capture or external

display device)

SlaveType

<3>

Slave mode type, refer to BAS#0A<2>

0

1

Output timing is driven by capture timing

Output timing is driven by external display device

CSYNCType

<5:4> Compsit SYNC type

00

01

10

11

XOR

AND

NXOR

NAND

YPbPrAnalogOut

YPbPrDigitalOut

<6>

<7>

YPbPr analog output

0

1

RGB output

YpbPr output

YPbPr digital output

0

1

RGB output

YpbPr output

Version B1.0

35

AL260

0E

Group Access ID (R/W) [GROUPACCESS]

GroupAccessID

<1:0> Group register access control

00

01

10

11

Access only Base control registers

Access Capture and Base control registers

Access Memory and Base control registers

Access Display and Base control registers

Reserved

<7:2> Reserved

11

Input Video Source Format (R/W) [INSRCFORMAT]

CapInFormat

<1:0> Capture data input format

00

01

10

11

Reserved

16-bit

8-bit

Reserved

<5:2> Reserved

<6>

<7>

Tie to 0

Reserved

12

Input Control (R/W) [INPUTCTRL]

Reserved

HsPol

<2:0> Tie to “000”

<3>

Enable HS polarity detection

0

1

Disable, when turn on auto position function

Enable

VsPol

<4>

Enable VS polarity detection

0

1

Disable, when turn on auto position function

Enable

Reserved

<7:5> Reserved

13

14

Horizontal Reference Delay (R/W) [HREFDLY]

CapHRefDly

Reserved

<3:0> Capture HRef delay

<7:4> Reserved

Capture control 1 (R/W) [CAPCTRL1]

CapHScaleDn <0> Enable horizontal capture scale down

Version B1.0

36

AL260

Reserved

<1>

<2>

Reserved

Cap656SyncSel

Capture SYNC source when ITU656 input

0

1

From external SYNC input pin

From decoded ITU656 data

CapSoftRef

Reserved

<3>

Capture HREF source

0

1

From external HREF input pin

Software programmable

<7:4> Reserved

16

Capture control 2 (R/W) [CAPCTRL2]

Reserved

InvOddField

Reserved

Cap444En

<1:0> Tie to “00”

<2>

<3>

<4>

Invert internal detected capture odd field signal

Reserved

Input data format

0

1

YPbPr input format

YCbCr input format

Cap656En

DEdgeEn

Reserved

<5>

<6>

<7>

Enable input source is ITU656 format

Double edge sampling for ITU656 input

Reserved

17

Memory Access Control Register(R/W) [MEMACCR]

MemWEn

MemREn

HostMode

<0>

<1>

<2>

Directly write enable

Directly read enable

Host data mode

0

1

2x16-bit per each host cycle

1x24-bit per each host cycle

Reserved

DMAEn

<3>

<4>

<5>

<6>

Tie to “1”

Enable data output of directly memory

Reserved

WCopyEn

Window copy enable

0

1

Disable window copy

Enable window copy

MclkSel

<7>

Memory clock select

Memory clock from external PIN (XIN)

0

Version B1.0

37

AL260

1

Memory clock from internal PLL

18

Inverted MSB of Capture Data Format (R/W) [INVMSB]

InvBit7

<0>

<1>

<2>

Inverted bit 7 of input data

Inverted bit 15 of input data

Inverted bit 23 of input data

InvBit15

InvBit23

Reserved

<7:3> Reserved

Note: Please refer to General Application Note

PLL Registers

1B

PLL Setting Register for Memory and Display(R/W) [PLLSETR]

Power Down for Display PLL

OPLLPd

OPLLVon

OPLLBp

OPLLOe

MPLLPd

MPLLVon

MPLLBp

MPLLOe

<0>

<1>

<2>

<3>

<4>

<5>

<6>

<7>

0

1

PLL normal Operation

PLL Power Down

Reset for Display PLL

0

1

PLL normal Operation

Reset the PLL NF & NR Divider

Bypass Mode for Display PLL

0

1

PLL normal Operation

Bypass the PLL & FOUT=FIN

Output Control for Display PLL

0

1

FOUT= Fck/NO

FOUT=0

Power Down for Memory PLL

0

1

PLL normal Operation

PLL Power Down

Reset for Memory PLL

0

1

PLL normal Operation

Reset the PLL NF & NR Divider

Bypass Mode for Memory PLL

0

1

PLL normal Operation

Bypass the PLL & FOUT=FIN

Output control for memory PLL

FOUT= Fck/NO

0

Version B1.0

38

AL260

1

FOUT=0

Note: FOUT = FIN * NF/(NR*NO) = FVCO/NO, here FVCO is between 80MHz and 190Mhz

Here, FIN is input clock (example:14.31818MHz XTAL)

NF/NR, and NO are refer to BAS#1C~1F definition

1C

LSB of NF Value for Memory PLL(R/W) [MPLLNF]

MPLLNF <7:0> MPLLNF<7:0> Value for memory PLL

Note: NF is MPLLNF+2

1D

MSB of NF/NR/NO Value for Memory PLL(R/W) [MPLLNRO]

MPLLNR

MPLLNO

MPLLNF

<4:0> MPLLNR<4:0> value for memory PLL

<6:5> MPLLNO<1:0> value for memory PLL

<7>

MPLLNF<8> Value for memory PLL

Note: NR is MPLLNR+2, NO is MPLLNO+1

1E

LSB of NF Value for Display PLL(R/W) [OPLLNF]

OPLLNF <7:0> OPLLNF<7:0> Value for display PLL

Note: NF is OPLLNF+2

1F

MSB of NF/NR/NO Value for Display PLL(R/W) [OPLLNRO]

OPLLNR

OPLLNO

OPLLNF

<4:0> OPLLNR<4:0> value for display PLL

<6:5> OPLLNO<1:0> value for display PLL

<7>

OPLLNF<8> Value for display PLL

Note: NR is OPLLNR+2, NO is OPLLNO+1

Version B1.0

39

AL260

¾

Capture Control Group Registers (Accessible when BAS#0E = 01h)

I. Capture Timing

INDEX

(HEX)

Register Description

Register Name BITS

Function Description

20

21

Horizontal Capture Start LSB (R/W) [CAPHSTART]

CapHStartL

<7:0> Bits<7:0> of horizontal capture start position (Unit: 1 pixel)

Horizontal Capture Start MSB (R/W) [CAPHSTART]

CapHStartH

Reserved

<3:0> Bits<11:8> of horizontal capture start position

<7:4> Reserved

22

23

Horizontal Capture Source Size LSB (R/W) [CAPHSRCSIZE]

CapHSrcSizeL

<7:0> Bits<7:0> of horizontal capture source size (Unit: 1 pixel)

Horizontal Capture Source Size MSB (R/W) [CAPHSRCSIZE]

CapHSrcSizeH

Reserved

<3:0> Bits<11:8> of horizontal capture source size

<7:4> Reserved

24

25

Horizontal Capture Destination Size LSB (R/W) [CAPHDESTSIZE]

CapHDestSizeL

<7:0> Bits<7:0> of horizontal capture destination size (Unit: 1 pixel)

Horizontal Capture Destination Size MSB (R/W) [CAPHDESTSIZE]

CapHDestSizeH

Reserved

<3:0> Bits<11:8> of horizontal capture destination size

<7:4> Reserved

26

27

Vertical Capture Start LSB (R/W) [CAPVSTART]

CapVStartL

<7:0> Bits<7:0> of vertical capture start position (Unit: 1 line)

Vertical Capture Start MSB (R/W) [CAPVSTART]

CapVStartH

Reserved

<2:0> Bits<10:8> of vertical capture start position

<7:4> Reserved

Version B1.0

40

AL260

28

29

Vertical Capture Source Size LSB (R/W) [CAPVSRCSIZE]

CapVSrcSizeL

<7:0> Bits<7:0> of vertical capture source size (Unit: 1 line)

Vertical Capture Source Size MSB (R/W) [CAPVSRCSIZE]

CapVSrcSizeH

Reserved

<2:0> Bits<10:8> of vertical capture source size

<7:4> Reserved

2A

2B

Vertical Capture Destination Size LSB (R/W) [CAPVDESTSIZE]

CapVDestSizeL

<7:0> Bits<7:0> of vertical capture destination size (Unit: 1 line).

Vertical Capture Destination Size MSB (R/W) [CAPVDESTSIZE]

CapVDestSizeH

Reserved

<2:0> Bits<10:8> of vertical capture destination size

<7:4> Reserved

2E

Interlace Control (R/W) [INTERLACECTR]

InterlaceEn

FieldCap

<0>

Enable interlace timing input

<2:1> Field capture into memory

00

01

10

11

Capture even and odd field into memory

Capture odd field only

Capture even field only

Reserved

Fieldoffset

<7:4> Field capture offset

30

31

Horizontal Scale Down Ratio LSB (R/W) [HDNRATIO]

HDnRatioL

<7:0> Bits<7:0> of horizontal scale down ratio

Horizontal Scale Down Ratio MSB (R/W) [HDNRATIO]

HDnRatioH

Reserved

<0>

Bit<8> of horizontal scale down ratio

<7:1> Reserved

32

33

Vertical Scale Down Ratio LSB (R/W) [VDNRATIO]

VDnRatioL

<7:0> Bits<7:0> of vertical scale down ratio

Vertical Scale Down Ratio MSB (R/W) [VDNRATIO]

Version B1.0

41

AL260

VDnRatioH

Reserved

<0>

Bit<8> of vertical scale down ratio

<7:1> Reserved

Note: HDNRATIO = CAPHDESTSIZE / CAPHSRCSIZE * 256

VDNRATIO = CAPVDESTSIZE / CAPVSRCSIZE * 256

II. VBI Input timing:

VBI captured data is always been stored in DRAM address, starting at 0.

To Disable VBI capture, set VBIVStart > VBIVEnd, and VBIHStart > VBIHEnd

34

35

36

37

VBI Vertical Start (R/W) [VBIVSTART]

VBIVStart

<7:0> VBI vertical capture start position

VBI Vertical End (R/W) [VBIVEND]

VBIVend

<7:0> VBI vertical capture end

VBI Horizontal Start (R/W) [VBIHSTART]

VBIHStart

<7:0> VBI horizontal capture start position

VBI Horizontal Size (R/W) [VBIVSIZE]

VBIHSize

<7:0> VBI horizontal capture size

III. ITU-656 Detection:

38

39

3A

3B

ITU-656 Hsync Start (R/W) [656HSTART]

656HStart <7:0> ITU656data horizontal sync start position, default value 20h

ITU-656 Hsync End (R/W) [656HEND]

656HEnd

<7:0> ITU656data horizontal sync end position, default value 80h

ITU-656 Vsync Start (R/W) [656VSTART]

656VStart

<7:0> ITU656data vertical sync start position, default value 02h

ITU-656 Vsync End (R/W) [656VEND]

Version B1.0

42

AL260

656VEnd

<7:0> ITU656data vertical sync end position, default value 04h

<7:0> Luma(brightness) threshold value

IV: Position Detection:

50

Data Threshold for Position Detection (R/W) [POSDATATH]

PosDataTh

Note: CAP#50 is used to determine input non-blanking pixel for both horizontal and vertical direction. Any pixel

luma value less than this value will be considered as blanking.

52

53

Horizontal Active Start LSB (R) [POSHDESTART]

PosHDEStartL

<7:0> Bits<7:0> of detected horizontal active start position (Unit: 1 pixel)

Horizontal Active Start MSB (R) [POSHDESTART]

PosHDEStartH

Reserved

<2:0> Bits<10:8> of detected horizontal active start position

<7:3> Reserved

54

55

Horizontal Active End LSB (R) [POSHDEEND]

PosHDEEndL

<7:0> Bits<7:0> of detected horizontal active start position (Unit: 1 pixel)

Horizontal Active End MSB (R) [POSHDEEND]

PosHDEEndH

Reserved

<2:0> Bits<10:8> of detected horizontal active end position

<7:3> Reserved

56

57

Vertical Active Start LSB (R) [POSVDESTART]

PosVDEStartL

<7:0> Bits<7:0> of detected vertical active start line (Unit: 1 line)

Vertical Active Start MSB (R) [POSVDESTART]

PosVDEStartH

Reserved

<2:0> Bits<10:8> of detected vertical active start line

<7:3> Reserved

58

Vertical Active End LSB (R) [POSVDEEND]

PosVDEEndL

<7:0> Bits <7:0> of detected vertical active end line (Unit: 1 line)

Version B1.0

43

AL260

59

Vertical Active End MSB (R) [POSVDEEND]

PosVDEEndH

Reserved

<2:0> Bits<10:8> of detected vertical active end line

<7:3> Reserved

V: Mode Detection:

62

63

Horizontal Capture Total Counter LSB (R) [CAPHTOTALCNT]

CapHtotalCntL <7:0> Bits<7:0> of horizontal total count value

Horizontal Capture Total Counter MSB (R) [CAPHTOTALCNT]

CapHtotalCntH

Reserved

<2:0> Bits<10:8> of horizontal total count value

<7:3> Reserved

64

65

Vertical Capture Total Counter LSB (R) [CAPVTOTALCNT]

CapVtotalCntL <7:0> Bits<7:0> of vertical total count value

Vertical Capture Total Counter MSB (R) [CAPVTOTALCNT]

CapVtotalCntH

Reserved

<2:0> Bits<10:8> of vertical total count value

<7:3> Reserved

73

Tune Input Clock Phase (R/W) [TUNEINCLK]

TuneInclk

<2:0> Phase delay number(8 steps)

<4:3> Phase delay types

00

01

10

11

Inclk

Inclk + delay phase

Inversed Inclk

Inversed Inclk + delay phase

Reserved

<7:5> Reserved

Version B1.0

44

AL260

¾

Memory Control Group Registers (Accessible when BAS#0E = 02h)

I.DRAM control

INDEX

(HEX)

Register Description

Register Name BITS

Function Description

20

DRAM Access control (R/W) [DRAMACCESSCTRL]

InputEnable

Reserved

<0>

<1>

<2>

<3>

<4>

<5>

<6>

<7>

Enable input data to DRAM

Reserved

PowerUp

Enable power up

OutputEnable

Reserved

Enable output data from DRAM

Reserved

RefreshEnable

PowerDown

SetMode

Enable DRAM refresh

Enable power down

Enable DRAM setmode cycle

21

DRAM Write (R/W) [DRAMWRITE]

PMCLKSel

<0>

Select DRAM read clock signal path

0

1

Internal loop

External loop from pad MCLK to PMCLK

WriteMask1

WriteMask2

SoftRest

<1>

<2>

<3>

Write mask of DRAM byte 0, 1

Write mask of DRAM byte 2

Software Reset

DataDelay

<5:4> DRAM data delay

DataRdyDelay

<7:6> DRAM data ready delay

22

23

Output & FIFO Control (R/W) [OUTFIFOCTRL]

OutputLevel

Reserved

<3:0> Output FIFO level control

<7:4> Reserved

Input FIFO Control (R/W) [INFIFOCTRL]

InputLevel

Reserved

<3:0> Input FIFO level control

<7:4> Reserved

Version B1.0

45

AL260

Note: These are DRAM FIFO water mark, when FIFO reach this urgent level, the corresponding video source

needs to be serviced(R/W or to/from DRAM)

24~27: Reserved

28

29

DRAM Minimum Refresh (R/W) [DRAMMINREFRESH]

MinRefresh <7:0> Minimum refresh requirement within the period of a output VSYNC,

usually 1/60 sec

DRAM Control 0 (R/W) [DRAMCTRL]

TRAS

<1:0> DRAM RAS control signal

00

01

11

5 memory clocks

6 memory clocks

7 memory clocks

8 memory clocks

TRC

<4:2> DRAM RC control signal

000

001

011

100

101

111

7 memory clocks

8 memory clocks

9 memory clocks

10 memory clocks

11 memory clocks

12 memory clocks

13 memory clocks

14 memory clocks

TRCD

TRP

<5>

<6>

<7>

DRAM RCD control signals

0

1

No delay

Delay 1 memory clock

DRAM RP control signal

0

1

No delay

Delay 1 memory clock

TRPD

DRAM RPD control signal

0

1

No delay

Delay 1 memory clock

Version B1.0

46

AL260

2A

DRAM Control 1 (R/W) [DRAMCTRL]

TWR

<0>

<1>

<2>

DRAM WR control signal

0

1

No delay

Delay 1 memory clock

TCL

DRAM CL control signal

0

1

No delay

Delay 1 memory clock

TRW

DRAM RW control signal

0

1

No delay

Delay 1 memory clock

MemConfig

<4:3> SDRAM Size

00

01

10

11

16Mb

64Mb

Reserved

BankConfig

<5>

Bank selector

0

A22, 0-4M = bank 0, 4-8M = bank 1

A21, 4-6M = bank 0, 6-8M = bank 1

1

Reserved

TXSR

<6>

<7>

Tie to 1

DRAM XSR control signal

Note: MEM#29&2A is SDRAM timing parameters. Default value: MEM#29=”ef”, MEM#2A=”4f”

2B

2C

2D

DRAM Read Address 0 (R/W) [DRAMRADDR]

MemReadAddr0

<7:0> Bits<7:0> of DRAM read address. (unit: 2 pixels)

DRAM Read Address 1 (R/W) [DRAMRADDR]

MemReadAddr1

<7:0> Bits<15:8> of DRAM read address

DRAM Read Address 2 (R/W) [DRAMRADDR]

MemReadAddr2

Reserved

<4:0> Bits<20:16> of DRAM read address

<7:5> Reserved

30

XY Mirror Input (R/W) [XYMIRRORIN]

Version B1.0

47

AL260

InputFlipX

InputFlipY

Reserved

<0>

<1>

Enable X mirror capture (horizontally captured in the reversed

direction)

Enable Y mirror capture (vertically captured in the reversed

direction, i.e. up side down capture)

<7:2> Reserved

31

32

XY Mirror Output (R/W) [XYMIRROROUT]

OutputFlipX

OutputFlipY

Reserved

<0>

Enable X mirror display (horizontally display in the reversed

direction)

<1>

Enable Y mirror display (vertically displayed in the reversed

direction, i.e. up side down display)

<7:2> Reserved

Skip Mode (R/W) [SKIPMODE]

InputSkip

<1:0> DRAM input address pointer incremental unit

00

2 fields/1 frame stockpile, even1, odd1, even1, odd1 ….,

Note: Stride >= size

01

10

Reserved

4 fields/2frames stockpile

F1(1),F2(1),F3(1),F4(1),F1(2),F2(2),F3(2)…

Note: Stride >= size * 4

11

Reserved

<2>

<3>

<4>

<5>

Reserved

TwoField

Two field mode enable

Reserved

MemControlEn

0

1

Disable sdram controller

Enable sdram controller

DbufferEn

Reserved

<6>

<7>

Dobule buffering enable

Reserved

II. DRAM input window control

33

DRAM Input Start (R/W) [DRAMINSTART]

DRAMINStart

<7:0> Input DRAM address start (Unit: 8192 pixels)

Version B1.0

48

AL260

34

35

DRAM Input Horizontal Stride (R/W) [DRAMINHSTRIDE]

DRAMINHStride

<7:0> Input DRAM horizontal stride (Unit: 4 pixels)

DRAM Input Horizontal Size (R/W) [DRAMINHSIZE]

DRAMINHSize

<7:0> Input DRAM horizontal size (Unit: 4 pixels)

Note: Set stride value at 64/128/256 boundary, will better ease DRAM timing.

DRAMINHSIZE = CAPHDESTSIZE(CAP#25&24) / 4

III. DRAM window copy control

39

3A

3B

Window Copy Source Start LSB (R/W) [WCSRCSTART]

GSInputStart1

<7:0> Bits<7:0> of GS input DRAM address start. (Unit: 8192 pixels)

Window Copy Source Start (R/W) [WCSRCSTART]

GSInputStart2

<7:0> Bits<15:8> of GS input DRAM address start

Window Copy Source Start MSB (R/W) [WCSRCSTART]

GSInputStart3

Reserved

<3:0> Bits<18:16> of GS input DRAM address start

<7:4> Reserved

3C

3D

3E

3F

Window Copy Source Stride (R/W) [GSDRAMINPUTSTRIDE]

GSIStride <7:0> GS input DRAM stride. (8 pixels)

Window Copy Size (R/W) [GSDRAMINPUTSIZE]

GSHSize

<7:0> GS input DRAM size. (Unit: 8 pixels)

Direct Write Stride (R/W) [WCSTRIDE]

WCStride

<7:0> DRAM window copy stride. (Unit: 8 pixels)

Window Copy Destination Start LSB (R/W) [WCDESTSTART]

WCSrcStart1

<7:0> Bits<7:0> of DRAM window copy source address start. (Unit: 8

pixels)

Version B1.0

49

AL260

40

41

Window Copy Destination Start (R/W) [WCDESTSTART]

WCDestStart2

<7:0> Bits<15:8> of DRAM window copy source address start

Window Copy Destination Start MSB (R/W) [WCDESTSTART]

WCDestStart3

Reserved

<3:0> Bits<20:16> of DRAM window copy source address start

<7:4> Reserved

Note: After writing to MEM#41, the Window Copy operation will be carried out.

42

Direct Read/Write Address LSB (R/W) [DASTART]

DAddrStart1

<7:0> Bits<7:0> of DRAM window copy source address start. (Unit: 8

pixels)

43

44

Direct Read/Write Address (R/W) [DASTART]

DAddrStart2

<7:0> Bits<15:8> of DRAM window copy source address start

Direct Read/Write Address MSB (R/W) [DASTART]

DAddrStart3

Reserved

<3:0> Bits<20:16> of DRAM window copy source address start

<7:4> Reserved

45

46

Window Copy Size (R/W) [WCSIZE]

WCSize <7:0> DRAM Directly Write size. (Unit: 8 pixels) or DRAM window copy

total lines [7:0] for Window Copy.

Window Copy Line Total (R/W) [WCLINETOTAL]

WCLineTotal <7:0> DRAM window copy total lines[2:0]. (1 line)

IV. DRAM output window control

47

48

DRAM Output Start (R/W) [DRAMOUTSTART]

DRAMOutStart <7:0> Output DRAM address start. (Unit: 8192 pixels)

DRAM Output Horizontal Stride (R/W) [DRAMOUTHSTRIDE]

Version B1.0

50

AL260

DRAMOutHStride

<7:0> Output DRAM horizontal stride. (Unit: 4/8/12 pixels)

49

DRAM Output Horizontal Size (R/W) [DRAMOUTHSIZE]

DRAMOutHSize <7:0> Output DRAM horizontal size. (Unit: 4/8/12 pixels)

DRAMOHSIZE = DISHSRCSIZE(DIS#41&40) / 4

4D

4E

4F

VBI Start Address LSB (R/W) [VBISTART]

VBIAddrStart1

<7:0> Bit<7:0> of VBI starting address.

VBI Start Address (R/W) [VBISTART]

VBIAddrStart2

<7:0> Bit<15:8> of VBI starting address.

VBI Start Address MSB (R/W) [VBISTART]

VBIAddrStart3

Reserved

<3:0> Bit<19:16> of VBI starting address.

<7:4> Reserved

50

51

Front Motion Detect Control (R/W) [FRONTM]

FrontMYth

EnFrontM

<6:0> Y threshold Value for Front Motion

<7> Enable Front Motion Detection

Tune Memory Write Clock Phase (R/W) [TUNEMCLK]

TuneMclk

<2:0> Phase delay number(8 steps)

<4:3> Phase delay types

00

01

10

11

Mclk

Mclk + delay phase

Inversed Mclk

Inversed Mclk + delay phase

Reserved

<7:5> Reserved

52

Tune Memory Read Clock Phase (R/W) [TUNEPMCLK]

TunePMclk

<2:0> Phase delay number(8 steps)

<4:3> Phase delay types

00

PMclk

Version B1.0

51

AL260

01

10

11

PMclk + delay phase

Inversed PMclk

Inversed PMclk + delay phase

Reserved

<7:5> Reserved

V. DRAM data port

60

Read Status (R) [READSTATUS]

Status

<0>

Data Ready

Reserved

<7:1> Reserved

61

Byte 0 (R)(W) [BYTE0]

RByte0(R)

<7:0> Bits<7:0> of DRAM for read-out

WByte0(W)

<7:0> Bits<7:0> of Pixel 0 for 16-bit mode Write, or

Dummy field for 24-bit mode Write

62

63

64

65

Byte 1 (R)(W) [BYTE1]

RByte1(R)

<7:0> Bits<15:8> of DRAM read-out

WByte1(W)

<7:0> Bits<15:8> of Pixel 0 for 16-bit mode Write, or

Blue field for 24-bit mode Write

Byte 2 (R)(W) [BYTE2]

RByte2(R)

<7:0> Bits<23:16> of DRAM read-out

WByte2(W)

<7:0> Bits<7:0> of Pixel 1 for 16-bit mode Write, or

Green field for 24-bit mode Write

Byte 3 (R)(W) [BYTE3]

RByte3(R)

<7:0> Bits<31:24> of DRAM read-out

WByte3(W)

<7:0> <15:8> of Pixel 1 for 16-bit mode Write, or

Red field for 24-bit mode Write

Byte 4 (R) [BYTE4]

RByte4

<7:0> Bits<39:32> of DRAM read-out

Version B1.0

52

AL260

66

Byte5 (R) [BYTE5]

RByte4

<7:0> Bits<47:40> of DRAM read-out

DRAM data read ports are defined in MEM#61~66. MemReadAddr is defined in MEM#42~44. After reading

MEM#60, the read cycle will be strobe if bit-0 is 0. MEM#60 should be read until bit 0 is 1. Then, read

MEM#61~66 for the data read from SDRAM.

Version B1.0

53

AL260

¾

Display Control Group Registers (Accessible when BAS#0E = 03h)

I. Display Timing

INDEX

(HEX)

Register Description

Register Name BITS

Function Description

20

21

Horizontal Display Total LSB (R/W) [DISHTOTAL]

DisHTotalL

<7:0> Bits<7:0> of display horizontal total (Unit: 1 pixel)

Horizontal Display Total MSB (R/W) [DISHTOTAL]

DisHTotalH

Reserved

<3:0> Bits<11:8> of display horizontal total

<7:4> Reserved

22

23

Horizontal Display Sync LSB (R/W) [DISHSEND]

DisHSEndL

<7:0> Bits<7:0> of display horizontal sync end (Unit: 1 pixel)

Horizontal Display Sync MSB (R/W) [DISHSEND]

DisHSEndH

Reserved

<3:0> Bits<11:8> of display horizontal sync end

<7:4> Reserved

Note: Horizontal sync start at position 1.

24

25

Horizontal Display Start LSB (R/W) [DISHDESTART]

DisHDEStartL <7:0> Bits<7:0> of horizontal display start (Unit: 1 pixel)

Horizontal Display Start MSB (R/W) [DISHDESTART]

DisHDEStartH

Reserved

<3:0> Bits<11:8> of horizontal display start

<7:4> Reserved

26

27

Horizontal Display End LSB (R/W) [DISHDEEND]

DisHDEEndL

<7:0> Bits<7:0> of horizontal display end (Unit: 1 pixel)

Horizontal Display End MSB (R/W) [DISHDEEND]

DisHDEEndH

<3:0> Bits<11:8> of horizontal display end

Version B1.0

54

AL260

Reserved

<7:4> Reserved

28

29

Display Vertical Total LSB (R/W) [DISVTOTAL]

DisVTotalL

<7:0> Bits<7:0> of display vertical total (Unit: 1 pixel)

Display Vertical Total MSB (R/W) [DISVTOTAL]

DisVTotalH

Reserved

<3:0> Bits <11:8> of display vertical total

<7:4> Reserved

2A

2B

Display Vertical Sync LSB (R/W) [DISVSEND]

DisVSEndL

<7:0> Bits<7:0> of display vertical sync end (Unit: 1 pixel)

Display Vertical Sync MSB (R/W) [DISVSEND]

DisVSEndH

Reserved

<3:0> Bits<11:8> of display vertical sync end

<7:4> Reserved

Note: Vertical sync start at line 1.

2C

2D

Vertical Display Start LSB (R/W) [DISVDESTART]

DisVDEStartL

<7:0> Bits<7:0> of vertical display start (Unit: 1 pixel)

Vertical Display Start MSB (R/W) [DISVDESTART]

DisVDEStartH

Reserved

<3:0> Bits<11:8> of vertical display start

<7:4> Reserved

2E

2F

Vertical Display End LSB (R/W) [DISVDEEND]

DisVDEEndL

<7:0> Bits<7:0> of vertical display end(Unit: 1 pixel)

Vertical Display End MSB (R/W) [DISVDEEND]

DisVDEEndH

Reserved

<3:0> Bits<11:8> of vertical display end

<7:4> Reserved

II. Window Output Timing

Version B1.0

55

AL260

30

31

Horizontal Display Active Start LSB (R/W) [DISHDESTART]

DisHDEStartL

<7:0> Bits<7:0> of horizontal display active start (Unit: 1 pixel)

Horizontal Display Active Start MSB (R/W) [DISHDESTART]

DisHDEStartH

Reserved

<3:0> Bits<11:8> of horizontal display active start

<7:4> Reserved

32

33

Horizontal Display Active End LSB (R/W) [DISHDEEND]

DisHDEEndL

<7:0> Bits<7:0> of horizontal display active end (Unit: 1 pixel)

Horizontal Display Active End MSB (R/W) [DISHDEEND]

DisHDEEndH

Reserved

<3:0> Bits<11:8> of horizontal display active end

<7:4> Reserved

34

35

Vertical Display Active Start LSB (R/W) [DISVDESTART]

DisVDEStartL

<7:0> Bits<7:0> of vertical display active start (Unit: 1 pixel)

Vertical Display Active Start MSB (R/W) [DISVDESTART]

DisVDEStartH

Reserved

<3:0> Bits<11:8> of vertical display active start

<7:4> Reserved

36

37

Vertical Display Active End LSB (R/W) [DISVDEEND]

DisVDEEndL

<7:0> Bits<7:0> of vertical display active end (Unit: 1 pixel)

Vertical Display Active End MSB (R/W) [DISVDEEND]

DisVDEEndH

Reserved

<3:0> Bits<11:8> of vertical display active end

<7:4> Reserved

III. Zoom In Control Registers

40

41

Horizontal Display Source Size LSB (R/W) [DISHSRCSIZE]

DisHSrcSizeL

<7:0> Bits<7:0> of horizontal display source size (Unit: 1 pixel)

Horizontal Display Source Size MSB (R/W) [DISHSRCSIZE]

Version B1.0

56

AL260

DisHSrcSizeH

Reserved

<3:0> Bits<11:8> of horizontal display source size

<7:4> Reserved

42

43

Horizontal Display Destination Size LSB (R/W) [DISHDESTSIZE]

DisHDestSizeL

<7:0> Bits<7:0> of horizontal display destination size (Unit: 1 pixel).

Horizontal Display Destination Size MSB (R/W) [DISHDESTSIZE]

DisHDestSizeH

Reserved

<3:0> Bits<11:8> of horizontal display destination size

<7:4> Reserved

44

45

Vertical Display Source Size LSB (R/W) [DISVSRCSIZE]

DisVSrcSizeL

<7:0> Bits<7:0> of vertical display source size (Unit:1 pixel)

Vertical Display Source Size MSB (R/W) [DISVSRCSIZE]

DisVSrcSizeH

Reserved

<3:0> Bits<11:8> of vertical display source size

<7:4> Reserved

46

47

Vertical Display Destination Size LSB (R/W) [DISVDESTSIZE]

DisVDestSizeL

<7:0> Bits<7:0> of vertical display source size (Unit:1 pixel)

Vertical Display Destination Size MSB (R/W) [DISVDESTSIZE]

DisVDestSizeH

Reserved

<3:0> Bits<11:8> of vertical display destination size

<7:4> Reserved

Note : DISHDESTSIZE >= DISHSRCSIZE,

DISVDESTSIZE >= DISVSRCSIZE

48

Zoom In Filter Control (R/W) [ZOOMFCTRL]

VZoomEn

HZoomEn

Reserved

<0>

<1>

Enable vertical scale-up filtering

Enable horizontal scale-up filtering

<7:2> Reserved

4A

Horizontal Scale Up Ratio LSB (R/W) [HUPRATIO]

HUpRatioL

<7:0> Bits<7:0> of horizontal scale up ratio

Version B1.0

57

AL260

4B

4A

4B

Horizontal Scale Up Ratio MSB (R/W) [HUPRATIO]

HUpRatioH

<7:0> Bits<15:8> of horizontal scale up ratio

Delta Horizontal Scale Up Ratio LSB (R/W) [DELTAHUPRATIO]

DeltaHUpRatioL

<7:0> Bits<7:0> delta of horizontal scale up ratio for Keystone

Delta Horizontal Scale Up Ratio MSB (R/W) [DELTAHUPRATIO]

DeltaHUpRatioH

HDEStartInc

<3:0> Bits<11:8> delta of horizontal scale up ratio for Keystone

<5:4> Delta of starting point of horizontal DE for Keystone

00

01

10

11

Added by 0

Added by 1

Added by 0

Substrate by 1

HDEEndInc

<7:6> Delta of Ending point of horizontal DE for Keystone

00

01

10

11

Added by 0

Added by 1

Added by 0

Substrate by 1

Note: This definition is valid when DIS#CB<4>=’1’ and used in Keystone

4C

4D

Vertical Scale Up Ratio LSB (R/W) [VUPRATIO]

VUpRatioL

<7:0> Bits<7:0> of vertical scale up ratio

Vertical Scale Up Ratio MSB (R/W) [VUPRATIO]

VUpRatioH

<7:0> Bits<15:8> of vertical scale up ratio

Note: HUPRATIO = DISHSRCSIZE / DISHDESTSIZE * 8192

Note: VUPRATIO = DISVSRCSIZE / DISVDESTSIZE * 8192

4E

4F

Horizontal Scale Up Initial Phase LSB (R/W) [HPHASE]

HUpPhaseL

<7:0> Bit<7:0> of horizontal scale up initial phase

Horizontal Scale Up Initial Phase MSB (R/W) [HPHASE]

HUpPhaseH

<7:0> Bit<15:8> of horizontal scale up initial phase

Version B1.0

58

AL260

50

51

54

Vertical Scale Up Initial Phase LSB (R/W) [VPHASE]

VUpPhaseL

<7:0> Bit<7:0> of vertical scale up initial phase

Vertical Scale Up Initial Phase MSB (R/W) [VPHASE]

VUpPhaseH

<7:0> Bit<15:8> of vertical scale up initial phase

Output Mode (R/W) [OUTPUTMODE]

OutputMode

<1:0> Output enable

00

01

10

11

Enable

Reserved

Disable, Zero output

Reserved

<4:2> Reserved

DitherMode

<5>

Enable dither output

0

1

No dither

8 bits to 6 bits

Reserved

LutEn

<6>

<7>

Reserved

Enable built-in LUT look-up table

55

5C

5D

5E

5F

LUT Write Index (R/W) [LUTWINDEX]

LUTWIndex

<7:0> LUT access index

LUT Red Color LSB (R/W) [LUTRED]

LUTRed

<7:0> LUT red color port

LUT Green Color LSB (R/W) [LUTGREEN]

LUTGreen

<7:0> LUT green color port

LUT Blue Color LSB (R/W) [LUTBLUE]

LUTBlue

<7:0> LUT blue color port

LUT Read/Write Trigger (R/W) [LUTWEN]

Reserved

<5:0> Reserved

Version B1.0

59

AL260

LUTWEn

<7:6> Write color field enable

00

01

10

11

Red, Green and Blue written into LUT

Only Red is written into LUT

Only Green written into LUT

Only Blue written into LUT

56

Pattern Generator and GPO (R/W) [PATTERNGEN]

PatternMode

<1:0> 00

Fram line

Color bar

Gray level

Line moier

01

10

11

PatternEn

GPO

<4>

Enable pattern generation

<7:5> General purpose output port

Note: Set register GPO(DIS#56<7:5>) value will effect pin GPO2~0 output status in phase

IV. OSD Color Registers

58

59

OSD Write Address LSB (R/W) [OSDRAMWADDR]

OSDRamWAddrL <7:0> Bit<7:0> of OSD ram write address

OSD Write Address MSB (R/W) [OSDRAMWADDR]

OSDRamWAddrH <2:0> Bit<10:8> of OSD ram write address

Reserved

<7:3> Reserved

5A

60

61

OSD Write Data Port (W) [OSDRAMWDATA]

OSDWData

<7:0> OSD ram write data port

Color 0 Red (R/W) [COLOR0RED]

Color0Red

<7:0> Color 0 Red Component

Color 0 Green (R/W) [COLOR0GREEN]

Color0Green

<7:0> Color 0 Green Component

Version B1.0

60

AL260

62

63

64

65

66

67

68

69

6A

6B

6C

6D

Color 0 Blue (R/W) [COLOR0RED]

Color0Blue

<7:0> Color 0 Blue Component

Color 1 Red (R/W) [COLOR1RED]

Color1Red

<7:0> Color 1 Red Component

Color 1 Green (R/W) [COLOR1GREEN]

Color1Green

<7:0> Color 1 Green Component

Color 1 Blue (R/W) [COLOR1BLUE]

Color1Blue

<7:0> Color 1 Blue Component

Color 2 Red (R/W) [COLOR2RED]

Color2Red

<7:0> Color 2 Red Component

Color 2 Green (R/W) [COLOR2GREEN]

Color2Green

<7:0> Color 2 Green Component

Color 2 Blue (R/W) [COLOR2BLUE]

Color2Blue

<7:0> Color 2 Blue Component

Color 3 Red (R/W) [COLOR3RED]

Color3Red

<7:0> Color 3 Red Component

Color 3 Green (R/W) [COLOR3GREEN]

Color3Green

<7:0> Color 3 Green Component

Color 3 Blue (R/W) [COLOR3BLUE]

Color3Blue

<7:0> Color 3 Blue Component

Color 4 Red (R/W) [COLOR4RED]

Color4Red

<7:0> Color 4 Red Component

Color 4 Green (R/W) [COLOR0GREEN]

Version B1.0

61

AL260

Color4Green

<7:0> Color 4 Green Component

6E

6F

70

71

72

73

74

75

76

77

Color 4 Blue (R/W) [COLOR4BLUE]

Color4Blue

<7:0> Color 4 Blue Component

Color 5 Red (R/W) [COLOR5RED]

Color5Red

<7:0> Color 5 Red Component

Color 5 Green (R/W) [COLOR5GREEN]

Color5Green

<7:0> Color 5 Green Component

Color 5 Blue (R/W) [COLOR5BLUE]

Color5Blue

<7:0> Color 5 Blue Component

Color 6 Red (R/W) [COLOR6RED]

Color6Red

<7:0> Color 6 Red Component

Color 6 Green (R/W) [COLOR6GREEN]

Color6Green

<7:0> Color 6 Green Component

Color 6 Blue (R/W) [COLOR6BLUE]

Color6Blue

<7:0> Color 6 Blue Component

Color 7Red (R/W) [COLOR7RED]

Color7Red

<7:0> Color 7 Red Component

Color 7 Green (R/W) [COLOR7GREEN]

Color7Green

<7:0> Color 7 Green Component

Color 7 Blue (R/W) [COLOR7BLUE]

Color7Blue

<7:0> Color 7 Blue Component

V. OSD Control Register

Version B1.0

62

AL260

78

OSD Color Select (R/W) [OSDCOLORSEL]

Osd1ColorSel

<1:0> OSD1 color selection, 8 colors only apply when Font2byte= ’1’

and PixDepth1= ’1’

00

01

10

11

select OSD1 colors from index 3..0

select OSD1 colors from index 7..4

select OSD1 colors from index 7..0

Reserved

Osd2ColorSel

<3:2> OSD2 color selection, 8 colors only apply when Font2byte= ’1’

and PixDepth2= ’1’

00

01

10

11

select OSD2 colors from index 3..0

select OSD2 colors from index 7..4

select OSD2 colors from index 7..0

Reserved

Font2byte

Reserved

<4>

Two-byte font charter code mode, effective only when RomMode

= '1'

<7:5> Reserved

79

Blink Time (R/W) [BLINKTIME]

BlinkTimer

BlinkType

<6:0> Blinking timing value

<7>

0

1

Reverse color

Bypass

Note: OSD Blinking frequency = Vsync frequency / BlinkTimer

80

OSD Modes (R/W) [OSDMODE]

RomMode

<0>

Enable ROM mode

0

Internal RAM mode

External ROM mode

1

Reserved

Number

<1>

Tie to 0

<7:2> Adjust rom address width to access external rom data

Note: The method of select the Number value show on OSD application note

81

Logic Operation (R/W) [FOREOP]

Version B1.0

63

AL260

Color0Op

Color1Op

Color2Op

Color3Op

<1:0> Logic operation between color 0 and video

00

01

10

11

NOP, show only OSD

OR, video or color 0

AND, video and color 0

XOR, video xor color 0

<3:2> Logic operation between color 1 and video

00

01

10

11

NOP, show only OSD

OR, video or color 1

AND, video and color 1

XOR, video xor color 1

<5:4> Logic operation between color 2 and video

00

01

10

11

NOP, show only OSD

OR, video or color 2

AND, video and color 2

XOR, video xor color 2

<7:6> Logic operation between color 3 and video

00

01

10

11

NOP, show only OSD

OR, video or color 3

AND, video and color 3

XOR, video xor color 3

83

Logic Operation (R/W) [FOREOP]

Color4Op

Color5Op

Color6Op

<1:0> Logic operation between color 4 and video

00

01

10

11

NOP, show only OSD

OR, video or color 4

AND, video and color 4

XOR, video xor color 4

<3:2> Logic operation between color 5 and video

00

01

10

11

NOP, show only OSD

OR, video or color 5

AND, video and color 5

XOR, video xor color 5

<5:4> Logic operation between color 6 and video

00 NOP, show only OSD

Version B1.0

64

AL260

01

10

11

OR, video or color 6

AND, video and color 6

XOR, video xor color 6

Color7Op

<7:6> Logic operation between color 7 and video

00

01

10

11

NOP, show only OSD

OR, video or color 7

AND, video and color 7

XOR, video xor color 7

Note: Color 0 ~ 7 are defined in DIS#60~77.

82

Fading Alpha Value (R/W) [FADEALPHA]

FadeAlpha

Reserved

<5:0> The alpha factor for fading effect ranging

<7:6> Reserved

Note: FADEALPHA range from 00h to 20h, there is 33-level of fade-in/fade-out effect.

Output = Image * FADEALPHA/32 + OSD * (1 – (FADEALPHA /32))

Show only OSD: FADEALPHA = “000000“ --- minimum alpha value(00h)

Show only Image: FADEALPHA = “100000“ --- maximum alpha value(20h)

VI. OSD 1 Registers

84

OSD1 Control (R/W) [OSDCONTROL1]

PixDepth1

BlinkEn1

HZoom1

<0>

Number of bits per pixel of OSD1

0

1

One bit per pixel

Two bits per pixel

<1>

OSD1 blinking enable, effective when RomMode = ‘1’

0

1

Disable blinking

Enable blinking

<3:2> OSD1 horizontal zoom factor

00

01

10

11

OSD1 pixel H size equals to 1X of video pixel

OSD1 pixel H size equals to 2X of video pixel

OSD1 pixel H size equals to 4X of video pixel

OSD1 pixel H size equals to 8X of video pixel

Version B1.0

65

AL260

VZoom1

<5:4> OSD1 vertical zoom factor

00

01

10

11

OSD1 pixel V size equals to 1X of video pixel

OSD1 pixel V size equals to 2X of video pixel

OSD1 pixel V size equals to 4X of video pixel

OSD1 pixel V size equals to 8X of video pixel

Reserved

OsdEn1

<6>

<7>

Reserved

OSD1 enable

0

1

Disable OSD1

Enable OSD1

85

86

OSD1 ROM Start Address (R/W) [ROMSTARTADDR1]

RomStAddr1H

<7:0> Bits<11:4> of OSD1 ROM start address (Unit: 16 bytes)

OSD1 Font Address Unit (R/W) [FONTADDRUNIT1]

RomStAddr1L

FontAddrUnit1

<3:0> Bits<3:0> OSD1 ROM start address (Unit: 16 bytes)

<7:4> OSD1 font address unit (n), font address is multiple of 2(n+5)

bytes, max. is 216

90

91

92

8B

OSD1 Horizontal Start (R/W) [OSDHSTART1]

OsdHStart1

<7:0> On Screen Display horizontal start position (Unit: 8 video pixels)

OSD1 Vertical Start (R/W) [OSDVSTART1]

OsdVStart1

<7:0> On Screen Display vertical start position (Unit: 4 video lines)

OSD1 RAM Start Address (R/W) [RAMADDRST1]

RamAddrSt1

<7:0> OSD1 RAM start address (Unit: 8 bytes)

OSD1 RAM Horizontal Stride MSB (R/W) [RAMSTRIDE1]

RamStride1H

Reserved

<1:0> Bits <9:8> of OSD1 RAM line stride (Unit: 1 bytes)

<7:2> Reserved

93

OSD1 RAM Horizontal Stride LSB (R/W) [RAMSTRIDE1]

RamStride1L

<7:0> Bits<7:0> of OSD1 RAM line stride(Unit: 1 bytes)

Version B1.0

66

AL260

94

95

OSD1 Bitmap Horizontal Size LSB (R/W) [BMAPHSIZE1]

BmapHSize1L

<7:0> Bits<7:0> of OSD1 horizontal bitmap size (Unit: 1 OSD pixel)

OSD1 Bitmap Horizontal Size MSB (R/W) [BMAPHSIZE1]

BmapHSize1H

Reserved

<1:0> Bits<9:8> of OSD1 bitmap horizontal size

<7:2> Reserved

96

97

OSD1 Bitmap Horizontal Total Pixels LSB (R/W) [BMAPHTOTAL1]

BmapHTotal1L

<7:0> Bits<7:0> of OSD1 bitmap horizontal total (Unit: 1 OSD pixel)

OSD1 Bitmap Horizontal Total Pixels MSB (R/W) [BMAPHTOTAL1]

BmapHTotal1H

Reserved

<1:0> Bits<9:8> of OSD1 bitmap horizontal total

<7:2> Reserved

98

99

OSD1 Bitmap Vertical Size LSB (R/W) [BMAPVSIZE1]

BmapVSize1L

<7:0> Bits<7:0> of OSD1 bitmap vertical size (Unit: 1 OSD line)

OSD1 Bitmap Vertical Size MSB (R/W) [BMAPVSIZE1]

BmapVSize1H

Reserved

<1:0> Bits<9:8> of OSD1 bitmap vertical size

<7:2> Reserved

9A

9B

OSD1 Bitmap Vertical total Lines LSB (R/W) [BMAPVTOTAL1]

BmapVTotal1L

<7:0> Bits<7:0> of OSD1 bitmap vertical total(Unit: 1 OSD line)

OSD1 Bitmap Vertical Total Lines MSB (R/W) [BMAPVTOTAL1]

BmapVTotal1H

Reserved

<1:0> Bits<9:8> of OSD1 bitmap vertical total

<7:2> Reserved

9C

9D

OSD1 Icon Horizontal Total (R/W) [ICONHTOTAL1]

IconHtotal1

<7:0> OSD1 horizontal icon total (Unit: 1 icon)

OSD1 Icon Vertical Total (R/W) [ICONVTOTAL1]

IconVTotal1

<7:0> OSD1 vertical icon total (Unit: 1 icon)

Version B1.0

67

AL260

AE

OSD1 Font Line Size (R/W) [FONTLINESIZE1]

Fontlinesize1 <7:0> memory size of a line of font (Unit: 1 byte)

VII. OSD 2 Registers

88

OSD2 Control (R/W) [OSDCONTROL2]

PixDepth2

BlinkEn2

Hzoom2

<0>

Number of bits per pixel of OSD2

0

1

One bit per pixel

Two bits per pixel

<1>

OSD2 blinking enable, effective when RomMode = ‘1’

0

1

Disable blinking

Enable blinking

<3:2> OSD2 horizontal zoom factor

00

01

10

11

OSD pixel H size equals to 1X of video pixel

OSD pixel H size equals to 2X of video pixel

OSD pixel H size equals to 4X of video pixel

OSD pixel H size equals to 8X of video pixel

Vzoom2

<5:4> OSD2 vertical zoom factor

00

01

10

11

OSD pixel V size equals to 1X of video pixel

OSD pixel V size equals to 2X of video pixel

OSD pixel V size equals to 4X of video pixel

OSD pixel V size equals to 8X of video pixel

Reserved

OsdEn2

<6>

<7>

Reserved

OSD2 enable

0

1

Disable OSD2

Enable OSD2

89

8A

OSD2 ROM Start Address (R/W) [ROMSTARTADDR2]

RomStAddr1H

<7:0> Bits<11:4> of OSD2 ROM start address (Unit: 16 bytes)

OSD2 Font Address Unit (R/W) [FONTADDRUNIT2]

RomStAddr2L

FontAddrUnit2

<3:0> Bits<3:0> OSD2 ROM start address (Unit: 16 bytes)

<7:4> OSD1 font address unit (n), font address is multiple of 2(n+5)

bytes, max. is 216

Version B1.0

68

AL260

A0

A1

A2

8C

OSD2 Horizontal Start (R/W) [OSDHSTART2]

OsdHStart2

<7:0> On Screen Display horizontal start position (Unit: 8 video pixels)

OSD2 Vertical Start (R/W) [OSDVSTART1]

OsdVStart2

<7:0> On Screen Display vertical start position (Unit: 4 video lines)

OSD2 RAM Start Address (R/W) [RAMADDRST2]

RamAddrSt2

<7:0> OSD2 RAM start address (Unit: 8 bytes)

OSD2 RAM Horizontal Stride MSB (R/W) [RAMSTRIDE2]

RamStride2H

Reserved

<1:0> Bits <9:8> of OSD2 RAM line stride (Unit: 1 bytes)

<7:2> Reserved

A3

A4

A5

OSD2 RAM Horizontal Stride LSB (R/W) [RAMSTRIDE2]

RamStride2L

<7:0> Bits<7:0> of OSD2 RAM line stride (Unit: 1 bytes)

OSD2 Bitmap Horizontal Size LSB (R/W) [BMAPHSIZE2]

BmapHSize2L

<7:0> Bits<7:0> of OSD1 horizontal bitmap size (Unit: 1 OSD pixel)

OSD2 Bitmap Horizontal Size MSB (R/W) [BMAPHSIZE2]

BmapHSize2H

Reserved

<1:0> Bits<9:8> of OSD1 bitmap horizontal size

<7:2> Reserved

A6

A7

OSD2 Bitmap Horizontal Total Pixels LSB (R/W) [BMAPHTOTAL2]

BmapHTotal2L

<7:0> Bits<7:0> of OSD2 bitmap horizontal total (Unit: 1 OSD pixel)

OSD2 Bitmap Horizontal Total Pixels MSB (R/W) [BMAPHTOTAL2]

BmapHTotal2H

Reserved

<1:0> Bits<9:8> of OSD2 bitmap horizontal total

<7:2> Reserved

A8

OSD2 Bitmap Vertical Size LSB (R/W) [BMAPVSIZE2]

BmapVSize2L

<7:0> Bits<7:0> of OSD2 bitmap vertical size (Unit: 1 OSD line)

Version B1.0

69

AL260

A9

OSD2 Bitmap Vertical Size MSB (R/W) [BMAPVSIZE2]

BmapVSize2H

Reserved

<1:0> Bits<9:8> of OSD2 bitmap vertical size

<7:2> Reserved

AA

AB

OSD2 Bitmap Vertical total Lines LSB (R/W) [BMAPVTOTAL2]

BmapVTotal2L

<7:0> Bits<7:0> of OSD2 bitmap vertical total(Unit: 1 OSD line)

OSD2 Bitmap Vertical Total Lines MSB (R/W) [BMAPVTOTAL2]

BmapVTotal2H

Reserved

<1:0> Bits<9:8> of OSD2 bitmap vertical total

<7:2> Reserved

AC

AD

AF

OSD2 Icon Horizontal Total (R/W) [ICONHTOTAL2]

IconHtotal2

<7:0> OSD2 horizontal icon total (Unit: 1 icon)

OSD2 Icon Vertical Total (R/W) [ICONVTOTAL2]

IconVTotal2

<7:0> OSD2 vertical icon total (Unit: 1 icon)

OSD2 Font Line Size (R/W) [FONTLINESIZE2]

Fontlinesize2

<7:0> memory size of a line of font (Unit: 1 byte)

VIII. Desktop Color Registers

B3

B4

B5

Desktop Color Component Red (R/W) [DESKR]

DeskColorRed <7:0> Desktop color red

Desktop Color Component Green (R/W) [DESKG]

DeskColorGreen <7:0> Desktop color green

Desktop Color Component Blue (R/W) [DESKB]

DeskColorBlue <7:0> Desktop color blue

IX. Film Detection/Motion Adaptive Registers

C4

Motion Pixels Threshold LSB (R/W) [MOTIONCNTTH]

Version B1.0

70

AL260

MvCntThL

<7:0> Bit<7:0> of motion counter threshold

C5

C6

Motion Pixels Threshold MSB (R/W) [MOTIONCNTTH]

MvCntThH

<7:0> Bit<15:8> of motion counter threshold

Lumina(Y) Threshold (R/W) [LUMATH]

YThL

<6:0> Y threshold for film & motion compensation

<7> Reserved

Reserved

C7

C8

Chroma(C) Threshold (R/W) [CHROMATH]

CThH

<6:0> C threshold for film & motion compensation

<7> Reserved

Reserved

De-interlacing Control Register(R/W) [MCCTRL]

MCEn

<0>

Motion Compensation Enable

0

1

Field Merge De-interlace Mode

Motion Adaptive De-interlace Mode

MvMode

<1>

Motion Estimation Type

0

1

Y/C Comparison

Y Comparison Only

Reserved

TestMv

<2>

<3>

Reserved

Display Motion Part

Reserved

<7:4> Reserved

C9

Film Detection Control Register(R/W) [FILMCTRL]

FilmDetEn

ResetType

FilmReset

<0>

<1>

<2>

Film detection enable

0

1

Disable

Enable

Non-Film Detection Type

0

1

H/W Auto Detection

S/W Reset to Non-Film after Film Detected

Reset Film Detection, depending on bit1

0

1

Disable Reset

Reset when bit 1 is turn on

Version B1.0

71

AL260

Reserved

PdMatch

<3>

Reserved

<7:4> Number of film sequence matched

CE

CF

Motion Pixel Numbers LSB (R) [MVCNT]

MvCountL

<7:0> Bit<7:0> of pixels numbers of difference between 2-field/frame

Motion Pixel Numbers MSB (R) [MVCNT]

MvCountH

<7:0> Bit<15:8> of pixels numbers of difference between 2-field/frame

X. Keystone/Sharpness Registers

CB

Keyston/Sharpness Control Register(R/W) [SHPKEYCTRL]

ShapEn

<0>

Sharpness enable

0

1

Disable

Enable

KeyEn

<4>

Keystone enable

0

1

Disable

Enable

Interlace

EvenField

TriLevel

<5>

<6>

<7>

Interlace output enable

Even field mode

Tri level analog data output enable

C0

C1

Keystone Parameters Address LSB (R/W) [KEYADDR]

KeyAddrL <7:0> Bit<7:0> of keystone FIFO address

Keystone Parameters Address MSB (R/W) [KEYADDR]

KeyAddrH

Reserved

KeyWriteEn

<3:0> Bit<11:8> of keystone FIFO address

<6:4> Reserved

<7>

Keystone fifo write enable

0

1

Disable

Enable

Note: Keystone parameter for each scan line is stored into 1280x32 SRAM inside AL310. KeyAddr is the

address of read/write pointer of this SRAM.

Version B1.0

72

AL260

XI. Tri-Level Sync Registers

D0

D1

D2

Tri Level Sync Parameter (W) [TRISYNCA]

PeriodA <7:0> Tri level sync parameter Period_a

Tri Level Sync Parameter (W) [TRISYNCB]

PeriodB

<7:0> Tri level sync parameter Period_a

Tri Level Sync Parameter (W) [TRISYNCD1]

Delta1

<6:0> Bit<6> is sign bit

ex. 60h means from blank_level , - 32 every unit

<7> Reserved

Reserved

D3

Tri Level Sync Parameter (W) [TRISYNCD2]

Delta2

<6:0> Bit<6> is sign bit

ex. 20h means from sync_level, + 32 every unit

<7> Reserved

Reserved

D4

D7

Tri Level Sync Parameter (W) [TRISYNBLANK]

BlankData <7:0> Data of blanking period

Tri Level Sync Parameter (W) [TRISYNCLEVEL]

SyncLevel <7:0> Sync level value

XIII. Display Parameter Registers

C2

Tune Display Horizontal Sync Phase (R/W) [DISTUNEHS]

DisHsDelay <4:0> Output horizontal sync delay (Unit: 1 oclk)

CC

Tune Display Pixel Clock Phase (R/W) [DISTUNESCLK]

TuneSclk

<2:0> Phase delay number(8 steps)

<4:3> Phase delay types

00

Sclk

Version B1.0

73

AL260

01

10

11

Sclk + delay phase

Inversed Sclk

Inversed Sclk + delay phase

Reserved

<7:5> Reserved

CA

Phase Detection Control Register(R/W) [PHASECTRL]

PhaseEn

<0>

Phase detection Enable

0

1

Disable

Enable

PhaseMode

<2:1> Phase detection precision

00

01

10

11

8-bit comparison

7-bit comparison

6-bit comparison

5-bit comparison

Reserved

<7:3> Tie to “00110“

D7

D8

Display Horizontal Total Counter LSB (R) [DISHTOTALCNT]

HTotalCntL <7:0> Bit<7:0> of display horizontal total count

Display Horizontal Total Counter MSB (R) [DISHTOTALCNT]

HTotalCntH

Reserved

<2:0> Bit<10:8> of display horizontal total count

<7:3> Reserved

D9

DA

Display Vertical Total Counter LSB (R) [DISVTOTALCNT]

VTotalCntL <7:0> Bit<7:0> of display vertical total count

Display Vertical Total Counter MSB (R) [DISVTOTALCNT]

VTotalCntH

Reserved

<2:0> Bit<10:8> of display vertical total count

<7:3> Reserved

DB

DC

Phase Counter LSB (R) [PHASECNT]

PhaseCntL

<7:0> Bit<7:0> of phase count value

Phase Counter MSB (R) [PHASECNT]

Version B1.0

74

AL260

PhaseCntH

Reserved

<4:0> Bit<12:8> of phase count value

<7:5> Reserved

F0

Enable Brightness/Contrast/Saturation (W) [DISADJEN]

PanelAdjEn

Reserved

<0>

Enable brightness/contrast/saturation

<7:1> Reserved

F1

F2

F3

Brightness Value (W) [BRIGHTNESS]

Brightness <7:0> Brightness value, Default: "80"

Contrast Value (W) [CONTRAST]

Contrast <7:0> Contrast value, Default: "40"

Saturation Value (W) [SATURATION]

Saturation <7:0> Saturation value, Default: "40"

Version B1.0

75

AL260

10 Electrical Characteristics

10.1 Absolute Maximum Ratings

(Excessive ratings are harmful to the lifetime. Only for user guidelines, not tested.)

3.3V Rating

Parameter

Unit

V_DD

V_P

Supply Voltage

-0.3 ~ +3.8

-0.3 ~ +(V_DD+0.3)

-20 ~ +20

0 ~ +85

V

Input Pin Voltage

I_O

Output Current

mA

°C

T_AMB

T_stg

T_VSOL

Ambient Op. Temperature

Storage Temperature

-40 ~ +125

220

Vapor Phase Soldering

Temperature (15 Sec.)

10.2 Recommended Operating Conditions

3.3V Rating

Parameter

Unit

Min.

Typical

+3.3

Max.

+3.6

V_DD

V_IH

Supply Voltage

+3.0

V

High Level Input Voltage

Low Level Input Voltage

Ambient Op. Temperature

0.7 V_DD

V_DD

V_IL

0

0.3 V_DD

+70

V

T_AMB

°C

10.3 DC Characteristics

(V_DD= 3.3V, Vss=0V. T_AMB= 0 to 70°C; Some parameters are guaranteed by design only,

not production tested)

3.3V Rating

Parameter

Unit

Min.

Typical

Max.

Version B1.0

76

AL260

3.3V Rating

Parameter

Unit

Min.

Typical

-

Max.

V_DD

V_IH

V_IL

V_OH

V_OL

I_LI

Hi-level Input Voltage

Lo-level Input Voltage

Hi-level Output Voltage

Lo-level Output Voltage

Input Leakage Current

Output Leakage Current

0.7 V_DD

V

0

2.4

-

0.3 V_DD

V_DD

-

V

+0.4

+5

V

-5

µA

I_LO

+5

10.4 AC Characteristics

(V_DD= 3.3V, Vss=0V, T_AMB= 0 to 70°C; Some parameters are guaranteed by design only,

not production tested)

Version B1.0

77

AL260

11 Timing Diagrams

TBD.

Version B1.0

78

AL260

12 Mechanical Drawing- PQFP-208

Version B1.0

79

AL260

CONTACT INFORMATION

Averlogic Technologies Corp.

4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan

Tel: +886 2-27915050

Fax: +886 2-27912132

E-mail: sales@averlogic.com.tw

URL: http://www.averlogic.com.tw

Averlogic Technologies, Inc.

90 Great Oaks Blvd. #204, San Jose, CA 95119, U.S.A.

Tel: 1 408 361-0400

Fax: 1 408 361-0404

E-mail: sales@averlogic.com

URL: http://www.averlogic.com

Version B1.0

80


型号：	AL260
厂家：	ETC
描述：	Video Enhancement Processor 视频增强处理器
文件：	总80页 (文件大小：791K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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