AM27C1024-150PC [ETC]

IC-1MB CMOS PROM ; IC- 1MB的CMOS PROM\n
AM27C1024-150PC
型号: AM27C1024-150PC
厂家: ETC    ETC
描述:

IC-1MB CMOS PROM
IC- 1MB的CMOS PROM\n

内存集成电路 光电二极管 可编程只读存储器 OTP只读存储器
文件: 总12页 (文件大小:56K)
中文:  中文翻译
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FINAL  
Am27C1024  
1 Megabit (65,536 x 16-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
±10% power supply tolerance available  
— 55 ns maximum access time  
Low power consumption  
— 100 µA typical CMOS standby current  
JEDEC-approved pinouts  
— 40-Pin DIP/PDIP  
100% Flashrite programming  
Typical programming time of 8 seconds  
Latch-up protected to 100 mA from –1V toV + 1V  
CC  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
— 44-Pin PLCC  
Single +5 V power supply  
GENERAL DESCRIPTION  
The Am27C1024 is a 1 Mbit ultraviolet erasable program-  
mable read-only memory.It is organized as 64K words by  
16 bits per word, operates from a single +5 V supply, has  
a static standby mode, and features fast single address  
location programming. Products are available in win-  
dowed ceramic DIP packages as well as plastic one time  
programmable (OTP) PDIP and PLCC packages.  
controls, thus eliminating bus contention in a multiple  
bus microprocessor system.  
AMD’s CMOS process technology provides high speed, low  
power, and high noise immunity.Typical power consumption is  
only 125 mW in active mode, and 100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random.The Am27C1024 supports AMD’s  
Flashrite programming algorithm (100 µs pulses) re-  
sulting in a typical programming time of 8 seconds.  
Typically, any byte can be accessed in less than 70 ns,  
allowing operation with high-performance microproces-  
sors without any WAIT states. The Am27C1024 offers  
separate Output Enable (OE) and Chip Enable (CE)  
BLOCK DIAGRAM  
Data Outputs  
DQ0–DQ15  
V
V
CC  
SS  
V
PP  
Output Enable  
Chip Enable  
and  
OE  
Output  
Buffers  
CE  
PGM  
Prog Logic  
Y
Y
Gating  
Decoder  
A0–A15  
Address  
Inputs  
X
1,048,576-Bit  
Cell Matrix  
Decoder  
06780I-1  
Publication# 06780 Rev: I Amendment/+2  
Issue Date: July 1997  
PRODUCT SELECTOR GUIDE  
Family Part No:  
Am27C1024  
-55  
-55  
55  
-255  
Ordering Part No: V = 5.0 V ± 5%  
CC  
V
= 5.0 V ± 10%  
-70  
70  
70  
40  
-90  
90  
90  
40  
-120  
120  
120  
50  
-150  
150  
150  
65  
-200  
200  
200  
75  
CC  
Max Access Time (ns)  
CE (E) Access (ns)  
OE (G) Access (ns)  
250  
250  
75  
55  
40  
CONNECTION DIAGRAMS  
Top View  
DIP  
PLCC  
VPP  
CE (E)  
DQ15  
DQ14  
DQ13  
DQ12  
DQ11  
DQ10  
DQ9  
1
40 VCC  
39 PMG (P)  
38 A16  
37 A15  
36 A14  
35 A13  
34 A12  
33 A11  
32 A10  
31 A9  
30 VSS  
29 A8  
28 A7  
27 A6  
26 A5  
25 A4  
24 A3  
23 A2  
22 A1  
21 A0  
2
3
4
40  
1
44 43 42 41  
6
5
4
3
2
5
A13  
A12  
DQ12  
39  
7
6
DQ11  
38  
8
7
A11  
A10  
A9  
DQ10  
DQ9  
DQ8  
VSS  
37  
36  
35  
34  
9
8
10  
11  
12  
9
DQ8  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VSS  
VSS  
NC  
A8  
A7  
A6  
A5  
NC  
DQ7  
DQ6  
DQ5  
DQ4  
33  
32  
31  
30  
29  
13  
14  
15  
16  
17  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
28  
18 19 20 21 22 23 24 25 26 27  
DQ2  
DQ1  
DQ0  
OE (G)  
06780I-2  
06780I-3  
Note:  
1. JEDEC nomenclature is in parenthesis.  
PIN DESIGNATIONS  
LOGIC SYMBOL  
A0–A15  
= Address Inputs  
CE (E)  
= Chip Enable  
16  
DQ0–DQ15 = Data Inputs/Outputs  
16  
A0–A15  
OE (G)  
= Output Enable Input  
= Program Enable Input  
DQ0–DQ15  
PGM (P)  
CE (E)  
V
V
V
= V Supply Voltage  
CC  
PP  
SS  
CC  
PMG (P)  
= Program Voltage Input  
= Ground  
OE (G)/V  
PP  
06780I-4  
NC  
DU  
= No Internal Connection  
= No External Connection (Do Not Use)  
2
Am27C1024  
ORDERING INFORMATION  
UV EPROM Products  
AMD standard products are available in several packages and operating ranges.The order number (Valid Combination) is formed  
by a combination of:  
5
AM27C1024  
-55  
D
C
B
OPTIONAL PROCESSING  
Blank = Standard Processing  
B
= Burn-In  
VOLTAGE TOLERANCE  
= V ± 5%, 55 ns only  
5
CC  
See Product Selector Guide and  
Valid Combinations  
TEMPERATURE RANGE  
C
I
E
= Commercial (0°C to +70°C)  
= Industrial (–40°C to +85°C)  
= Extended (–55°C to +125°C)  
PACKAGE TYPE  
= 40-Pin Ceramic DIP (CDV040)  
D
SPEED OPTION  
See Product Selector Guide and  
Valid Combinations  
DEVICE NUMBER/DESCRIPTION  
Am27C1024  
1 Megabit (65,536 x 16-Bit) CMOS UV EPROM  
Valid Combinations  
Valid Combinations  
AM27C1024-55  
Valid Combinations list configurations planned to be sup-  
ported in volume for this device. Consult the local AMD sales  
office to confirm availability of specific valid combinations and  
to check on newly released combinations.  
DC5, DC5B, DI5, DI5B  
V
= 5.0 V ± 5%  
CC  
AM27C1024-55  
= 5.0 V ± 10%  
V
CC  
DC, DCB, DI, DIB  
AM27C1024-70  
AM27C1024-90  
AM27C1024-120  
AM27C1024-150  
AM27C1024-200  
AM27C1024-255  
DC, DCB, DE, DEB, DI, DIB  
DC, DCB, DI, DIB  
V
= 5.0 V ± 5%  
CC  
Am27C1024  
3
ORDERING INFORMATION  
OTP EPROM Products  
AMD standard products are available in several packages and operating ranges.The order number (Valid Combination) is formed  
by a combination of:  
5
AM27C1024  
-55  
J
C
OPTIONAL PROCESSING  
Blank = Standard Processing  
VOLTAGE TOLERANCE  
5
= V ± 5%, -55 ns only  
CC  
See Product Selector Guide and  
Valid Combinations  
TEMPERATURE RANGE  
C
I
= Commercial (0°C to +70°C)  
= Industrial (–40°C to +85°C)  
PACKAGE TYPE  
P
J
= 40-Pin Plastic DIP (PD 040)  
= 44-Pin Square Plastic Leaded Chip  
Carrier (PL 044)  
SPEED OPTION  
See Product Selector Guide and  
Valid Combinations  
DEVICE NUMBER/DESCRIPTION  
Am27C1024  
2 Megabit (131,072 x 16-Bit) CMOS OTP EPROM  
Valid Combinations  
Valid Combinations  
AM27C1024-55  
Valid Combinations list configurations planned to be sup-  
ported in volume for this device. Consult the local AMD sales  
office to confirm availability of specific valid combinations and  
to check on newly released combinations.  
PC5, PI5, JC5, JI5  
V
= 5.0 V ± 5%  
CC  
AM27C1024-55  
= 5.0 V ± 10%  
V
CC  
AM27C1024-70  
AM27C1024-90  
AM27C1024-120  
AM27C1024-150  
AM27C1024-200  
AM27C1024-255  
PC, PI, JC, JI  
V
= 5.0 V ± 5%  
CC  
4
Am27C1024  
Am27C1024 CE input with V = 12.75 V ± 0.25 V, and  
FUNCTIONAL DESCRIPTION  
Erasing the Am27C1024  
PP  
PGM Low will program that Am27C1024. A high-level  
CE input inhibits the other Am27C1024 devices from  
being programmed.  
In order to clear all locations of their programmed con-  
tents, it is necessary to expose the Am27C1024 to an  
ultraviolet light source. A dosage of 15 W seconds/cm  
Program Verify  
2
is required to completely erase an Am27C1024. This  
dosage can be obtained by exposure to an ultraviolet  
lamp—wavelength of 2537 (Å)—with intensity of  
A verify should be performed on the programmed bits  
to determine that they were correctly programmed.The  
verify should be performed with OE and CE at V ,  
IL  
2
12,000 µW/cm for 15 to 20 minutes. The Am27C1024  
PGM at V and V between 12.75 V ± 0.25 V.  
IH PP  
should be directly under and about one inch from the  
source and all filters should be removed from the UV  
light source prior to erasure.  
Auto Select Mode  
The auto select mode allows the reading out of a binary  
code from an EPROM that will identify its manufacturer  
and type.This mode is intended for use by programming  
equipment for the purpose of automatically matching the  
device to be programmed with its corresponding pro-  
gramming algorithm.This mode is functional in the 25°C  
± 5°C ambient temperature range that is required when  
programming the Am27C1024.  
It is important to note that the Am27C1024 and similar  
devices will erase with light sources having wavelengths  
shorter than 4000 Å. Although erasure times will be  
much longer than with UV sources at 2537 Å, exposure  
to fluorescent light and sunlight will eventually erase the  
Am27C1024 and exposure to them should be prevented  
to realize maximum system reliability. If used in such an  
environment, the package window should be covered by  
an opaque label or substance.  
To activate this mode, the programming equipment  
must force 12.0 V ± 0.5 V open address the A9 of the  
Am27C1024. Two identifier bytes may then be se-  
quenced from the device outputs by toggling address  
Programming the Am27C1024  
Upon delivery or after each erasure the Am27C1024  
has all 1,048,576 bits in the “ONE” or HIGH  
state. “ZEROs” are loaded into the Am27C1024  
through the procedure of programming.  
line A0 from V to V . All other address lines must be  
IL IH  
held at V during auto select mode.  
IL  
Byte 0 (A0 = V ) represents the manufacturer code,  
IL  
and byte 1 (A0 = V ), the device code. For the  
IH  
The programming mode is entered when 12.75 V ±  
Am27C1024, these two identifier bytes are given in the  
Mode Select Table. All identifiers for manufacturer and  
device codes will possess odd parity, with the MSB  
(DQ7) defined as the parity bit.  
0.25V is applied to the V pin and CE and PGM are  
PP  
atV .  
IL  
For programming, the data to be programmed is applied  
16 bits in parallel to the data output pins.  
Read Mode  
The Flashrite algorithm reduces programming time by  
using 100 µs programming pulses and by giving each  
address only as many pulses as is necessary in order to  
reliably program the data. After each pulse is applied to  
a given address, the data in that address is verified.If the  
data does not verify, additional pulses are given until it  
verifies or the maximum is reached. This process is re-  
peated while sequencing through each address of the  
The Am27C1024 has two control functions, both of  
which must be logically satisfied in order to obtain data  
at the outputs. Chip Enable (CE) is the power control  
and should be used for device selection. Output Enable  
(OE) is the output control and should be used to gate  
data to the output pins, independent of device selection.  
Assuming that addresses are stable, address access  
time (t  
) is equal to the delay from CE to output (t ).  
ACC  
CE  
Am27C1024.This part of the algorithm is done at V  
=
Data is available at the outputs t after the falling edge  
CC  
OE  
6.25 V to assure that each EPROM bit is programmed to  
a sufficiently high threshold voltage. After the final ad-  
dress is completed, the entire EPROM memory is veri-  
of OE, assuming that CE has been LOW and addresses  
have been stable for at least t  
–t  
.
ACC OE  
Standby Mode  
fied at V = V = 5.25 V.  
CC  
PP  
The Am27C1024 has a CMOS standby mode which re-  
duces the maximum V current to 100 µA. It is placed  
Please refer to Section 6 for programming flow chart  
and characteristics.  
CC  
in CMOS-standby when CE is at V  
± 0.3 V. The  
CC  
Am27C1024 also has a TTL-standby mode which re-  
duces the maximum V current to 1.0 mA. It is placed  
Program Inhibit  
CC  
Programming of multiple Am27C1024 in parallel with  
different data is also easily accomplished. Except for  
CE, all like inputs of the parallel Am27C1024 may be  
common. A TTL low-level program pulse applied to an  
in TTL-standby when CE is at V . When in standby  
IH  
mode, the outputs are in a high-impedance state, inde-  
pendent of the OE input.  
Am27C1024  
5
Output OR-Tieing  
System Applications  
To accommodate multiple memory connections, a  
two-line control function is provided to allow for:  
During the switch between active and standby condi-  
tions, transient current peaks are produced on the ris-  
ing and falling edges of Chip Enable.The magnitude of  
these transient current peaks is dependent on the out-  
put capacitance loading of the device. At a minimum, a  
0.1 µF ceramic capacitor (high frequency, low inherent  
inductance) should be used on each device between  
Low memory power dissipation  
Assurance that output bus contention will not occur  
It is recommended that CE be decoded and used as  
the primary device-selecting function, while OE be  
made a common connection to all devices in the array  
and connected to the READ line from the system con-  
trol bus. This assures that all deselected memory de-  
vices are in low-power standby mode and that the  
output pins are only active when data is desired from a  
particular memory device.  
V
and V to minimize transient effects. In addition,  
CC  
SS  
to overcome the voltage drop caused by the inductive  
effects of the printed circuit board traces on EPROM ar-  
rays, a 4.7 µF bulk electrolytic capacitor should be used  
between V and V for each eight devices.The loca-  
CC  
SS  
tion of the capacitor should be close to where the  
power supply is connected to the array.  
MODE SELECT TABLE  
Pins  
CE  
OE  
PGM  
A0  
X
A9  
X
V
Outputs  
Mode  
PP  
Read  
V
V
X
X
X
X
X
X
X
X
D
OUT  
IL  
IL  
Output Disable  
Standby (TTL)  
Standby (CMOS)  
Program  
X
V
X
X
Hi-Z  
Hi-Z  
Hi-Z  
IH  
V
X
X
X
IH  
V
± 0.3 V  
X
X
X
X
CC  
V
V
X
X
V
D
IN  
IL  
IL  
IH  
IL  
PP  
PP  
PP  
Program Verify  
Program Inhibit  
V
V
V
X
X
V
V
D
OUT  
IL  
IH  
V
X
X
X
X
Hi-Z  
01H  
8CH  
Manufacturer Code  
Device Code  
V
V
V
V
V
V
V
X
X
IL  
IL  
IL  
IH  
IH  
IL  
H
H
Autoselect  
(Note 3)  
V
V
V
IL  
IH  
Notes:  
1. V = 12.0 V ± 0.5 V  
H
2. X = Either V or V  
IH  
IL  
3. A1–A8 = A10–A15 = V  
IL  
4. See DC Programming Characteristics for V voltage during programming.  
PP  
6
Am27C1024  
ABSOLUTE MAXIMUM RATINGS  
OPERATING RANGES  
Storage Temperature  
Commercial (C) Devices  
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C  
All Other Products . . . . . . . . . . . . . . –65°C to +150°C  
Ambient Temperature (T ). . . . . . . . . . . .0°C to +70°C  
A
Industrial (I) Devices  
Ambient Temperature  
Ambient Temperature (T ). . . . . . . . . .–40°C to +85°C  
A
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C  
Extended (E) Devices  
Voltage with Respect to V  
Ambient Temperature (T ). . . . . . . . .–55°C to +125°C  
SS  
A
All pins except A9,V ,V  
. . . .0.6 V to V + 0.6 V  
PP CC  
CC  
Supply Read Voltages  
A9 and V (Note 2). . . . . . . . . . . . . –0.6 V to +13.5 V  
PP  
V
V
for Am27C1024-55, 255 . . . . +4.75 V to +5.25 V  
for Am27C1024 (All Others) . +4.50 V to +5.50 V  
CC  
CC  
V
(Note 1). . . . . . . . . . . . . . . . . . . . –0.6 V to +7.0 V  
CC  
Notes:  
Operating ranges define those limits between which the func-  
tionality of the device is guaranteed.  
1. Minimum DC voltage on input or I/O pins is –0.5 V. During  
voltage transitions, the inputs may overshoot V to –2.0  
SS  
V for periods of up to 20 ns. Maximum DC voltage on input  
and I/O pins is V  
+ 0.5 V. During voltage transitions,  
CC  
input and I/O pins may overshoot to V  
periods up to 20ns.  
+ 2.0 V for  
CC  
2. Minimum DC input voltage on A9 pin is –0.5 V. During volt-  
age transitions, A9 and V may overshoot V to –2.0 V  
PP  
SS  
for periods of up to 20 ns. A9 and V must not exceed  
CC  
+13.5 V for any period of time.  
Stresses above those listed under “Absolute Maximum Rat-  
ings” may cause permanent damage to the device. This is a  
stress rating only; functional operation of the device at these  
or any other conditions above those indicated in the opera-  
tional sections of this specification is not implied. Exposure of  
the device to absolute maximum rating conditions for ex-  
tended periods may affect device reliability.  
Am27C1024  
7
DC CHARACTERISTICS over operating range unless otherwise specified  
(Notes 1, 2, and 4)  
Parameter  
Symbol  
Parameter Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min  
Max  
Unit  
V
V
I
= –400 mA  
= 2.1 mA  
OL  
2.4  
OH  
OH  
V
I
0.45  
V
OL  
V
2.0  
V
+ 0.5  
V
IH  
CC  
V
–0.5  
+0.8  
1.0  
5.0  
5.0  
50  
V
IL  
C/I Devices  
E Devices  
I
Input Load Current  
V
= 0 V to +V  
CC  
µA  
µA  
LI  
IN  
I
Output Leakage Current  
V
= 0 V to +V  
LO  
OUT CC  
C/I Devices  
E Devices  
CE = V , f = 10 MHz  
IL  
I
V
Active Current (Note 3)  
mA  
CC1  
CC  
I
= 0 mA  
OUT  
60  
I
I
V
V
V
TTL Standby Current  
CMOS Standby Current  
Current During (Read)  
CE = V  
IH  
1.0  
100  
100  
mA  
µA  
µA  
CC2  
CC  
CC  
PP  
CE = V ± 0.3 V  
CC3  
CC  
I
CE = OE = V , V = V  
IL PP CC  
PP1  
Notes:  
1. V must be applied simultaneously or before V , and removed simultaneously or after V .  
PP  
CC  
PP  
2. Caution: The Am27C1024 must not be removed from (or inserted into) a socket when V or V is applied.  
CC  
PP  
3. I  
is tested with OE = V to simulate open outputs.  
IH  
CC1  
4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.  
Maximum DC Voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods less than 20 ns.  
CC  
CC  
40  
35  
30  
25  
20  
40  
35  
30  
25  
20  
1
2
3
4
5
6
7
8
9
10  
–75 –50 –25  
0
25 50 75 100 125 150  
Frequency in MHz  
Temperature in °C  
06780I-5  
Figure 1. Typical Supply Current vs. Frequency  
= 5.5 V,T = 25°C  
Figure 2. Typical Supply Current vs. Frequency  
= 5.5 V,T = 25°C  
V
V
CC  
CC  
8
Am27C1024  
CAPACITANCE  
CDV040  
PD 040  
PL 044  
Parameter  
Test  
Symbol  
Parameter Description  
Conditions  
Typ  
Max  
12  
Typ  
Max  
12  
Typ  
Max  
10  
Unit  
pF  
C
Input Capacitance  
Output Capacitance  
V
= 0  
9
7
8
IN  
IN  
C
V
= 0  
12  
14  
11  
14  
11  
14  
pF  
OUT  
OUT  
Notes:  
1. This parameter is only sampled and not 100% tested.  
2. T = +25°C, f = 1 MHz.  
A
AC CHARACTERISTICS  
Parameter  
Symbols  
Am27C1024  
-55 -70 -90 -120 -150 -200 -255 Unit  
JEDEC Standard  
Description  
Test Setup  
CE,  
OE = V  
t
t
Address to Output Delay  
Max  
55  
70  
90 120 150 200 250  
90 120 150 200 250  
ns  
AVQV  
ACC  
IL  
IL  
IL  
t
t
Chip Enable to Output Delay  
Output Enable to Output Delay  
OE = V  
Max  
Max  
55  
40  
70  
40  
ns  
ns  
ELQV  
CE  
t
t
CE = V  
45  
50  
65  
75  
75  
GLQV  
OE  
Chip Enable to Output High Z or  
Output Enable to Output High Z  
(Note 3) to Output Float, whichever occurs  
first  
t
t
t
EHQZ  
GHQZ  
DF  
Max  
Min  
30  
0
30  
0
40  
50  
50  
50  
50  
ns  
ns  
Output Hold Time from  
Addresses, CE or OE, whichever  
occurs first  
t
t
0
0
0
0
0
AXQX  
OH  
Notes:  
1. Caution: Do not remove the Am27C1024 from (or insert it into) a socket or board that has V or V applied.  
PP  
CC  
2.  
V
must be applied simultaneously or before V , and removed simultaneously or after V  
.
PP  
CC  
PP  
3. This parameter is sampled and not 100% tested.  
4. Switching characteristics are over operating range, unless otherwise specified.  
5. Test Conditions for Am27C1024-55:  
Output Load: 1 TTL gate and C = 30 pF  
L
Input rise and fall times: 20 ns  
Input pulse levels: 0.0 V to 3.0 V  
Timing measurement reference level Inputs and Outputs: 1.5 V  
Test Conditions for all others:  
Output Load: 1 TTL gate and C = 100 pF  
L
Input rise and fall times: 20 ns  
Input pulse levels: 0.45 V to 2.4 V  
Timing measurement reference level Inputs and Outputs: 0.8 and 2.0 V  
Am27C1024  
9
SWITCHING TEST CIRCUIT  
5.0 V  
IN3064  
or Equivalent  
2.7 kΩ  
Device  
Under  
Test  
C
L
6.2 kΩ  
Diodes = IN3064  
or Equivalent  
Notes:  
For -55: C = 30 pF including jig capacitance  
L
For all others: C = 100 pF including jig capacitance  
L
06780I-8  
Test Conditions  
SWITCHING TEST WAVEFORM  
3 V  
2.4 V  
2.0 V  
0.8 V  
2.0 V  
Test Points  
1.5 V  
Test Points  
1.5 V  
0.8 V  
0 V  
0.45 V  
Input  
Output  
Input  
Output  
AC Testing for -55 devices: Inputs are driven at 3.0 V for a  
logic “1” and 0 V for a logic “0”. Input pulse rise and fall times  
are 20 ns.  
AC Testing (except for -55 devices): Inputs are driven at 2.4 V  
for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and  
fall times are 20 ns.  
06780I-9  
10  
Am27C1024  
KEY TO SWITCHING WAVEFORMS  
WAVEFORM  
INPUTS  
OUTPUTS  
Must be  
Steady  
Will be  
Steady  
May  
Change  
from H to L  
Will be  
Changing  
from H to L  
May  
Change  
from L to H  
Will be  
Changing  
from L to H  
Don’t Care,  
Any Change  
Permitted  
Changing,  
State  
Unknown  
Does Not  
Apply  
Center  
Line is High-  
Impedance  
“Off” State  
KS000010  
SWITCHING WAVEFORMS  
2.4  
2.0  
0.8  
2.0  
0.8  
Addresses  
Addresses Valid  
0.45  
CE  
OE  
t
CE  
t
DF  
t
OE  
(Note 2)  
t
ACC  
t
OH  
(Note 1)  
High Z  
High Z  
Output  
Valid Output  
06780I-10  
Notes:  
1. OE may be delayed up to t  
– t after the falling edge of the addresses without impact on t  
ACC  
OE  
ACC.  
2. DF is specified from OE or CE, whichever occurs first.  
Am27C1024  
11  
Operating Ranges:  
REVISION SUMMARY FOR AM27C1024  
Distinctive Characteristics:  
Changed Supply Read Voltages listings to match those  
in the Product Selector Guide.  
The fastest speed grade available is now 55 ns.  
AC Characteristics:  
Product Selector Guide:  
Added column for 55 ns speed grade, rearranged  
notes, moved text from table title to Note 4, renamed  
table.  
Added 55 ns column.  
Ordering Information, UV EPROM Products:  
The 55 ns part number is now listed in the example.  
The nomenclature now has a method of clearly desig-  
nating the voltage operating range and speed grade.  
Switching Test Circuit:  
Added 55 ns to the C note on 30 pF test condition.  
L
Switching Test Waveform:  
Ordering Information, OTP EPROM Products:  
Added the 3 V test waveform.  
Changed the part number example from -70 to -55.The  
nomenclature now has a method of clearly designating  
the voltage operating range and speed grade.  
12  
Am27C1024  

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