AM29240 [ETC]
High-Performance RISC Microcontrollers(333.44 k) ; 高性能RISC微控制器（ 333.44 K）\n
| 型号： | AM29240 |
| 厂家： | 
ETC |
| 描述： | High-Performance RISC Microcontrollers(333.44 k)
|
| 文件： | 总31页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
Advanced
Micro
Am29240 , Am29245 , and Am29243
High-Performance RISC Microcontrollers
Devices
DISTINCTIVE CHARACTERISTICS
Am29240 Microcontroller
All three microcontrollers in the Am29240 microcon-
troller series have the following characteristics:
The Am29240 microcontroller has the following addi-
tional features:
Completely integrated system for embedded
applications
2-Kbyte, two-way set-associative data cache
Single-cycle 32-bit multiplier for faster integer
math; two-cycle Multiply Accumulate (MAC)
function
Full 32-bit architecture
4-Kbyte, two-way set-associative instruction
cache
16-entry on-chip Memory Management Unit
(MMU) with one Translation Look-Aside Buffer
4-Gbyte virtual address space, 304-Mbyte
physical space implemented
4-channel double-buffered DMA controller with
queued reload
Glueless system interfaces with on-chip wait
state control
Two serial ports (UARTs)
36 VAX million instructions per second (MIPS)
sustained at 25 MHz
Bidirectional bit serializer/deserializer
20- and 25-MHz operating frequencies
Four banks of ROM, each separately
programmable for 8-, 16-, or 32-bit interface
Scalable Clocking feature with full- and
double-speed internal clock
Four banks of DRAM, each separately
programmable for 16- or 32-bit interface
Am29245 Microcontroller
Single-cycle ROM burst-mode and DRAM
page-mode access
The low-cost Am29245 microcontroller is similar to the
Am29240 microcontroller, without the data cache and
32-bit multiplier. It includes the following features:
6-port peripheral interface adapter
16-line programmable I/O port
Bidirectional parallel port controller
Interrupt controller
16-entry on-chip MMU with one TLB
Bidirectional bit serializer/deserializer
Two-channel DMA controller
One serial port (UART)
Fully pipelined integer unit
16-MHz operating frequency
Three-address instruction architecture
192 general purpose registers
Am29243 Microcontroller
Traceable Cache technology instruction and
data cache tracing
The Am29243 data microcontroller is similar to the
Am29240 microcontroller, without the video interface. It
includes the following features:
IEEE Std 1149.1-1990 (JTAG) compliant
Standard Test Access Port and
Boundary Scan Architecture
2-Kbyte, two-way set-associative data cache
Single-cycle 32-bit multiplier for faster integer
math; two-cycle MAC
Binary compatibility with all 29K family
microprocessors and microcontrollers
32-entry on-chip MMU with dual TLBs
Fully static system-clock capabilities
CMOS technology/TTL compatible
196-pin Plastic Quad Flat Pack (PQFP) package*
5-V power supply*
4-channel, double-buffered DMA controller with
queued reload
Two serial ports (UARTs)
20- and 25-MHz operating frequencies
Note: * The new Am29240EH, Am29245EH, and Am29243EH
microcontrollers are packaged as 208-pin PQFPs and use a 3.3-V
power supply with 5-V-tolerant I/O. Before beginning a new design,
check with your field representative for schedule and availability of the
Am29240EHmicrocontrollerseries, describedinAmendment1(order
#17787/1).
Scalable Clocking feature with full- and
double-speed internal clock
DRAM parity
Publication #: 17787 Rev. C Amendment: /0
Issue Date: August 1995. WWW: 11/7/94
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
AMD
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Am29240 MICROCONTROLLER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Am29245 MICROCONTROLLER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Am29243 MICROCONTROLLER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CUSTOMER SERVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Am29240 MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Am29245 MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Am29243 MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
29K FAMILY DEVELOPMENT SUPPORT PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
KEY FEATURES AND BENEFITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PERFORMANCE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LOGIC SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC CHARACTERISTICS over COMMERCIAL Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CAPACITANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SWITCHING TEST CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PQB 196 PLASTIC QUAD FLAT PACK, TRIMMED AND FORMED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SOLDER LAND RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
Am29240 MICROCONTROLLER BLOCK DIAGRAM
Clock/
Control
Lines
4 DREQ
4 DACK
GREQ/GACK/TDMA
Parallel Port
Control/Status
Lines
4
5
8
11
STAT
MEMCLK
6
JTAG
4
6
6
16
Parallel Port
Controller
4-Channel DMA
Controller
r
Am29000 CPU
Serial
Data
I/O
Dual
Serial Ports
Programmable
I/O Port
4K ICache
Printer/Scanner
Video
Interrupts, Traps
Serializer/
Deserializer
Interrupt
Controller
2K DCache
ROM
Chip Selects
RAS/CAS
4/4
ROM
Controller
DRAM Controller
Timer/Counter
32x32 Multiply
4
PIA
Controller
MMU
ROM
Space
Memory
6
24
32
DRAM
Address
Bus
Instruction/Data
Bus
PIA
Chip Selects
Peripherals
Am29245 MICROCONTROLLER BLOCK DIAGRAM
Clock/
Control
Lines
2 DREQ
2 DACK
GREQ/GACK/TDMA
Parallel Port
Control/Status
Lines
4
5
8
7
STAT
MEMCLK
6
JTAG
4
4
6
16
Parallel Port
Controller
2-Channel DMA
Controller
Am29000 CPU
4K ICache
Serial
Data
I/O
Single
Serial Port
Programmable
I/O Port
Printer/Scanner
Video
Interrupts, Traps
Serializer/
Interrupt
Deserializer
Controller
ROM
Chip Selects
RAS/CAS
4/4
ROM
Controller
DRAM Controller
Timer/Counter
4
PIA
Controller
MMU
ROM
Space
Memory
6
24
32
Instruction/Data
Bus
DRAM
Address
Bus
PIA
Chip Selects
Peripherals
3
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
Am29243 MICROCONTROLLER BLOCK DIAGRAM
Clock/
Control
Lines
4 DREQ
Parallel Port
Control/Status
Lines
4
8
11
4 DACK
STAT
MEMCLK
6
GREQ/GACK/TDMA
5
6
6
16
Parallel Port
Controller
4-Channel DMA
Controller
Am29000 CPU
4K ICache
Serial
Data
I/O
Dual
Serial Ports
Programmable
I/O Port
Interrupts, Traps
Interrupt
2K DCache
JTAG
Controller
ROM
Chip Selects
RAS/CAS
4/4
ROM
Controller
DRAM Controller
Timer/Counter
32x32 Multiply
4
PIA
Controller
MMU
32
36
ROM
Space
Memory
6
24
32
DRAM
Address
Bus
Instruction/Data
Bus
PIA
Chip Selects
Peripherals
CUSTOMER SERVICE
AMD’s customer service network includes U.S. offices,
international offices, and a customer training center. Ex-
pert technical assistance is available from AMD’s world-
wide staff of field application engineers and factory
support staff.
(512) 602-5031
fax
epd.support@amd.com
e-mail
Bulletin Board
(800) 292-9263, ext. 1
(512) 602-7604
toll-free for U.S.
direct dial worldwide
Hotline, E-mail, and Bulletin Board Support
Product Information
For answers to technical questions, AMDr provides a
toll-free number for direct access to our engineering
support staff. For overseas customers, the easiest way
to reach the engineering support staff with your ques-
tions is via fax with a short description of your question.
AMD 29K family customers also receive technical sup-
port through electronic mail. This worldwide service is
available to 29K family product users via the international
Internet e-mail service. Also available is the AMD bulletin
board service, whichprovidesthelatest29Kfamilyprod-
uct information, including technical information and data
on upcoming product releases.
A simple phone call gets you free printed publications,
such as data books, user’s manuals, data sheets, ap-
plication notes, the Fusion29K Partner Solutions Cata-
log and Newsletter, and other literature. Internationally,
contact your local AMD sales office for complete 29K
family literature. For electronic copies of the most cur-
rent product information and publications on the 29K
family, visit AMD’s worldwide web site on the Internet.
Literature Request
(800) 292-9263, ext. 3
(512) 602-5651
toll-free for U.S.
direct dial worldwide
fax for U.S.
Engineering Support Staff
(512) 602-7639
(800) 292-9263, ext. 2
0031-11-1163
toll-free for U.S.
(800) 222-9323, option 2
AMD Facts-On-Demand
fax information service
toll-free for U.S.
toll-free for Japan
(512) 602-4118
direct dial worldwide
U.K. and Europe hotline
44-(0)256-811101
http://www.amd.com
worldwide web
4
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
The Am29245 microcontroller also provides an easy up-
grade path for Am29200, Am29202 , and Am29205
microcontroller-based products.
GENERAL DESCRIPTION
The Am29240 microcontroller series is an enhanced
bus-compatible extension of the Am29200 RISC mi-
crocontroller family, with two to four times the perfor-
mance. The Am29240 microcontroller series includes
the Am29240 microcontroller, the low-cost Am29245
microcontroller, and the Am29243 data microcontroller.
The on-chip caches, MMU, faster integer math, and ex-
tended DMA addressing capability of the Am29240 mi-
crocontroller series allow the embedded systems
designer to provide increasing levels of performance
and software compatibility throughout a range of prod-
ucts (see Table 1 on page 7).
Am29243 Microcontroller
With DRAM parity support and a full MMU, the
Am29243 data microcontroller is recommended for
communications applications that require high-speed
data movement and fast protocol processing in a fault-
tolerant environment.
Both the Am29243 and Am29240 microcontrollers sup-
port fly-by DMA at 100 Mbytes/s for LANs and switching
applications, and a two-cycle Multiply Accumulate func-
tion for DSP applications. The low power requirements
make either microcontroller a good choice for field-
deployed devices.
Based on a static low-voltage design, these CMOS-
technology devices offer a complete set of system pe-
ripherals and interfaces commonly used in embedded
applications. Compared to CISC processors, the
Am29240 microcontroller series offers better perfor-
mance, more efficient use of low-cost memories, lower
system cost, and complete design flexibility for the de-
signer. Coupled with hardware and software develop-
ment tools from AMD and the AMD Fusion29Kr
partners, the Am29240 microcontroller series provides
the embedded product designer with the cost and per-
formance edge required by today’s marketplace.
29K Family
Development Support Products
Contact your local AMD representative for information
on the complete set of development support tools. The
following software and hardware development products
are available on several hosts:
Optimizing compilers for common high-level
languages
Am29240 Microcontroller
Assembler and utility packages
Source- and assembly-level software debuggers
Target-resident development monitors
Simulators
For general-purpose embedded applications, such as
mass-storage controllers, communications, digital sig-
nal processing, networking, industrial control, pen-
based systems, and multimedia, the Am29240
microcontroller provides a high-performance solution
with a low total-system cost. The memory interface of
the Am29240 microcontroller provides even faster di-
rect memory access than the Am29200 microcontroller.
This performance improvement minimizes the effect of
memory latency, allowing designers to use low-cost
memory with simpler memory designs. On-chip instruc-
tion and data caches provide even better performance
for time-critical code.
Execution boards
Third-Party
Development Support Products
The Fusion29K Program of Partnerships for Application
Solutions provides the user with a vast array of products
designed to meet critical time-to-market needs. Prod-
ucts/solutions available from the AMD Fusion29K part-
ners include the following:
Other on-chip functions include: a ROM controller,
DRAM controller, peripheral interface adapter control-
ler, DMA controller, programmable I/O port, parallel port
controller, serial ports, and an interrupt controller. For a
complete description of the technical features, on-chip
peripherals, programming interface, and instruction set,
please refer to the Am29240, Am29245, and Am29243
RISC Microcontrollers User’s Manual (order #17741).
Silicon products
Software generation and debug tools
Hardware development tools
Board-level products
Laser-printer solutions
Multiuser, kernel, and real-time operating systems
Graphics solutions
Am29245 Microcontroller
Networking and communication solutions
Manufacturing support
The low-cost Am29245 microcontroller is designed for
embedded applications in which cost and space
constraints, along with increased performance require-
ments, are primary considerations.
Custom software consulting, support, and training
5
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am29240
–25
K
C
\W
PROCESSING
\W = Trimmed and Formed (PQB 196)
TEMPERATURE RANGE
C = Commercial (TC = 0°C to +85°C)
PACKAGE TYPE
K = 196-Lead Plastic Quad Flat Pack (PQB 196)
SPEED OPTION
–25 = 25 MHz
–20 = 20 MHz
–16 = 16 MHz
DEVICE NUMBER/DESCRIPTION
Am29240 RISC Microcontroller
Am29245 RISC Microcontroller
Am29243 RISC Data Microcontroller
Valid Combinations
Am29240–20
KC\W
Valid Combinations
Am29240–25
Valid Combinations lists configurations
planned to be supported in volume. Consult
the local AMD sales office to confirm
availability of specific valid combinations, to
check on newly released combinations, and
to obtain additional data on AMD standard
military grade products.
Am29243–20
Am29243–25
KC\W
KC\W
Am29245–16
RELATED AMD PRODUCTS
29K Family Devices
Product
Description
R
Am29000
Am29005
Am29030
Am29035
Am29040
Am29050
Am29200
Am29202
Am29205
32-bit RISC microprocessor
Low-cost 32-bit RISC microprocessor with no MMU and no branch target cache
32-bit RISC microprocessor with 8-Kbyte instruction cache
32-bit RISC microprocessor with 4-Kbyte instruction cache
32-bit RISC microprocessor with 8-Kbyte instruction cache and 4-Kbyte data cache
32-bit RISC microprocessor with on-chip floating point
32-bit RISC microcontroller
Low-cost 32-bit RISC microcontroller with IEEE-1284-compliant parallel interface
Low-cost 32-bit RISC microcontroller
6
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
Table 1. Product Comparison—Am29200 Microcontroller Family
FEATURE
Am29205
Controller
Am29202
Controller
Am29200
Controller
Am29245
Controller
Am29240
Controller
Am29243
Controller
Instruction Cache
Data Cache
—
—
—
—
—
—
4 Kbytes
—
4 Kbytes
2 Kbytes
2-way
4 Kbytes
2 Kbytes
2-way
Cache Associativity
Integer Multiplier
—
—
—
2-way
Software
Software
—
Software
—
Software
—
32 x 32-bit
32 x 32-bit
Memory Management
Unit (MMU)
1 TLB
16 Entry
1 TLB
16 Entry
2 TLBs
32 Entry
Data Bus Width
Internal
External
32 bits
16 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
ROM Interface
Banks
Width
ROM Size (Max/Bank)
Boot-Up ROM Width
Burst-Mode Access
3
4
4
4
4
4
8, 16 bits
4 Mbytes
16 bits
8, 16, 32 bits
4 Mbytes
8, 16, 32 bits
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
Not Supported
Not Supported
DRAM Interface
Banks
Width
Size: 32-Bit Mode
Size: 16-Bit Mode
Video DRAM
Access Cycles
Initial/Burst
4
4
4
4
4
4
16 bits only
—
8 Mbytes/bank
16, 32 bits
16, 32 bits
16, 32 bits
16, 32 bits
16, 32 bits
16 Mbytes/bank 16 Mbytes/bank 16 Mbytes/bank 16 Mbytes/bank 16 Mbytes/bank
8 Mbytes/bank
Not Supported
8 Mbytes/bank
Supported
8 Mbytes/bank
Supported
8 Mbytes/bank
Supported
8 Mbytes/bank
Not Supported
Not Supported
3/2
No
3/2
No
3/2
No
3/1
No
3/1
No
3/1
Yes
DRAM Parity
On-Chip DMA
Width (ext. peripherals)
Total Number of Channels
Externally Controlled
External Master Access
External Master Burst
External Terminate Signal
8, 16 bits
8, 16, 32 bits
8, 16, 32 bits
8, 16, 32 bits
8, 16, 32 bits
8, 16, 32 bits
2
1
No
No
No
2
1
No
No
No
2
2
Yes
No
Yes
2
2
Yes
Yes
Yes
4
4
Yes
Yes
Yes
4
4
Yes
Yes
Yes
Scalable Clocking Double-
Frequency CPU Option
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Low-Voltage Operation
Yes
Peripheral Interface
Adapter (PIA)
PIA Ports
Data Width
Min. Cycles Access
2
8, 16 bits
3
2
6
6
6
6
8, 16, 32 bits
3
8, 16, 32 bits
3
8, 16, 32 bits
1
8, 16, 32 bits
1
8, 16, 32 bits
1
Programmable I/O Port
(PIO)
Signals
Signals programmable
for interrupt generation
8
8
12
8
16
8
16
8
16
8
16
8
Serial Ports
Ports
DSR/DTR
1 Port
PIO signals
1 Port
PIO signals
1 Port
Supported
1 Port
Supported
2 Ports
2 Ports
1 Port Supported 1 Port Supported
Interrupt Controller
External Interrupt Pins
External Trap and Warn
Pins
2
0
2
0
4
3
4
3
4
3
4
3
Parallel Port Controller
32-Bit Transfer
IEEE-1284 Interface
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
JTAG Debug Support
Serializer/Deserializer
Pin Count and Package
Operating Voltage
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
100 PQFP
132 PQFP
168 PQFP
196 PQFP
196 PQFP
196 PQFP
V
CC
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
I/O Tolerance
Processor Clock Rate
12, 16 MHz
12, 16, 20 MHz
16, 20 MHz
16 MHz
20, 25 MHz
20, 25 MHz
7
Am29240 Microcontroller Series
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A D V A N C E I N F O R M A T I O N
KEY FEATURES AND BENEFITS
Complete Set of Common Peripherals
The Am29240 microcontroller series extends the line of
RISC microcontrollers based on 29K family architec-
ture, providing performance upgrades to the Am29205
and Am29200 microcontrollers. The RISC microcontrol-
ler product line allows users to benefit from the very high
performance of the 29K family architecture, while also
capitalizing on the very low system cost made possible
by integrating processor and peripherals.
The Am29240 microcontroller series minimizes system
cost by incorporating a complete set of system facilities
commonly found in embedded applications, eliminating
the cost of additional components. The on-chip func-
tionsinclude:aROMcontroller, aDRAMcontroller, ape-
ripheral interface adapter, a DMA controller, a
programmable I/O port, a parallel port, up to two serial
ports, and an interrupt controller. A video interface is
also included in the Am29240 and Am29245 microcon-
trollers for printer, scanner, and other imaging applica-
tions. These facilities allow many simple systems to be
built using only the Am29240 microcontroller series, ex-
ternal ROM, and/or DRAM memory.
The Am29240 microcontroller series expands the price/
performance range of systems that can be built with the
29K family. The Am29240 microcontroller series is fully
software compatible with the Am29000, Am29005,
Am29030, Am29035, Am29040, and Am29050 micro-
processors, as well as the Am29200 and Am29205 mi-
crocontrollers. It can be used in existing 29K family
microcontroller applications without software modifica-
tions.
ROM Controller
The ROM controller supports four individual banks of
ROM or other static memory, each with its own timing
characteristics. Each ROM bank may be a different size
and may be either 8, 16, or 32 bits wide. The ROM banks
can appear as a contiguous memory area of up to 64
Mbytes in size. The ROM controller also supports byte,
half-word, and word writes to the ROM memory space
for devices such as flash EPROMs and SRAMs.
On-Chip Caches
The Am29240 microcontroller series incorporates a
4-Kbyte, two-way instruction cache that supplies most
processor instructions without wait states at the proces-
sor frequency. For best performance, the instruction
cache supports critical-word-first reloading with fetch-
through, so that the processor receives the required
instruction and the pipeline restarts with minimum delay.
The instruction cache has a valid bit per word to mini-
mize the reload overhead. All cache array elements are
visible to software for testing and preload.
DRAM Controller
The DRAM controller supports four separate banks of
dynamicmemory. Eachbankmaybeadifferentsizeand
may be either 16 or 32 bits wide. The DRAM banks can
appear as a contiguous memory area of up to 64 Mbytes
in size. The DRAM controller supports three-cycle ac-
cesses, with single-cycle page-mode and burst-mode
accesses.
The Am29240 and Am29243 microcontrollers incorpo-
ratea2-Kbyte, two-wayset-associativedatacache. The
data cache appears in the execute stage of the proces-
sor pipeline, so that loaded data is available immediate-
ly to the next instruction. This provides the maximum
performance for loads without requiring load schedul-
ing. The data cache performs critical-word-first, wrap-
around, and burst-mode refill with load-through. This
minimizes the time the processor waits on external data
as well as minimizing the reload time. The data cache
uses a write-through policy with a two-entry write buffer.
Byte, half-word, and word reads and writes are sup-
ported. All cache array elements are visible to software
for testing and preload.
Peripheral Interface Adapter
The Peripheral Interface Adapter (PIA) permits glueless
interfacing to as many as six external peripheral chips.
The PIA allows for additional system features imple-
mented by external peripheral chips.
DMA Controller
The DMA controller provides up to four channels for
transferring data between the DRAM and internal or ex-
ternal peripherals. The DMA channels are double buff-
ered to relax constraints on reload time.
I/O Port
Single-Cycle Multiplier
The I/O port permits direct access to 16 individually pro-
grammable external input/output signals. Eight of these
signals can be configured to cause interrupts.
The Am29240 and Am29243 microcontrollers incorpo-
rate a full combinatorial multiplier that accepts two
32-bit input operands and produces a 32-bit result in a
single cycle. The multiplier can produce a 64-bit result
in two cycles. The multiplier permits maximum perfor-
mance without requiring instruction scheduling, since
the latency of the multiply is the same as the latency of
other integer operations. High-performance multiplica-
tion benefits imaging, signal processing, and state
modeling applications.
Parallel Port
The parallel port implements a bidirectional IBM PC-
compatible parallel interface to a host processor.
Serial Port
The serial port implements up to two full-duplex UARTs.
8
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
Serializer/Deserializer
Processor outputs have edge-rate control that allows
them to drive a wide range of load capacitances with low
noise and ringing. This eliminates the cost of external
logic and buffering.
The serializer/deserializer (video interface) on the
Am29240 and Am29245 microcontrollers permits direct
connection to a number of laser-marking engines, video
displays, or raster input devices such as scanners.
Bus and Software Compatibility
Interrupt Controller
Compatibility within a processor family is critical for
achieving a rational, easy upgrade path. Processors in
the Am29240 microcontroller series are all members of
a bus-compatible family of RISC microcontrollers. All
members of this family—the Am29205, Am29202,
Am29200, Am29240, Am29245, and Am29243 micro-
controllers—allow improvements in price, performance,
and system capabilities without requiring that users re-
design their system hardware or software. Bus compati-
bility ensures a convenient upgrade path for future
systems.
The interrupt controller generates and reports the status
of interrupts caused by on-chip peripherals.
Wide Range of Price/Performance Points
To reduce design costs and time-to-market, the product
designer can use the Am29200 microcontroller family
and one basic system design as the foundation for an
entire product line. From this design, numerous imple-
mentations of the product at various levels of price and
performance may be derived with minimum time, effort,
and cost.
The Am29240 microcontroller series is available in a
196-pin plastic quad flat-pack (PQFP) package. The
Am29240 microcontroller series is signal-compatible
with the Am29200 and the Am29205 microcontrollers.
The Am29240 RISC microcontroller series supports this
capability through various combinations of on-chip
caches, programmable memory widths, programmable
wait states, burst-mode and page-mode access sup-
port, bus compatibility, and 29K family software compat-
ibility. A system can be upgraded using various memory
architectures without hardware and software redesign.
Moreover, the Am29240 microcontroller series is
binary compatible with existing RISC microcontrollers
and other members of the 29K family (the Am29000,
Am29005, Am29030, Am29035, Am29040, and
Am29050 microprocessors, as well as the Am29200,
Am29202, and Am29205 microcontrollers). The
Am29240 microcontroller series provides a migration
path to low-cost, high-performance, highly integrated
systems from other 29K family members, without re-
quiring expensive rewrites of application software.
Within the Am29240 microcontroller series, the external
interfaces and the processor operate at frequencies in
the range of 16 to 25 MHz. Using the Scalable Clocking
feature on the Am29240 and Am29243 microcon-
trollers, the internal processor core can operate either at
the interface frequency or twice this frequency. For ex-
ample, the processor can operate at 25 MHz while the
interface operates at 12.5 MHz.
Complete Development and
Support Environment
The ROM controller accommodates memories that are
either 8, 16, or 32 bits wide, and the DRAM controller ac-
commodates dynamic memories that are either 16 or 32
bits wide. This unique feature provides a flexible inter-
face to low-cost memory, as well as a convenient, flex-
ible upgrade path. For example, a system can start with
a 16-bit memory design and can subsequently improve
performance by migrating to a 32-bit memory design.
One particular advantage is the ability to add memory in
half-megabyte increments. This provides significant
cost savings for applications that do not require larger
memory upgrades.
A complete development and support environment is vi-
tal for reducing a product’s time-to-market. Advanced
Micro Devices has created a standard development en-
vironment for the 29K family of processors. In addition,
theFusion29Kthird-partysupportorganizationprovides
the most comprehensive customer/partner program in
the embedded processor market.
Advanced Micro Devices offers a complete set of hard-
ware and software tools for design, integration, debug-
ging, and benchmarking. These tools, which are
available now for the 29K family, include the following:
Software development kit that includes the
High Cr 29K optimizing C compiler with assem-
bler, linker, ANSI library functions, 29K family archi-
tectural simulator, and MiniMON29Kr debug
monitor
The Am29200, Am29202, Am29205, Am29240,
Am29245, and Am29243 microcontrollers allow users
toaddressanextremelywiderangeofcostperformance
points, with higher performance and lower cost than ex-
isting designs based on CISC microprocessors.
XRAY29K source-level debugger
Glueless System Interfaces
A complete family of demonstration and develop-
ment boards
The Am29240 microcontroller series also minimizes
system cost by providing a glueless attachment to exter-
nal ROMs, DRAMs, and other peripheral components.
9
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
In addition, Advanced Micro Devices has developed a
standard host interface (HIF) specification for operating
system services, the Universal Debugger Interface
(UDI) for seamless connection of debuggers to ICEs
and target hardware, and extensions for the UNIX com-
mon object file format (COFF).
series by overlapping them with instruction execution,
by taking advantage of pipelining, by an on-chip data
cache, and by organizing the flow of external data into
the processor so that the impact of external accesses is
minimized.
Pipelining
This support is augmented by an engineering hotline, an
on-line bulletin board, and field application engineers.
Instruction operations are overlapped with instruction
fetch, instruction decode and operand fetch, instruction
execution, and result write-back to the Register File.
Pipeline forwarding logic detects pipelinedependencies
and routes data as required, avoiding delays that might
arise from these dependencies. Pipeline interlocks are
implemented by processor hardware. Except for a few
special cases, it is not necessary to rearrange programs
to avoid pipeline dependencies, although this is some-
times desirable for performance.
Debugging and Testing
The Am29240 microcontroller series provides debug-
ging and testing features at both the software and
hardware levels.
Software debugging is facilitated by the instruction
trace facility and instruction breakpoints. Instruction
tracing is accomplished by forcing the processor to trap
after each instruction has been executed. Instruction
breakpoints are implemented by the HALT instruction
or by a software trap.
On-Chip Instruction and Data Caches
On-chip instruction and data caches satisfy most pro-
cessor fetches without wait states, even when the pro-
cessor operates at twice the system frequency. The
caches are pipelined for best performance. The reload
policies minimize the amount of time spent waiting for
reload, while optimizing the benefit of locality of
reference.
The processor provides several additional features to
assist system debugging and testing:
The Test/Development Interface is composed of a
group of pins that indicate the state of the processor
and control the operation of the processor.
A Traceable Cache feature permits a hardware-
development system to track accesses to the on-
chip caches, permitting a high level of visibility into
processor operation.
Burst-Mode and Page-Mode Memories
The Am29240 microcontroller series directly supports
burst-mode memories. The burst-mode memory sup-
plies instructions at the maximum bandwidth, without
the complexity of an external cache or the performance
degradation due to cache misses.
An IEEE Std 1149.1-1990 (JTAG) compliant Stan-
dard Test Access Port and Boundary-Scan Architec-
ture. The Test Access Port provides a scan interface
for testing processor and system hardware in a pro-
duction environment, and contains extensions that
allow a hardware-development system to control
and observe the processor without interposing hard-
ware between the processor and system.
The processor can also use the page-mode capability of
common DRAMs to improve the access time in cases
where page-mode accesses can be used. This is partic-
ularly useful in very low-cost systems with 16-bit-wide
DRAMs, where the DRAM must be accessed twice for
each 32-bit operand.
PERFORMANCE OVERVIEW
Instruction Set Overview
The Am29240 microcontroller series offers a significant
margin of performance over CISC microprocessors in
existing embedded designs, since the majority of pro-
cessor features were defined for the maximum achiev-
able performance at very low cost. This section
describes the features of the Am29240 microcontroller
series from the point of view of system performance.
All29Kfamilymembersemployathree-addressinstruc-
tion set architecture. The compiler or assembly-lan-
guage programmer is given complete freedom to
allocate register usage. There are 192 general-purpose
registers, allowing the retention of intermediate calcula-
tions and avoiding needless data destruction. Instruc-
tion operands may be contained in any of the
general-purpose registers, and the results may be
stored into any of the general-purpose registers.
Instruction Timing
TheAm29240microcontrollerseriesusesanarithmetic/
logic unit, a field shift unit, and a prioritizer to execute
most instructions. Each of these is organized to operate
on 32-bit operands and provide a 32-bit result. All opera-
tions are performed in a single cycle.
TheAm29240microcontrollerseriesinstructionsetcon-
tains 117 instructions that are divided into nine classes.
These classes are integer arithmetic, compare, logical,
shift, data movement, constant, floating point, branch,
and miscellaneous. The floating-point instructions are
not executed directly, but are emulated by trap handlers.
The performance degradation of load and store opera-
tions is minimized in the Am29240 microcontroller
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Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
All directly implemented instructions are capable of
executing in one processor cycle, with the exception of
interrupt returns, loads, and stores.
Interrupts and traps are dispatched through a 256-entry
vector table that directs the processor to a routine that
handles a given interrupt or trap. The vector table may
be relocated in memory by the modification of a proces-
sor register. There may be multiple vector tables in the
system, though only one is active at any given time.
Data Formats
The Am29240 microcontroller series defines a word as
32 bits of data, a half-word as 16 bits, and a byte as 8
bits. The hardware provides direct support for word-
integer (signed and unsigned), word-logical, word-Bool-
ean, half-word integer (signed and unsigned), and char-
acter data (signed and unsigned).
The vector table is a table of pointers to the interrupt and
trap handlers, and requires only 1 Kbyte of memory. The
processor performs a vector fetch every time an inter-
rupt or trap is taken. The vector fetch requires at least
three cycles, in addition to the number of cycles required
for the basic memory access.
Word-Boolean data is based on the value contained in
the most significant bit of the word. The values TRUE
and FALSE are represented by the most significant bit
values 1 and 0, respectively.
PIN DESCRIPTIONS
A23–A0
Address Bus (output, synchronous)
Other data formats, such as character strings, are sup-
ported by instruction sequences. Floating-point formats
(single and double precision) are defined for the proces-
sor; however, there is no direct hardware support for
these formats in the Am29240 microcontroller series.
The Address Bus supplies the byte address for all ac-
cesses, except for DRAM accesses. For DRAM ac-
cesses, multiplexed row and column addresses are
provided on A14–A1. A2–A0 are also used to provide a
clock to an optional burst-mode EPROM.
Protection
BOOTW
The Am29240 microcontroller series offers two mutually
exclusive modes of execution—the User and Supervi-
sor modes—that restrict or permit accesses to certain
processor registers and external storage locations.
Boot ROM Width (input, asynchronous)
This input configures the width of ROM Bank 0, so the
ROM can be accessed before the ROM configuration
has been set by the system initialization software. The
BOOTW signal is sampled during and after a processor
reset. If BOOTW is High before and after reset (tied
High), the boot ROM is 32 bits wide. If BOOTW is Low
before and after reset (tied Low), the boot ROM is 16 bits
wide. If BOOTW is Low before reset and High after reset
(tied to RESET), the boot ROM is 8 bits wide. This signal
has special hardening against metastable states, allow-
ingittobedrivenwithaslow-rise-timesignalandpermit-
ting it to be tied to RESET.
The register file may be configured to restrict accesses
to Supervisor-mode programs on a bank-by-bank basis.
Memory Management Unit
The Am29240 microcontroller series provides a
memory-management unit (MMU) for translating virtual
addresses into physical addresses. The page size for
translation ranges from 1 Kbyte to 16 Mbytes in powers
of 4. The Am29245 and Am29240 microcontrollers each
have a single, 16-entry TLB. The Am29243 microcon-
troller has dual 16-entry TLBs, each capable of mapping
pages of different size.
BURST
Burst-Mode Access (output, synchronous)
Interrupts and Traps
This signal is asserted to perform sequential accesses
from a burst-mode device.
When a member of the Am29240 microcontroller series
takes an interrupt or trap, it does not automatically save
its current state information in memory. This lightweight
interrupt and trap facility greatly improves the perfor-
mance of temporary interruptions such as simple
operating-system calls that require no saving of state in-
formation.
CAS3–CAS0
Column Address Strobes, Byte 3–0
(output, synchronous)
A High-to-Low transition on these signals causes the
DRAM selected by RAS3–RAS0 to latch the column ad-
dress and complete the access. To support byte and
half-word writes, column address strobes are provided
for individual DRAM bytes. CAS3 is the column address
strobe for the DRAMs, in all banks, attached to
ID31–ID24. CAS2 is for the DRAMs attached to
ID23–ID16, and so on. These signals are also used in
other special DRAM cycles.
In cases where the processor state must be saved, the
saving and restoring of state information is under the
control of software. The methods and data structures
used to handle interrupts—and the amount of state
saved—may be tailored to the needs of a particular
system.
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Am29240 Microcontroller Series
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A D V A N C E I N F O R M A T I O N
CNTL1–CNTL0
GACK
CPU Control
(input, asynchronous, internal pull-ups)
External Memory Grant Acknowledge
(output, synchronous)
These inputs specify the processor mode: Load Test
Instruction, Step, Halt, or Normal.
This signal indicates to an external device that it has
been granted an access to the processor’s ROM or
DRAM, and that the device should provide an address.
DACKD–DACKA
The processor can be placed into a slave configuration
that allows tracing of a master processor. In this configu-
ration, GACK is used to indicate that the processor pipe-
line was held during the previous processor cycle.
DMA Acknowledge D through A
(output, synchronous)
These signals acknowledge an external transfer on a
DMA channel. DMA acknowledgments are not dedi-
cated to a particular DMA channel—each channel spec-
ifies which acknowledge line, if any, it is using. Only one
channel at a time can use either DACKD, DACKC,
DACKB, or DACKA, and the same channel uses the re-
spective DREQD–DREQA signal for transfer requests.
DMA transfers can occur to and from internal peripher-
als independent of these acknowledgments. The
DACKD and DACKC signals are supported on the
Am29240 and Am29243 microcontrollers only.
GREQ
External Memory Grant Request
(input, synchronous, pull-up resistor)
This signal is used by an external device to request an
access to the processor’s ROM or DRAM. To perform
this access, the external device supplies an address to
the ROM controller or DRAM controller.
To support a hardware-development system, GREQ
should be either tied High or held at a high-impedance
state during a processor reset.
DREQD–DREQA
DMA Request D through A
ID31–ID0
(input, asynchronous, pull-up resistors)
These inputs request an external transfer on a DMA
channel. DMA requests are not dedicated to a particular
channel—each channel specifies which request line, if
any, it is using. Only one channel at a time can use either
DREQD, DREQC, DREQB, or DREQA. This channel ac-
knowledges a transfer using the respective DACKD–
DACKA signal. These requests are individually program-
mable to be either level- or edge-sensitive for either po-
larity of level or edge. DMA transfers can occur to and
from internal peripherals independent of these requests.
Instruction/Data Bus (bidirectional, synchronous)
The Instruction/Data Bus (ID Bus) transfers instructions
to, and data to and from the processor.
IDP3–IDP0
Instruction/Data Parity
(bidirectional, synchronous)
If parity checking is enabled by the PCE bit of the
DRAM Control Register, IDP3–IDP0 are parity bits for
the ID Bus during DRAM accesses. IDP3 is the parity
bit for ID31–ID24, IDP2 is the parity bit for ID23–ID16,
and so on. If parity is enabled, the processor drives
IDP3–IDP0 with valid parity during DRAM writes, and
expects IDP3–IDP0 to be driven with valid parity during
DRAM reads. These signals are supported on the
Am29243 microcontroller only.
The DMA request/acknowledge pairs DREQA/DACKA
and DREQB/DACKB correspond to the Am29200 micro-
controller signals DREQ0/DACK0 and DREQ1/DACK1,
respectively. The pin placement reflects this correspon-
dence, and a processor reset dedicates these request/
acknowledge pairs to DMA channels 0 and 1,
respectively. This permits backward-compatible up-
grade to an Am29200 microcontroller. The DREQD and
DREQC signals are supported on the Am29240 and
Am29243 microcontrollers only.
INCLK
Input Clock (input)
This is an oscillator input at twice the system operating
frequency. The processor operates either at the system
operating frequency or at the INCLK frequency, as con-
trolled by the TBO bit in the Configuration Register. The
processor can operate at the INCLK frequency only if
MEMCLK is an output.
DSRA
Data Set Ready, Port A (output, synchronous)
This indicates to the host that the serial port is ready to
transmit or receive data on Serial Port A.
DTRA
INTR3–INTR0
Data Terminal Ready, Port A
(input, asynchronous)
Interrupt Requests 3–0
(input, asynchronous, internal pull-up resistors)
This indicates to the processor that the host is ready to
transmit or receive data on Serial Port A.
These inputs generate prioritized interrupt requests.
The interrupt caused by INTR0 has the highest priority,
12
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
and the interrupt caused by INTR3 has the lowest prior-
PIACS5–PIACS0
ity. The interrupt requests are masked in prioritized or-
der by the Interrupt Mask field in the Current Processor
StatusRegisterandaredisabledbytheDAandDIbitsof
the Current Processor Status Register. These signals
have special hardening against metastable states, al-
lowing them to be driven with slow-transition-time
signals.
Peripheral Chip Selects, Regions 5–0
(output, synchronous)
These signals are used to select individual peripheral
devices. DMA channels may be programmed to use
dedicated chip selects during an external peripheral
access.
PIAOE
LSYNC
Peripheral Output Enable (output, synchronous)
Line Synchronization (input, asynchronous)
This signal enables the selected peripheral device to
drive the ID bus.
This signal indicates the start of a raster line. This signal
is supported on the Am29240 and Am29245 microcon-
trollers only.
PIAWE
MEMCLK
Peripheral Write Enable (output, synchronous)
Memory Clock (input/output)
This signal causes data on the ID bus to be written into
the selected peripheral.
This is either a clock output or an input from an external
clockgenerator, asdeterminedbytheMEMDRVinput. It
operates at the system operating frequency, which is
half of the INCLK frequency. Most processor inputs and
outputs are synchronous to MEMCLK. MEMCLK must
be driven with CMOS levels. MEMCLK must be an out-
put if the processor operates at the INCLK frequency.
PIO15–PIO0
Programmable Input/Output
(input/output, asynchronous)
These signals are available for direct software control
and inspection. PIO15–PIO8 may be individually pro-
grammed to cause processor interrupts. These signals
have special hardening against metastable states, al-
lowing them to be driven with slow-transition-time
signals.
MEMDRV
MEMCLK Drive Enable
(input, internal pull-up resistor)
This input determines whether MEMCLK is an output or
an input. If this pin is High, the processor generates a
clock on the MEMCLK output. If this pin is Low, the pro-
cessor accepts a clock generated by the system on the
MEMCLK input. This signal is tied High through an inter-
nal pull-up resistor so the signal can be left unconnected
to configure MEMCLK as an output.
The PIO signals are sampled during a processor reset.
After reset, the sampled value is held in the PIO Input
Register. This sampled value is supplied the first time
this register is read, unless the read is preceded by write
to the PIO Input Register or by a read or write of any oth-
er PIO register. This may be used to indicate system
configuration information to the processor during a
reset.
PACK
Parallel Port Acknowledge (output, synchronous)
POE
This signal is used by the processor to acknowledge a
transfer from the host or to indicate to the host that data
has been placed on the port.
Parallel Port Output Enable (output, synchronous)
This signal enables an external data buffer containing
data from the host to drive the ID Bus.
PAUTOFD
PSTROBE
Parallel Port Autofeed (input, asynchronous)
Parallel Port Strobe (input, asynchronous)
This signal is used by the host to indicate how line feeds
should be performed or is used to indicate that the host
is busy and cannot accept a data transfer.
This signal is used by the host to indicate that data is on
the Parallel Port or to acknowledge a transfer from the
processor.
PBUSY
PSYNC
Parallel Port Busy (output, synchronous)
Page Synchronization
(input/output, asynchronous)
This indicates to the host that the Parallel Port is busy
and cannot accept a data transfer.
Thissignalindicatesthebeginningofarasterpage. This
signal is supported on the Am29240 and Am29245 mi-
crocontrollers only.
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Am29240 Microcontroller Series
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A D V A N C E I N F O R M A T I O N
PWE
RXDB
Parallel Port Write Enable (output, synchronous)
Receive Data, Port B (input, asynchronous)
This signal writes a buffer with data on the ID Bus. Then,
the buffer drives data to the host.
This input is used to receive data to Serial Port B. This
signal is supported on the Am29240 and Am29243 mi-
crocontrollers only.
R/W
STAT2–STAT0
Read/Write (output, synchronous)
CPU Status (output, synchronous)
During an external ROM, DRAM, DMA, or PIA access,
this signal indicates the direction of transfer: High for a
read and Low for a write.
These outputs indicate information about the processor
or the current access for the purposes of hardware
debug.
RAS3–RAS0
TCK
Row Address Strobe, Banks 3–0
(output, synchronous)
Test Clock Input
(input, asynchronous, pull-up resistor)
A High-to-Low transition on one of these signals causes
a DRAM in the corresponding bank to latch the row ad-
dress and begin an access. RAS3 starts an access in
DRAMBank3, andsoon. Thesesignalsalsoareusedin
other special DRAM cycles.
This input is used to operate the Test Access Port. The
state of the Test Access Port must be held if this clock is
held either High or Low. This clock is internally synchro-
nized to MEMCLK for certain operations of the Test Ac-
cess Port controller, so signals internally driven and
sampled by the Test Access Port are synchronous to
processor internal clocks.
RESET
Reset (input, asynchronous)
This input places the processor in the Reset mode. This
signal has special hardening against metastable states,
allowing it to be driven with a slow-rise-time signal.
TDI
Test Data Input
(input, synchronous to TCK, pull-up resistor)
ROMCS3–ROMCS0
This input supplies data to the test logic from an external
source. It is sampled on the rising edge of TCK. If it is not
driven, it appears High internally.
ROM Chip Selects, Banks 3–0
(output, synchronous)
A Low level on one of these signals selects the memory
devices in the corresponding ROM bank. ROMCS3 se-
lects devices in ROM Bank 3, and so on. The timing and
access parameters of each bank are individually pro-
grammable.
TDMA
Terminate DMA (input/output, synchronous)
Thissignaliseitheraninputoranoutputascontrolledby
the corresponding DMA Control Register. As an input,
this signal can be asserted during an external DMA
transfer (non-fly-by) to terminate the transfer after the
current access. The TDMA input is ignored during fly-by
transfers. As an output, this signal is asserted to indicate
the final transfer of a sequence.
ROMOE
ROM Output Enable (output, synchronous)
This signal enables the selected ROM Bank to drive the
ID bus. It is used to prevent bus contention when switch-
ing between different ROM banks or switching between
a ROM bank and another device or DRAM bank.
TDO
Test Data Output
(three-state output, synchronous to TCK)
RSWE
This output supplies data from the test logic to an exter-
nal destination. It changes on the falling edge of TCK. It
is in the high-impedance state except when scanning is
in progress.
ROM Space Write Enable (output, synchronous)
This signal is used to write an alterable memory in a
ROM bank (such as an SRAM or Flash EPROM).
RXDA
TMS
Receive Data, Port A (input, asynchronous)
This input is used to receive serial data to Serial Port A.
Test Mode Select
(input, synchronous to TCK, pull-up resistor)
This input is used to control the Test Access Port. If it is
not driven, it appears High internally.
14
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
TR/OE
UCLK
Video DRAM Transfer/Output Enable
(output, synchronous)
UART Clock (input)
This is an oscillator input for generating the UART (Seri-
al Port) clock. To generate the UART clock, the oscillator
frequency may be divided by any amount up to 65,536.
The UART clock operates at 16 times the Serial Port’s
baud rate. As an option, UCLK may be driven with
MEMCLK or INCLK. It can be driven with TTL levels.
This signal is used with video DRAMs to transfer data to
the video shift register. It is also used as an output en-
able in normal video DRAM read cycles. This signal is
supported on the Am29240 and Am29245 microcontrol-
lers only.
TRAP1–TRAP0
VCLK
Trap Requests 1–0
Video Clock (input, asynchronous)
(input, asynchronous, internal pull-ups)
This clock is used to synchronize the transfer of video
data. As an option, VCLK may be driven with MEMCLK
or INCLK. It can be driven with TTL levels. This signal is
supported on the Am29240 and Am29245 microcon-
trollers only.
These inputs generate prioritized trap requests. The
trap caused by TRAP0 has the highest priority. These
trap requests are disabled by the DA bit of the Current
Processor Status Register. These signals have special
hardening against metastable states, allowing them to
be driven with slow-transition-time signals.
VDAT
Video Data (input/output, synchronous to VCLK)
TRIST
This is serial data to or from the video device. This signal
is supported on the Am29240 and Am29245 microcon-
trollers only.
Three-State Control
(input, asynchronous, pull-up resistor)
This input is asserted to force all processor outputs into
the high-impedance state. This signal is tied High
through an internal pull-up resistor.
WAIT
Add Wait States
(input, synchronous, internal pull-up)
Note: TRIST does not control the MEMCLK pin. To
three-state MEMCLK, the user must drive MEMDRV
Low.
External accesses are normally timed by the processor.
However, the WAIT signal may be asserted during a
PIA, ROM, or DMA access to extend the access
indefinitely.
TRST
Test Reset Input
(input, asynchronous, pull-up resistor)
WARN
Warn (input, asynchronous, edge-sensitive,
internal pull-up)
This input asynchronously resets the Test Access Port.
If TRST is not driven, it appears High internally. TRST
must be tied to RESET, even if the Test Access Port is
not being used.
A High-to-Low transition on this input causes a non-
maskable WARN trap to occur. This trap bypasses the
normaltrapvectorfetchsequence, andisusefulinsitua-
tions where the vector fetch may not work (e.g., when
data memory is faulty). This signal has special harden-
ing against metastable states, allowing it to be driven
with a slow-transition-time signal.
TXDA
Transmit Data, Port A (output, asynchronous)
This output is used to transmit serial data from Serial
Port A.
WE
TXDB
Write Enable (output, synchronous)
Transmit Data, Port B (output, asynchronous)
This signal is used to write the selected DRAM bank.
“Early write” cycles are used so the DRAM data inputs
and outputs can be tied to the common ID Bus.
This output is used to transmit data from Serial Port B.
This signal is supported on the Am29240 and Am29243
microcontrollers only.
15
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAM
196-Pin PQFP
Top Side View
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Am29240 Microcontroller Series
8
7
6
5
4
3
2
1
Note:
Pin 1 marked for orientation.
16
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
PQFP PIN DESIGNATIONS (Pin Number)
Pin No.
1
Pin Name
VCC
Pin No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Pin Name
VCC
Pin No.
99
Pin Name
VCC
Pin No.
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
Pin Name
VCC
2
MEMCLK
MEMDRV
INCLK
ID31
ID30
ID29
ID28
ID27
ID26
ID25
ID24
GND
VCC
Reserved
Reserved
TXDB 3
RXDB 3
DTRA
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Reserved
Reserved
A23
Reserved
PIO12
PIO11
PIO10
PIO9
3
4
5
A22
6
A21
7
RXDA
A20
PIO8
8
UCLK
A19
PIO7
9
DSRA
A18
PIO6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
TXDA
A17
PIO5
ROMCS3
ROMCS2
ROMCS1
ROMCS0
VCC
A16
PIO4
GND
VCC
GND
VCC
A15
PIO3
ID23
ID22
ID21
ID20
ID19
ID18
ID17
ID16
GND
VCC
A14
PIO2
GND
A13
PIO1
BURST
RSWE
ROMOE
RAS3
A12
PIO0
A11
TDO
A10
STAT2
STAT1
STAT0
VDAT 2
PSYNC 2
GND
A9
RAS2
A8
RAS1
GND
VCC
RAS0
CAS3
A7
ID15
ID14
ID13
ID12
ID11
CAS2
A6
VCC
VCC
A5
GREQ
DREQB
DREQA
TDMA
TRAP0
TRAP1
INTR0
INTR1
INTR2
INTR3
GND
GND
A4
CAS1
A3
CAS0
A2
ID10
ID9
TR/OE
WE
A1
A0
ID8
GACK
PIACS5
PIACS4
PIACS3
PIACS2
VCC
GND
VCC
GND
VCC
BOOTW
WAIT
PAUTOFD
PSTROBE
PWE
POE
PACK
PBUSY
GND
VCC
ID7
ID6
ID5
VCC
ID4
GND
WARN
VCLK 2
LSYNC 2
TMS
ID3
PIACS1
PIACS0
PIAWE
PIAOE
R/W
ID2
ID1
ID0
TRST
TCK
GND
VCC
DACKB
DACKA
DACKD 3
DACKC 3
Reserved
GND
PIO15
PIO14
PIO13
DREQD 3
DREQC 3
GND
TDI
IDP3 1, 3
IDP2 1, 3
IDP1 1, 3
IDP0 1, 3
GND
RESET
CNTL1
CNTL0
TRIST
GND
2. Defined as a no-connect on the Am29243 microcontroller.
3. Defined as a no-connect on the Am29245 microcontroller.
Notes: All values are typical and preliminary.
1. Defined as a no-connect on the Am29240 microcontroller.
17
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
PQFP PIN DESIGNATIONS (Pin Name)
Pin Name
A0
Pin No.
129
128
127
126
125
124
123
122
119
118
117
116
115
114
113
112
109
108
107
106
105
104
103
102
132
66
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GREQ
ID0
Pin No.
76
87
98
110
120
130
140
147
159
171
183
196
173
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
25
22
21
20
19
18
17
16
15
12
11
Pin Name
INCLK
INTR0
Pin No.
4
Pin Name
Reserved
RESET
ROMCS0
ROMCS1
ROMCS2
ROMCS3
ROMOE
RSWE
RXDA
RXDB 3
STAT0
STAT1
STAT2
TCK
Pin No.
149
192
63
A1
179
180
181
182
187
2
A2
INTR1
A3
INTR2
62
A4
INTR3
61
A5
LSYNC 2
MEMCLK
MEMDRV
PACK
60
A6
68
A7
3
67
A8
138
134
139
89
56
A9
PAUTOFD
PBUSY
PIACS0
PIACS1
PIACS2
PIACS3
PIACS4
PIACS5
PIAOE
PIAWE
PIO0
54
A10
168
167
166
190
191
176
165
188
79
A11
A12
88
A13
85
A14
ID1
84
TDI
A15
ID2
83
TDMA
TDO
A16
ID3
82
A17
ID4
91
TMS
A18
ID5
90
TR/OE
TRAP0
TRAP1
TRIST
TRST
TXDA
TXDB 3
UCLK
VCC
A19
ID6
164
163
162
161
158
157
156
155
154
153
152
151
150
144
143
142
137
135
170
136
92
177
178
195
189
59
A20
ID7
PIO1
A21
ID8
PIO2
A22
ID9
PIO3
A23
ID10
ID11
ID12
ID13
ID14
ID15
ID16
ID17
ID18
ID19
ID20
ID21
ID22
ID23
ID24
ID25
ID26
ID27
ID28
ID29
ID30
ID31
IDP0 1, 3
IDP1 1, 3
IDP2 1, 3
IDP3 1, 3
PIO4
BOOTW
BURST
CAS0
CAS1
CAS2
CAS3
CNTL0
CNTL1
DACKA
DACKB
DACKC 3
DACKD 3
DREQA
DREQB
DREQC 3
DREQD 3
DSRA
DTRA
GACK
GND
GND
GND
GND
GND
GND
PIO5
53
PIO6
57
78
PIO7
1
77
PIO8
VCC
14
74
PIO9
VCC
24
73
PIO10
VCC
34
194
193
94
PIO11
VCC
44
PIO12
VCC
50
PIO13
VCC
64
93
PIO14
VCC
75
96
PIO15
VCC
86
95
POE
VCC
99
175
174
146
145
58
PSTROBE
PSYNC 2
PWE
VCC
111
121
131
141
148
160
172
184
186
169
133
185
80
VCC
VCC
10
9
R/W
VCC
RAS0
72
VCC
55
8
RAS1
71
VCC
81
7
RAS2
70
VCC
13
6
RAS3
69
VCC
23
5
Reserved
Reserved
Reserved
Reserved
Reserved
51
VCLK 2
VDAT 2
WAIT
WARN
WE
33
48
47
46
45
52
43
97
49
100
101
65
2. Defined as a no-connect on the Am29243 microcontroller.
3. Defined as a no-connect on the Am29245 microcontroller.
Notes: All values are typical and preliminary.
1. Defined as a no-connect on the Am29240 microcontroller.
18
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
Am29240 MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
3
STAT2–STAT0
24
A23–A0
R/W
TRIST
CNTL1–CNTL0
2
RESET
WARN
ROMCS3–ROMCS0
4
4
INTR3–INTR0
2
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
CAS3–CAS0
4
4
BOOTW
WE
TR/OE
PIACS5–PIACS0
6
4
Am29240 Microcontroller
PIAOE
PIAWE
DACKD–DACKA
GACK
4
DREQD–DREQA
GREQ
PBUSY
PACK
POE
PSTROBE
PAUTOFD
PWE
UCLK
RXDB–RXDA
DTRA
2
2
TXDB–TXDA
DSRA
VCLK
LSYNC
TCK
TDI
TDO
TMS
TRST
MEMCLK VDAT PSYNC TDMA PIO15–PIO0 ID31–ID0
16
32
19
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
Am29245 MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
3
STAT2–STAT0
24
A23–A0
R/W
TRIST
CNTL1–CNTL0
2
RESET
WARN
ROMCS3–ROMCS0
4
4
2
INTR3–INTR0
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
CAS3–CAS0
4
4
BOOTW
WE
TR/OE
PIACS5–PIACS0
6
2
PIAOE
PIAWE
Am29245 Microcontroller
DACKB–DACKA
GACK
2
DREQB–DREQA
GREQ
PBUSY
PACK
POE
PSTROBE
PAUTOFD
PWE
UCLK
RXDA
DTRA
TXDA
DSRA
VCLK
LSYNC
TCK
TDI
TDO
TMS
TRST
MEMCLK VDAT PSYNC TDMA PIO15–PIO0 ID31–ID0
16
32
20
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
Am29243 MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
3
STAT2–STAT0
24
A23–A0
R/W
TRIST
CNTL1–CNTL0
2
RESET
WARN
ROMCS3–ROMCS0
4
4
INTR3–INTR0
2
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
CAS3–CAS0
4
4
BOOTW
WE
TR/OE
PIACS5–PIACS0
6
4
Am29243 Microcontroller
PIAOE
PIAWE
DACKD–DACKA
GACK
4
DREQD–DREQA
GREQ
PBUSY
PACK
POE
PSTROBE
PAUTOFD
PWE
UCLK
RXDB–RXDA
DTRA
2
2
TXDB–TXDA
DSRA
TCK
TDI
TDO
TMS
TRST
MEMCLK
TDMA PIO15–PIO0 ID31–ID0
IDP3–IDP0
4
16
32
21
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +125°C
Voltage on any Pin
Commercial (C) Devices
Case Temperature (TC) . . . . . . . . . . . . . . 0°C to +85°C
Supply Voltage (VCC) . . . . . . . . . . . +4.75 V to +5.25 V
with Respect to GND . . . . . . . –0.5 V to VCC +0.5 V
Stresses abovethoselistedunderAbsoluteMaximumRatings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum rat-
ings for extended periods may affect device reliability.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL Operating Ranges
Advance Information
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
–0.5
VCC +0.5
0.8
V
V
V
VILINCLK
VIHINCLK
VOL
INCLK Input Low Voltage
INCLK Input High Voltage
Note 1
Note 1
VCC –0.8
VCC +0.5
Output Low Voltage for
All Outputs except MEMCLK
IOL = 3.2 mA
0.45
V
V
Output High Voltage for
All Outputs except MEMCLK
VOH
IOH = –400 µA
2.4
0.45 V ≤ VIN ≤ VCC –0.45 V
Note 2
±10 or
+10/–200
ILI
Input Leakage Current
Output Leakage Current
µA
µA
ILO
0.45 V ≤ VOUT ≤ VCC –0.45 V
±10
14
Operating Power-Supply Current with VCC = 5.25 V, Outputs Floating;
ICCOP
mA/MHz
respect to MEMCLK
Holding RESET active at 25 MHz
VOLC
MEMCLK Output Low Voltage
MEMCLK Output High Voltage
MEMCLK GND Short Circuit Current
MEMCLK VCC Short Circuit Current
IOLC = 20 mA
0.6
V
V
VOHC
IOHC = –20 mA
VCC –0.6
100
IOSGND
VCC = 5.0 V
mA
mA
IOSVCC
Notes:
VCC = 5.0 V
100
1. INCLK is driven with CMOS input levels.
2. The Low input leakage current for the inputs CNTL1–CNTL0, INTR3–INTR0, TRAP1–TRAP0, DREQD–DREQA, TCK, TDI,
TRST, TMS, GREQ, WARN, MEMDRV, WAIT, and TRIST is –200 µA. These pins have internal pull-up resistors.
CAPACITANCE
Advance Information
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
CIN
Input Capacitance
15
pF
CINCLK
CMEMCLK
COUT
INCLK Input Capacitance
MEMCLK Capacitance
Output Capacitance
15
20
20
20
pF
pF
pF
pF
fC = 10 MHz
CI/O
I/O Pin Capacitance
Note: Limits guaranteed by characterization.
22
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges
Advance Information
16 MHz
20 MHz
25 MHz
No.
Parameter Description
Test Conditions 1, 8
Min
Max
Min
Max
Min
Max Unit
1
2
3
4
5
6
INCLK Period (=0.5T)
INCLK High Time
Notes 9, 10, 11
Note 9
30
12
12
1
1
1
1
7
25
10
10
1
1
1
1
7
20
8
1
1
1
7
ns
ns
ns
ns
ns
ns
INCLK Low Time
Note 9
8
INCLK Rise Time
Note 9
1
INCLK Fall Time
Note 9
1
7
1
7
1
7
MEMCLK Delay from INCLK
MEMCLK Output
Notes 3, 8
1
7
1
7
1
7
0.5T–3
0.5T–3
0.5T–3
0.5T–3
0.5T–3
0.5T–3
8
9
MEMCLK High Time
MEMCLK Low Time
MEMCLK Output
Notes 3, 8
1
1
1
1
1
1
ns
ns
MEMCLK Output
Notes 3, 8
10
11
MEMCLK Rise Time
MEMCLK Fall Time
Notes 3, 8
Notes 3, 8
1
1
4
4
1
1
4
4
1
1
4
4
ns
ns
Synchronous Output Valid Delay from MEMCLK Rising Edge
12a
PIO15–PIO0, STAT2–STAT0,
and PIACS5–PIACS0
MEMCLK Output
Note 1A
1
1
1
13
17/11
12
1
1
1
12
15/9
11
1
1
1
11
13/7
10
ns
ns
ns
CAS3–CAS0 Rising Edge/
CAS3–CAS0 Falling Edge
MEMCLK Output
Notes 1B, 4B
All others
MEMCLK Output
Note 1B
Synchronous Output Valid from MEMCLK Falling Edge
12b
PIO15–PIO0, STAT2–STAT0,
and PIACS5–PIACS0
MEMCLK Output
Note 1A
1
1
1
1
12
11
11
12
1
1
1
1
11
9
1
1
1
1
10
7
ns
ns
ns
ns
MEMCLK Output
Notes 1B, 4B
CAS3–CAS0 Falling Edge
All others
MEMCLK Output
Note 1B
10
11
9
13
14
Synchronous Output Disable
Delay from MEMCLK Rising
Edge
MEMCLK Output
10
Synchronous Input Setup Time to MEMCLK Rising Edge
ID31–ID0 and IDP3–IDP0 for
DRAM access
Parity Enabled
Note 4A
18
10
10
16
8
15
7
ns
ID31–ID0 for DRAM access
Parity Disabled
Note 4A
ns
ns
ns
All others
8
7
15
Available CAS Access Time
Notes 4A, 4B
Note 4A
24
23
18
(TCAS–TSetup
)
16a
16b
Synchronous Input Hold Time to
MEMCLK Rising Edge
0
3
0
3
0
3
ns
ns
Synchronous Input Hold Time to
CAS Rising Edge
Note 4B
23
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued)
Advance Information
16 MHz
20 MHz
25 MHz
No.
Parameter Description
Test Conditions 1, 8
Min
Max
Min
Max
Min
Max
Unit
Asynchronous Input Pulse Width
LSYNC and PSYNC
All others
17
Note 5
4T
30
25
10
8
Note 5
Note 5
4T
25
20
8
4T
20
15
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UCLK Period
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 6
18
19
20
21
22
VCLK Period
UCLK High Time
VCLK High Time
UCLK Low Time
VCLK Low Time
UCLK Rise time
VCLK Rise time
UCLK Fall Time
VCLK Fall Time
6
4
10
8
8
6
6
4
0
3
3
0
3
3
0
3
3
0
0
0
0
3
0
3
0
3
0
3
0
3
0
3
23
24
Synchronous Output Valid Delay
from VCLK Rise and Fall
1
16
1
14
1
14
Input Setup Time to VCLK Rise
and Fall
Notes 6, 7
Notes 6, 7
10
0
9
0
9
0
ns
ns
25
Input Hold Time to VCLK Rise
and Fall
Notes:
1. All outputs driving 80 pF, measured at VOL = 1.5 V and VOH = 1.5 V. For higher capacitance:
A. Add 1-ns output delay per 15 pF loading up to 150-pF total. The minimum delay from PIAOE to PIACSx is 0 ns if the
capacitance loading on PIACSx is equal to or higher than the capacitance loading on PIAOE.
B. Add 1-ns output delay per 25 pF loading up to 300-pF total.
2. VCLK and UCLK can be driven with TTL inputs. UCLK must be tied High if it is unused.
3. MEMCLK can drive an external load of 100 pF.
4. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of MEMCLK for all non-DRAM accesses, simple DRAM accesses,
and the first access of a DRAM page-mode access. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of CASx for all
DRAM page-mode accesses, except the first access of a DRAM page-mode access. (See Figures 1–4 on pages 26–27.)
A. Applies to ID31–ID0 and IDP3–IDP0 for simple DRAM accesses and the first access of a DRAM page-mode access.
B. Applies to ID31–ID0 and IDP3–IDP0 for DRAM page-mode accesses, except the first access of a DRAM page-mode access.
When ID31–ID0 and IDP3–IDP0 are sampled on CASx, there is no additional setup time required for ID31–ID0 and
IDP3–IDP0 when the parity is enabled.
5. LSYNC and PSYNC minimum width is two bit-times. A bit-time is one period of the internal video clock, which is determined by
the CLKDIV field in the Video Control Register and VCLK.
6. Active VCLK edge depends on the CLKI bit in the Video Control Register.
7. LSYNC and PSYNC can be treated as synchronous signals by meeting the setup and hold times, though the synchronization
delay still applies.
8. The MEMCLK as an input option (i.e., MEMDRV pin is connected to GND) is not supported.
9. INCLK is driven with CMOS input levels.
10. When the user sets the TBO bit, the INCLK period must not be greater than the operating frequency of the part.
11. For the 25 MHz part, INCLK = 20 ns minimum (50 MHz maximum) when turbo mode is disabled. When turbo mode is enabled,
INCLK = 30 ns minimum (33 MHz maximum).
24
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
SWITCHING WAVEFORMS
1
3
5
2
4
V
CC – 0.5 V
INCLK
2.5 V
0.5 V
6
8
9
10
11
VCC –1.0 V
MEMCLK
1.5 V
0.8 V
12a
12b
13
SYNCHRONOUS
OUTPUTS
1.5 V
14
16a
SYNCHRONOUS
INPUTS
1.5 V
1.5 V
Note: Applies to ID31–ID0 and
IDP3–IDP0 for DRAM page-mode
accesses, except the first access
of a DRAM page-mode access.
See Note 4 on page 24.
15
16b
CASx
17
ASYNCHRONOUS
INPUTS
1.5 V
1.5 V
18
19
20
22
21
2.0 V
1.5 V
0.8 V
UCLK, VCLK
23
VCLK-RELATIVE
OUTPUTS
Note: Video Timing may be
relative to VCLK falling edge
if CLK = 1.
25
24
VCLK-RELATIVE
INPUTS
1.5 V
1.5 V
Note:
During AC testing, all inputs are driven at V = 0.4 V, V = 2.4 V.
IL
IH
25
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
SWITCHING WAVEFORMS (continued)
1.5 V
MEMCLK
A14–A1
R/W
Row Address
Column Address
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
16a
14
1.5 V
ID31–ID0
IDP3–IDP0
1.5 V
Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK.
Figure 1. Simple 3/1 DRAM Read Cycle, Am29240 Microcontroller Series
MEMCLK
A14–A1
Row Address
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Figure 2. Simple 3/1 DRAM Write Cycle, Am29240 Microcontroller Series
Am29240 Microcontroller Series
26
A D V A N C E I N F O R M A T I O N
AMD
SWITCHING WAVEFORMS (continued)
1.5 V
MEMCLK
A14–A1
+2/4
+4/8
+6/12
Row Address
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
1.5 V
1.5 V
1.5 V
WE
TR/OE
14
16a
15
16b
15
16b
15
16b
ID31–ID0
IDP3–IDP0
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK.
Figure 3. 3/1 DRAM Page-Mode Read, Am29240 Microcontroller Series
MEMCLK
+2/4
+4/8
+6/12
Row Address
Column Address
A14–A1
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Data
Data
Data
Figure 4. 3/1 DRAM Page-Mode Write, Am29240 Microcontroller Series
Am29240 Microcontroller Series
27
AMD
A D V A N C E I N F O R M A T I O N
SWITCHING TEST CIRCUIT
VL
IOL = 3.2 mA
Am29240 Microcontroller
Pin Under Test
CL
V
VREF = 1.5 V
IOH = 400 µA
VH
THERMAL CHARACTERISTICS
The Am29240 microcontroller series is specified for op-
eration with case temperature ranges for a commercial
temperature device. Case temperature is measured at
the top center of the PQFP package as shown in Figure 5.
The various temperatures and thermal resistances can
be determined using the equations shown in Figure 6
along with information given in Table 2. (The variable P
is power in watts.)
θJA = θJC + θCA
θJA
θCA
P = ICCOP freq VCC
TJ = TC + P θJC
TJ = TA + P θJA
TC = TJ – P θJC
TC = TA + P θCA
TA = TJ – P θJA
TA = TC – P θCA
TC
θJC
θJA = θJC + θCA
Figure 5. Thermal Resistance — °C/Watt
Figure 6. Thermal Characteristics Equations
Table 2. Thermal Characteristics (°C/Watt) Surface Mounted
Parameter
°C/Watt
38
8
θJA
θJC
θCA
Junction-to-Ambient
Junction-to-Case
Case-to-Ambient
30
28
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
PHYSICAL DIMENSIONS
PQB 196, Trimmed and Formed
Plastic Quad Flat Pack (measured in inches)
1.495
1.505
1.475
1.485
1.345
1.355
Pin 196
Pin 1
Pin
147
Pin 1 ID
1.345
1.355
1.475
1.485
–A–
–B–
1.495
1.505
Pin 49
–D–
Pin 98
0.008
0.012
Top View
See Detail
X
0.025 Basic
0.160
0.180
0.130
0.150
S
Seating
Plane
–C–
S
1.20 Ref.
0.020
0.040
Side View
Note:
Not to scale. For reference only.
29
Am29240 Microcontroller Series
AMD
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS (continued)
PQB 196, Trimmed and Formed
Plastic Quad Flat Pack (measured in inches)
0.008
0.012
0.006
0.008
Section S–S
7° Typ.
0.010 Min
Flat Shoulder
0.045 x 45° Chamfer
0° Min
0.015
Pin 147
0.008
Gage Plane
0.036
0.010
7° Typ.
0.046
0°≤0≤8°
0.065 Ref.
Detail X
Note:
Not to scale. For reference only.
30
Am29240 Microcontroller Series
A D V A N C E I N F O R M A T I O N
AMD
PHYSICAL DIMENSIONS (continued)
Solder Land Recommendations—196-Lead PQFP
1.500
1.500
0.075
0.025
0.012
Note:
Not to scale. For reference only.
Trademarks
Copyright 1995 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, Am29000, MiniMON29K, and Fusion29K are registered trademarks; 29K, AMD Facts-On-Demand, Am29005, Am29030,
Am29035, Am29040, Am29050, Am29200, Am29202, Am29205, Am29240, Am29243, Am29245, Traceable Cache, Scalable Clocking, and
XRAY29K are trademarks of Advanced Micro Devices, Inc.
High C is a registered trademark of MetaWare, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
31
Am29240 Microcontroller Series
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