AM29F080B-90FE [ETC]
x8 Flash EEPROM ; X8闪存EEPROM\n
| 型号： | AM29F080B-90FE |
| 厂家： | 
ETC |
| 描述： | x8 Flash EEPROM
|
| 文件： | 总38页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29F080B
8 Megabit (1 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10%, single power supply operation
■ Minimum 1,000,000 program/erase cycles per
sector guaranteed
— Minimizes system level power requirements
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package options
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F080 device
■ High performance
— 40-pin TSOP
— Access times as fast as 55 ns
— 44-pin SO
■ Low power consumption
■ Compatible with JEDEC standards
— 25 mA typical active read current
— 30 mA typical program/erase current
— Pinout and software compatible with
single-power-supply Flash standard
— 1 µA typical standby current (standard access
— Superior inadvertent write protection
■ Data# Polling and toggle bits
time to active mode)
■ Flexible sector architecture
— 16 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Provides a software method of detecting program
or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
— Group sector protection:
program or erase cycle completion
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
■ Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■ Hardware reset pin (RESET#)
■ Embedded Algorithms
— Resets internal state machine to the read mode
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ Command sequence optimized for mass storage
— Specific addresses not required for unlock cycles
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
Publication# 21503 Rev: G Amendment/+1
Issue Date: January 3, 2002
1
GENERAL DESCRIPTION
The Am29F080B is an 8 Mbit, 5.0 volt-only Flash mem-
ory organized as 1,048,576 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F080B is offered in
40-pin TSOP and 44-pin SO packages. This device is
designed to be programmed in-system with the standard
system 5.0 volt VCC supply. A 12.0 volt VPP is not re-
quired for program or erase operations. The device can
also be programmed in standard EPROM programmers.
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and
benefits of the Am29F080, which was manufactured
using 0.5 µm process technology.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 55, 70, 90,
120, and 150 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE#), write
enable (WE#), and output enable (OE#) controls.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
2
Am29F080B
January 3, 2002
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8
Table 1. Am29F080B Device Bus Operations ..................................8
Requirements for Reading Array Data .....................................8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 8
Standby Mode ..........................................................................9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode ................................................................ 9
Table 1. Am29F080B Sector Address Table ...................................10
Autoselect Mode ..................................................................... 10
Table 2. Am29F080B Autoselect Codes (High Voltage Method) ....10
Sector Group Protection/Unprotection .................................... 11
Table 3. Sector Group Addresses ...................................................11
Temporary Sector Group Unprotect ....................................... 11
Figure 1. Temporary Sector Group Unprotect Operation ................11
Hardware Data Protection ......................................................12
Low VCC Write Inhibit ......................................................................12
Write Pulse “Glitch” Protection ........................................................12
Logical Inhibit ..................................................................................12
Power-Up Write Inhibit ....................................................................12
Command Definitions . . . . . . . . . . . . . . . . . . . . . .12
Reading Array Data ................................................................ 12
Reset Command ..................................................................... 12
Autoselect Command Sequence ............................................ 12
Byte Program Command Sequence ....................................... 13
Figure 2. Program Operation ..........................................................13
Chip Erase Command Sequence ........................................... 13
Sector Erase Command Sequence ........................................ 14
Erase Suspend/Erase Resume Commands ........................... 14
Figure 3. Erase Operation ...............................................................15
Command Definitions ............................................................. 16
Table 4. Am29F080B Command Definitions ..................................16
Write Operation Status . . . . . . . . . . . . . . . . . . . . .17
DQ7: Data# Polling ................................................................. 17
Figure 4. Data# Polling Algorithm ...................................................17
RY/BY#: Ready/Busy# ........................................................... 18
DQ6: Toggle Bit I .................................................................... 18
DQ2: Toggle Bit II ................................................................... 18
Reading Toggle Bits DQ6/DQ2 .............................................. 18
DQ5: Exceeded Timing Limits ................................................ 19
DQ3: Sector Erase Timer ....................................................... 19
Figure 5. Toggle Bit Algorithm .........................................................19
Table 5. Write Operation Status ......................................................20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 21
Figure 6. Maximum Negative Overshoot Waveform ...................... 21
Figure 7. Maximum Negative Overshoot Waveform ...................... 21
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
TTL/NMOS Compatible ..........................................................22
CMOS Compatible ..................................................................22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Test Setup ....................................................................... 23
Table 2. Test Specifications ........................................................... 23
Key to Switching Waveforms . . . . . . . . . . . . . . . 23
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
Read-only Operations .............................................................24
Figure 9. Read Operation Timings ................................................. 24
Hardware Reset (RESET#) .................................................... 25
Figure 10. RESET# Timings .......................................................... 25
Erase and Program Operations .............................................. 26
Figure 11. Program Operation Timings .......................................... 27
Figure 12. Chip/Sector Erase Operation Timings .......................... 28
Figure 13. Data# Polling Timings (During Embedded Algorithms) . 29
Figure 14. Toggle Bit Timings (During Embedded Algorithms) ...... 29
Figure 15. DQ2 vs. DQ6 ................................................................. 30
Temporary Sector Unprotect .................................................. 30
Figure 16. Temporary Sector Group Unprotect Timing Diagram ... 30
Erase and Program Operations .............................................. 31
Alternate CE# Controlled Writes .................................................... 31
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 32
Erase and Programming Performance . . . . . . 33
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 33
TSOP and SO Pin Capacitance . . . . . . . . . . . . . 33
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 34
SO 044—44-Pin Small Outline Package ................................ 34
TS 040—40-Pin Standard Thin Small Outline Package ......... 35
TSR040—40-Pin Reverse Thin Small Outline Package .........36
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision A (July 1997) ............................................................ 37
Revision B (January 1998) ..................................................... 37
Revision C (January 1998) ..................................................... 37
Revision D (May 1998) ........................................................... 37
Revision E (January 1999) ..................................................... 37
Revision E+1 (March 23, 1999) .............................................. 37
Revision E+2 (April 9, 1999) ................................................... 37
Revision F (November 15, 1999) ............................................ 37
Revision F+1 (May 18, 2000) ................................................. 37
Revision G (December 4, 2000) ............................................. 37
Revision G+1 (January 3, 2002) ............................................. 38
January 3, 2002
Am29F080B
3
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F080B
V
CC = 5.0 V ± 5%
-55
Speed Option
VCC = 5.0 V ± 10%
-70
70
70
30
-90
-120
120
120
50
-150
150
150
75
Max Access Time, ns (tACC
)
55
55
30
90
90
40
Max CE# Access, ns (tCE
)
Max OE# Access, ns (tOE
)
Note: See the “AC Characteristics” section for more information.
BLOCK DIAGRAM
DQ0–DQ7
Sector Switches
VCC
VSS
Erase Voltage
Generator
Input/Output
Buffers
RY/BY#
RESET#
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
A0–A19
4
Am29F080B
January 3, 2002
CONNECTION DIAGRAMS
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VSS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Standard TSOP
RESET#
A11
A10
A9
VSS
DQ3
DQ2
DQ1
DQ0
A0
A8
A7
A6
A5
A4
A1
A2
A3
NC
NC
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
RESET#
A11
A10
A9
A8
A7
A6
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
40-Pin Reverse TSOP
A5
A4
NC
RESET#
A11
A10
A9
1
2
3
4
5
6
7
8
9
44 VCC
43 CE#
42 A12
41 A13
40 A14
39 A15
38 A16
37 A17
36 A18
35 A19
34 NC
A8
A7
A6
A5
A4 10
NC 11
NC 12
A3 13
SO
33 NC
32 NC
31 NC
A2 14
A1 15
30 WE#
29 OE#
28 RY/BY#
27 DQ7
26 DQ6
25 DQ5
24 DQ4
23 VCC
A0 16
DQ0 17
DQ1 18
DQ2 19
DQ3 20
VSS 21
VSS 22
January 3, 2002
Am29F080B
5
PIN CONFIGURATION
LOGIC SYMBOL
A0–A19
=
20 Addresses
20
DQ0–DQ7 = 8 Data Inputs/Outputs
A0–A19
8
CE#
=
=
=
=
=
=
Chip Enable
DQ0–DQ7
WE#
Write Enable
OE#
Output Enable
CE#
OE#
RESET#
RY/BY#
VCC
Hardware Reset Pin, Active Low
Ready/Busy Output
+5.0 V single power supply
WE#
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
RESET#
RY/BY#
VSS
NC
=
=
Device Ground
Pin Not Connected Internally
6
Am29F080B
January 3, 2002
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29F080B
-55
E
I
TEMPERATURE RANGE
C
I
=
=
=
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Extended (–55°C to +125°C)
E
PACKAGE TYPE
E
F
S
=
=
=
40-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 040)
40-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR040)
44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F080B
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
Valid Combinations
Valid Combinations
VCC Voltage
Valid Combinations list configurations planned to be support-
ed in volume for this device. Consult the local AMD sales of-
fice to confirm availability of specific valid combinations and
to check on newly released combinations.
AM29F080B-55
AM29F080B-70
EC, EI,
FC, FI,
SC, SI
5.0 V ± 5%
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
AM29F080B-90
5.0 V ± 10%
AM29F080B-120
AM29F080B-150
January 3, 2002
Am29F080B
7
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F080B Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
A0–A19
DQ0–DQ7
DOUT
Read
L
L
X
H
AIN
AIN
X
Write
L
H
X
X
H
X
X
L
X
X
H
X
X
H
DIN
TTL Standby
CMOS Standby
Output Disable
Hardware Reset
H
H
CC ± 0.3 V
H
HIGH Z
HIGH Z
HIGH Z
HIGH Z
X
V
CC ± 0.3 V
V
X
L
X
X
X
VIL
X
Temporary Sector Group Unprotect (See Note)
VID
AIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, DOUT = Data Out, DIN = Data In, AIN = Address In, X = Don’t Care. See DC Charac-
teristics for voltage levels.
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
set. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
table represents the active current specification for
reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
8
Am29F080B
January 3, 2002
Status” for more information, and to each AC Charac-
teristics section in the appropriate data sheet for timing
diagrams.
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS
0.5 V, the device enters the CMOS standby mode.
±
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
RESET#: Hardware Reset Pin
Output Disable Mode
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
January 3, 2002
Am29F080B
9
Table 1. Am29F080B Sector Address Table
Sector
SA0
A19
0
A18
0
A17
0
A16
0
Address Range
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
SA1
0
0
0
1
SA2
0
0
1
0
SA3
0
0
1
1
SA4
0
1
0
0
SA5
0
1
0
1
SA6
0
1
1
0
SA7
0
1
1
1
SA8
1
0
0
0
SA9
1
0
0
1
SA10
SA11
SA12
SA13
SA14
SA15
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: All sectors are 64 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In ad-
dition, when verifying sector protection, the sector ad-
Table 2. Am29F080B Autoselect Codes (High Voltage Method)
A19 A11
to to
A12 A10
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
CE#
L
OE#
WE#
H
A9
VID
VID
A6
L
A1
L
A0
L
Manufacturer ID: AMD
Device ID: Am29F080B
L
L
X
X
X
X
X
X
X
X
01h
D5h
L
H
L
L
H
01h (protected)
Sector Group
Protection Verification
L
L
H
SGA
X
VID
X
L
X
H
L
00h
(unprotected)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SGA = Sector Group Address, X = Don’t care.
Note:The system may also autoselect information in-system via the command register. See Table 4.
10
Am29F080B
January 3, 2002
control pins. Details on this method are provided in a
supplement, listed in publication number 19945. Con-
tact an AMD representative to obtain a copy of the ap-
propriate document.
Sector Group Protection/Unprotection
The hardware group sector protection feature dis-
ables both program and erase operations in any sec-
tor group. Each sector group consists of two adjacent
sectors. Table 3 shows how the sectors are grouped,
and the address range that each sector group con-
tains. The hardware sector group unprotection fea-
ture re-enables both program and erase operations
in previously protected sector groups.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sector groups at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Sector group protection/unprotection must be imple-
mented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the
It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.
Table 3. Sector Group Addresses
Sector
Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
A19
A18
A17
Sectors
SA0–SA1
SA2–SA3
SA4–SA5
SA6–SA7
SA8–SA9
SA10–SA11
SA12–SA13
SA14–SA15
START
0
0
0
0
0
1
RESET# = VID
(Note 1)
0
1
0
0
1
1
1
0
0
Perform Erase or
Program Operations
1
0
1
1
1
0
1
1
1
RESET# = VIH
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated
by setting the RESET# pin to VID. During this mode,
formerly protected sector groups can be programmed
or erased by selecting the sector group addresses.
Once VID is removed from the RESET# pin, all the
previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram
shows the timing waveforms, for this feature.
Temporary Sector Group
Unprotect
Completed (Note 2)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group Unprotect
Operation
January 3, 2002
Am29F080B
11
proper signals to the control pins to prevent uninten-
Hardware Data Protection
tional writes when VCC is greater than VLKO
.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
12
Am29F080B
January 3, 2002
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
START
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
Write Program
Command Sequence
Data Poll
from System
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Address tables for valid sector addresses.
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
No
Increment Address
Last Address?
Yes
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
Programming
Completed
Note:See the appropriate Command Definitions table for pro-
gram command sequence.
Figure 2. Program Operation
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
January 3, 2002
Am29F080B
13
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#.
See “Write Operation Status” for information on
these status bits. When the Embedded Erase algo-
rithm is complete, the device returns to reading
array data and addresses are no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. The Command Definitions table shows the
address and data requirements for the sector erase
command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the ris-
ing edge of the final WE# pulse in the command se-
quence.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
14
Am29F080B
January 3, 2002
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
START
Write Erase
Command Sequence
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
January 3, 2002
Am29F080B
15
Command Definitions
Table 4. Am29F080B Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Addr
Second
Third
Fourth
Fifth
Sixth
Data
RD
F0
Addr
Data
Addr
Data Addr Data Addr Data Addr Data
Cycles
Read (Note 3)
Reset (Note 4)
1
1
RA
XXX
Autoselect
Manufacturer ID
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
Autoselect
Device ID
D5
00
Autoselect
Sector Group
Protect Verify
(Note 5)
SGA
X02
4
555
AA
2AA
55
555
90
01
Byte Program
Chip Erase
4
6
6
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
555
555
PD
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend
(Note 6)
1
1
XXX
XXX
B0
30
Erase Resume
(Note 7)
Legend:
RA = Address of the memory location to be read.
PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.
RD = Data read from location RA during read operation.
SA = Address of the sector to be erased. Address bits A19–
A16 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or CE#
pulse.
SGA = Address of the sector group to be verified.
Notes:
1. All values are in hexadecimal.
6. Read and program functions in non-erasing sectors are
allowed in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
2. See Table 1 for descriptions of bus operations.
3. No unlock or command cycles required when device is in
read mode.
7. The Erase Resume command is valid only during the
Erase Suspend mode.
4. The Reset command is required to return to the read
mode when the device is in the autoselect mode or if DQ5
goes high.
8. Unless otherwise noted, address bits A19–A11 are don’t
care.
5. The data is 00h for an unprotected sector group and 01h
for a protected sector group. The complete bus address
in the fourth cycle is composed of the sector group
address (A19–A17), A1 = 1, and A0 = 0.
16
Am29F080B
January 3, 2002
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 5 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the ris-
ing edge of the final WE# pulse in the program or
erase command sequence.
Addr = VA
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Figure 4. Data# Polling Algorithm
January 3, 2002
Am29F080B
17
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC
.
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 5 shows the outputs for RY/BY#. The timing dia-
grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs
for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle
bit after the first read. After the second read, the sys-
tem would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
18
Am29F080B
January 3, 2002
the system must write the reset command to return to
reading array data.
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 5 shows the outputs for DQ3.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
START
Read DQ7–DQ0
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Read DQ7–DQ0
Note 1
No
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
(Notes
1, 2)
Read DQ7–DQ0
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Se-
quence” section.
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 5. Toggle Bit Algorithm
January 3, 2002
Am29F080B
19
Table 5. Write Operation Status
DQ7
DQ5
DQ2
RY/BY#
Operation
(Note 1)
DQ6
(Note 2)
DQ3
N/A
1
(Note 1)
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
20
Am29F080B
January 3, 2002
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
20 ns
20 ns
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, RESET# (Note 2). . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . .–2.0 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
20 ns
Notes:
Figure 6. Maximum Negative
Overshoot Waveform
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on output and I/O pins is VCC + 0.5 V. During
voltage transitions, outputs may overshoot to VCC + 2.0 V
for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V. During voltage transitions, A9, OE#, RESET# pins
may overshoot VSS to –2.0 V for periods of up to 20 ns.
See Figure 6. Maximum DC input voltage on A9, OE#,
and RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.
20 ns
VCC
+2.0 V
VCC
+0.5 V
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
2.0 V
20 ns
20 ns
Stresses greater than those listed in this section may cause
permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure of the device to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 7. Maximum Negative
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
V
Supply Voltages
CC
VCC for ± 5% devices. . . . . . . . . . .+4.75 V to +5.25 V
VCC for± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
January 3, 2002
Am29F080B
21
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max, A9 = 12.5 V
VOUT = VSS to VCC, VCC = VCC Max
CE# = VIL, OE# = VIH
Min
Typ
Max
±1.0
50
Unit
µA
ILI
Input Load Current
ILIT
A9 Input Load Current
Output Leakage Current
VCC Read Current (Notes 1, 2)
µA
ILO
±1.0
40
µA
ICC1
ICC2
25
30
mA
mA
VCC Write Current (Notes 2, 3, 4) CE# = VIL, OE# = VIH
40
VCC Standby Current
ICC3
ICC4
CE# = VIH, RESET# = VIH
(CE# Controlled) (Notes 2, 5)
0.4
0.4
1.0
1.0
mA
mA
VCC Standby Current
RESET# = VIL
(RESET# Controlled) (Notes 2, 5)
VIL
Input Low Level
Input High Level
–0.5
0.8
V
V
VIH
2.0
VCC + 0.5
Voltage for Autoselect and Sector
Protect
VID
VCC = 5.0 V
11.5
12.5
0.45
V
VOL
VOH
Output Low Voltage
Output High Level
IOL = 12 mA, VCC = VCC Min
V
V
V
IOH = –2.5 mA VCC = VCC Min
2.4
3.2
VLKO
Low VCC Lock-out Voltage
4.2
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max, A9 = 12.5 V
VOUT = VSS to VCC, VCC = VCC Max
CE# = VIL, OE# = VIH
Min
Typ
Max
±1.0
50
Unit
µA
ILI
Input Load Current
ILIT
A9 Input Load Current
Output Leakage Current
VCC Read Current (Notes 1, 2)
µA
ILO
±1.0
40
µA
ICC1
ICC2
25
30
mA
mA
VCC Write Current (Notes 2, 3, 4) CE# = VIL, OE# = VIH
40
VCC Standby Current (CE#
Controlled) (Notes 2, 5)
CE# = VCC ± 0.5 V,
RESET# = VCC ± 0.5 V
ICC3
ICC4
1
1
5
5
µA
µA
VCC Standby Current (RESET#
Controlled) (Notes 2, 5)
RESET# = VSS ± 0.5 V
VIL
Input Low Level
Input High Level
–0.5
0.8
V
V
VIH
0.7x VCC
VCC + 0.3
Voltage for Autoselect
and Sector Protect
VID
V
CC = 5.0 V
11.5
12.5
0.45
V
VOL
VOH1
VOH2
VLKO
Output Low Voltage
IOL = 12 mA, VCC = VCC Min
OH = –2.5 mA, VCC = VCC Min
IOH = –100 µA, VCC = VCC Min
V
V
V
V
I
0.85 VCC
VCC – 0.4
3.2
Output High Voltage
Low VCC Lock-out Voltage
4.2
Notes for DC Characteristics (both tables):
1. The ICC current listed includes is typically less than 1 mA/MHz, with OE# at VIH
2. Maximum ICC specifications are tested with VCC = VCCmax
.
.
3. ICC active while Embedded Program or Embedded Erase algorithm is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = ICC4 = 20 µA max at extended temperatures (> +85°C).
22
Am29F080B
January 3, 2002
TEST CONDITIONS
Table 2. Test Specifications
5.0 V
All
Test Condition
Output Load
-55
others
Unit
2.7 kΩ
Device
Under
Test
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
5
100
20
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
ns
V
0.0–3.0 0.45–2.4
Input timing measurement
reference levels
1.5
1.5
0.8, 2.0
0.8, 2.0
V
V
Output timing measurement
reference levels
Note:Diodes are IN3064 or equivalent
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
January 3, 2002
Am29F080B
23
AC CHARACTERISTICS
Read-only Operations
Parameter
Symbol
Speed Options
JEDEC Std.
Parameter Description
Test Setup
-55
-70
-90
-120 -150 Unit
tAVAV tRC Read Cycle Time (Note 1)
Min
55
70
90
120
150
ns
CE# = VIL
OE# = VIL
tAVQV
tACC Address to Output Delay
Max
55
70
90
120
150
ns
tELQV
tGLQV
tCE Chip Enable to Output Delay
tOE Output Enable to Output Delay
OE# = VIL
Max
Max
Min
55
30
70
30
90
40
0
120
50
150
55
ns
ns
ns
Read
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
Data# Polling
Min
10
ns
tEHQZ
tGHQZ
tDF Chip Enable to Output High Z
tDF Output Enable to Output High Z
Max
Max
20
20
20
20
20
20
30
30
35
35
ns
ns
Output Hold Time From Addresses CE# or
OE# Whichever Occurs First
tAXQX
tOH
Min
0
ns
µs
RESET# Pin Low to Read Mode
(Note 1)
tReady
Max
20
Notes:
1. Not 100% tested.
2. Refer to Figure 8 and Table 2 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 9. Read Operation Timings
24
Am29F080B
January 3, 2002
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
tREADY
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RESET# High Time Before Read (See Note)
tRPD RESET# Low to Standby Mode
tRB RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 10. RESET# Timings
January 3, 2002
Am29F080B
25
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Parameter Description
Write Cycle Time (Note 1)
-55
-70
-90
-120
-150
Unit
ns
Min
Min
Min
Min
Min
Min
55
70
90
120
150
tAVWL
tWLAX
tDVWH
tWHDX
Address Setup Time
Address Hold Time
Data Setup Time
0
ns
tAH
45
25
45
30
45
45
50
50
50
50
ns
tDS
ns
tDH
Data Hold Time
0
0
ns
tOES
Output Enable Setup Time
ns
Read Recover Time Before Write
(OE# high to WE# low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tCS
tCH
tWP
tWPH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
Min
0
0
ns
ns
ns
ns
µs
sec
µs
ns
CE# Hold Time
tWLWH
tWHWL
tWHWH1
tWHWH2
Write Pulse Width
Write Pulse Width High
30
35
45
50
50
20
7
tWHWH1 Byte Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
1
tVCS
VCC Set Up Time (Note 1)
WE# to RY/BY# Valid
50
tBUSY
30
30
40
50
60
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
26
Am29F080B
January 3, 2002
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note:PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 11. Program Operation Timings
January 3, 2002
Am29F080B
27
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note:
SA = Sector Address. VA = Valid Address for reading status data.
Figure 12. Chip/Sector Erase Operation Timings
28
Am29F080B
January 3, 2002
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Valid Data
Status Data
True
Status Data
tBUSY
RY/BY#
Note:VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note:VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
January 3, 2002
Am29F080B
29
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note:The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 must be read at an address within the erase-suspended
sector.
Figure 15. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 16. Temporary Sector Group Unprotect Timing Diagram
30
Am29F080B
January 3, 2002
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Parameter Symbol
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Parameter Description
Write Cycle Time (Note 1)
-55
-70
-90
-120
-150
Unit
ns
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
55
70
90
120
150
tAVEL
Address Setup Time
Address Hold Time
Data Setup Time
0
ns
tELAX
tAH
45
25
45
30
45
45
0
50
50
50
50
ns
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
tDS
ns
tDH
Data Hold Time
ns
tGHEL
tWS
tWH
tCP
Read Recover Time Before Write
CE# Setup Time
0
ns
0
ns
CE# Hold Time
0
ns
Write Pulse Width
30
35
45
20
7
50
50
ns
tEHEL
tCPH
Write Pulse Width High
ns
tWHWH1
tWHWH2
Notes:
tWHWH1 Byte Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
µs
1
sec
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
January 3, 2002
Am29F080B
31
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
32
Am29F080B
January 3, 2002
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
1
16
7
8
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time
128
300
21.6
Byte Programming Time
Chip Programming Time (Note 3)
Excludes system-level overhead
(Note 5)
7.2
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 for -55), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 4 for further
information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 1,000,000 cycles are guaranteed.
LATCHUP CHARACTERISTIC
Min
Max
Input Voltage with respect to VSS on I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Conditions
Min
6
Max
7.5
12
Unit
CIN
VIN = 0
VOUT = 0
VIN = 0
pF
pF
pF
COUT
CIN2
Output Capacitance
8.5
7.5
Control Pin Capacitance
9
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
January 3, 2002
Am29F080B
33
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
34
Am29F080B
January 3, 2002
PHYSICAL DIMENSIONS
TS 040—40-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
January 3, 2002
Am29F080B
35
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse Thin Small Outline Package
Dwg rev AA; 10/99
36
Am29F080B
January 3, 2002
REVISION SUMMARY
Revision A (July 1997)
Initial release.
Erase and Programming Performance
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Revision B (January 1998)
Revision E (January 1999)
Global
Global
Formatted for consistency with other 5.0 volt-only
data sheets.
Updated for CS39S process technology.
Figure 9, Read Operation Timings
Distinctive Characteristics
Corrected RESET# waveform so that it is high for the
duration of the read cycle.
Added:
■ 20-year data retention at 125°C
Figure 11, Chip/Sector Erase Operation Timings
— Reliable operation for the life of the system
Corrected data unlock cycle in diagram to 55h.
DC Characteristics—CMOS Compatible
Figure 17, Alternate CE# Controlled Program
Operation Timings
Added note “For CMOS mode only, ICC3 = ICC4 = 20 µA
max at extended temperatures (> +85°C)”.
Corrected command for sector erase to 30h, chip erase
to 10h.
DC Characteristics—TTL/NMOS Compatible and
CMOS Compatible
I
CC1, ICC2, ICC3, ICC4: Added Note 2 “Maximum ICC
Revision C (January 1998)
specifications are tested with VCC = VCCmax”.
Standby Mode
ICC3, ICC4: Deleted VCC = VCCMax.
Removed sentence in first paragraph referring to
RESET# pulse.
Revision E+1 (March 23, 1999)
Sector Group Protection/Unprotection, Temporary
Sector Group Unprotect
Operating Ranges
The temperature ranges are now specified as ambient.
Changed references from “sector” to “sector group”.
Corrected text to indicate sector groups are composed
of two adjacent sectors.
Revision E+2 (April 9, 1999)
Ordering Information, Operating Ranges
Revision D (May 1998)
Added the extended temperature range.
Distinctive Characteristics
Revision F (November 15, 1999)
Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.
AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations
DC Characteristics, CMOS Compatible
For ICC3 and ICC4, the voltage tolerances given for CE#
and RESET# are now ±0.5 V.
Deleted tGHWL and changed OE# waveform to start at
high.
AC Characteristics
Physical Dimensions
Erase/Program Operations; Erase and Program Oper-
ations Alternate CE# Controlled Writes: Corrected the
notes reference for tWHWH1 and tWHWH2. These param-
eters are 100% tested. Corrected the note reference
for tVCS. This parameter is not 100% tested.
Replaced figures with more detailed illustrations.
Revision F+1 (May 18, 2000)
DC Characteristics
Temporary Sector Unprotect Table
TTL/NMOS Compatible: The ICC2 specifications are
now identical to those for CMOS compatible.
Added note reference for tVIDR. This parameter is not
100% tested.
Revision G (December 4, 2000)
Command Definitions
Added table of contents.
Corrected the shift in the table header.
Ordering Information
Deleted burn-in option.
January 3, 2002
Am29F080B
37
Revision G+1 (January 3, 2002)
Global
Changed -75 speed option to -70 (70 ns, VCC = 5.0 ±
10 %). Added -55 (55 ns, VCC = 5.0 V ± 5%) speed
option.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
38
Am29F080B
January 3, 2002
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