AM7943-2JC [ETC]
Telecommunication IC ; 电信IC\n
| 型号： | AM7943-2JC |
| 厂家： | 
ETC |
| 描述： | Telecommunication IC
|
| 文件： | 总20页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am7943
Subscriber Line Interface Circuit
DISTINCTIVE CHARACTERISTICS
Programmable constant-current feed
Current gain = 200
–19 V to –58 V battery operation
Two-wire impedance set by single external
impedance
Programmable loop-detect threshold
Low power Standby state
On-hook transmission
On-chip ring relay driver and relay snubber
circuit
Performs polarity reversal
Ground-key detector
On-chip Thermal Management (TMG) feature
Ideal for DLC and PABX applications
Tip Open state for ground-start lines
BLOCK DIAGRAM
TMG
Ring Relay
Driver
RINGOUT
C1
C2
A(TIP)
Input
C3
E0
Decoder
Ground-Key
Detector
and Control
E1
HPA
Two-Wire
Interface
DET
RSN
VTX
Signal
Transmission
HPB
Off-Hook
Detector
RD
Power-Feed
Controller
RDC
CAS
B(RING)
DA
Ring-Trip
Detector
DB
VBAT
BGND
AGND/DGND
VCC
VEE
Publication# 080136 Rev: D Amendment: /0
Issue Date: October 1999
ORDERING INFORMATION
Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am7943
–1
J
C
TEMPERATURE RANGE
C = Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 32-pin Plastic Leaded Chip Carrier (PL 032)
PERFORMANCE GRADE
–1 = Performance Grading
–2 = Performance Grading
DEVICE NUMBER/DESCRIPTION
Am7943
Subscriber Line Interface Circuit
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Legerity sales office to confirm
availability of specific valid combinations, to check
on newly released combinations, and to obtain
additional data on Legerity’s standard military–
grade products.
–1
–2
Am7943
JC
Note:
* Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C
is guaranteed by characterization and periodic sampling of production units.
2
Am7943 Data Sheet
CONNECTION DIAGRAM
Top View
32-Pin PLCC
4
3
2
1
32 31 30
TP
TP
5
6
29
28
RINGOUT
NC
DA
RD
7
27
26
TMG
8
HPB
NC
9
VBAT
C3
25
24
HPA
10
E1
C2
11
12
VTX
VEE
RSN
23
22
13
DET
21
14 15 16 17 18 19 20
Notes:
1. Pin 1 is marked for orientation.
2. TP is a thermal conduction pin tied to substrate.
3. NC = No Connect
SLIC Products
3
PIN DESCRIPTIONS
Pin Names
AGND/DGND
A(TIP)
Type
Description
Gnd
Analog and Digital ground
Output
Gnd
Output of A(TIP) power amplifier
Battery (power) ground
BGND
B(RING)
C3–C1
Output
Input
Output of B(RING) power amplifier
Decoder. TTL compatible. C3 is MSB and C1 is LSB.
CAS
Capacitor
Anti-saturation pin for capacitor to filter reference voltage when operating in anti-
saturation region.
DA
Input
Ring-trip negative. Negative input to ring-trip comparator.
Ring-trip positive. Positive input to ring-trip comparator.
DB
Input
DET
Output
Switchhook detector. When enabled, a logic Low indicates the selected detector is
tripped. The detector is selected by the logic inputs (C3–C1, E1–E0). The output is open-
collector with a built-in 15 kΩ pull-up resistor.
E0
E1
Input
Input
DET Enable. A logic High enables DET. A logic Low disables DET. (DET = Logic High).
(PLCC only)
Ground-Key Enable. E1 = Low connects the ground-key or ring-trip detector to DET.
E1 = High connects the off-hook or ring-trip detector to DET. (PLCC only)
HPA
HPB
RD
Capacitor
Capacitor
Resistor
Resistor
High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.
High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.
Detector resistor. Threshold modification and filter point for the off-hook detector.
RDC
DC feed resistor. Connection point for the DC feed current programming network. The
other end of the network connects to the receiver summing node (RSN). The sign of
VRDC is negative for normal polarity and positive for reverse polarity.
RINGOUT
RSN
Output
Input
Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING)
is equal to 200 times the current into this pin. The networks that program receive gain,
two-wire impedance, and feed current all connect to this node.
TMG
TP
—
Thermal management. A resistor connected from this pin to VBAT reduces the on-chip
power dissipation in the normal polarity, Active state only. Refer to Table 2.
Thermal
Thermal pin. Connection for heat dissipation. Internally connected to substrate (VBAT).
Leave as open circuit or connected to VBAT. In both cases, the TP pins can connect to
an area of copper on the board to enhance heat dissipation.
VBAT
VCC
VEE
VTX
Battery
Power
Power
Output
Battery supply
+5 V power supply
–5 V power supply
Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic
voltage. VTX also sources the two-wire input impedance programming network.
4
Am7943 Data Sheet
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage temperature . . . . . . . . . . . . –55°C to +150°C
Commercial (C) Devices
V
CC with respect to AGND/DGND . . .–0.4 V to +7.0 V
Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
VEE . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to –5.25 V
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to –56.5 V
AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
VEE with respect to AGND/DGND . . .+0.4 V to –7.0 V
VBAT with respect to AGND/DGND:
Continuous . . . . . . . . . . . . . . . . . . +0.4 V to –70 V
10 ms . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –75 V
BGND with respect to AGND/DGND . . . .+3 V to –3 V
BGND with respect to
A(TIP) or B(RING) to BGND:
AGND/DGND. . . . . . . . . . . . –100 mV to +100 mV
Continuous . . . . . . . . . . . . . . . . . . . .–70 V to +1 V
10 ms (f = 0.1 Hz) . . . . . . . . . . . . . . .–70 V to +5 V
1 ms (f = 0.1 Hz) . . . . . . . . . . . . . . . .–80 V to +8 V
10 µs (f = 0.1 Hz) . . . . . . . . . . . . . .–90 V to +12 V
Load resistance on VTX to ground . . . . . . . 10 kΩ min
Operating Ranges define those limits between which device
functionality is guaranteed.
Current from A(TIP) or B(RING). . . . . . . . . . . . 150 mA
* Functionality of the device from 0°C to +70°C is guaranteed
by production testing. Performance from –40°C to +85°C is
guaranteed by characterization and periodic sampling of
production units.
Current from TMG . . . . . . . . . . . . . . . . . . . . . 100 mA
Voltage on RINGOUT:
During transient . . . . . . . . . . . . . . BGND to +10 V
During steady state. . . . . . . . . . . . . BGND to +7 V
Current through relay drivers . . . . . . . . . . . . . . 60 mA
DA and DB inputs
Voltage on ring-trip inputs. . . . . . . . . . .VBAT to 0 V
Current into ring-trip inputs . . . . . . . . . . . . . . 10 mA
C3–C1, E0, E1
to AGND/DGND . . . . . . . . . . –0.4 V to VCC +0.4 V
Maximum power dissipation, TA = 85°C
No heat sink (see note):
In 32-pin PLCC package. . . . . . . . . . . . . . . . 1.4 W
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .θJA
In 32-pin PLCC package. . . . . . . . . . . .43°C/W typ
Note: Thermal limiting circuitry on chip will shut down the cir-
cuit at a junction temperature of about 165°C. The device
should never be exposed to this temperature. Operation
above 145°C junction temperature may degrade device reli-
ability. See the SLIC Packaging Considerations for more in-
formation.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
SLIC Products
5
ELECTRICAL CHARACTERISTICS
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Analog (VTX) output impedance
Analog (VTX) output offset
3
Ω
–35
–40
+35
+40
—
4
mV
–40°C to +85°C
Analog (RSN) input impedance
300 Hz to 3.4 kHz
1
20
35
4
Ω
Longitudinal impedance
at A or B
Overload level
4-wire and 2-wire Active state
–2.5
+2.5
Vpk
2a
2b
On-hook, RLAC = 900 Ω,
Active or OHT state
0.95
Vrms
Transmission Performance
2-wire return loss
200 to 3400 Hz
26
dB
4, 8
(See Test Circuit D)
Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C); RL = 740 Ω at VBAT = 48 V
Longitudinal to metallic L-T, L-4
200 Hz to 1 kHz
normal polarity
normal polarity
reverse polarity
–1*
–2
–2
–2
52
63
58
58
—
—
4
0°C to +70°C
–40°C to +85°C
—
1 kHz to 3.4 kHz
normal polarity
normal polarity
reverse polarity
–1*
–2
–2
–2
52
58
54
54
—
—
4
dB
0°C to +70°C
–40°C to +85°C
—
Longitudinal signal
generation 4-L
300 Hz to 800 Hz
normal polarity
42
Longitudinal current per pin
Active state and OHT state
27
35
mArms
Insertion Loss (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B)
BAT = –48 V, RL = 900 Ω
Gain accuracy
0 dBm, 1 kHz
0°C to +70°C
–40°C to +85°C
—
—
4
–0.15
–0.20
+0.15
+0.20
Gain accuracy, OHT state
Variation with frequency
–10 dBm, on-hook, RLAC = 900 Ω
–0.5
+0.5
4
dB
300 to 3400 Hz
—
—
4
relative to 1 kHz
0°C to +70°C
–40°C to +85°C
–0.10
–0.15
+0.10
+0.15
Gain tracking
+7 dBm to –55 dBm
–0.1
+0.1
4
Reference: 0 dBm
—
Balance Return Signal (4- to 4-Wire, See Test Circuit B)
BAT = –48 V, RL = 900 Ω
Gain accuracy
0 dBm, 1 kHz
0°C to +70°C
–40°C to +85°C
—
3
4
–0.15
–0.20
+0.15
+0.20
Variation with frequency
Gain tracking
300 to 3400 Hz
relative to 1 kHz
—
3
4
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
dB
+3 dBm to –55 dBm
Reference: 0 dBm
0°C to +70°C
—
—
3, 4
4
–0.1
–0.15
+0.1
+0.15
–40°C to +85°C
Group delay
f = 1 kHz
4
µs
4, 8
Note:
* P.G. = Performance Grade
6
Am7943 Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Total Harmonic Distortion (2- to 4-Wire or 4- to 2-Wire) (See Test Circuits A and B)
BAT = –48 V, RL = 900 Ω
Harmonic distortion
300 Hz to 3400 Hz
2-wire level = 0 dBm
2-wire level = +7 dBm
–64
–55
–50
–40
dB
Idle Channel Noise (2-wire and 4-wire)
C-message weighted noise
0°C to +85°C
+7
+7
+10
+12
—
4
dBrnC
dBmp
–40°C to 0°C
Psophometric
weighted noise
0°C to +85°C
–40°C to 0°C
–83
–80
–78
—
4
Line Characteristics, Active State (See Figure 1)
Short loops, Active state
BAT = –43 V, RLDC = 600 Ω
BAT = –48 V, RLDC = 600 Ω
25.0
27.0
29.0
Long loops, Active state
BAT = –43 V, RLDC = 1.4 kΩ
BAT = –48 V, RLDC = 1.9 kΩ
20.0
18.0
23.8
20.4
OHT state
BAT = –48 V, RLDC = 600 Ω
16.0
0.7IL
18.0
IL
20.0
1.3IL
mA
Standby state
VBAT – 3 V
IL = -------------------------------
RL + 1800
TA = 25°C
RL = 600 Ω, BAT = –48 V
15.0
17.4
TA = 70oC
Loop current
Tip Open, RL = 0
Disconnect, RL = 0
Tip Open, Bwire to GND
Tip Open, Bwire = VBAT + 6 V
—
—
30
30
100
100
—
µA
µA
mA
mA
—
ILLIM (Itip + Iring)
Tip and ring shorted to GND
100
130
mA
V
Ground-start signaling
(tip voltage)
Active state
–7.5
–5.0
4
—
—
R
TIP to –48 V = 7.0 kΩ
RRING to GND = 100 Ω
Open circuit voltage
Active and OHT
40.5
42.0
BAT = –48 V
Power Dissipation, Normal Loop Polarity, BAT = –48 V
On hook, Open Circuit state
25
70
On hook, OHT state
120
210
RTMG = Open
160
195
260
280
On hook, Active state
RTMG = 1700 Ω
mW
W
On hook, Standby state
Off hook, OHT state
Off hook, Active state
35
85
RL = 300 Ω, RTMG = ∞
BAT = –48 V
735
1050
RL = 300 Ω, RTMG = ∞
BAT = –48 V
1.25
0.57
0.68
1.45
0.85
1.0
RL = 300 Ω, RTMG = ∞
RL = 600 Ω, TA = 25°C
Off hook, Standby state
SLIC Products
7
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Supply Currents, BAT = –48 V
Open Circuit state
OHT state
Standby state
Active state
1.7
4.9
2.2
6.3
2.5
7.5
3.0
8.5
VCC on-hook supply current
VEE on-hook supply current
VBAT on-hook supply current
Open Circuit state
OHT state
Standby state
Active state
0.7
2.0
0.77
2.1
2.0
3.5
2.0
5.0
mA
Open Circuit state
OHT state
Standby state
Active state
0.18
1.9
0.45
4.2
1.0
4.7
1.5
5.7
Power Supply Rejection Ratio (VRIPPLE = 50 mVrms), Active Normal State
VCC
50 Hz to 3400 Hz
50 Hz to 3400 Hz
50 Hz to 3400 Hz
CAS pin to GND
33
29
30
85
40
35
VEE
dB
5
VBAT
50
Effective internal resistance
RFI rejection
170
255
1.0
kΩ
4
4
100 kHz to 30 MHz
(See Figure E)
mVrms
Off-Hook Detector
375
RD
Current threshold
IDET = --------
–10
+10
%
Ground-Key Detector Thresholds, Active State, BAT = –48 V
Ground-key resistance threshold B(RING) to GND
2.0
5.0
9
10.0
kΩ
Ground-key current threshold
Ring-Trip Detector Input
Bias current
B(RING) to GND
mA
–0.5
–50
–0.05
µA
Offset voltage
Source resistance = 2 MΩ
0
+50
0.8
mV
6
Logic Inputs (C3–C1, E0, E1)
Input High voltage
2.0
V
Input Low voltage
Input High current
All inputs except C3 and E1
Input C3
Input E1
–75
–75
–75
40
200
45
µA
Input Low current
–0.4
mA
Logic Output (DET)
Output Low voltage
IOUT = 0.8 mA
0.4
V
Output High voltage
Relay Driver Output (RINGOUT)
On voltage
IOUT = –0.1 mA
2.4
35 mA sink
VOH = +5 V
100 µA
+0.25
+0.4
100
V
Off leakage
µA
Zener breakover
Zener on voltage
6
7.2
10
V
30 mA
8
Am7943 Data Sheet
RELAY DRIVER SCHEMATIC
RINGOUT
BGND
SWITCHING CHARACTERISTICS
(32-pin PLCC only)
Temperature
Symbol
Parameter
Test Conditions
Range
Min Typ Max Unit Note
tgkde
E1 Low to DET High (E0 = 1)
0°C to 70°C
–40° to +85°C
3.8
4.0
E1 Low to DET Low (E0 = 1)
0°C to 70°C
1.1
1.6
–40° to +85°C
Ground-Key Detect state
RL open, RG connected
(See Figure G)
tgkdd
tgkd0
tshde
E0 High to DET Low (E1 = 0)
E0 Low to DET High (E1 = 0)
0°C to 70°C
–40° to +85°C
1.1
1.6
0°C to 70°C
–40° to +85°C
3.8
4.0
µs
4
E1 High to DET Low (E0 = 1)
E1 High to DET High (E0 = 1)
0°C to 70°C
1.2
1.7
–40° to +85°C
0°C to 70°C
–40° to +85°C
3.8
4.0
Switchhook Detect state
RL = 600 Ω, RG open
(See Figure F)
tshdd
tshd0
E0 High to DET Low (E1 = 1)
E0 Low to DET High (E1 = 1)
0°C to 70°C
–40° to +85°C
1.1
1.6
0°C to 70°C
–40° to +85°C
3.8
4.0
SLIC Products
9
SWITCHING WAVEFORMS
E1 to DET
E1
DET
tgkde
tshde
tgkde
tshde
E0 to DET
E1
E0
DET
tgkdd
tshdd
tshd0
tgkd0
Note:
All delays measured at 1.4 V level.
10
Am7943 Data Sheet
Notes:
1. Unless otherwise noted, test conditions are VCC = +5 V, VEE = –5 V, CHP = 0.33 µF, R DC1 = RDC2 = 9.26 kΩ, CDC = 0.33 µF,
Rd = 35.4 kΩ, CCAS = 0.33 µF, no fuse resistors, BAT = –48 V, RL = 900 Ω, and RTMG = 1700 Ω.
2. a. Overload level is defined when THD = 1%.
b. Overload level is defined when THD = 1.5%.
3. Balance return signal is the signal generated at VTX by VRX. This specification assumes the two-wire AC load impedance
matches the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz with a termination impedance of 900 Ω and an RL of 600 Ω in production. Performance at
other frequencies is guaranteed by characterization.
6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
7. Assumes the following ZT networks:
(900 Ω):
VTX
VTX
RSN
RSN
90 kΩ
60 kΩ
90 kΩ
60 kΩ
150 pF
(600 Ω):
150 pF
8. Group delay can be considerably reduced by using a ZT network such as that shown in Note 7 above. The network reduces
the group delay to less than 2 µs. The effect of group delay on the linecard performance may be compensated for by using
the QSLAC™ or DSLAC™ device.
Table 1. SLIC Decoding
DET Output
State
C3 C2 C1
Two-wire Status
Open Circuit
Ringing
E1 = 1
Ring trip
E1 = 0
Ring trip
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Ring trip
Ring trip
Active
Loop detector
Loop detector
Loop detector
Loop detector
Ground key
Ground key
Ground key
Ground key
Ground key
Ground key
On-hook TX (OHT)
Tip Open
Standby
Active Polarity Reversal Loop detector
OHT Polarity Reversal Loop detector
Note:
E0 High enables the DET pin.
SLIC Products
11
Table 2. User-Programmable Components
ZT is connected between the VTX and RSN pins. The fuse resistors
ZT = 200(Z2WIN – 2RF)
are RF and Z2WIN is the desired 2-wire AC input impedance. When
computing ZT, the internal current amplifier pole and any external
stray capacitance between VTX and RSN must be taken into
account.
ZL
200 • ZT
ZRX is connected from VRX to RSN. ZT is defined above and G42L
is the desired receive gain.
----------- -------------------------------------------------
ZRX
=
•
G42L ZT + 200(ZL + 2RF)
RDC1, RDC2, and CDC form the network connected to the RDC pin.
RDC1 and RDC2 are approximately equal. ILOOP is the desired loop
current in the constant-current region.
500
RDC1 + RDC2 = -------------
ILOOP
R
DC1 + RDC2
-------------------------------
CDC = 1.5 ms •
RDC1 • RDC2
RD and CD form the network connected from RD to –5 V and IT is
the threshold current between on hook and off hook.
375
0.5 ms
--------
IT
RD
=
, CD = ----------------
RD
OHT loop current (constant-current region)
500 V • 0.66
IOHT = -------------------------------
RDC1 + RDC2
CCAS is the regulator filter capacitor and fc is the desired filter cut-off
frequency.
1
CCAS = -----------------------------
3.4 • 105πfc
Thermal Management Equations (Normal Active and Tip Open states)
RTMG is connected from TMG to VBAT and is used to limit power
dissipation within the SLIC in Normal Active and Tip Open states
only.
VBAT – 6 V
RTMG = ----------------------------
ILOOP
(VBAT – 6 V – (IL • RL))2
Power dissipated in the thermal management resistor, RTMG
during Active and Tip Open states
,
PRTMG = ---------------------------------------------------------------
RTMG
PSLIC = VBAT • IL – PRTMG – RL(IL)2 + 0.12 W
Power dissipated in the SLIC while in Active and Tip Open states
Thermal Management Equations (Polarity Reverse State)
Note: SLIC die temperature should not exceed 140oC.
PSLIC = VBAT • IL – RL(IL)2 + 0.12 W
TSLIC = PSLIC • θJA + TAmbient
Power dissipated in the SLIC while in the Polarity Reverse state
Total die temperature
Theta JA (θJA) PLCC = 43°C ⁄ watt
Thermal impedance of the 32-pin plastic leaded chip carrier
package
12
Am7943 Data Sheet
DC FEED CHARACTERISTICS
3
4
VBAT = 51.3 V
3
2
V
BAT = 47.3 V
1
Active state
OHT state
RDC1 + RDC2 = RDC = 18.52 kΩ
Notes:
1. Constant-current region:
Active state,
500
IL = ---------
RDC
2
500
-- ---------
OHT state,
IL
=
•
3
RDC
2. Anti-sat (battery tracking) turn-on: VAB = 1.017 VBAT – 10.7
3. Open circuit voltage:
VAB = 1.017 VBAT – 6.3
RDC
---------
120
4. Anti-sat (battery tracking) region:
VAB = 1.017 VBAT – 6.3 – IL
a. VA–VB (VAB) Voltage vs. Loop Current (Typical)
SLIC Products
13
DC FEED CHARACTERISTICS (continued)
RDC1 + RDC2 = RDC = 18.52 kΩ
VBAT = 47.3 V
b. Loop Current vs. Load Resistance (Typical)
A
a
RSN
RDC
RL
IL
SLIC
RDC1
b
CDC
RDC2
B
Feed current programmed by RDC1 and RDC2
c. Feed Programming
Figure 1. DC Feed Characteristics
Am7943 Data Sheet
14
TEST CIRCUITS
A(TIP) VTX
VTX
A(TIP)
RL
2
RT
SLIC
SLIC
RT
AGND
AGND
VAB
VAB
VL
RL
RL
2
RRX
RRX
RSN
RSN
B(RING)
B(RING)
VRX
IL4-2 = –20 log (VAB / VRX
)
IL2-4 = –20 log (VTX / VAB
)
BRS = 20 log (VTX / VRX
)
B. Four- to Two-Wire Insertion Loss and Balance Return Signal
A. Two- to Four-Wire Insertion Loss
ZD
1
A
(TIP)
VTX
--------
<< RL
A(TIP)
VTX
ωC
RL
2
SLIC
RT1
R
R
SLIC
AGND
C
S1
RT
VM
VL
VAB
VS
VL
ZIN
RL
2
RT2
CT1
S2 RRX
RSN
B(RING)
B(RING)
RSN
VRX
RRX
S2 Open, S1 Closed
L-T Long. Bal. = 20 log (VAB / VL)
L-4 Long. Bal. = 20 log (VTX / VL)
Note:
ZD is the desired impedance (e.g., the characteristic
impedance of the line).
S2 Closed, S1 Open
4-L Long. Sig. Gen. = 20 log (VL / VRX
)
RL = –20 log (2 VM / VS)
D. Two-Wire Return Loss Test Circuit
C. Longitudinal Balance
SLIC Products
15
TEST CIRCUITS (continued)
RF1
C1
L1
50 Ω
200 Ω
200 Ω
A(TIP)
CAX
33 nF
RF2
50 Ω
B(RING)
HF
GEN
CBX
33 nF
L2
C2
VTX
50 Ω
SLIC
under test
1.5 Vrms
80% Amplitude
Modulated
100 kHz to 30 MHz
E. RFI Test Circuit
VCC
6.2 kΩ
A(TIP)
A(TIP)
DET
15 pF
B(RING)
RL = 600 Ω
RG: 2 kΩ at VBAT = –48 V
B(RING)
RG
E1
F. Loop-Detector Switching
G. Ground-Key Switching
16
Am7943 Data Sheet
TEST CIRCUITS (continued)
+5 V
–5 V
VEE
VCC
DA
DB
RD
RD
2.2 nF
A(TIP)
VTX
VTX
A(TIP)
HPA
RT
RRX
CHP
RSN
RDC
VRX
HPB
B(RING)
2.2 nF
B(RING)
RDC2
RDC1
CDC
RINGOUT
BGND
AGND/
DGND
E1
C3
C2
C1
VBAT
TMG
BAT
D6
DET
CAS
RTMG
1700 Ω
BATTERY
GROUND
ANALOG
GROUND
CCAS
DIGITAL
GROUND
H. Am7943 Test Circuit
SLIC Products
17
PHYSICAL DIMENSION
PL032
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
REVISION SUMMARY
Revision A to B
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
Revision B to Revision C
•
In Pin Description table, inserted/changed TP pin description to: “Thermal pin. Connection for heat dissipation.
Internally connected to substrate (VBAT). Leave as open circuit or connected to VBAT. In both cases, the TP
pins can connect to an area of copper on the board to enhance heat dissipation.”
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
Revision C to Revision D
•
•
•
The physical dimension (PL032) was added to the Physical Dimension section.
Deleted the Ceramic DIP and Plastic DIP packages and references to them.
Updated the Pin Description table to correct inconsistencies.
18
Am7943 Data Sheet
The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with re-
spect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever,
and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness
for a particular purpose, or infringement of any intellectual property right.
Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create
a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or
make changes to its products at any time without notice.
© 1999 Legerity, Inc.
All rights reserved.
Trademarks
Legerity, the Legerity logo and combinations thereof, DSLAC and QSLAC are trademarks of Legerity, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Fax: (512) 228-5510
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or to download or order product literature, visit
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or email:
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