AM79865/AM79866A? [ETC]
Am79865/Am79866A? 110KB (PDF) Physical Data Transmitter/Physical Data Receiver ? ; Am79865 / Am79866A ？ 110KB （ PDF ）物理数据发送/物理数据接收？\n
| 型号： | AM79865/AM79866A? |
| 厂家： | 
ETC |
| 描述： | Am79865/Am79866A? 110KB (PDF) Physical Data Transmitter/Physical Data Receiver ?
|
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FINAL
Am79865/Am79866A
Physical Data Transmitter/Physical Data Receiver
DISTINCTIVE CHARACTERISTICS
■ Fully compliant with ANSI X3T9.5 FDDI,
■ The on-chip Phase-Locked-Loop (PLL) only
TP-FDDI, and 100BASE-TX/FX PHY standards
requires an external frequency reference
■ 125 MBaud (100 Mbps) serial link data rate
■ Interfaces to fiber or copper media
■ Provides data and clock recovery functions for
FDDI and Fast Ethernet applications
■ Parallel input to the PDT is a 5-bit encoded NRZ
■ Dedicated pins provide electrical loopback
symbol clocked by LSCLK
data path
■ Parallel output from the PDR is a 5-bit
■ 20-pin Plastic Leaded Chip Carrier (PLCC)
■ Single +5 V power supply operation
unframed NRZ symbol clocked by RSCLK
GENERAL DESCRIPTION
The Physical Data Transmitter (Am79865) and the
Physical Data Receiver (Am79866) devices provide
clock recovery/generation functions meeting the re-
quirements of FDDI, TP-FDDI, and 100BASE-TX PHY
standards.
includes, among others, the 4B5B encoding and
decoding.
The PDT converts encoded symbols into a serial NRZI
data stream.The on-chip PLL generates a bit rate clock
from the LSCLK reference.
The PDT and PDR devices are part of the SUPERNET
2 FDDI Physical Layer Protocol chip set which also in-
cludes the Physical Layer Controller with Scrambler
(PLC-S).The PLC-S (Am79C864A), PDT and PDR de-
vices are collectively known as the AmPHY.The PLC-S
performs the FDDI physical layer functions which
The PDR uses a built-in clock recovery PLL to extract
clock information from the received data stream. The
recovered clock is used for serial-to-parallel data
conversion.
Publication# 15451 Rev: D Amendment/0
Issue Date: June 1996
BLOCK DIAGRAM
Am79865 PDT
LPBCK
TDAT 4-0
Input Register
Output
Control
LTX, LTY
NRZ
Shifter
NRZI
Test Mode
Sync Logic
÷5
Clock Multiplier
(PLL)
LSCLK
Output
Control
TEST
FOTOFF
15451D-1
TX, TY
Am79866A PDR
RDAT 4-0
RSCLK
Output Register
Clock
Recovery
PLL
NRZ
NRZI
Shifter
÷5
TEST
LSCLK
SDO
Q
D
Media Interface
LSCLK
SDI
15451D-2
LRX, LRY
RX, RY
2
Am79865/Am79866A
CONNECTION DIAGRAMS
Top View
20-Pin PLCC
20-Pin PLCC
3
2 1 20 19
3
2 1 20 19
RSCLK
RDAT3
RDAT4
4
5
6
7
8
18
17
LTX
GND
4
5
6
7
8
18
17
2
GND
1
VCC
2
TDAT1
VCC
1
Am79865
PDT
Am79866A
PDR
GND
2
TEST
16
15
GND
NC
TDAT0
16
15
1
SDO
VCC
2
LSCLK
LSCLK
14
VCC
14
LPBCK
1
9 10 11 12
13
9 10 11 12
13
15451D-4
15451D-3
Am79865/Am79866A
3
LOGIC SYMBOLS
Am79C864A PLC-S Interface
Forcing Optical Loopback
Transmitter Off
Control
Parallel Data Symbol
TDAT 4–0
FOTOFF
LPBCK
Data Loopback
to Local PDR
LTX, LTY
25 MHz
Local Symbol
Clock
Am79865
PDT
LSCLK
TEST
Test Mode Select
TX, TY
Serial Data Transmitted in
NRZI Format
Note:
Three V pins and two GND pins.
CC
Fiber or Copper Interface
15451D-5
Am79C864A PLC-S Interface
Recovered
Symbol
Clock
Light
Level
Signal
Parallel Data
Symbol
Loopback
Control
RDAT 4–0
RSCLK
SDO
LPBCK
Data Loopback
from Local PDT
LRX, LRY
Am79866A
PDR
25 MHz
Local Symbol
Clock
LSCLK
TEST
Test Mode Select
RX, RY
SDI
Serial Data Received
in NRZI Format
Light
Level
Signal
Note:
Fiber or Copper Interface
15451D-6
Two V pins and three GND pins.
CC
4
Am79865/Am79866A
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges.The order number (Valid Combination) is formed
by a combination of the elements below.
AM79865/
AM79866A
J
C
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 20-Pin Plastic Leaded Chip Carrier
(PL 020)
SPEED OPTION
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79865 = Physical Data Transmitter
Am79866A = Physical Data Receiver
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM79865
JC
AM79866A
Am79865/Am79866A
5
Am79865 PDT PIN DESCRIPTION
TDAT 4–0
Transmit Data (TTL Inputs)
TX, TY**
Transmit Data (PECL Differential Outputs)
These five inputs accept data symbols from the
Am79C864 PLC, latched by the rising edge of LSCLK.
These transmit outputs carry differential NRZI data.
They can be forced to logical 0 (TX LOW, TY HIGH) by
asserting the FOTOFF input.
LSCLK
Local Symbol Clock (TTL Input)
LTX, LTY**
Loopback Transmit Data (PECL Differential
Outputs)
This pin supplies the frequency and phase reference to
the internal PLL clock multiplier. It should be driven by
an external 25 MHz crystal-controlled clock source.
These differential outputs carry the same signal as TX/
TY when the LPBCK input is asserted (LOW). LTX/LTY
should be connected to the LRX/LRY pins of
Am79866A PDR to perform loopback function. When
LPBCK is deasserted (HIGH), LTX is forced LOW and
LTY is forced HIGH.
FOTOFF
Fiber Optic Transmitter Off (TTL Input, active LOW)
When held LOW, the TX output is forced LOW and TY
output is forced HIGH so that the Fiber Optic Transmit-
ter will output logical 0. In test mode, FOTOFF is used
as the test clock input and does not control TX/TY.
**All differential PECL outputs carry data at ECL volt-
age levels referenced to +5.0 V (PECL levels). The ex-
ternal terminations required are shown in the Interface
Connection Diagram in the Appendix.
LPBCK
Loopback Control (TTL Input, active LOW)
V
, V
CC2
CC1
Power Supply
,V are +5.0 V nominal power supply pins.V
When asserted, the LTX/LTY outputs transmit the NRZI
serial bit stream to the PDR to establish the loopback
data path. When deasserted, the LTX output is forced
LOW and LTY output is forced HIGH.
V
CC1 CC2
CC1
powers all TTL and ECL I/O circuits.V
powers all in-
CC2
ternal logic gates and analog circuits. They must be
connected to a common external supply.
TEST
Test Mode Enable (TTL Input)
GND1, GND2
Ground Pins
When asserted, the PDT is in Test mode. For normal
operation, TEST pin must be tied LOW.
GND1 is TTL and ECL I/O ground. GND2 is the internal
logic and analog ground. They must be connected to a
common external ground reference.
6
Am79865/Am79866A
Am79866A PDR PIN DESCRIPTION
LSCLK
Local Symbol Clock (TTL Input)
SDO
Signal Detect Output (TTL Output)
LSCLK is driven by an external frequency source at the
25 MHz symbol rate.This signal is used as a frequency
reference for the PDR clock-recovery PLL.
SDO is the SDI input synchronized by LSCLK. It has
the same logical sense as SDI, i.e., HIGH indicates the
received optical signal is above the detection threshold.
LPBCK
RX, RY*
Loopback (TTL Input, active LOW)
Received Data (PECL Differential Line Receiver
Inputs)
When active, LPBCK selects the serial data stream at
LRX/LRY inputs as the received data.When HIGH, RX/
RY are selected. This function is used during system
loopback test to bypass the transmission medium.
These pins receive NRZI data.
LRX, LRY*
Loopback Received Data (PECL Differential Line
Receiver Inputs)
TEST
TEST Mode Enable (TTL Input)
This input pair should be connected to the PDT LTX/
LTY outputs through properly terminated lines to estab-
lish the loopback data path. When LPBCK is asserted,
LRX/LRY carry the data to be used as the input to the
PDR. In Test mode, LRX/LRY become the test clock
input.
When asserted, the PDR is in Test mode. For normal
operation, TEST pin must be tied LOW.
RDAT 4–0
Received Data (TTL Outputs)
These 5-bit parallel outputs are clocked by the falling
edge of RSCLK and carry the NRZ data symbols to the
PLC.
*RX/RY and LRX/LRY are differential line receivers
which have high input sensitivity and wide
common-mode range. They can also accept PECL
voltage swings and shall be driven by properly termi-
nated transmission lines.
RSCLK
Recovered Symbol Clock (TTL Output)
V
, V
CC2
CC1
Power Supply
,V are +5.0 V nominal power supply pins.V
RSCLK is derived from the clock synchronization PLL
circuit. It is synchronous to the received serial data,
and is the recovered bit clock divided-by-five. This is a
25 MHz clock.
V
CC1 CC2
CC1
powers all TTL and ECL I/O circuits.V
powers all in-
CC2
ternal logic gates and analog circuits. They must be
connected to a common external supply.
SDI
Signal Detect Input (PECL Single-Ended Input)
GND , GND
Ground Pins
SDI typically comes from the fiber optic receiver to indi-
cate that the received optical signal is above the detec-
tion threshold. When asserted (HIGH), the data on RX/
RY are used for the input to the PDR.When deasserted
(LOW), the RX/RY data stream is gated off and the PLL
locks onto the LSCLK.
1
2
GND1 is TTL and ECL I/O ground. GND2 is the internal
logic and analog ground. They must be connected to a
common external ground reference.
Am79865/Am79866A
7
FUNCTIONAL DESCRIPTION
Normal Operation Mode
received serial stream and aligns its internal bit clock
with these data transitions. In order to guarantee the
correct operation of the PLL, the encoding scheme
(such as the FDDI 4B5B code) must insure adequate
transition density of the encoded data stream.
The Am79865 PDT accepts encoded data symbols at
TDAT 4–0 pins. The 5-bit symbol is latched into the
PDT by the rising edge of LSCLK, serialized, converted
to NRZI format and shifted to the outputs (TDAT4 bit is
transmitted first).There are two pairs of serial data out-
puts capable of driving either Fiber Optic Interface
hardware or wire transmission lines without external
buffering.The TX/TY pair is connected to the serial link
and the LTX/LTY pair is used in the loopback connec-
tion to the Am79866A PDR.
The PDR has input jitter tolerance characteristics that
meet or exceed the recommendations of Physical
Layer Medium Dependent (PMD) FDDI document.Typ-
ically, at 125 MBaud (8 ns/bit), the peak-to-peak
Duty-Cycle Distortion (DCD) tolerance is 1.4 ns, the
peak-to-peak Data-Dependent Jitter (DDJ) tolerance is
2.2 ns, and the peak-to-peak Random Jitter (RJ) toler-
ance is 2.27 ns. The total combined peak-to-peak jitter
The PDT uses LSCLK as the frequency reference to
generate the serial link data rate. The external clock
source must be crystal controlled and continuous. All of
the internal logic of PDT runs on an internal clock that
is PLL-multiplied from the external reference source.
The PDT’s internal PLL is referenced to the rising
edges of LSCLK only.
tolerance is typically 5 ns with bit error rate (BER) less
–10
than 2.5 x 10
.
The PDR’s PLL typically has an acquisition time of 100
µs or less when ‘Master’ symbols (one data transition
within ten bits) are received. The acquisition time re-
duces with increasing transition density in the data
stream.
The input clock frequency required to achieve
125 MBaud on the serial link is 25 MHz at LSCLK. In
order to generate the serial output waveforms conform-
ing to the FDDI specification, the external reference
clock (LSCLK) must meet FDDI frequency and stability
requirements. The PDT serial output typically contains
less than 0.4 ns peak-to-peak jitter at 125 MBaud. The
latency from the LSCLK to the serial output is typically
4 to 6 bits (8 ns/bit).
The SDI input qualifies the data at RX/RY. When SDI is
LOW, the PDR uses LSCLK as the PLL input and
forces LOW at the Output Register. The LPBCK input
selects the data source between RX/RY and LRX/LRY.
When LPBCK is LOW, the SDI input is ignored.
When SDI is HIGH and the RX/RY input stream con-
tains no data transition for PLL input, the PLL operating
frequency range is limited by the LSCLK reference.The
observed RSCLK output frequency is generally within
0.5% of the LSCLK frequency.
The Am79866A PDR accepts encoded NRZI serial
data on the RX/RY inputs and converts them to NRZ
format. It then latches the unframed symbol (5 bits) to
the RDAT 4-0 outputs on the falling edge of RSCLK.
Under normal conditions, the frequency of LSCLK mul-
tiplied by five must be within 0.25% of the expected re-
ceived data for the PLL to operate correctly. (Note,
FDDI specifies the two frequencies to be within 50 ppm
or 0.005% of each other.)
The heart of the Am79866A PDR chip is its
clock-recovery PLL which extracts encoded clock infor-
mation from the serial NRZI data stream and recovers
the data.The PLL examines every data transition in the
8
Am79865/Am79866A
accept the encoded NRZI serial data. LRX/LRY are
also differential line receiver inputs which accept the
loopback data stream from the local PDT LTX/LTY
outputs.
Am79865 PDT Functional Block
Description
Clock Multiplier
LSCLK supplies the reference frequency which is mul-
tiplied by five using an on-chip PLL. The transmission
rate and all serialization logic are controlled by the
internally generated bit clock.
NRZI-TO-NRZ Converter
Serial data are retimed and associated jitter is re-
moved. Retimed data are converted into NRZ format
prior to the Shifter input.
Input Register
Shifter
TDAT 4–0 are clocked into the Input Register by the ris-
ing edge of LSCLK.
The Shifter is serially loaded from the NRZI_TO_NRZ
converter, using the recovered bit clock.
Shifter
Output Register
Parallel data are loaded from the Input Register into the
Shifter at the internally generated symbol boundary,
and serially shifted at the bit clock rate.
The Output Register is clocked by RSCLK falling edges.
RSCLK is the recovered bit clock divided-by-five and is
synchronous to the received serial data.
NRZ-to-NRZI Converter
Test Mode
The NRZ output of the Shifter is converted into NRZI
data patterns for transmission.
Asserting PDT TEST input pin forces PDT into its test
mode. This allows testing of the internal logic without
the PLL clock multiplier.The internal clock source is re-
placed by the test clock provided at the FOTOFF input.
An automatic test system can clock the PDT through
functional test patterns at any rate, typically less than
25 MHz, or any sequence to facilitate logic verification.
Output Control
The differential outputs carry the encoded serial NRZI
bit stream. The TX/TY pair can be forced to logical 0
(TX LOW, TY HIGH) by asserting FOTOFF input. The
LTX/LTY pair can be forced to logical 0 (LTX LOW, LTY
HIGH) by deasserting the LPBCK input.
In PDT test mode, LSCLK strobes data into the Input
Register and provides initialization to the internal
counter.
Am79866A PDR Functional Block
Description
The PDR test mode allows testing of the internal logic
without the PLL. When TEST is HIGH, the internal
clock source is replaced by the test clock provided at
the LRX/LRY inputs. Note: The loopback data path in
the Am79866A PDR cannot be tested in test mode.
Clock-Recovery PLL
The clock-recovery PLL separates the input data
stream into clock and data patterns.The PLL operating
frequency is established by the reference at LSCLK.
The PLL is capable of tracking data correctly within +
0.25% of LSCLK (exceeds the frequency range defined
by the FDDI specification).
An automatic test system can clock the PDR through
functional test patterns at any rate, typically less than
25 MHz, or any sequence to facilitate logic verification.
Media Interface
The RX/RY inputs are typically driven by differential
PECL voltages, referenced to +5 V. These inputs
Am79865/Am79866A
9
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature Under Bias . . . . . . 0°C to 70°C
Commercial (C) Devices
Ambient Temperature (T ). . . . . . . . . . . . .0°C to 70°C
A
Supply Voltage (V ) . . . . . . . . . . +4.75 V to +5.25 V
CC
Supply Voltage (V ) to
CC
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Ground Potential Continuous. . . . . . . –0.5 V to +7.0 V
DC Voltage Applied to Outputs. . . . . .–0.5 to V Max
CC
DC Input Voltage . . . . . . . . . . . . . . . . –0.5 V to +5.5 V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .±100 mA
DC Input Current . . . . . . . . . . . . . –30 mA to +5.0 mA
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at or
above these limits is not implied.Exposure to AbsoluteMaximum
Ratings for extended periods may affect device reliability.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Am79865 PDT
Parameter
Symbol
Parameter Description
Test Description
Min
Max
TTL Inputs:TDAT 4–0, LSCLK, FOTOFF, LPBCK,TEST
V
Input HIGH Voltage
Input LOW Voltage
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Input Leakage Current
V
= Max (Note 2)
= Max (Note 2)
CC
2.0 V
IH
CC
V
V
0.8 V
–1.5 V
50 µA
IL
V
V
= Min, I = –18 mA
I
CC IN
I
V
= Max, V = 2.7 V
IH
CC IN
I
V
= Max, V = 0.4 V
–400 µA
50 µA
IL
CC
IN
I
V
= Max, V = 5.5 V
I
CC IN
PECL Outputs:TX,TX; LTX, LTY
V
Input HIGH Voltage
Input LOW Voltage
PECL Load (Note 3)
PECL Load (Note 3)
V
– 1.025 V
V
– 0.88 V
OH
CC
CC
V
V
– 1.81 V
0.8V – 1.62 V
OL
CC
CC
Power Supplies
I
I
V
Supply Current
Supply Current
V
V
= V
= V
= Max (Note 4)
= Max
20
65
CC1
CC2
CC1
CC2
CC1
CC2
V
CC1
CC2
10
Am79865/Am79866A
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Am79866 PDT
Parameter
Symbol
Parameter Description
Test Description
Min
Max
TTL Inputs: LSCLK, LPBCK,TEST
V
Input HIGH Voltage
Input LOW Voltage
Input Clamp Voltage
Input HIGH Current
Input LOW Current
Input Leakage Current
V
= Max (Note 2)
= Max (Note 2)
CC
2.0 V
IH
CC
V
V
0.8 V
–1.5 V
50 µA
IL
V
V
= Min, I = –18 mA
I
CC IN
I
V
= Max, V = 2.7 V
IH
CC IN
I
V
= Max, V = 0.4 V
–400 µA
50 µA
IL
CC
IN
I
V
= Max, V = 5.5 V
I
CC IN
TTL Outputs: RDAT 4–0, SDO, RSCLK
V
Output HIGH Voltage
Output LOW Voltage
V
= Min, I = –1 mA
2.4 V
OH
CC
OH
V
V
= Min, I = 4 mA
0.45 V
OL
SC
CC
OL
I
Output Short Circuit Current
V
= Max (Note 5)
–15 mA V
–85 mA
CC
Differential PECL Inputs: RX, RY; LRX, LRY
Input Voltage
V
V
V
= Max (Note 2)
2.5 V
V
CC
IN
CC
(Absolute High or Low)
Input Differential Voltage
Input HIGH Current
V
= Max (Note 2, 6)
50 mV
1.1 V
dif
IH
CC
I
V
= Max, V = V – 0.88 V
220 µA
CC
IN
CC
I
Input LOW Current
V
= Max, V = V – 1.81 V
0.5 µA
IL
CC
IN
CC
Single-Ended PECL Input: SDI
V
Input Single-Ended HIGH Voltage
Input Single-Ended LOW Voltage
Input HIGH Current
V
= Max (Note 2, 7)
= Max (Note 2, 7)
V
– 1.165 V
V
– 0.88 V
– 1.475 V
IHS
CC
CC
CC
V
I
V
V – 1.81 V
CC
V
ILS
CC
CC
V
= Max, V = V – 0.88 V
220 µA
IH
CC
IN
CC
I
Input LOW Current
V
= Max, V = V – 1.81 V
0.5 µA
IL
CC
IN
CC
Power Supplies
I
I
V
V
Supply Current
Supply Current
V
V
= V
= V
= Max
= Max
25
CC1
CC2
CC1
CC2
CC1
CC2
145
CC1
CC2
Am79865/Am79866A
11
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
Am79865 PDT
Parameter
No.
1
Symbol
Parameter Description
LSCLK Period
Test Conditions (Note 8)
Min
40
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ps
t
40
P
2
t
t
LSCLK Pulse Width HIGH
15
PW
PW
3
LSCLK Pulse Width LOW
15
4
t
TDAT 4–0 to LSCLK Rise Setup Time
TDAT 4–0 to LSCLK Rise Hold Time
TX, TY, LTX, LTY Rise Time
TX, TY, LTX, LTY Hold Time
TX/TY, LTX/LTY Skew
12
S
5
t
2.5
0.3
0.3
H
†
6
t
PECL load
PECL load
PECL load
3
3
R
†
7
t
F
†
8
t
±200
SK
Am79866A PDR
Parameter
No.
21
22
23
24
25
26
27
28
29
30
Symbol
Parameter Description
LSCLK to received data frequency offset
LSCLK Pulse Width HIGH
Test Conditions (Note 8)
Min
Max
Unit
%
f
(Note 9)
±0.25
OS
PW
PW
PW
PW
t
t
t
t
15
16
10
20
13
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
LSCLK Pulse Width LOW
RSCLK Pulse Width HIGH
TTL load (Note 10)
TTL load (Note 10)
TTL load (Note 11)
TTL load (Note 11)
RSCLK Pulse Width LOW
t
RDAT4–0 Valid to RSCLK Rise
RSCLK Rise to RDAT4–0 Invalid
SDI to LSCLK Rise Setup Time
SDI to LSCLK Rise Hold Time
LSCLK Rise to SDO Delay
PD
PD
t
t
S
t
7
H
t
TTL load
30
PD
Notes:
1. For conditions shown as Min or Max, use the appropriate values specified under operating range.
2. Typically measured with device in Test mode while monitoring output logic states.
3. Tested for V = Min, shown limits are specified over entire V operating range.
CC
CC
4. PDT I
is tested with all PECL outputs terminated to V (unloaded). The PECL outputs contribute 25 mA/pair nominally
CC
CC1
to I
when they are loaded with PECL loads, 50 Ω to (V – 2). In calculating the chip power dissipation, the contribution
CC1
CC
by the output loads shall be multiplied by 1 V instead of by V
.
CC
5. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
†
Not included in the production test.
12
Am79865/Am79866A
Notes (continued):
6. V is tested with each input voltage within the V range.
dif
IN
7. Device thresholds on the SDI pin are verified during production test by ensuring that the input threshold is less than V (min)
IHS
and greater than V (Max). The figure below shows the acceptable range (shaded area) for the transition voltage.
ILS
V
(max)
(min)
V
V
– 0.88 V
CC
CC
V
IHS
– 1.165 V
input threshold
transition voltage
– 1.475 V
V
V
(max)
(min)
CC
V
ILS
– 1.81 V
CC
8. All timing references are made with respect to + 1.5 V for TTL-level signals or to the 50% point between V and V for PECL
OH
OL
signals. PECL input rise and fall times must be 2 ns + 0.2 ns between 20% and 80% points.TTL input rise and fall times must
be 2 ns between 1 V and 2 V.
9. Received data frequency is determined by serial data inputs. Multiply LSCLK frequency by 5 to convert the receive data bit
rate.
10. Tested for 125 MBaud received data rate (1 bit-time is 8 ns). t (HIGH) is functionally 2 bit-time wide. t (LOW) is
PW
PW
functionally 3 bit-time wide.
11. Tested for 125 MBaud received data rate (1 bit-time 8 ns).
Am79865/Am79866A
13
SWITCHING WAVEFORMS
Am79865 PDT
1
3
2
LSCLK
4
5
Symbol k
Valid
Symbol
k+1
TDAT 4–0
Latency
TX, TY
LTX, LTY
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Symbol k
Bit 4 corresponds
to TDAT4
6
V
7
OH
80%
20%
TX, TY
LTX, LTY
V
50%
TX
TY
OL
8
50%
15451D-7
Am79866A PDR
RSCLK
24
25
24
27
26
27
Parallel 5-Bit
Symbol Valid
Parallel 5-Bit
Symbol Valid
Parallel 5-Bit
Symbol Valid
RDAT 4–0
LSCLK
22
23
28
29
SDI
(PECL)
30
SDO
15451D-8
14
Am79865/Am79866A
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUITS
V
CC
R
1
V
OUT
V
OUT
50 Ω
3 pF
30 pF
2.4 K
V
– 2 V
CC
15451D-9
15451D-10
TTL Output Load
PECL Output Load
Notes:
1. R = 1 KΩ for the I = 4 mA
Notes:
1. C = 30 pF includes scope probe, wiring and stray
1
OL
L
capacitances without device in text fixture.
2. All diodes IN916 or IN3064, or equivalent.
2. AMD uses Automatic Test Equipment (A.T.E.) load
configurations and forcing functions. This figure is for ref-
erence only.
3. C = 30 pF includes scope probe, wiring and stray
L
capacitances without device in text fixture.
4. AMD uses constant current (A.T.E.) load configurations
and forcing functions. This figure is for reference only.
Am79865/Am79866A
15
SWITCHING TEST WAVEFORMS
V
– 0.9 V
CC
3.0 V
80%
2.0 V
1.5 V
1.0 V
50%
20%
0.0V
V
– 1.7 V
CC
2 ± 0.2 ns
2 ± 0.2 ns
2 ± 0.2 ns
2 ± 0.2 ns
15451D-11
15451D-10
TTL Input Waveform
ECL Input Waveform
16
Am79865/Am79866A
PHYSICAL DIMENSIONS
Am79865/Am79866A Physical Data Transmitter/Data Receiver
PL 020
20-Pin Plastic Leaded Chip Carrier (measured in inches)
.062
.083
.385
.395
.042
.056
.350
.356
Pin 1 I.D.
.385
.395
.200 .290
REF .330
.350
.356
.013
.021
.009
.015
.026
.032
.090
.120
.050 REF
.165
.180
SEATING PLANE
16-038-SQ
PL 020
DF79
2-20-96 lv
TOP VIEW
SIDE VIEW
Trademarks
Copyright © 1996 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am79865/Am79866A
17
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