AMD-K6-2E+_技术文档

Preliminary Information

AMD-K6™-2E+

Embedded Processor

Data Sheet

Publication # 23542

Rev: A Amendment/0

Issue Date: September 2000

The contents of this document are provided in connection with Advanced Micro

Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with

respect to the accuracy or completeness of the contents of this publication and

reserves the right to make changes to specifications and product descriptions at any

time without notice. No license, whether express, implied, arising by estoppel or

otherwise, to any intellectual property rights is granted by this publication. Except

as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no

liability whatsoever, and disclaims any express or implied warranty, relating to its

products including, but not limited to, the implied warranty of merchantability,

fitness for a particular purpose, or infringement of any intellectual property right.

AMD's products are not designed, intended, authorized or warranted for use as

components in systems intended for surgical implant into the body, or in other

applications intended to support or sustain life, or in any other application in which

the failure of AMD's product could create a situation where personal injury, death,

or severe property or environmental damage may occur. AMD reserves the right to

discontinue or make changes to its products at any time without notice.

Trademarks

AMD, the AMD logo, K6, 3DNow!, and combinations thereof, AMD PowerNow!, E86, and Super7are trademarks,

FusionE86 is a service mark, and AMD-K6 and RISC86 are registered trademarks of Advanced Micro Devices,

Inc.

Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.

NetWare is a registered trademark of Novell, Inc.

MMX is a trademark of Intel Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks of

their respective companies.

The TAP State Diagram is reprinted from IEEE Std 1149.1-1990 “IEEE Standard Test Access Port and

The IEEE disclaims any responsibility or liability resulting fromthe placement and usein the described manner.

Information is reprinted with the permission of the IEEE.

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU.

The AMD customer service network includes U.S. offices, international offices, and a

customer training center. Expert technical assistance is available from the AMD

worldwide staff of field application engineers and factory support staff to answer

E86™ family hardware and software development questions.

Frequently accessed numbers are listed below. Additional contact information is

listed on the back of this manual. AMD’s WWW site lists the latest phone numbers.

Technical Support

Answers to technical questions are available online, through e-mail, and by telephone.

Go to AMD’s home page at www.amd.com and follow the Support link for the latest

AMD technical support phone numbers, software, and Frequently Asked Questions.

For technical support questions on all E86 embedded products, send e-mail to

epd.support@amd.com (in the US and Canada) or

euro.tech@amd.com (in Europe and the UK).

You can also call the AMD Corporate Applications Hotline at:

(800) 222-9323

44-(0) 1276-803-299

WWW Support

Toll-free for U.S. and Canada

U.K. and Europe hotline

For specific information on E86 products, access the AMD home page at

www.amd.com and follow the Embedded Processors link. These pages provide

information on upcoming product releases, overviews of existing products,

information on product support and tools, and a list of technical documentation.

Support tools include online benchmarking tools and CodeKit software—tested

source code example applications. Many of the technical documents are available

online in PDF form.

Questions, requests, and input concerning AMD’s WWW pages can be sent via e-mail

to web.feedback@amd.com.

Documentation and Literature Support

Data books, user’s manuals, data sheets, application notes, and product CDs are free

with a simple phone call. Internationally, contact your local AMD sales office for

product literature.

iii

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

To order literature:

Web: www.amd.com/support/literature.html

U.S. and Canada: (800) 222-9323

Third-Party Support

SM

AMD FusionE86 program partners provide an array of products designed to meet

critical time-to-market needs. Products and solutions available include chipsets, emulators,

hardware and software debuggers, board-level products, and software development tools,

among others. The WWW site and the E86™ Family Products Development Tools CD,

order #21058, describe these solutions. In addition, mature development tools and

applications for the x86 platform are widely available in the general marketplace.

iv

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

About this Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xix

1

AMD-K6™-2E+ Embedded Processor ........................................ 1

1.1

1.2

1.3

AMD-K6™-2E+ Embedded Processor Features . . . . . . . . . . . 3

Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Super7™ Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2

Internal Architecture ................................................................ 11

2.1

2.2

2.3

2.4

2.5

2.6

Microarchitecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . 16

Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 17

Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3

Software Environment ............................................................... 27

3.1

3.2

3.3

3.4

3.5

3.6

3.7

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 44

Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 54

Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Instructions Supported by the AMD-K6™-2E+ Processor . . 63

4

5

Logic Symbol Diagram ............................................................... 91

Signal Descriptions .................................................................... 93

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 94

A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 96

AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 99

BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.10 BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.11 BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.12 BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.13 BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . 104

5.14 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.15 CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . 105

5.16 CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.17 D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.18 D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Contents

v

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.19 DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.20 EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . 109

5.21 EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . 110

5.22 FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . 111

5.23 FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.24 HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.25 HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . 113

5.26 HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.27 HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.28 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 116

5.29 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.30 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.31 INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.32 KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.33 LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.34 M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.35 NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

5.36 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 123

5.37 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.38 PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.39 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.40 RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.41 RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.42 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.43 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 130

5.44 SMIACT# (System Management Interrupt Active) . . . . . . 131

5.45 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.46 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.47 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.48 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.49 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.50 TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.51 VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.52 VCC2H/L# (VCC2 High/Low) . . . . . . . . . . . . . . . . . . . . . . . . 136

5.53 VID[4:0] (Voltage Identification) . . . . . . . . . . . . . . . . . . . . . 137

5.54 W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.55 WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 139

5.56 Pin Tables by Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

5.57 Bus Cycle Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

6

AMD PowerNow!™ Technology ............................................. 143

6.1

6.2

Enhanced Power Management Features . . . . . . . . . . . . . . . 143

Dynamic Core Frequency and Core Voltage Control . . . . . 150

7

Bus Cycles ................................................................................. 153

7.1

7.2

7.3

7.4

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 158

I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

vi

Contents

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7.5

7.6

Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 168

Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8

Power-on Configuration and Initialization ............................ 199

8.1

Signals Sampled During the Falling Transition of

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 200

State of Processor After INIT . . . . . . . . . . . . . . . . . . . . . . . . 203

8.2

8.3

8.4

9

Cache Organization .................................................................. 205

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

MESI States in the L1 Data Cache and L2 Cache . . . . . . . . 207

Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Cache Disabling and Flushing . . . . . . . . . . . . . . . . . . . . . . . 211

L2 Cache Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Cache-Line Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

9.10 Cache States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

9.11 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

9.12 Writethrough and Writeback Coherency States . . . . . . . . . 227

9.13 A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . 227

10

Write Merge Buffer ................................................................. 229

10.1 EWBE# Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

10.2 Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . 231

10.3 Memory-Range Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 233

10.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

11

12

Floating-Point and Multimedia Execution Units .................. 237

11.1 Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . 237

11.2 Multimedia and 3DNow!™ Execution Units . . . . . . . . . . . . 239

11.3 Floating-Point and MMX™/3DNow!™ Instruction

Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

System Management Mode (SMM) ........................................ 241

12.1 SMM Operating Mode and Default Register Values . . . . . 241

12.2 SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

12.3 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

12.4 SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

12.5 Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

12.6 I/O Trap Doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

12.7 I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

12.8 Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 250

13

Test and Debug ......................................................................... 251

13.1 Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

13.2 Three-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

13.3 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 253

Contents

vii

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

13.4 Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

13.5 L2 Cache and Tag Array Testing . . . . . . . . . . . . . . . . . . . . . 264

13.6 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

14

Clock Control ............................................................................ 275

14.1 Clock Control States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

14.2 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

14.3 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

14.4 Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

14.5 EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

14.6 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

15

16

Electrical Data .......................................................................... 285

15.1 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

15.2 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

15.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

15.4 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

15.5 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Signal Switching Characteristics ............................................ 295

16.1 CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 296

16.2 Clock Switching Characteristics for 100-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

16.3 Clock Switching Characteristics for 66-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

16.4 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . 298

16.5 Output Delay Timings for 100-MHz Bus Operation . . . . . . 298

16.6 Input Setup and Hold Timings for 100-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

16.7 Output Delay Timings for 66-MHz Bus Operation . . . . . . . 302

16.8 Input Setup and Hold Timings for 66-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

16.9 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . 306

16.10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

17

Thermal Design ........................................................................ 313

17.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 313

17.2 Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 317

17.3 Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . . 317

18

19

20

Pin Designations ....................................................................... 321

18.1 Pins Designations for CPGA Package . . . . . . . . . . . . . . . . . 322

18.2 Pins Designations for OBGA Package . . . . . . . . . . . . . . . . . 326

Package Specifications ............................................................ 331

19.1 321-Pin Staggered CPGA Package Specification . . . . . . . . 331

19.2 349-Ball OBGA Package Specification . . . . . . . . . . . . . . . . . 332

Ordering Information .............................................................. 333

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

viii

Contents

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

List of Figures

Figure 1. AMD-K6™-2E+ Processor Block Diagram . . . . . . . . . . . . . . . . . 13

Figure 2. Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4. AMD-K6™-2E+ Processor Decode Logic . . . . . . . . . . . . . . . . . . 19

Figure 5. AMD-K6™-2E+ Processor Scheduler . . . . . . . . . . . . . . . . . . . . . 22

Figure 6. Register X and Y Pipeline Functional Units. . . . . . . . . . . . . . . 24

Figure 7. EAX Register with 16-Bit and 8-Bit Name Components. . . . . . 28

Figure 8. Integer Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 9. Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10. Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. FPU Status Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 13. FPU Control Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 14. FPU Tag Word Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15. Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16. Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. MMX™/3DNow!™ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18. MMX™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19. 3DNow!™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20. EFLAGS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 21. Control Register 4 (CR4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 22. Control Register 3 (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 23. Control Register 2 (CR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 24. Control Register 1 (CR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 25. Control Register 0 (CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 26. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 27. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 28. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 29. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . . 43

Figure 30. Machine-Check Address Register (MCAR) . . . . . . . . . . . . . . . . 45

Figure 31. Machine-Check Type Register (MCTR). . . . . . . . . . . . . . . . . . . 45

Figure 32. Test Register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 33. Time Stamp Counter (TSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 34. Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . . 47

Figure 35. SYSCALL/SYSRET Target Address Register (STAR) . . . . . . . 48

Figure 36. Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . . 48

List of Figures

ix

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 37. UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . . 49

Figure 38. Processor State Observability Register (PSOR) . . . . . . . . . . . . 49

Figure 39. Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . . 50

Figure 40. L2 Tag or Data Location for AMD-K6™-2E+

Processor—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 41. L2 Data —EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 42. L2 Tag Information for AMD-K6™-2E+ Processor—EAX . . . . 52

Figure 43. Enhanced Power Management Register (EPMR). . . . . . . . . . . 53

Figure 44. Memory Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 45. Task State Segment (TSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 46. 4-Kbyte Paging Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 47. 4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE). . . . . . . . . . . 58

Figure 49. Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 58

Figure 50. Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 51. Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 52. System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 53. Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 54. Enhanced Power Management Register (EPMR). . . . . . . . . . 144

Figure 55. EPM 16-Byte I/O Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 56. Bus Divisor and Voltage ID Control (BVC) Field . . . . . . . . . . 147

Figure 57. Processor State Observability Register (PSOR)—Low-

Power Versions of the Processor . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 58. Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 59. Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and

Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 61. Misaligned Single-Transfer Memory Read and Write . . . . . . 161

Figure 62. Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 163

Figure 63. Burst Writeback due to Cache-Line Replacement . . . . . . . . . 165

Figure 64. Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 65. Misaligned I/O Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 66. Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 171

Figure 68. HOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . . . . 173

Figure 69. AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 70. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . 177

Figure 71. AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 179

Figure 72. AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

x

List of Figures

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 73. BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 74. Basic Locked Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 75. Locked Operation with BOFF# Intervention. . . . . . . . . . . . . . 187

Figure 76. Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 189

Figure 77. Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 191

Figure 78. Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 79. Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 194

Figure 80. Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 195

Figure 81. INIT-Initiated Transition from Protected Mode to Real

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 82. L1 and L2 Cache Organization for the AMD-K6™-2E+

Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 83. L1 Cache Sector Organization. . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 84. Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 217

Figure 85. Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 218

Figure 86. Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . 224

Figure 87. UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . 232

Figure 88. External Logic for Supporting Floating-Point Exceptions. . . 239

Figure 89. SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 90. TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor . . . . . . 265

Figure 92. L2 Cache Sector and Line Organization . . . . . . . . . . . . . . . . . 265

Figure 93. L2 Tag or Data Location for the AMD-K6™-2E+

Processor—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 94. L2 Data - EAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 95. L2 Tag Information for the AMD-K6™-2E+

Processor—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 96. LRU Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 97. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 98. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 99. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 100. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 271

Figure 101. Clock Control State Transitions for Standard-Power

Versions of the AMD-K6™-2E+ Processor . . . . . . . . . . . . . . . . 276

Figure 102. Clock Control State Transitions for Low-Power

Versions of the AMD-K6™-2E+ Processor . . . . . . . . . . . . . . . . 277

Figure 103. Suggested Component Placement for CPGA Package . . . . . . 292

Figure 104. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 105. Key to Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

List of Figures

xi

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 106. Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 107. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 108. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 109. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 110. TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 111. TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 112. Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 113. Thermal Model (CPGA Package) . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 114. Power Consumption and Thermal Resistance

(CPGA Package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 115. Processor Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . 316

Figure 116. Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 117. Voltage Regulator Placement. . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 118. Airflow for a Heatsink with Fan. . . . . . . . . . . . . . . . . . . . . . . . 319

Figure 119. Airflow Path in a Dual-Fan System . . . . . . . . . . . . . . . . . . . . . 319

Figure 120. Airflow Path in an ATX Form-Factor System . . . . . . . . . . . . . 320

Figure 121. CPGA Connection Diagram (Top-Side View) . . . . . . . . . . . . . 322

Figure 122. CPGA Connection Diagram (Bottom-Side View) . . . . . . . . . . 323

Figure 123. OBGA Connection Diagram (Top-Side View) . . . . . . . . . . . . . 326

Figure 124. OBGA Connection Diagram (Bottom-Side View) . . . . . . . . . . 327

Figure 125. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 331

Figure 126. 349-Ball OBGA Package Specification . . . . . . . . . . . . . . . . . . . 332

xii

List of Figures

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

List of Tables

Table 1.

Table 2.

Table 3.

Execution Latency and Throughput of Execution Units . . . . . 23

General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

General-Purpose Register Doubleword, Word, and Byte

Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

AMD-K6™-2E+ Processor Model-Specific Registers . . . . . . . . 44

Extended Feature Enable Register (EFER) Definition. . . . . . 47

SYSCALL/SYSRET Target Address Register (STAR)

Table 4.

Table 5.

Table 6.

Table 7.

Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Memory Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . 54

Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 8.

Table 9.

Table 10. System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 11. Summary of Exceptions and Interrupts. . . . . . . . . . . . . . . . . . . 62

Table 12. Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 13. Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 14. MMX™ Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 15. 3DNow!™ Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 16. 3DNow!™ Technology DSP Extensions . . . . . . . . . . . . . . . . . . . 90

Table 17. Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 18. Output Pin Float Conditions for VCC2 High/Low. . . . . . . . . . 136

Table 19. Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 20. Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 21. Input/Output Pin Float Conditions. . . . . . . . . . . . . . . . . . . . . . 141

Table 22. Test Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 23. Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 24. Special Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 25. Enhanced Power Management Register (EPMR) Definition 145

Table 26. EPM 16-Byte I/O Block Definition . . . . . . . . . . . . . . . . . . . . . . 146

Table 27. Bus Divisor and Voltage ID Control (BVC) Definition. . . . . . 147

Table 28. Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 29. Bus-Cycle Order During Misaligned Memory Transfers . . . . 160

Table 30. A[4:3] Address-Generation Sequence During Bursts . . . . . . . 162

Table 31. Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 167

Table 32. Interrupt Acknowledge Operation Definition. . . . . . . . . . . . . 188

Table 33. Encodings for Special Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . 190

Table 34. Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 200

Table 35. Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 36. PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 37. PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 38. CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 39. L1 and L2 Cache States for Read and Write Accesses. . . . . . 221

List of Tables

xiii

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 40. Valid L1 and L2 Cache States and Effect of Inquire Cycles . 225

Table 41. L1 and L2 Cache States for Snoops, Flushes, and

Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 42. EWBEC Settings and Performance . . . . . . . . . . . . . . . . . . . . . 231

Table 43. WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 44. Valid Masks and Range Sizes for UWCCR Register . . . . . . . 234

Table 45. Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 243

Table 46. SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 47. SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 48. I/O Trap Doubleword Configuration . . . . . . . . . . . . . . . . . . . . 248

Table 49. I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 50. Boundary Scan Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 51. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 259

Table 52. Supported TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Table 53. Tag versus Data Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 54. DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 273

Table 55. Operating Ranges for Low-Power AMD-K6™-2E+ Devices . . 286

Table 56. Operating Ranges for Standard-Power AMD-K6™-2E+

Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Table 57. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 58. DC Characteristics for the AMD-K6™-2E+ Processor . . . . . . 287

Table 59. Power Dissipation for Low-Power AMD-K6™-2E+ Devices . . 289

Table 60. Power Dissipation for Standard-Power AMD-K6™-2E+

Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table 61. Supported Voltages and Operating Frequencies for Low-

Power AMD-K6™-2E+ Processors Enabled with AMD

PowerNow!™ Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table 62. CLK Switching Characteristics for 100-MHz Bus Operation . 296

Table 63. CLK Switching Characteristics for 66-MHz Bus Operation . . 297

Table 64. Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 298

Table 65. Input Setup and Hold Timings for 100-MHz Bus Operation . 300

Table 66. Output Delay Timings for 66-MHz Bus Operation . . . . . . . . . 302

Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation . . 304

Table 68. RESET and Configuration Signals for 100-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Table 69. RESET and Configuration Signals for 66-MHz Bus

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Table 70. TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 308

Table 71. Test Signal Timing at 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . 308

Table 72. Package Thermal Specification for Low-Power

AMD-K6™-2E+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Table 73. Package Thermal Specification for Standard-Power

AMD-K6™-2E+ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Table 74. Pin Differences Between the CPGA and OBGA Packages. . . 321

xiv

List of Tables

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 75. CPGA Pin Designations by Functional Grouping . . . . . . . . . . 324

Table 76. CPGA Pin Designations for No Connect, Reserved, Power,

and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Table 77. OBGA Pin Designations by Functional Grouping . . . . . . . . . . 328

Table 78. OBGA Pin Designations for No Connect, Reserved, Power,

and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Table 79. AMD-K6™-2E+ Embedded Processor Valid Ordering Part

Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

List of Tables

xv

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

xvi

List of Tables

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Revision History

Date

Rev Description

September 2000

A

Initial published release.

Second Printing: Revised trademarks.

Second Printing: Changed setting of NOL2 bit on page 148.

Second Printing: Revised headings in Table 59 on page 289, Table 60 on page 290, and Table 61 on

page 290. Changed Note 2 in Table 60 on page 290 to apply to 400-MHz parts only.

September 2000

A

Revision History

xvii

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

xviii

Revision History

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

About this Data Sheet

The AMD-K6™-2E+ Embedded Processor Data Sheet is the

complete specification of the AMD-K6™-2E+ embedded

processor.

Overview

This data sheet is organized into the following sections:

Chapter 1, “AMD-K6™-2E+ Embedded Processor” on page 1,

provides a list of the AMD-K6-2E+ processor’s distinguishing

characteristics, a description of the key features, and a

discussion about the Super7™ platform initiative.

Chapter 2, “Internal Architecture” on page 11, describes the

functional elements of the advanced design techniques, known

®

as the RISC86 microarchitecture, implemented by the

AMD-K6-2E+ processor.

Chapter 3, “Software Environment” on page 27, provides a

general overview of the AMD-K6-2E processor’s x86 software

environment and briefly describes the data types, registers,

operating modes, interrupts, and instructions supported by the

AMD-K6-2E+ processor’s architecture and design

implementation.

Chapter 4, “Logic Symbol Diagram” on page 91, contains the

AMD-K6-2E+ processor logic symbol diagram.

Chapter 5, “Signal Descriptions” on page 93, lists the signals

and their descriptions alphabetically and by function.

Chapter 6, “AMD PowerNow!™ Technology” on page 143,

describes the enhanced power management features available

on the low-power versions of the AMD-K6-2E+ processor.

Chapter 7, “Bus Cycles” on page 153, describes and illustrates

the timing and relationship of bus signals during various types

of bus cycles.

About this Data Sheet

xix

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Chapter 8, “Power-on Configuration and Initialization” on

page 199, describes how the system logic resets the

AMD-K6-2E+ processor using the RESET signal.

Chapter 9, “Cache Organization” on page 205, describes the

basic architecture and resources of the AMD-K6-2E+

processor’s internal caches.

Chapter 10, “Write Merge Buffer” on page 229, describes the 8-

byte write merge buffer and how merging multiple write cycles

into a single write cycle ultimately increases overall system

performance.

Chapter 11, “Floating-Point and Multimedia Execution Units”

on page 237, describes the AMD-K6-2E+ processor’s IEEE 754-

compatible and 854-compatible floating point execution unit,

the multimedia and 3DNow!™ technology execution units, and

the floating-point and MMX™/3DNow! technology instruction

compatibility.

Chapter 12, “System Management Mode (SMM)” on page 241,

describes SMM, the state-save area, entry into and exit from

SMM, exceptions and interrupts in SMM, memory allocation

and addressing in SMM, and the SMI# and SMIACT# signals.

Chapter 13, “Test and Debug” on page 251, describes the

various test and debug modes that enable the functional and

manufacturing testing of systems and boards that use the

AMD-K6-2E+ processor and that allow designers to debug the

instruction execution of software components.

Chapter 14, “Clock Control” on page 275, describes the five

modes of clock control supported by the AMD-K6-2E+

processor.

Chapter 15, “Electrical Data” on page 285, includes operating

ranges, absolute ratings, DC characteristics, power dissipation

data, power and grounding information, and decoupling

recommendations.

Chapter 16, “Signal Switching Characteristics” on page 295,

provides tables listing valid delay, float, setup, and hold timing

specifications for the AMD-K6-2E+ processor signals.

xx

About this Data Sheet

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Chapter 17, “Thermal Design” on page 313, lists the package

thermal specifications, discusses how to measure case

temperature, and provides layout and airflow considerations.

Chapter 18, “Pin Designations” on page 321, provides top- and

bottom-view connection diagrams for each package type and

lists the AMD-K6-2E+ processor’s pin designations by

functional grouping.

Chapter 19, “Package Specifications” on page 331, provides

diagrams showing the specifications for the 321-pin CPGA

package and the 349-ball OBGA package.

Chapter 20, “Ordering Information” on page 333, provides the

ordering part number (OPN) and valid OPN combinations.

About this Data Sheet

xxi

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

xxii

About this Data Sheet

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

1

AMD-K6™-2E+ Embedded Processor

The following are key features of the AMD-K6™-2E processor:

■ Member of the AMD-K6™E family of 32-bit embedded processors

◆

Brings the power, performance, and value of the AMD-K6 family to the

embedded market

Enables improved time-to-market by leveraging existing hardware and software

infrastructure and field-proven development tools

Offers a wide software- and platform-compatible growth path with product

longevity to help preserve development investments

■ Functionally-compatible embedded version of the AMD-K6-2+ processor with

internal 128-Kbyte L2 cache

◆

Provides higher Super7™ platform performance with reduced total system cost

®

Microsoft Windows compatible processor

x86 binary software compatible

Supports real-time operating systems such as pSOS, QNX, RTXC, and VxWorks

®

■ Advanced 6-issue RISC86 superscalar microarchitecture

◆

Ten parallel specialized execution units

Multiple sophisticated x86-to-RISC86 instruction decoders

Advanced two-level branch prediction

Speculative and out-of-order execution

Register renaming and data forwarding

Up to six RISC86 instructions per clock

■ Innovative cache design

192-Kbyte total internal cache

◆

•

Internal split, two-way set associative, 64-Kbyte L1 Cache

- 32-Kbyte instruction cache with additional 20-Kbytes of predecode cache

- 32-Kbyte writeback dual-ported data cache

- MESI protocol support

•

Internal full-speed, four-way set associative, 128-Kbyte, L2 Cache

◆

Multiport internal cache design enabling simultaneous 64-bit reads/writes of

L1 and L2 caches

■ Super7 platform is Socket 7-compatible

◆

Leverages high-speed 100-MHz processor bus

2x Accelerated Graphic Port (AGP) support

◆

Chapter 1

AMD-K6™-2E+ Embedded Processor

1

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

◆

Takes advantage of existing system support, logic integration, and designs for

superior value

Provides an easy upgrade path for embedded applications and a bridge to

legacy applications

■ AMD PowerNow!™ technology dynamically manages power and performance

◆

Monitors application requirements for performance or power utilization

◆

Supports continuously varying operating frequency and voltage, delivering

performance on demand while dissipating the lowest amount of power possible

■ 3DNow!™ technology for better multimedia and audio performance

◆

x86 instruction set extension accelerates 3D graphics and other single-

precision floating-point compute-intensive operations

◆

Offers fast frame rates on high-resolution graphics applications, superior

modeling of real-world environments and physics, life-like images and

graphics, and big-screen sound and video

◆

Additional 3DNow! technology DSP instructions enhance communications

applications

Separate multiplier and ALU for superscalar instruction execution

■ High-performance IEEE 754-compatible and 854-compatible floating-point unit

■ High-performance industry-standard MMX™ instructions

◆

Dual-integer ALU for superscalar execution

■ Industry-standard System Management Mode (SMM)

■ IEEE 1149.1 boundary scan

■ 321-Pin Ceramic Pin Grid Array (CPGA) or 349-Ball Organic Ball Grid Array

(OBGA) package

■ Low-voltage 0.18-micron process technology

◆

Split-plane power with support for full 3.3 V I/O

Lower core voltages enable low-power operation

◆

■ Operating frequencies

◆

Standard-power and standard-temperature devices: 400, 450, and 500 MHz

Low-power and extended-temperature devices: 350, 400, and 450 MHz

◆

2

AMD-K6™-2E+ Embedded Processor

Chapter 1

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

1.1

AMD-K6™-2E+ Embedded Processor Features

The innovative AMD-K6-2E+ processor brings industry-leading performance to

embedded systems. Its Super7™ platform-compatible, 321-pin ceramic pin grid array

(CPGA) or 349-ball organic ball grid array (OBGA) package enables embedded

system designers to reduce time-to-market by leveraging today’s cost-effective,

industry-standard infrastructure.

Manufactured using AMD’s 0.18 micron low-power process, the AMD-K6-2E+

®

processor incorporates the innovative and efficient RISC86 microarchitecture, a

192-Kbyte total internal cache, a fast 100 MHz frontside bus, and a powerful IEEE

754-compatible and 854-compatible floating-point execution unit. The AMD-K6-2E+

processor also incorporates a superscalar MMX™ unit and AMD’s innovative 3DNow!

technology for high-performance multimedia and 3D graphics operation.

The AMD-K6-2E+ processor is a functionally compatible embedded version of the

AMD-K6-2+ processor with an internal 128-Kbyte L2 cache. The AMD-K6-2E+

processor offers a clock-for-clock performance boost at a lower total system cost over

existing Socket 7 systems because no external L2 cache is required. The low-power

versions of the AMD-K6-2E+ processor also support AMD’s enhanced power

management features, called AMD PowerNow! technology.

The AMD-K6-2E+ processor is part of the AMD-K6E family of embedded processors.

Within this family:

■ The AMD-K6-2E processor provides the best value and performance for cost-

sensitive embedded applications.

■ The AMD-K6-2E+ with its 128-Kbyte internal L2 cache offers higher performance

balanced with cost.

■ The AMD-K6-IIIE+ with its 256-Kbyte internal L2 cache offers the highest

performance available for Super7 and Socket 7 platforms.

All AMD-K6E family processors in the CPGA package share the same footprint and

support the Socket 7-compatible Super7 platform. The AMD-K6E family provides

embedded designers with an assured growth plan and supply stability, along with

product longevity. All AMD-K6E family processors are x86-binary compatible,

allowing preservation of the initial software investment.

The AMD-K6-2E+ embedded processor is particularly well-suited for use in

applications where high performance is required. It is designed to offer compelling,

yet affordable, power and performance for high-end embedded applications, such as

information appliances, set-top boxes, embedded PCs, point-of-sale terminals, public

and private communications infrastructure, and industrial control.

Chapter 1

AMD-K6™-2E+ Embedded Processor

3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The AMD-K6-2E+ embedded processor is available in two versions.

■ The low-power version operates at the lowest core voltage in order to offer the

lowest available power and extended temperature ratings. Enhanced power

management features are provided via AMD PowerNow! technology in the low-

power versions of the processor.

■ The standard-power version has a 2.0-V core voltage and offers standard power

and temperature specifications similar to desktop PC processors.

Innovative Cache Design for Faster Data Access

Recognizing the benefits of a large and fast cache design in feeding performance-

hungry applications, AMD developed an innovative cache architecture that enhances

the performance available for embedded applications based on the Super7 platform.

AMD’s cache design innovations include:

■ An internal 128-Kbyte L2 write-back cache operating at the full speed of the

processor and complementing the 64-Kbyte L1 cache, which is standard in all

AMD-K6 family processors.

■ A multiport internal cache design, enabling simultaneous 64-bit reads and writes

to both the L1 cache and the L2 cache.

■ A 4-way set associative backside L2 cache design enabling optimal data

management and external frontside data bus bandwidth efficiency.

The processor's multiport internal cache design enables both the 64-Kbyte L1 cache

and the 128-Kbyte L2 cache to perform simultaneous 64-bit read and write operations

in a clock cycle. This multiport capability allows data to be processed faster and more

efficiently than non-multiported designs. In addition, the processor core can access

both L1 and L2 caches simultaneously, which further enhances overall CPU

throughput.

The cache design is exceptionally fast, with the backside 128-Kbyte L2 cache

operating at full processor speed.

For example, the internal L2 cache of an AMD-K6-2E+/450 processor operates at 450

MHz and provides nine times the peak bandwidth of an external L2 cache operating

at 100 MHz. The maximum peak bandwidth of an external L2 cache operating at 100

MHz is 800 Mbytes/s, while an internal L2 cache operating at 450 MHz delivers a

maximum peak bandwidth of 3,600 Mbytes/s per port. Because the internal L2 cache

of the AMD-K6-2E+ processor is dual-ported for simultaneous reads and writes, the

total peak bandwidth is doubled to 7,200 Mbytes/s, resulting in a maximum peak

bandwidth nine times as large as a 100-MHz cache implementation.

4

AMD-K6™-2E+ Embedded Processor

Chapter 1

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

3DNow!™ Technology

The AMD-K6-2E+ processor supports AMD’s 3DNow! technology, an extension to the

x86 instruction set that includes 21 new instructions to accelerate 3D graphics and

other single-precision floating-point compute intensive operations.

3DNow! technology was defined and implemented in collaboration with Microsoft,

application developers, and graphics vendors, and has received an enthusiastic

reception. It is compatible with today’s existing x86 software and requires no

operating system support, thereby enabling a broad class of applications to benefit

from 3DNow! technology.

The worldwide installed base of 3DNow! technology-enhanced PCs has grown to more

than 25 million desktop and notebook systems, revolutionizing the 3D experience

with up to four times the peak floating-point performance of previous sixth

generation solutions. Support for 3DNow! technology exists today in leading industry-

®

standard APIs, including Microsoft DirectX and SGI’s OpenGL APIs. Additionally,

numerous hardware and software products have been optimized for 3DNow!

technology. AMD is now bringing this advanced capability to embedded systems.

3DNow! technology enables fast frame rates on high-resolution 3D-rendered scenes,

realistic physical modeling of real-world environments, sharp and detailed 3D

imaging, smooth video playback, and theater-quality audio.

In addition, the AMD-K6-2E+ processor adds support for five new digital signal

processing (DSP) instructions, developed to enhance the performance of

communications applications, including soft xDSL modems, MP3 recording, and

Dolby Digital and Surround Sound processing.

Chapter 1

AMD-K6™-2E+ Embedded Processor

5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

AMD PowerNow!™ Technology for Enhanced Power Management

AMD has added a number of new power management features to the low-power

versions of the AMD-K6-2E+ processor. Collectively, these hardware and software

features are called AMD PowerNow!™ technology.

AMD PowerNow! technology allows the AMD-K6-2E+ processor to run at different

frequencies and voltages, depending on the application’s need for maximum

performance or the most efficient power utilization.

AMD PowerNow! technology includes AMD’s unique “automatic mode” feature, which

allows the system to monitor application usage and to continuously vary the operating

frequency and voltage, delivering performance on demand while dissipating the

lowest amount of power possible.

■ When application demands require the processor to run at maximum

performance, the AMD PowerNow! technology steps up the performance to meet

the demand.

■ As platform demand for performance subsides, AMD PowerNow! technology can

dynamically drop into a lower power state.

AMD PowerNow! technology enables embedded products to dynamically manage

power and performance.

System Management Mode and Other Power Management Features

The AMD-K6-2E+ processor includes the complete industry-standard system

management mode (SMM), which is critical to system resource and power

management.

The AMD-K6-2E+ processor also features the industry-standard Stop-Clock

(STPCLK#) control circuitry and the Halt instruction, both required for

implementing the ACPI power management specification.

Microarchitecture

The AMD-K6-2E+ processor’s 6-issue RISC86 microarchitecture is a decoupled

decode/execution superscalar design that implements state-of-the-art design

techniques to achieve leading-edge performance.

Advanced design techniques implemented in the AMD-K6-2E+ processor include

multiple x86 instruction decode, single-clock internal RISC operations, ten execution

units that support superscalar operation, out-of-order execution, data forwarding,

speculative execution, and register renaming.

6

AMD-K6™-2E+ Embedded Processor

Chapter 1

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

In addition, the processor supports advanced branch prediction logic by

implementing an 8192-entry branch history table, a branch target cache, and a return

address stack, which combine to deliver better than a 95% prediction rate. These

design techniques enable the AMD-K6-2E+ processor to issue, execute, and retire

multiple x86 instructions per clock, resulting in excellent scaleable performance.

Industry-Standard x86 Architecture

The AMD-K6-2E+ processor is x86 binary code compatible. AMD’s extensive

experience through six generations of x86 processors has been carefully integrated

®

into the processor to enable compatibility with Windows 98, Windows 95, Windows

®

3.x, Windows NT, DOS, Linux, OS/2, Unix, Solaris, NetWare , and other leading x86

operating systems and applications. The AMD-K6-2E+ processor is also compatible

with leading real-time operating systems (RTOS) commonly used in embedded

applications, such as pSOS, QNX, RTXC, and VxWorks. Additionally, the AMD

SM

FusionE86 third-party tool support program offers extensive development support

for AMD-K6-2E+ processor designs.

The AMD-K6-2E+ processor is Super7 and Socket 7-compatible. The Super7 platform

is an extension to the popular and robust Socket 7 platform. See “Super7™ Platform”

on page 8 for more information.

AMD is the world’s second-leading supplier of PC processors compatible with the

Windows operating system, having shipped more than 120 million x86

microprocessors, including more than 60 million Windows-compatible processors. The

AMD-K6-2E+ processor for embedded applications is the latest member in this long

line of processors. With its combination of state-of-the-art features, industry-leading

performance, high-performance 3DNow! technology and multimedia engines, x86

compatibility, and low-cost infrastructure, the AMD-K6-2E+ processor is the superior

choice for high-performance embedded systems.

1.2

Process Technology

The AMD-K6-2E+ processor is implemented using an AMD-developed, state-of-the-art

low power 0.18-micron process technology. This process technology features a split-

plane design that enables the AMD-K6-2E+ processor to deliver excellent

performance solutions while utilizing a lower processor core voltage, which results in

lower power consumption, while the I/O portion operates at the industry-standard

3.3-V level.

Chapter 1

AMD-K6™-2E+ Embedded Processor

7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

1.3

Super7™ Platform

The Super7 platform is an extension to the popular Socket 7 platform. AMD and its

industry partners have invested in the future of Socket 7 with the Super7 platform

initiative. The goal of the initiative is to maintain the competitive vitality of the

Socket 7 infrastructure through a series of enhancements, including the development

of an industry-standard 100-MHz processor bus protocol.

In addition to the 100-MHz processor bus protocol, the Super7 initiative includes the

introduction of chipsets that support the AGP specification, and support for a

backside L2 cache. Currently, over 40 motherboard vendors and all major BIOS and

chipset vendors offer Super7-based products.

All AMD-K6 embedded processors in CPGA packages remain pin compatible with

existing Socket 7 solutions; however, for maximum system performance, the

AMD-K6-2E+processor works optimally in Super7 designs that incorporate advanced

features such as support for the 100-MHz frontside bus and AGP graphics.

100-MHz Processor Bus

The AMD-K6-2E+ processor supports a 100-MHz, 800 Mbyte/second frontside bus to

provide a high-speed interface to Super7 platform-based chipsets. The 100-MHz

interface speeds up access to main memory by 50 percent over the 66-MHz Socket 7

interface—resulting in a significant 10 percent increase in overall system

performance.

Accelerated Graphics Port Support

Accelerated Graphics Port (AGP) support improves the performance of video

graphics systems that have small amounts of video memory on the graphics card. The

industry-standard AGP specification enables a 133-MHz graphics interface and will

scale to even higher levels of performance.

Support For Backside L2 Cache

The Super7 platform has the ‘headroom’ to support higher-performance AMD-K6

processors like the AMD-K6-2E+ processor, which features a full-speed, internal

backside 128-Kbyte L2 cache designed to enable new levels of performance to

leading-edge embedded systems.

8

AMD-K6™-2E+ Embedded Processor

Chapter 1

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Super7™ Platform Advantages

The Super7 platform:

■ Delivers performance and features competitive with alternate platforms at the

same clock speed, and at a significantly lower cost

■ Takes advantage of existing system designs for superior value

■ Enables OEMs and resellers to take advantage of mature, high-volume

infrastructure supported by multiple BIOS, chipset, graphics, and motherboard

suppliers

■ Reduces inventory and design costs with one motherboard for a wide range of

products

■ Builds on a huge installed base of more than 100 million motherboards

■ Provides an easy upgrade path for embedded applications, as well as a bridge to

legacy applications

By taking advantage of the low-cost, mature Socket 7 infrastructure, the Super7

platform will continue to provide superior value and leading-edge performance for

embedded systems.

Chapter 1

AMD-K6™-2E+ Embedded Processor

9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

10

AMD-K6™-2E+ Embedded Processor

Chapter 1

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

2

Internal Architecture

The AMD-K6-2E+ processor implements advanced design

techniques known as the RISC86 microarchitecture. The

RISC86 microarchitecture is a decoupled decode/execution

design approach that yields superior sixth-generation

performance for x86-based software. This chapter describes the

techniques used and the functional elements of the RISC86

microarchitecture.

2.1

Microarchitecture Overview

When discussing processor design, it is important to understand

the terms architecture, microarchitecture, and design

implementation.

■ Architecture refers to the instruction set and features of a

processor that are visible to software programs running on

the processor. The architecture determines what software

the processor can run. The architecture of the AMD-K6-2E+

processor is the industry-standard x86 instruction set.

■ Microarchitecture refers to the design techniques used in the

processor to reach the target cost, performance, and

functionality goals. The AMD-K6 family of processors are

based on a sophisticated RISC core known as the Enhanced

RISC86 microarchitecture. The Enhanced RISC86

microarchitecture is an advanced, second-order decoupled

decode/execution

design

approach

that

enables

industry-leading performance for x86-based software.

■ Design implementation refers to the actual logic and circuit

designs from which the processor is created according to the

microarchitecture specifications.

Chapter 2

Internal Architecture

11

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

®

Enhanced RISC86

The Enhanced RISC86 microarchitecture defines the

characteristics of the AMD-K6 family of processors. The

innovative RISC86 microarchitecture approach implements the

x86 instruction set by internally translating x86 instructions

into RISC86 operations. These RISC86 operations were

specially designed to include direct support for the x86

instruction set while observing the RISC performance

principles of fixed length encoding, regularized instruction

fields, and a large register set.

Microarchitecture

The Enhanced RISC86 microarchitecture used in the

AMD-K6-2E+ processor enables higher processor core

performance and promotes straightforward extensions, such as

those added in the current AMD-K6-2E+ processor and those

planned for the future. Instead of directly executing complex

x86 instructions, which have lengths of 1 to 15 bytes, the

AMD-K6-2E+ processor executes the simpler and easier

fixed-length RISC86 operations, while maintaining the

instruction coding efficiencies found in x86 programs.

The AMD-K6-2E+ processor contains parallel decoders, a

centralized RISC86 operation scheduler, and ten execution

units that support superscalar operation—multiple decode,

execution, and retirement—of x86 instructions. These elements

are packed into an aggressive and highly efficient six-stage

pipeline.

AMD-K6-2E+

Processor Block

Diagram

As shown in Figure 1 on page 13, the high-performance,

out-of-order execution engine of the AMD-K6-2E+ processor is

mated to a split, level-one, 64-Kbyte, writeback cache with 32

Kbytes of instruction cache and 32 Kbytes of data cache.

Backing up the level-one (L1) cache is a large, unified, level-two

(L2), 128-Kbyte, writeback cache. The L1 instruction cache

feeds the decoders and, in turn, the decoders feed the

scheduler. The ICU issues and retires RISC86 operations

contained in the scheduler. The system bus interface is an

industry-standard 64-bit Super7 and Socket 7 demultiplexed

bus.

The AMD-K6-2E+ processor combines the latest in processor

microarchitecture to provide the highest x86 performance for

today’s computational systems. The AMD-K6-2E+ processor

offers true sixth-generation performance and x86 binary

software compatibility.

12

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 1. AMD-K6™-2E+ Processor Block Diagram

Decoders

Decoding of the x86 instructions begins when the on-chip L1

instruction cache is filled. Predecode logic determines the

length of an x86 instruction on a byte-by-byte basis. This

predecode information is stored, along with the x86

instructions, in the L1 instruction cache, to be used later by the

decoders. The decoders translate on-the-fly, with no additional

latency, up to two x86 instructions per clock into RISC86

operations.

Note: In this chapter, “clock” refers to a processor clock.

The AMD-K6-2E+ processor categorizes x86 instructions into

three types of decodes—short, long, and vector. The decoders

process either two short, one long, or one vector decode at a

time.

The three types of decodes have the following characteristics:

■ Short decodes—x86 instructions less than or equal to seven

bytes in length

Chapter 2

Internal Architecture

13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ Long decodes—x86 instructions less than or equal to 11

bytes in length

■ Vector decodes—complex x86 instructions

Short and long decodes are processed completely within the

decoders. Vector decodes are started by the decoders and then

completed by fetched sequences from an on-chip ROM. After

decoding, the RISC86 operations are delivered to the scheduler

for dispatching to the executions units.

Scheduler/Instruction

Control Unit

The centralized scheduler or buffer is managed by the

Instruction Control Unit (ICU). The ICU buffers and manages

up to 24 RISC86 operations at a time. This equals from 6 to 12

x86 instructions. This buffer size (24) is perfectly matched to

the processor’s six-stage RISC86 pipeline and four

RISC86-operations decode rate.

The scheduler accepts as many as four RISC86 operations at a

time from the decoders and retires up to four RISC86

operations per clock cycle. The ICU is capable of

simultaneously issuing up to six RISC86 operations at a time to

the execution units. This consists of the following types of

operations:

■ Memory load operation

■ Memory store operation

■ Complex integer, MMX or 3DNow! register operation

■ Simple integer, MMX or 3DNow! register operation

■ Floating-point register operation

■ Branch condition evaluation

Registers

When managing the RISC86 operations, the ICU uses 69

physical registers contained within the RISC86

microarchitecture.

■ Forty-eight of the physical registers are located in a general

register file.

•

Twenty-four of these are rename registers.

•

The other twenty-four are committed or architectural

registers, consisting of 16 scratch registers and 8 registers

that correspond to the x86 general-purpose registers—

EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI.

14

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ An analogous set of 21 registers is available specifically for

MMX and 3DNow! operations.

•

Twelve of these are MMX/3DNow! rename registers.

■ Nine are MMX/3DNow! committed or architectural registers,

consisting of one scratch register and eight registers that

correspond to the MMX registers (mm0–mm7, as shown in

Figure 17 on page 35.

Branch Logic

The AMD-K6-2E+ processor is designed with highly

sophisticated dynamic branch logic consisting of the following:

■ Branch history/prediction table

■ Branch target cache

■ Return address stack

The AMD-K6-2E+ processor implements a two-level branch

prediction scheme based on an 8192-entry branch history table.

The branch history table stores prediction information that is

used for predicting conditional branches. Because the branch

history table does not store predicted target addresses, special

address ALUs calculate target addresses on the fly during

instruction decode.

The branch target cache augments predicted branch

performance by avoiding a one clock cache-fetch penalty. This

specialized target cache does this by supplying the first 16 bytes

of target instructions to the decoders when branches are

predicted. The return address stack is a unique device

specifically designed for optimizing CALL and RETURN pairs.

In summary, the AMD-K6-2E+ processor uses dynamic branch

logic to minimize delays due to the branch instructions that are

common in x86 software.

3DNow!™ Technology

AMD has taken a lead role in improving the multimedia and 3D

capabilities of the x86 processor family with the introduction of

3DNow! technology, which uses a packed, single-precision,

floating-point data format and Single Instruction Multiple Data

(SIMD) operations based on the MMX technology model.

Chapter 2

Internal Architecture

15

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

2.2

Cache, Instruction Prefetch, and Predecode Bits

The writeback level-one (L1) cache on the AMD-K6-2E+

processor is organized as a separate 32-Kbyte instruction cache

and a 32-Kbyte data cache with two-way set associativity.

The level-two (L2) cache is 128 Kbytes, and is organized as a

unified, four-way set-associative cache. The cache line size is 32

bytes, and lines are fetched from external memory using an

efficient pipelined burst transaction.

As the L1 instruction cache is filled from the L2 cache or from

external memory, each instruction byte is analyzed for

instruction boundaries using predecoding logic. Predecoding

annotates information (5 bits per byte) to each instruction byte

that later enables the decoders to efficiently decode multiple

instructions simultaneously.

Cache

The processor cache design takes advantage of a sectored

organization (see Figure 2). Each sector consists of 64 bytes

configured as two 32-byte cache lines. The two cache lines of a

sector share a common tag but have separate pairs of MESI

(Modified, Exclusive, Shared, Invalid) bits that track the state

of each cache line.

Tag Address

Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits

Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits

Figure 2. Cache Sector Organization

Two forms of cache misses and associated cache fills can take

place—a tag-miss cache fill and a tag-hit cache fill.

■ Tag-Miss Cache Fill—The L1 cache miss is due to a tag

mismatch, in which case the required cache line is filled

either from the L2 cache or from external memory, and the

L1 cache line within the sector that was not required is

marked as invalid.

■ Tag-Hit Cache Fill—The address matches the tag, but the

requested cache line is marked as invalid. The required L1

cache line is filled from the L2 cache or from external

memory, and the L1 cache line within the sector that is not

required remains in the same cache state.

16

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Prefetching

The AMD-K6-2E+ processor conditionally performs cache

prefetching, which results in the filling of the required cache

line first, and a prefetch of the second cache line making up the

other half of the sector. From the perspective of the external

bus, the two cache-line fills typically appear as two 32-byte

burst read cycles occurring back-to-back or, if allowed, as

pipelined cycles.

The 3DNow! technology includes an instruction called

PREFETCH that allows a cache line to be prefetched into the

L1 data cache and the L2 cache. The PREFETCH instruction

format is defined in Table 15, “3DNow!™ Instructions,” on

page 89. For more detailed information, see the 3DNow!™

Technology Manual, order# 21928.

Predecode Bits

Decoding x86 instructions is particularly difficult because the

instructions are variable-length and can be from 1 to 15 bytes

long. Predecode logic supplies the five predecode bits that are

associated with each instruction byte. The predecode bits

indicate the number of bytes to the start of the next x86

instruction. The predecode bits are stored in an extended

instruction cache alongside each x86 instruction byte as shown

in Figure 2 on page 16. The predecode bits are passed with the

instruction bytes to the decoders where they assist with parallel

x86 instruction decoding.

2.3

Instruction Fetch and Decode

Instruction Fetch

The processor can fetch up to 16 bytes per clock out of the L1

instruction cache or branch target cache. The fetched

information is placed into a 16-byte instruction buffer that

feeds directly into the decoders (see Figure 3 on page 18).

Fetching can occur along a single execution stream with up to

seven outstanding branches taken.

The instruction fetch logic is capable of retrieving any 16

contiguous bytes of information within a 32-byte boundary.

There is no additional penalty when the 16 bytes of instructions

lie across a cache line boundary. The instruction bytes are

loaded into the instruction buffer as they are consumed by the

decoders.

Although instructions can be consumed with byte granularity,

the instruction buffer is managed on a memory-aligned word

Chapter 2

Internal Architecture

17

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

(two bytes) organization. Therefore, instructions are loaded and

replaced with word granularity. When a control transfer

occurs—such as a JMP instruction—the entire instruction

buffer is flushed and reloaded with a new set of 16 instruction

bytes.

Branch-Target Cache

16 Bytes

16 x 16 Bytes

32-Kbyte Level-One

Instruction Cache

16 Bytes

2:1

Branch Target

Address Adders

Return Address Stack

16 x 16 Bytes

Fetch Unit

16 Instruction Bytes

plus

16 Sets of Predecode Bits

Instruction Buffer

Figure 3. The Instruction Buffer

Instruction Decode

The AMD-K6-2E+ processor decode logic is designed to decode

multiple x86 instructions per clock (see Figure 4 on page 19).

The decode logic accepts x86 instruction bytes and their

predecode bits from the instruction buffer, locates the actual

instruction boundaries, and generates RISC86 operations from

these x86 instructions.

RISC86 operations are fixed-length internal instructions. Most

RISC86 operations execute in a single clock. RISC86 operations

are combined to perform every function of the x86 instruction

set. Some x86 instructions are decoded into as few as zero

RISC86 operations—for instance a NOP—or one RISC86

18

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

operation—a register-to-register add. More complex x86

instructions are decoded into several RISC86 operations.

Instruction Buffer

Short Decoder #1

Short Decoder #2

Long Decoder

On-Chip ROM

Vector Decoder

RISC86^®Sequencer

Vector Address

4 RISC86 Operations

Figure 4. AMD-K6™-2E+ Processor Decode Logic

The AMD-K6-2E+ processor uses a combination of decoders to

convert x86 instructions into RISC86 operations. The hardware

consists of three sets of decoders—two parallel short decoders,

one long decoder, and one vector decoder.

Parallel Short Decoders. The two parallel short decoders translate

the most commonly-used x86 instructions (moves, shifts,

branches, ALU, FPU) and the extensions to the x86 instruction

set (including MMX and 3DNow! instructions) into zero, one, or

two RISC86 operations each. The short decoders only operate

on x86 instructions that are up to seven bytes long. In addition,

Chapter 2

Internal Architecture

19

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

they are designed to decode up to two x86 instructions per

clock.

Long Decoder. The commonly-used x86 instructions that are

greater than seven bytes but not more than 11 bytes long and

less-commonly-used x86 instructions that are up to seven bytes

long are handled by the long decoder. The long decoder only

performs one decode per clock and generates up to four RISC86

operations.

Vector Decoder. All other translations (complex instructions,

serializing conditions, interrupts and exceptions, etc.) are

handled by a combination of the vector decoder and RISC86

operation sequences fetched from an on-chip ROM. For

complex operations, the vector decoder logic provides the first

set of RISC86 operations and a vector (initial ROM address) to a

sequence of further RISC86 operations. The same types of

RISC86 operations are fetched from the ROM as those that are

generated by the hardware decoders.

Note: Although all three sets of decoders are simultaneously fed a

copy of the instruction buffer contents, only one of the three

types of decoders is used during any one decode clock.

Grouped Operations. The decoders or the on-chip RISC86 ROM

always generate a group of four RISC86 operations. For decodes

that cannot fill the entire group with four RISC86 operations,

RISC86 NOP operations are placed in the empty locations of

the grouping. For example, a long-decoded x86 instruction that

converts to only three RISC86 operations is padded with a

single RISC86 NOP operation and then passed to the scheduler.

Up to six groups or 24 RISC86 operations can be placed in the

scheduler at a time.

Floating Point Instructions. All of the common, and a few of the

uncommon, floating-point instructions (also known as ESC

instructions) are hardware decoded as short decodes. This

decode generates a RISC86 floating-point operation and,

optionally, an associated floating-point load or store operation.

Floating-point or ESC instruction decode is only allowed in the

first short decoder, but non-ESC instructions can be decoded

simultaneously by the second short decoder along with an ESC

instruction decode in the first short decoder.

20

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

MMX™ and 3DNow!™ Instructions. All of the MMX and 3DNow!

instructions, with the exception of the EMMS, FEMMS, and

PREFETCH instructions, are hardware decoded as short

decodes. The MMX instruction decode generates a RISC86

MMX operation and, optionally, an associated MMX load or

store operation. A 3DNow! instruction decode generates a

RISC86 3DNow! operation and, optionally, an associated load or

store operation. MMX and 3DNow! instructions can be decoded

in either or both of the short decoders.

2.4

Centralized Scheduler

The scheduler is the heart of the AMD-K6-2E+ processor (see

Figure 5 on page 22). It contains the logic necessary to manage

out-of-order execution, data forwarding, register renaming,

simultaneous issue and retirement of multiple RISC86

operations, and speculative execution.

The scheduler’s buffer can hold up to 24 RISC86 operations.

This equates to a maximum of 12 x86 instructions. The

scheduler can issue RISC86 operations from any of the 24

locations in the buffer. When possible, the scheduler can

simultaneously issue a RISC86 operation to any available

execution unit (store, load, branch, register X

integer/multimedia, register Y integer/multimedia, or

floating-point). In total, the scheduler can issue up to six and

retire up to four RISC86 operations per clock.

The main advantage of the scheduler and its operation buffer is

the ability to examine an x86 instruction window equal to 12

x86 instructions at one time. This advantage is due to the fact

that the scheduler operates on the RISC86 operations in

parallel and allows the AMD-K6-2E+ processor to perform

dynamic on-the-fly instruction code scheduling for optimized

execution. Although the scheduler can issue RISC86 operations

for out-of-order execution, it always retires x86 instructions in

order.

Chapter 2

Internal Architecture

21

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

From Decode Logic

RISC86 #1

RISC86 #2

RISC86 #0

RISC86 #3

Centralized RISC86^®

Operation Scheduler

RISC86 Issue Buses

RISC86 Operation Buffer

Figure 5. AMD-K6™-2E+ Processor Scheduler

2.5

Execution Units

The AMD-K6-2E+ processor contains ten parallel execution

units—store, load, integer X ALU, integer Y ALU, MMX ALU

(X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU,

floating-point, and branch condition. Each unit is independent

and capable of handling the RISC86 operations issued to it.

Table 1 on page 23 details the execution units, functions

performed within these units, operation latency, and operation

throughput.

Note that the integer, MMX, and 3DNow! execution units share

the register X and Y issue pipelines. See “Register X and Y

Pipelines” on page 24.

The store and load execution units are two-stage pipelined

designs.

■ The store unit performs data writes and register calculation

for LEA/PUSH instructions. Data memory and register

22

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

writes from stores are available after one clock. Store

operations are held in a store queue prior to execution. From

there, they execute in order.

■ The load unit performs data memory reads. Data is available

from the load unit after two clocks.

The Integer X execution unit can operate on all ALU

operations, multiplies, divides (signed and unsigned), shifts,

and rotates.

The Integer Y execution unit can operate on the basic word and

doubleword ALU operations—ADD, AND, CMP, OR, SUB,

XOR, zero-extend and sign-extend operands.

The branch condition unit is separate from the branch

prediction logic (see “Branch-Prediction Logic” on page 25) in

that it resolves conditional branches such as JCC and LOOP

after the branch condition has been evaluated.

Table 1. Execution Latency and Throughput of Execution Units

Functional Unit

Store

Function

Latency Throughput

LEA/PUSH, Address (Pipelined)

Memory Store (Pipelined)

Memory Loads (Pipelined)

Integer ALU

1

Load

2

1

Integer X

Integer Multiply

2–3

1

2–3

1

Integer Shift

MMX ALU

1

Multimedia

(processes

MMX instructions)

MMX Shifts, Packs, Unpack

MMX Multiply

1

2

1

Integer Y

Branch

FPU

Basic ALU (16-bit and 32-bit operands)

Resolves Branch Conditions

FADD, FSUB, FMUL

3DNow! ALU

1

2

1

3DNow!

3DNow! Multiply

2

1

3DNow! Convert

2

1

Chapter 2

Internal Architecture

23

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Register X and Y

Pipelines

The functional units that execute MMX and 3DNow!

instructions share pipeline control with the Integer X and

Integer Y units.

The register X and Y functional units are attached to the issue

bus for the register X execution pipeline or the issue bus for the

register Y execution pipeline or both.

Each register pipeline has dedicated resources that consist of

an integer execution unit and an MMX ALU execution unit,

therefore allowing superscalar operation on integer and MMX

instructions.

In addition, both the X and Y issue buses are connected to the

3DNow! ALU, the MMX/3DNow! multiplier and MMX shifter,

which allows the appropriate RISC86 operation to be issued

through either bus. Figure 6 shows the details of the X and Y

register pipelines.

Scheduler

Buffer

(24 RISC86^®Operations)

Issue Bus

for the

Register X

Execution

Pipeline

Issue Bus

for the

Register Y

Execution

Pipeline

Integer X

ALU

MMXÉ

ALU

MMX

Shifter

3DNow!

ALU

MMX

ALU

Integer Y

ALU

MMX/

3DNow!É

Multiplier

Figure 6. Register X and Y Pipeline Functional Units

24

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

2.6

Branch-Prediction Logic

Sophisticated branch logic that can minimize or hide the impact

of changes in program flow is designed into the AMD-K6-2E+

processor. Branches in x86 code fit into two categories:

■ Unconditional branches always change program flow (that is,

the branches are always taken)

■ Conditional branches may or may not divert program flow

(that is, the branches are taken or not-taken). When a

conditional branch is not taken, the processor simply

continues decoding and executing the next instructions in

memory.

Typical applications have up to 10% of unconditional branches

and another 10% to 20% conditional branches. The

AMD-K6-2E+ processor branch logic has been designed to

handle this type of program behavior and to minimize its

negative effects on instruction execution, such as stalls due to

delayed instruction fetching and the draining of the processor

pipeline. The branch logic contains an 8192-entry branch

history table, a 16-entry by 16-byte branch target cache, a

16-entry return address stack, and a branch execution unit.

Branch History Table

The AMD-K6-2E+ processor handles unconditional branches

without any penalty by redirecting instruction fetching to the

target address of the unconditional branch. However,

conditional branches require the use of the dynamic

branch-prediction mechanism built into the AMD-K6-2E+

processor.

A two-level adaptive history algorithm is implemented in an

8192-entry branch history table. This table stores executed

branch information, predicts individual branches, and predicts

the behavior of groups of branches.

To accommodate the large branch history table, the

AMD-K6-2E+ processor does not store predicted target

addresses. Instead, the branch target addresses are calculated

on-the-fly using ALUs during the decode stage. The adders

calculate all possible target addresses before the instructions

are fully decoded and the processor chooses which addresses

are valid.

Chapter 2

Internal Architecture

25

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Branch Target Cache

To avoid a one clock cache-fetch penalty when a branch is

predicted taken, a built-in branch target cache supplies the first

16 bytes of instructions directly to the instruction buffer

(assuming the target address hits this cache). (See Figure 3 on

page 18.)

The branch target cache is organized as 16 entries of 16 bytes.

In total, the branch prediction logic achieves branch prediction

rates greater than 95%.

Return Address Stack

The return address stack is a special device designed to

optimize CALL and RET pairs. Software is typically compiled

with subroutines that are frequently called from various places

in a program. This is usually done to save space.

Entry into the subroutine occurs with the execution of a CALL

instruction. At that time, the processor pushes the address of

the next instruction in memory following the CALL instruction

onto the stack (allocated space in memory). When the processor

encounters a RET instruction (within or at the end of the

subroutine), the branch logic pops the address from the stack

and begins fetching from that location. To avoid the latency of

main memory accesses during CALL and RET operations, the

return address stack caches the pushed addresses.

Branch Execution

Unit

The branch execution unit enables efficient speculative

execution. This unit gives the processor the ability to execute

instructions beyond conditional branches before knowing

whether the branch prediction was correct.

The AMD-K6-2E+ processor does not permanently update the

x86 registers or memory locations until all speculatively

executed conditional branch instructions are resolved. When a

prediction is incorrect, the processor backs out to the point of

the mispredicted branch instruction and restores all registers.

The AMD-K6-2E+ processor can support up to seven

outstanding branches.

26

Internal Architecture

Chapter 2

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

3

Software Environment

This chapter provides a general overview of the AMD-K6-2E+

processor’s x86 software environment and briefly describes the

data types, registers, operating modes, interrupts, and

instructions supported by the AMD-K6-2E+ processor

architecture and design implementation.

The AMD-K6-2E+ processor implements the same ten Model-

Specific Registers (MSRs) as the AMD-K6-2 and AMD-K6-2E

processors Model 8/[F:8], and the bits and fields within these

ten MSRs are defined identically. The AMD-K6-2E+ processor

supports an additional MSR for cache control. The low-power

versions of the AMD-K6-2E+ processor support a twelfth MSR

to control the AMD PowerNow! technology functions.

See “Model-Specific Registers (MSR)” on page 44 for the MSR

definitions.

The model number for the AMD-K6-2E+ processor is Model

D/[7:4], where the actual stepping can be any value in the range

[7:4].

3.1

Registers

The AMD-K6-2E+ processor contains all the registers defined

by the x86 architecture, including general-purpose, segment,

floating-point, MMX/3DNow!, EFLAGS, control, task, debug,

test, and descriptor/memory-management registers.

In addition, this chapter provides information on the

AMD-K6-2E+ processor MSRs.

Note: Areas of the register designated as Reserved should not be

modified by software.

Chapter 3

Software Environment

27

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

General-Purpose

Registers

The eight 32-bit x86 general-purpose registers are used to hold

integer data or memory pointers used by instructions. Table 2

contains a list of the general-purpose registers and the

functions for which they are used.

Table 2. General-Purpose Registers

Register Function

EAX

EBX

ECX

EDX

EDI

ESI

Commonly used as an accumulator

Commonly used as a pointer

Commonly used for counting in loop operations

Commonly used to hold I/O information and to pass parameters

Commonly used as a destination pointer by the ES segment

Commonly used as a source pointer by the DS segment

Used to point to the stack segment

ESP

EBP

Used to point to data within the stack segment

In order to support byte and word operations, EAX, EBX, ECX,

and EDX can also be used as 8-bit and 16-bit registers. The

shorter registers are overlaid on the longer ones. For example,

the name of the 16-bit version of EAX is AX (low 16 bits of

EAX) and the 8-bit names for AX are AH (high order bits) and

AL (low order bits). The same naming convention applies to

EBX, ECX, and EDX.

EDI, ESI, ESP, and EBP can be used as smaller 16-bit registers

called DI, SI, SP, and BP respectively, but these registers do not

have 8-bit versions. Figure 7 shows the EAX register with its

name components, and Table 3 on page 29 lists the doubleword

(32-bit) general-purpose registers and their corresponding word

(16-bit) and byte (8-bit) versions.

31

16 15

8

7

0

EAX

AX

AL

AH

Figure 7. EAX Register with 16-Bit and 8-Bit Name Components

28

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 3. General-Purpose Register Doubleword, Word, and Byte Names

32-Bit Name

(Doubleword)

16-Bit Name

(Word)

8-Bit Name

(High-order Bits) (Low-order Bits)

8-Bit Name

EAX

EBX

ECX

EDX

EDI

ESI

AX

BX

CX

DX

DI

AH

BH

CH

DH

–

AL

BL

CL

DL

–

SI

–

ESP

EBP

SP

BP

–

Integer Data Types

Four types of data are used in general-purpose registers—byte,

word, doubleword, and quadword integers. Figure 8 shows the

format of the integer data registers.

Byte Integer

7

0

Precision —

8 Bits

Word Integer

15

0

Precision — 16 Bits

Doubleword Integer

31

0

Precision — 32 Bits

Quadword Integer

63

0

Precision — 64 Bits

Figure 8. Integer Data Registers

Chapter 3

Software Environment

29

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Segment Registers

The six 16-bit segment registers are used as pointers to areas

(segments) of memory. Table 4 lists the segment registers and

their functions. Figure 9 shows the format for all six segment

registers.

Table 4. Segment Registers

Segment

Segment Register Function

Register

CS

DS

ES

FS

GS

SS

Code segment, where instructions are located

Data segment, where data is located

Stack segment

15

0

Figure 9. Segment Register

Segment Usage

The operating system determines the type of memory model

that is implemented. The segment register usage is determined

by the operating system’s memory model. In a real mode

memory model, the segment register points to the base address

in memory.

In a protected mode memory model the segment register is

called a selector and it selects a segment descriptor in a

descriptor table. This descriptor contains a pointer to the base

of the segment, the limit of the segment, and various protection

attributes. For more information on descriptor formats, see

“Descriptors and Gates” on page 59. Figure 10 on page 31 shows

segment usage for Real mode and Protected mode memory

models.

30

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Physical Memory

Segment Base

Segment Register

Real Mode Memory Model

Descriptor Table

Physical Memory

Base

Limit

Base

Limit

Segment Base

Segment Selector

Protected Mode Memory Model

Figure 10. Segment Usage

Instruction Pointer

The instruction pointer (EIP or IP) is used in conjunction with

the code segment register (CS). The instruction pointer is

either a 32-bit register (EIP) or a 16-bit register (IP) that keeps

track of where the next instruction resides within memory. This

register cannot be directly manipulated, but can be altered by

modifying return pointers when a JMP or CALL instruction is

used.

Floating-Point

Registers

The floating-point execution unit in the AMD-K6-2E+ processor

is designed to perform mathematical operations on non-integer

numbers. This floating-point unit conforms to the IEEE 754 and

854 standards and uses several registers to meet these

standards—eight numeric floating-point registers, a status

word register, a control word register, and a tag word register.

Chapter 3

Software Environment

31

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The eight floating-point registers are physically 80 bits wide

and labeled FPR0–FPR7. Figure 11 shows the format of the

floating-point registers. See “Floating-Point Register Data

Types” on page 34 for information on allowable floating-point

data types.

79 78

Sign

64 63

0

Exponent

Significand

Figure 11. Floating-Point Register

The 16-bit FPU status word register contains information about

the state of the floating-point unit. Figure 12 shows the format

of the FPU status word register.

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

C

2

C

1

C

0

E

S

F

P

E

U

E

O

E

Z

E

I

E

C

3

D

E

B

TOSP

Symbol

B

C3

TOSP

C2

C1

C0

ES

SF

Description

FPU Busy

Bits

15

14

13–11

10

9

8

7

6

Condition Code

Top of Stack Pointer

Condition Code

Error Summary Status

Stack Fault

Exception Flags

Precision Error

Underflow Error

Overflow Error

Zero Divide Error

Denormalized Operation Error 1

Invalid Operation Error

TOSP Information

000 = FPR0

PE

UE

OE

ZE

DE

IE

5

4

3

2

0

111 = FPR7

Figure 12. FPU Status Word Register

32

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The FPU control word register allows a programmer to manage

the FPU processing options. Figure 13 shows the format of the

FPU control word register.

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Y

R

C

P

C

P

U

O

Z

I

M

D

M

M M M M

Reserved

Symbol

Description

Bits

Y

Infinity Bit (80287 compatibility) 12

RC

PC

Rounding Control

Precision Control

Exception Masks

Precision

Underflow

Overflow

Zero Divide

Denormalized Operation

Invalid Operation

11–10

9–8

PM

UM

OM

ZM

DM

IM

5

4

3

2

1

0

Rounding Control Information

00b = Round to the nearest or even number

01b = Round down toward negative infinity

10b = Round up toward positive infinity

11b = Truncate toward zero

Precision Control Information

00b = 24 bits Single Precision Real

01b = Reserved

10b = 53 bits Double Precision Real

11b = 64 bits Extended Precision Real

Figure 13. FPU Control Word Register

The FPU tag word register contains information about the

registers in the register stack. Figure 14 shows the format of the

FPU tag word register.

15

14 13

12 11

10 9

8 7

6 5

4 3

2 1

0

TAG

(FPR7)

TAG

(FPR6) (FPR5) (FPR4) (FPR3) (FPR2) (FPR1) (FPR0)

Tag Values

00 = Valid

01 = Zero

10 = Special

11 = Empty

Figure 14. FPU Tag Word Register

Chapter 3

Software Environment

33

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Floating-Point

Register Data Types

Floating-point registers use four different types of data—

packed decimal, single-precision real, double-precision real,

and extended-precision real. Figures 15 and 16 show the

formats for these registers.

79 78 72 71

0

Ignore

or

S

Precision — 18 Digits, 72 Bits Used, 4-Bits/Digit

Zero

Description

Ignored on Load, Zeros on Store 78-72

Sign Bit 79

Bits

Figure 15. Packed Decimal Data Register

31 30

23 22

0

Single-Precision Real

Biased

Exponent

Significand

S

S= Sign Bit

Double-Precision Real

63 62

S

52 51

0

Biased

Exponent

Significand

S = Sign Bit

Extended-Precision Real

79 78

S

64 63 62

0

Biased

Exponent

I

Significand

S= Sign Bit

I = Integer Bit

Figure 16. Precision Real Data Registers

34

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

MMX™/3DNow!™

Registers

The AMD-K6-2E+ processor implements eight 64-bit

MMX/3DNow! registers for use by multimedia software. These

registers are mapped on the floating-point register stack. The

MMX and 3DNow! instructions refer to these registers as mm0

to mm7. Figure 17 shows the format of these registers. For more

®

information, see the AMD-K6 Processor Multimedia Technology

Manual, order# 20726 and the 3DNow! Technology Manual,

order# 21928.

63

0

mm0

mm1

mm2

mm3

mm4

mm5

mm6

mm7

Figure 17. MMX™/3DNow!™ Registers

Chapter 3

Software Environment

35

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

MMX™ Technology

Data Types

For the MMX instructions, the MMX registers use three types of

data—packed eight-byte integer, packed quadword integer, and

packed dual doubleword integer. Figure 18 on page 36 shows

the format of these data types.

Packed Bytes Integer

63

56 55

48 47

40 39

32 31

24 23

16 15

8

7

0

Byte 7

Byte 6

Byte 5

Byte 4

Byte 3

Byte 2

Byte 1

Byte 0

Packed Words Integer

63

48 47

16 15

Word 3

Word 2

Word 1

Word 0

Packed Doubleword Integer

63

Doubleword 1

Doubleword 0

Figure 18. MMX™ Technology Data Types

36

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

3DNow!™ Technology

Data Types

For 3DNow! instructions, the MMX/3DNow! registers use

packed single-precision real data. Figure 19 shows the format of

the 3DNow! data type.

Packed Single Precision Floating Point

0

63 62

S

55 54

Biased

32 31 30

23 22

Biased

Exponent

S

Significand

Exponent

S = Sign Bit

Figure 19. 3DNow!™ Technology Data Types

Chapter 3

Software Environment

37

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

EFLAGS Register

The EFLAGS register provides for three different types of

flags—system, control, and status. The system flags provide

operating system controls, the control flag provides directional

information for string operations, and the status flags provide

information resulting from logical and arithmetic operations.

Figure 20 shows the format of the EFLAGS register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

I

V

I

P

V

I

F

O

P

L

I

D

A

C

V

M

R

F

N

T

O

F

D

F

I

F

T

F

S

F

Z

F

A

F

P

F

C

F

Reserved

Symbol

ID

Description

ID Flag

Bits

21

20

19

18

17

16

14

13–12

11

10

9

VIP

VIF

AC

VM

RF

NT

IOPL

OF

DF

IF

Virtual Interrupt Pending

Virtual Interrupt Flag

Alignment Check

Virtual-8086 Mode

Resume Flag

Nested Task

I/O Privilege Level

Overflow Flag

Direction Flag

Interrupt Flag

Trap Flag

TF

8

SF

Sign Flag

7

ZF

Zero Flag

6

AF

PF

Auxiliary Flag

Parity Flag

4

2

CF

Carry Flag

0

Figure 20. EFLAGS Registers

38

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Control Registers

31

The five control registers contain system control bits and

pointers. Figures 21 through 25 show the formats of the control

registers.

7

6

5

4

3

2

1

0

M

C

E

P

S

E

T

S

D

P

V

I

V

M

E

D

E

Reserved

Symbol

MCE

PSE

Description

Machine Check Enable

Page Size Extensions

Bit

6

4

DE

TSD

PVI

Debugging Extensions

Time Stamp Disable

Protected Virtual Interrupts

Virtual-8086 Mode Extensions

3

2

1

0

VME

Figure 21. Control Register 4 (CR4)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Page Directory Base

9

8

7

6

5

4

3

2

1

0

P

W

T

P

C

D

Reserved

Symbol

PCD

Description

Page Cache Disable

Bit

4

PWT

Page Writethrough

3

Figure 22. Control Register 3 (CR3)

31

0

Page Fault Linear Address

Figure 23. Control Register 2 (CR2)

Chapter 3

Software Environment

39

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

31

0

Reserved

Figure 24. Control Register 1 (CR1)

Symbol

PG

CD

NW

Description

Paging

Cache Disable

Not Writethrough

Bit

31

30

29

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

P

G

C

N

A

M

W

P

N

E

T

S

E

M

P

E

D W

Reserved

Symbol

AM

WP

NE

ET

TS

EM

MP

PE

Description

Alignment Mask

Write Protect

Numeric Error

Extension Type

Task Switched

Emulation

Bit

18

16

5

4

3

2

1

0

Monitor Coprocessor

Protection Enabled

Figure 25. Control Register 0 (CR0)

40

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Debug Registers

Figures 26 through 29 show the 32-bit debug registers

supported by the processor. These registers are further

described in “Debug” on page 268.

Symbol

LEN 3

R/W 3

LEN 2

R/W 2

LEN 1

R/W 1

LEN 0

R/W 0

Description

Length of Breakpoint #3

Bits

31–30

Type of Transaction(s) to Trap 29–28

Length of Breakpoint #2 27–26

Type of Transaction(s) to Trap 25–24

Length of Breakpoint #1 23–22

Type of Transaction(s) to Trap 21–20

Length of Breakpoint #0 19–18

Type of Transaction(s) to Trap 17–16

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

G

D

G

E

L

E

G

3

L

3

G

2

L

2

G

1

L

1

G

0

L

0

LEN

3

R/W LEN R/W

LEN

1

R/W LEN

R/W

0

3

2

1

0

Reserved

Symbol

GD

GE

LE

Description

General Detect Enabled

Global Exact Breakpoint Enabled

Local Exact Breakpoint Enabled

Bit

13

9

8

G3

L3

G2

L2

G1

L1

G0

L0

Global Exact Breakpoint # 3 Enabled

Local Exact Breakpoint # 3 Enabled

Global Exact Breakpoint # 2 Enabled

Local Exact Breakpoint # 2 Enabled

Global Exact Breakpoint # 1 Enabled

Local Exact Breakpoint # 1 Enabled

Global Exact Breakpoint # 0 Enabled

Local Exact Breakpoint # 0 Enabled

7

6

5

4

3

2

1

0

Figure 26. Debug Register DR7

Chapter 3

Software Environment

41

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

B

D

B

S

B

3

B

2

B

1

B

0

B

T

Reserved

Symbol

BT

BS

Description

Breakpoint Task Switch

Breakpoint Single Step

Bit

15

14

BD

B3

B2

B1

B0

Breakpoint Debug Access Detected 13

Breakpoint #3 Condition Detected

Breakpoint #2 Condition Detected

Breakpoint #1 Condition Detected

Breakpoint #0 Condition Detected

3

2

1

0

Figure 27. Debug Register DR6

DR5

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reserved

DR4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Reserved

9

8

7

6

5

4

3

2

1

0

Figure 28. Debug Registers DR5 and DR4

42

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

DR3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 3 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

DR2

DR1

DR0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 2 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 1 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 0 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

Figure 29. Debug Registers DR3, DR2, DR1, and DR0

Chapter 3

Software Environment

43

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

3.2

Model-Specific Registers (MSR)

The AMD-K6-2E+ processor provides eleven Model-Specific

Registers (MSRs) in the standard-power versions and twelve

MSRs in the low-power versions.

■ The value in the ECX register selects the MSR to be

addressed by the RDMSR and WRMSR instructions.

■ The values in EAX and EDX are used as inputs and outputs

by the RDMSR and WRMSR instructions.

Table 5 lists the MSRs and the corresponding value of the ECX

register. Figures 30 through 43 starting on page 45 show the

MSR formats.

Table 5. AMD-K6™-2E+ Processor Model-Specific Registers

Model-Specific Register

Value of ECX

00h

Machine Check Address Register (MCAR)

Machine Check Type Register (MCTR)

Test Register 12 (TR12)

01h

0Eh

Time Stamp Counter (TSC)

10h

Extended Feature Enable Register (EFER)

SYSCALL/SYSRET Target Address Register (STAR)

Write Handling Control Register (WHCR)

UC/WC Cacheability Control Register (UWCCR)

Processor State Observability Register (PSOR)

Page Flush/Invalidate Register (PFIR)

Level-2 Cache Array Register (L2AAR)

C000_0080h

C000_0081h

C000_0082h

C000_0085h

C000_0087h

C000_0088h

C000_0089h

C000_0086h

Enhanced Power Management Register (EPMR)¹

Notes:

1. The EPMR register is supported in the low-power versions only of the AMD-K6-2E+ processor.

For more information about the MSRs, see the Embedded

AMD-K6™ Processors BIOS Design Guide Application Note, order#

23913.

For more information about the RDMSR and WRMSR

instructions, see the AMD K86™ Family BIOS and Software Tools

Development Guide, order# 21062.

44

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Machine Check

Address Register

(MCAR) and Machine

Check Type Register

(MCTR)

The AMD-K6-2E+ processor does not support the generation of

a machine check exception. However, the processor does

provide a 64-bit machine check address register (MCAR), a

64-bit machine check type register (MCTR), and a machine

check enable (MCE) bit in CR4.

Because the processor does not support machine check

exceptions, the contents of the MCAR and MCTR are only

affected by the WRMSR instruction and by RESET being

sampled asserted (where all bits in each register are reset to 0).

The formats for the machine-check address register and the

machine-check type register are shown in Figure 30 and Figure

31, respectively. The MCAR register is MSR 00h, and the MCTR

register is MSR 01h.

63

0

MCAR

Figure 30. Machine-Check Address Register (MCAR)

63

5

4

0

MCTR

Reserved

Figure 31. Machine-Check Type Register (MCTR)

Chapter 3

Software Environment

45

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Test Register 12

(TR12)

Test register 12 provides a method for disabling the L1 caches.

Figure 32 shows the format of TR12. The TR12 register is MSR

0Eh.

63

4

2

1

0

3

C

I

Symbol Description

CI Cache Inhibit Bit

Bit

3

Reserved

Figure 32. Test Register 12 (TR12)

Time Stamp Counter

With each processor clock cycle, the processor increments the

64-bit time stamp counter (TSC) MSR. Figure 33 shows the

format of the TSC. The TSC register is MSR 10h.

The counter can be written or read using the WRMSR or

RDMSR instructions when the ECX register contains the value

10h and CPL = 0. The counter can also be read using the RDTSC

instruction, but the procedure must be executing at privilege

level 0 for the RDTSC instruction to execute. This condition is

reflected by the status of the Time Stamp Disable (TSD) bit in

CR4.

With either of these instructions, the EDX and EAX registers

hold the upper and lower dwords of the 64-bit value to be

written to or read from the TSC, as follows:

■ EDX—Upper 32 bits of TSC

■ EAX—Lower 32 bits of TSC

The TSC can be loaded with any arbitrary value. This feature is

compatible with the Pentium processor.

63

0

TSC

Figure 33. Time Stamp Counter (TSC)

46

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Extended Feature

Enable Register

(EFER)

The Extended Feature Enable Register (EFER) contains the

control bits that enable the extended features of the processor.

Figure 34 shows the format of the EFER register, and Table 6

defines the function of each bit of the EFER register. The EFER

register is MSR C000_0080h.

63

5

4

3

2

1

0

S

C

E

L

2

D

P

E

EWBEC

Reserved

Symbol

L2D

Description

L2 Cache Disable

Bit

4

EWBEC

DPE

SCE

EWBE# Control

Data Prefetch Enable

System Call Extension

3-2

1

0

Figure 34. Extended Feature Enable Register (EFER)

Table 6. Extended Feature Enable Register (EFER) Definition

Bit

Description

R/W Function

Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits

are always read as 0.

63–5 Reserved

R

If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for debug and

L2D

R/W testing purposes. For normal operation and maximum performance, this bit must be set

to 0 (this is the default setting following reset).

4

This 2-bit field controls the behavior of the processor with respect to the ordering of write

R/W cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE Disable (GEWBED)

and Speculative EWBE Disable (SEWBED), respectively.

EWBE Control

(EWBEC)

3-2

DPE must be set to 1 to enable data prefetching (this is the default setting following

R/W reset). If enabled, cache misses initiated by a memory read within a 32-byte line are

conditionally followed by cache-line fetches of the other line in the 64-byte sector.

Data Prefetch

Enable (DPE)

1

0

System Call

Extension (SCE)

R/W SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions.

For more information about the EWBEC bits, see “EWBE#

Control” on page 229.

Chapter 3

Software Environment

47

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

SYSCALL/SYSRET

Target Address

Register (STAR)

The SYSCALL/SYSRET target address register (STAR)

contains the target EIP address used by the SYSCALL

instruction and the 16-bit code and stack segment selector

bases used by the SYSCALL and SYSRET instructions. Figure

35 shows the format of the STAR register, and Table 7 defines

the function of each bit of the STAR register. For more

information, see the SYSCALL and SYSRET Instruction

Specification Application Note, order# 21086. The STAR register

is MSR C000_0081h.

63

32 31

0

48 47

SYSRET CS Selector and SS

Selector Base

SYSCALL CS Selector and SS

Selector Base

Target EIP Address

Figure 35. SYSCALL/SYSRET Target Address Register (STAR)

Table 7. SYSCALL/SYSRET Target Address Register (STAR) Definition

Bit

Description

R/W

63–48

47–32

31–0

SYSRET CS and SS Selector Base

SYSCALL CS and SS Selector Base

Target EIP Address

Write Handling

Control Register

(WHCR)

The Write Handling Control Register (WHCR) is a MSR that

contains two fields —the Write Allocate Enable Limit

(WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte

(WAE15M) bit (see Figure 36). For more information, see

“Write Allocate” on page 215. The WHCR register is MSR

C000_0082h.

63

32 31

22 21 17 16 15

0

W

A

E

WAELIM

1

5

M

Reserved

Symbol

WAELIM

WAE15M

Description

Write Allocate Enable Limit

Write Allocate Enable 15-to-16-Mbyte 16

Bits

31-22

Note: Hardware RESET initializes this MSR to all zeros.

Figure 36. Write Handling Control Register (WHCR)

48

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

UC/WC Cacheability

Control Register

(UWCCR)

The AMD-K6-2E+ processor provides two variable-range

Memory Type Range Registers (MTRRs)—MTRR0 and

MTRR1—that each specify a range of memory. Each range can

be defined as uncacheable (UC) or write-combining (WC)

memory. For more information, see “Memory Type Range

Registers” on page 231. The UWCCR register is MSR

C000_0085h.

.

Symbol Description

Bits

32

Symbol Description

Bits

0

UC1

Uncacheable Memory Type

UC0

Uncacheable Memory Type

WC1

Write-Combining Memory Type 33

WC0

Write-Combining Memory Type

1

63

49 48

34 33 32 31

17 16

2

1

0

W

C

1

U

C

1

W

C

0

U

C

0

Physical Base Address 1

Physical Address Mask 1

Physical Base Address 0

Physical Address Mask 0

MTRR1

MTRR0

Figure 37. UC/WC Cacheability Control Register (UWCCR)

Processor State

Observability

Register (PSOR)

The AMD-K6-2E+ processor provides the Processor State

Observability Register (PSOR). The PSOR is defined as shown

in Figure 38 for all standard-power versions of the AMD-K6-2E+

processor. For a description of the PSOR register supported by

the low-power versions of the processor, see page 148.

The PSOR register is MSR C000_0087h.

.

63

4

3

2

0

9

8

7

N

O

L

STEP

BF

2

Reserved

Symbol

NOL2

STEP

BF

Description

Bit

8

7-4

2-0

No L2 Functionality

Processor Stepping

Bus Frequency Divisor

Figure 38. Processor State Observability Register (PSOR)

Chapter 3

Software Environment

49

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Page Flush/Invalidate

Register (PFIR)

The AMD-K6-2E+ processor contains the Page Flush/Invalidate

Register (PFIR) (see Figure 39) that allows cache invalidation

and optional flushing of a specific 4-Kbyte page from the linear

address space. For more detailed information on PFIR, see

“Page Flush/Invalidate Register (PFIR)” on page 223. The

PFIR register is MSR C000_0088h.

63

32 31

12 11 9 8 7

1 0

F

/

I

P

F

LINPAGE

Reserved

Symbol

Description

Bit

LINPAGE 20-bit Linear Page Address

31-12

PF

F/I

Page Fault Occurred

Flush/Invalidate Command

8

0

Figure 39. Page Flush/Invalidate Register (PFIR)

Level-2 Cache Array

Access Register

(L2AAR)

The AMD-K6-2E+ processor provides the L2AAR register that

allows for direct access to the L2 cache and L2 tag arrays. The

L2AAR register is MSR C000_0089h.

The operation that is performed on the L2 cache is a function of

the instruction executed—RDMSR or WRMSR—and the

contents of the EDX register. The EDX register specifies the

location of the access, and whether the access is to the L2 cache

data or tags (refer to Figure 40).

50

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Symbol Description

Bit

T/D

Way

Selects Tag (1) or Data (0) access

Selects desired cache way

20

17-16

31

21 20 19 18 17 16 15 14

T

6

5

4

3 2

1

0

D

w

L

i

n

e

Octet

Way

/

Set

o

r

D

d

Reserved

Symbol Description

Bit

14-6

5

Set

Selects the desired cache set

Line

Octet

Selects Line1 (1) or Line0 (0)

Selects one of four octets

4-3

Dword Selects upper (1) or lower (0) dword

2

Figure 40. L2 Tag or Data Location for AMD-K6™-2E+ Processor—EDX

If the L2 cache data is read (as opposed to reading the tag

information), the result (doubleword) is placed in EAX in the

format as illustrated in Figure 41. Similarly, if the L2 cache data

is written, the write data is taken from EAX.

31

0

Data

Figure 41. L2 Data —EAX

If the L2 tag is read (as opposed to reading the cache data), the

result is placed in EAX in the format as illustrated in Figure 42

on page 52. Similarly, if the L2 tag is written, the write data is

taken from EAX.

Chapter 3

Software Environment

51

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

31

14 13 12 11 10 9

8

7

0

C

M

D

Line1ST Line0ST

Tag

LRU

Reserved

Symbol Description

Tag Tag data read or written

Bit

31-14

Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10

Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8

LRU

Two bits of LRU for each way

7-0

Figure 42. L2 Tag Information for AMD-K6™-2E+ Processor—EAX

For more detailed information, refer to “L2 Cache and Tag

Array Testing” on page 264.

Enhanced Power

ManagementRegister

(EPMR)

The AMD-K6-2E+ processor is designed with enhanced power

management features, called AMD PowerNow! technology,

which include dynamic bus divisor control and dynamic core

voltage control. The EPMR register (see Figure 43) defines the

base address for a 16-byte block of I/O address space. Enabling

the EPMR allows software to access the EPM 16-byte I/O block,

which contains bits for enabling, controlling, and monitoring

the AMD PowerNow! technology features. The EPMR is MSR

C000_0086h.

See “AMD PowerNow!™ Technology” on page 143 for more

information about the definition and use of this register.

Additional information can be found in the Embedded

AMD-K6™ Processors BIOS Design Guide Application Note, order#

23913.

52

Software Environment

Chapter 3

Preliminary Information

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

3

1

0

4

2

63

16 15

G

S

B

C

E

IOBASE

M

N

D

Reserved

Symbol

IOBASE

GSBC

EN

Description

I/O Base Address

Generate Special Bus Cycle

Enable AMD PowerNow! Technology

Management

Bit

15-4

1

0

Figure 43. Enhanced Power Management Register (EPMR)

Chapter 3

Software Environment

53

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

3.3

Memory Management Registers

The AMD-K6-2E+ processor controls segmented memory

management with the registers listed in Table 8. Figure 44

shows the formats of these registers.

Table 8. Memory Management Registers

Register Name

Function

Global Descriptor Table Register

Interrupt Descriptor Table Register

Local Descriptor Table Register

Task Register

Contains a pointer to the base of the global descriptor table

Contains a pointer to the base of the interrupt descriptor table

Contains a pointer to the local descriptor table of the current task

Contains a pointer to the task state segment of the current task

Global and Interrupt Descriptor Table Registers

15

16

0

47

32-Bit Linear Base Address

16-Bit Limit

Selector

Local Descriptor Table Register and Task Register

15

0

63

32 31

0

32-Bit Linear Base Address

32-Bit Limit

15

0

Attributes

Figure 44. Memory Management Registers

54

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Task State Segment

Figure 45 shows the format of the task state segment (TSS).

31

0

TSS Limit

from TR

I/O Permission Bitmap (IOPB)

(up to 8 Kbytes)

Interrupt Redirection Bitmap (IRB)

(eight 32-bit locations)

Operating System

Data Structure

Base Address of IOPB

0000h

T

64h

0000h

LDT Selector

GS

FS

DS

SS

CS

0000h

ES

EDI

ESI

EBP

ESP

EBX

EDX

ECX

EAX

EFLAGS

EIP

CR3

SS2

0000h

ESP2

ESP1

ESP0

SS1

SS0

Link (Prior TSS Selector)

0

Figure 45. Task State Segment (TSS)

Chapter 3

Software Environment

55

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

3.4

Paging

The AMD-K6-2E+ processor can physically address up to four

Gbytes of memory. This memory can be segmented into pages.

The size of these pages is determined by the operating system

design and the values set up in the page directory entries (PDE)

and page table entries (PTE).

The processor can access both 4-Kbyte pages and 4-Mbyte

pages, and the page sizes can be intermixed within a page

directory. When the page size extension (PSE) bit in CR4 is set,

the processor translates linear addresses using either the

4-Kbyte translation lookaside buffer (TLB) or the 4-Mbyte TLB,

depending on the state of the page size (PS) bit in the page

directory entry. Figures 46 and Figure 47 on page 57 show how

4-Kbyte and 4-Mbyte page translations work.

4-Kbyte

Page

Directory

Physical

Address

PDE

CR3

31

22 21

0

Page Directory

Offset

Page

Offset

Linear Address

Figure 47. 4-Mbyte Paging Mechanism

Figures 48 through 50 starting on page 58 show the formats of

the PDE and PTE. These entries contain information regarding

the location of pages and their status.

Chapter 3

Software Environment

57

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

31

12 11 10

9

8

7

0

6

5

A

4

3

2

1

0

P

U

/

S

P

W

T

W

/

R

A

V

L

P

C

D

Page Table Base Address

Symbol

Description

Bits

AVL

Available to Software

Reserved

Page Size

Reserved

Accessed

Page Cache Disable

Page Writethrough

User/Supervisor

Write/Read

11–9

8

7

6

5

4

3

2

1

0

PS

A

PCD

PWT

U/S

W/R

P

Present (valid)

Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE)

31

22 21

12 11 10

9

8

7

1

6

5

A

4

3

2

1

0

P

U

/

S

A

V

L

P

W

T

W

/

R

P

C

D

Physical Page Base Address

Reserved

Symbol

AVL

Description

Available to Software

Reserved

Page Size

Reserved

Bits

11–9

8

7

6

5

4

3

2

1

0

PS

A

Accessed

PCD

PWT

U/S

W/R

P

Page Cache Disable

Page Writethrough

User/Supervisor

Write/Read

Present (valid)

Figure 49. Page Directory Entry 4-Mbyte Page Table (PDE)

58

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

31

12 11 10

9

8

7

6

5

A

4

3

2

1

0

P

U

/

S

P

W

T

W

/

R

A

V

L

P

C

D

Physical Page Base Address

Symbol

Description

Bits

AVL

Available to Software

Reserved

Dirty

11–9

8–7

6

D

A

Accessed

5

PCD

PWT

U/S

W/R

P

Page Cache Disable

Page Writethrough

User/Supervisor

Write/Read

4

3

2

1

Present (valid)

0

Figure 50. Page Table Entry (PTE)

3.5

Descriptors and Gates

There are various types of structures and registers in the x86

architecture that define, protect, and isolate code segments,

data segments, task state segments, and gates. These structures

are called descriptors.

■ The application segment descriptor is used to point to either a

data or code segment. Figure 51 on page 60 shows the

application segment descriptor format. Table 9 on page 60

contains information describing the memory segment type

to which the descriptor points.

■ The system segment descriptor is used to point to a task state

segment, a call gate, or a local descriptor table. Figure 52 on

page 61 shows the system segment descriptor format.

Table 10 on page 61 contains information describing the

type of segment or gate to which the descriptor points.

■ The AMD-K6-2E+ processor uses gates to transfer control

between executable segments with different privilege

levels. Figure 53 on page 62 shows the format of the gate

descriptor types. Table 10 on page 61 contains information

describing the type of segment or gate to which the

descriptor points.

Chapter 3

Software Environment

59

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Symbol

G

Description

Granularity

Bits

23

D

32-Bit/16-Bit

22

AVL

P

DPL

DT

Available to Software

Present/Valid Bit

Descriptor Privilege Level

Descriptor Type

20

15

14-13

12

Reserved

Type See Table 9

11-8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

A

9

8

7

6

5

4

3

2

1

0

Base Address 31–24

G

D

Segment

Limit

P

DPL

1

Type

Base Address 23–16

V

L

Base Address 15–0

Segment Limit 15–0

Figure 51. Application Segment Descriptor

Table 9. Application Segment Types

Type Data/Code Description

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Read-Only

Read-Only—Accessed

Read/Write

Read/Write—Accessed

Read-Only—Expand-down

Data

Read-Only—Expand-down, Accessed

Read/Write—Expand-down

Read/Write—Expand-down, Accessed

Execute-Only

Execute-Only—Accessed

Execute/Read

Execute/Read—Accessed

Code

Execute-Only—Conforming

Execute-Only—Conforming, Accessed

Execute/Read-Only—Conforming

Execute/Read-Only—Conforming, Accessed

60

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Symbol

G

Description

Granularity

Bits

23

X

Not Needed

22

AVL

P

Availability to Software

Present/Valid Bit

20

15

Reserved

DPL

DT

Descriptor Privilege Level

Descriptor Type

14-13

12

Type See Table 10

11-8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

A

9

8

7

6

5

4

3

2

1

0

Base Address 31–24

G

X

Segment

Limit

P

DPL

0

Type

Base Address 23–16

V

L

Base Address 15–0

Segment Limit 15–0

Figure 52. System Segment Descriptor

Table 10. System Segment and Gate Types

Type Description

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Reserved

Available 16-bit TSS

LDT

Busy 16-bit TSS

16-bit Call Gate

Task Gate

16-bit Interrupt Gate

16-bit Trap Gate

Reserved

Available 32-bit TSS

Reserved

Busy 32-bit TSS

32-bit Call Gate

Reserved

32-bit Interrupt Gate

32-bit Trap Gate

Chapter 3

Software Environment

61

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Symbol

P

Description

Present/Valid Bit

Bits

15

DPL

DT

Descriptor Privilege Level

Descriptor Type

14-13

12

Reserved

Type See Table 10 on page 61

11-8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Offset 31–16

P

DPL

0

Type

Segment Selector

Offset 15–0

Figure 53. Gate Descriptor

3.6

Exceptions and Interrupts

Table 11 summarizes the exceptions and interrupts.

Table 11. Summary of Exceptions and Interrupts

Interrupt

Interrupt Type

Cause

Number

0

1

Divide by Zero Error

Debug

DIV, IDIV

Debug trap or fault

2

Non-Maskable Interrupt

Breakpoint

NMI signal sampled asserted

3

Int 3

4

Overflow

INTO

5

Bounds Check

BOUND

6

Invalid Opcode

Device Not Available

Double Fault

Invalid instruction

7

ESC and WAIT

8

Fault occurs while handling a fault

—

9

Reserved - Interrupt 13

Invalid TSS

10

11

12

13

14

16

17

0–255

Task switch to an invalid segment

Instruction loads a segment and present bit is 0 (invalid segment)

Stack operation causes limit violation or present bit is 0

Segment related or miscellaneous invalid actions

Page protection violation or a reference to missing page

Arithmetic error generated by floating-point instruction

Segment Not Present

Stack Segment

General Protection

Page Fault

Floating-Point Error

Alignment Check

Software Interrupt

Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are set to 1.)

INT n

62

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

3.7

Instructions Supported by the AMD-K6™-2E+ Processor

This section documents all of the x86 instructions supported by

the AMD-K6-2E+ processor. Tables 12 through 16 starting on

page 65 define the integer, floating-point, MMX, 3DNow!

technology instructions, and 3DNow! technology digital signal

processing (DSP) extensions for the AMD-K6-2E+ processor,

respectively. For details about the MMX instructions, 3DNow!

technology instructions, and 3DNow! technology DSP

extensions refer to the following manuals:

®

■ MMX

Instructions—AMD-K6

Processor

Multimedia

Technology Manual, order# 20726

■ 3DNow! Technology Instructions—3DNow! Technology

Manual, order# 21928

■ 3DNow! Technology DSP Extensions—AMD Extensions to the

3DNow! and MMX Instruction Set Manual, order# 22466

Each table shows the instruction mnemonic, opcode, modR/M

byte, decode type, and RISC86 operation(s) for each

instruction.

Instruction

Mnemonic and

Operand Types

The first column in these tables indicates the instruction

mnemonic and operand types with the following notations:

■ disp16/32—16-bit or 32-bit displacement value

■ disp32/48—doubleword or 48-bit displacement value

■ disp8—8-bit displacement value

■ eXX—register width depending on the operand size

■ imm16/32—16-bit or 32-bit immediate value

■ imm8—8-bit immediate value

■ mem16/32—word or doubleword integer value in memory

■ mem32/48—doubleword or 48-bit integer value in memory

■ mem32real—32-bit floating-point value in memory

■ mem48—48-bit integer value in memory

■ mem64—64-bit integer value in memory

■ mem64real—64-bit floating-point value in memory

■ mem8—byte integer value in memory

■ mem80real—80-bit floating-point value in memory

■ mmreg—MMX/3DNow! register

Chapter 3

Software Environment

63

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3

of the modR/M byte

■ mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0

of the modR/M byte

■ mreg16/32—word or doubleword integer register, or word or

doubleword integer value in memory defined by the

modR/M byte

■ mreg8—byte integer register or byte integer value in

memory defined by the modR/M byte

■ reg8—byte integer register defined by instruction byte(s) or

bits 5, 4, and 3 of the modR/M byte

■ reg16/32—word or doubleword integer register defined by

instruction byte(s) or bits 5, 4, and 3 of the modR/M byte

Opcode Bytes

ModR/M Byte

The second and third columns list all applicable opcode bytes.

The fourth column lists the modR/M byte when used by the

instruction. The modR/M byte defines the instruction as a

register or memory form. If modR/M bits 7 and 6 are

documented as mm (memory form), mm can only be 10b, 01b or

00b.

Decode Type

The fifth column lists the type of instruction decode—short,

long, and vector. The AMD-K6-2E+ processor decode logic can

process two short, one long, or one vector decode per clock.

RISC86® Operation

The sixth column lists the type of RISC86 operation(s) required

for the instruction. The operation types and corresponding

execution units are as follows:

■ alu—either of the integer execution units

■ alux—integer X execution unit only

■ branch—branch condition unit

■ float—floating-point execution unit

■ limm—load immediate, instruction control unit

■ load, fload, mload—load unit

■ meu—multimedia execution units for MMX and 3DNow!

instructions

■ store, fstore, mstore—store unit

64

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions

Instruction Mnemonic

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Operations

Type

vector

short

AAA

37h

D5h

D4h

3Fh

10h

11h

12h

13h

14h

15h

80h

81h

83h

00h

01h

02h

03h

04h

05h

80h

81h

83h

AAD

0Ah

AAM

AAS

ADC mreg8, reg8

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

ADC mem8, reg8

ADC mreg16/32, reg16/32

ADC mem16/32, reg16/32

ADC reg8, mreg8

ADC reg8, mem8

ADC reg16/32, mreg16/32

ADC reg16/32, mem16/32

ADC AL, imm8

ADC EAX, imm16/32

ADC mreg8, imm8

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-xxx-xxx

ADC mem8, imm8

ADC mreg16/32, imm16/32

ADC mem16/32, imm16/32

ADC mreg16/32, imm8 (signed ext.)

ADC mem16/32, imm8 (signed ext.)

ADD mreg8, reg8

alux

ADD mem8, reg8

mm-xxx-xxx

11-xxx-xxx

long

load, alux, store

ADD mreg16/32, reg16/32

ADD mem16/32, reg16/32

ADD reg8, mreg8

short

alu

mm-xxx-xxx

11-xxx-xxx

long

load, alu, store

short

alux

ADD reg8, mem8

mm-xxx-xxx

11-xxx-xxx

short

load, alux

ADD reg16/32, mreg16/32

ADD reg16/32, mem16/32

ADD AL, imm8

alu

mm-xxx-xxx

short

load, alu

short

alux

ADD EAX, imm16/32

ADD mreg8, imm8

short

alu

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-000-xxx

short

alux

ADD mem8, imm8

long

load, alux, store

alu

ADD mreg16/32, imm16/32

ADD mem16/32, imm16/32

ADD mreg16/32, imm8 (signed ext.)

short

long

load, alu, store

alux

short

Chapter 3

Software Environment

65

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

Operations

load, alux, store

alux

ADD mem16/32, imm8 (signed ext.)

AND mreg8, reg8

83h

20h

21h

22h

23h

24h

25h

80h

81h

83h

63h

62h

0Fh

mm-000-xxx

11-xxx-xxx

long

short

long

AND mem8, reg8

mm-xxx-xxx

11-xxx-xxx

load, alux, store

alu

AND mreg16/32, reg16/32

AND mem16/32, reg16/32

AND reg8, mreg8

short

long

mm-xxx-xxx

11-xxx-xxx

load, alu, store

alux

short

long

AND reg8, mem8

mm-xxx-xxx

11-xxx-xxx

load, alux

alu

AND reg16/32, mreg16/32

AND reg16/32, mem16/32

AND AL, imm8

mm-xxx-xxx

load, alu

alux

AND EAX, imm16/32

AND mreg8, imm8

AND mem8, imm8

alu

11-100-xxx

mm-100-xxx

11-100-xxx

mm-100-xxx

11-100-xxx

mm-100-xxx

11-xxx-xxx

alux

load, alux, store

alu

AND mreg16/32, imm16/32

AND mem16/32, imm16/32

AND mreg16/32, imm8 (signed ext.)

AND mem16/32, imm8 (signed ext.)

ARPL mreg16, reg16

ARPL mem16, reg16

BOUND

short

long

load, alu, store

alux

short

long

load, alux, store

vector

long

mm-xxx-xxx

BSF reg16/32, mreg16/32

BSF reg16/32, mem16/32

BSR reg16/32, mreg16/32

BSR reg16/32, mem16/32

BSWAP EAX

BCh

BDh

C8h

C9h

CAh

CBh

CCh

CDh

CEh

CFh

A3h

BAh

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

alu

BSWAP ECX

long

BSWAP EDX

long

BSWAP EBX

long

BSWAP ESP

long

BSWAP EBP

long

BSWAP ESI

long

BSWAP EDI

long

BT mreg16/32, reg16/32

BT mem16/32, reg16/32

BT mreg16/32, imm8

11-xxx-xxx

mm-xxx-xxx

11-100-xxx

vector

66

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

short

Operations

BT mem16/32, imm8

BTC mreg16/32, reg16/32

BTC mem16/32, reg16/32

BTC mreg16/32, imm8

BTC mem16/32, imm8

BTR mreg16/32, reg16/32

BTR mem16/32, reg16/32

BTR mreg16/32, imm8

BTR mem16/32, imm8

BTS mreg16/32, reg16/32

BTS mem16/32, reg16/32

BTS mreg16/32, imm8

BTS mem16/32, imm8

CALL full pointer

0Fh

9Ah

E8h

FFh

98h

F8h

FCh

FAh

0Fh

F5h

38h

39h

3Ah

3Bh

3Ch

3Dh

80h

BAh

BBh

BAh

B3h

BAh

ABh

BAh

mm-100-xxx

11-xxx-xxx

mm-xxx-xxx

11-111-xxx

mm-111-xxx

11-xxx-xxx

mm-xxx-xxx

11-110-xxx

mm-110-xxx

11-xxx-xxx

mm-xxx-xxx

11-101-xxx

mm-101-xxx

CALL near imm16/32

CALL mem16:16/32

CALL near mreg32 (indirect)

CALL near mem32 (indirect)

CBW/CWDE EAX

store

11-011-xxx

11-010-xxx

mm-010-xxx

vector

short

CLC

CLD

CLI

CLTS

06h

CMC

CMP mreg8, reg8

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

alux

CMP mem8, reg8

short

load, alux

alu

CMP mreg16/32, reg16/32

CMP mem16/32, reg16/32

CMP reg8, mreg8

short

load, alu

alux

short

CMP reg8, mem8

short

load, alux

alu

CMP reg16/32, mreg16/32

CMP reg16/32, mem16/32

CMP AL, imm8

short

load, alu

alux

short

CMP EAX, imm16/32

CMP mreg8, imm8

short

alu

11-111-xxx

short

alux

Chapter 3

Software Environment

67

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

Operations

load, alux

alu

CMP mem8, imm8

CMP mreg16/32, imm16/32

CMP mem16/32, imm16/32

CMP mreg16/32, imm8 (signed ext.)

CMP mem16/32, imm8 (signed ext.)

CMPSB mem8, mem8

CMPSW mem16, mem32

CMPSD mem32, mem32

CMPXCHG mreg8, reg8

CMPXCHG mem8, reg8

CMPXCHG mreg16/32, reg16/32

CMPXCHG mem16/32, reg16/32

CMPXCHG8B EDX:EAX

CMPXCHG8B mem64

CPUID

80h

81h

83h

A6h

A7h

0Fh

99h

27h

2Fh

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

FEh

FFh

F6h

F7h

F6h

mm-111-xxx

11-111-xxx

mm-111-xxx

11-111-xxx

mm-111-xxx

short

load, alu

long

vector

short

B0h

B1h

C7h

A2h

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

CWD/CDQ EDX, EAX

DAA

DAS

DEC EAX

alu

DEC ECX

short

DEC EDX

short

DEC EBX

DEC ESP

DEC EBP

short

DEC ESI

short

DEC EDI

short

DEC mreg8

11-001-xxx

mm-001-xxx

11-001-xxx

mm-001-xxx

11-110-xxx

mm-110-xxx

11-110-xxx

mm-110-xxx

11-111-xxx

vector

long

DEC mem8

load, alux, store

load, alu, store

DEC mreg16/32

vector

long

DEC mem16/32

DIV AL, mreg8

vector

DIV AL, mem8

DIV EAX, mreg16/32

DIV EAX, mem16/32

IDIV mreg8

68

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Operations

Instruction Mnemonic

Type

vector

short

IDIV mem8

F6h

F7h

69h

6Bh

mm-111-xxx

11-111-xxx

mm-111-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

11-xxx-xxx

mm-xxx-xxx

IDIV EAX, mreg16/32

IDIV EAX, mem16/32

IMUL reg16/32, imm16/32

IMUL reg16/32, mreg16/32, imm16/32

IMUL reg16/32, mem16/32, imm16/32

IMUL reg16/32, imm8 (sign extended)

IMUL reg16/32, mreg16/32, imm8 (signed) 6Bh

IMUL reg16/32, mem16/32, imm8 (signed) 6Bh

IMUL AX, AL, mreg8

IMUL AX, AL, mem8

IMUL EDX:EAX, EAX, mreg16/32

IMUL EDX:EAX, EAX, mem16/32

IMUL reg16/32, mreg16/32

IMUL reg16/32, mem16/32

IN AL, imm8

IN AX, imm8

IN EAX, imm8

IN AL, DX

F6h

F7h

0Fh

E4h

E5h

ECh

EDh

40h

41h

42h

43h

44h

45h

46h

47h

FEh

FFh

0Fh

AFh

IN AX, DX

IN EAX, DX

INC EAX

alu

INC ECX

short

INC EDX

short

INC EBX

short

INC ESP

short

INC EBP

short

INC ESI

short

INC EDI

short

INC mreg8

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

vector

long

INC mem8

load, alux, store

load, alu, store

INC mreg16/32

INC mem16/32

INVD

vector

long

08h

01h

vector

INVLPG

mm-111-xxx

Chapter 3

Software Environment

69

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

vector

short

vector

Operations

branch

JO short disp8

70h

71h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

E3h

0Fh

E9h

EAh

JB/JNAE short disp8

JNO short disp8

JNB/JAE short disp8

JZ/JE short disp8

JNZ/JNE short disp8

JBE/JNA short disp8

JNBE/JA short disp8

JS short disp8

JNS short disp8

JP/JPE short disp8

JNP/JPO short disp8

JL/JNGE short disp8

JNL/JGE short disp8

JLE/JNG short disp8

JNLE/JG short disp8

JCXZ/JEC short disp8

JO near disp16/32

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

branch

JNO near disp16/32

JB/JNAE near disp16/32

JNB/JAE near disp16/32

JZ/JE near disp16/32

JNZ/JNE near disp16/32

JBE/JNA near disp16/32

JNBE/JA near disp16/32

JS near disp16/32

JNS near disp16/32

JP/JPE near disp16/32

JNP/JPO near disp16/32

JL/JNGE near disp16/32

JNL/JGE near disp16/32

JLE/JNG near disp16/32

JNLE/JG near disp16/32

JMP near disp16/32 (direct)

JMP far disp32/48 (direct)

70

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

Operations

JMP disp8 (short)

EBh

EFh

FFh

9Fh

0Fh

C5h

8Dh

C9h

C4h

0Fh

ACh

ADh

E2h

E1h

E0h

0Fh

88h

89h

short

branch

JMP far mreg32 (indirect)

JMP far mem32 (indirect)

JMP near mreg16/32 (indirect)

JMP near mem16/32 (indirect)

LAHF

11-101-xxx

mm-101-xxx

11-100-xxx

mm-100-xxx

vector

short

LAR reg16/32, mreg16/32

LAR reg16/32, mem16/32

LDS reg16/32, mem32/48

LEA reg16/32, mem16/32

LEAVE

02h

11-xxx-xxx

mm-xxx-xxx

load, alu

long

load, alu, alu

LES reg16/32, mem32/48

LFS reg16/32, mem32/48

LGDT mem48

mm-xxx-xxx

mm-010-xxx

vector

long

B4h

01h

B5h

01h

00h

01h

LGS reg16/32, mem32/48

LIDT mem48

mm-011-xxx

11-010-xxx

LLDT mreg16

LLDT mem16

mm-010-xxx

11-100-xxx

mm-100-xxx

LMSW mreg16

LMSW mem16

LODSB AL, mem8

load, alu

alu, branch

LODSW AX, mem16

LODSD EAX, mem32

LOOP disp8

long

short

LOOPE/LOOPZ disp8

LOOPNE/LOOPNZ disp8

LSL reg16/32, mreg16/32

LSL reg16/32, mem16/32

LSS reg16/32, mem32/48

LTR mreg16

vector

short

03h

B2h

00h

11-xxx-xxx

mm-xxx-xxx

11-011-xxx

mm-011-xxx

11-xxx-xxx

LTR mem16

MOV mreg8, reg8

alux

store

alu

MOV mem8, reg8

mm-xxx-xxx

11-xxx-xxx

short

MOV mreg16/32, reg16/32

MOV mem16/32, reg16/32

short

mm-xxx-xxx

short

store

Chapter 3

Software Environment

71

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

long

Operations

MOV reg8, mreg8

8Ah

8Bh

8Ch

8Eh

A0h

A1h

A2h

A3h

B0h

B1h

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BDh

BEh

BFh

C6h

C7h

0Fh

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

alux

MOV reg8, mem8

load

MOV reg16/32, mreg16/32

MOV reg16/32, mem16/32

MOV mreg16, segment reg

MOV mem16, segment reg

MOV segment reg, mreg16

MOV segment reg, mem16

MOV AL, mem8

alu

load

vector

short

long

load

MOV EAX, mem16/32

MOV mem8, AL

load

store

limm

store

limm

store

MOV mem16/32, EAX

MOV AL, imm8

MOV CL, imm8

MOV DL, imm8

MOV BL, imm8

MOV AH, imm8

MOV CH, imm8

MOV DH, imm8

MOV BH, imm8

MOV EAX, imm16/32

MOV ECX, imm16/32

MOV EDX, imm16/32

MOV EBX, imm16/32

MOV ESP, imm16/32

MOV EBP, imm16/32

MOV ESI, imm16/32

MOV EDI, imm16/32

MOV mreg8, imm8

MOV mem8, imm8

MOV mreg16/32, imm16/32

MOV mem16/32, imm16/32

MOV reg32, CR0

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-000-xxx

11-010-xxx

11-011-xxx

short

long

20h

vector

MOV reg32, CR2

MOV reg32, CR3

72

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

long

Operations

MOV reg32, CR4

0Fh

A4h

A5h

0Fh

F6h

F7h

F6h

F7h

90h

F6h

F7h

08h

09h

0Ah

20h

22h

11-100-xxx

11-000-xxx

11-010-xxx

11-011-xxx

11-100-xxx

MOV CR0, reg32

MOV CR2, reg32

MOV CR3, reg32

MOV CR4, reg32

MOVSB mem8,mem8

MOVSD mem16, mem16

MOVSW mem32, mem32

MOVSX reg16/32, mreg8

MOVSX reg16/32, mem8

MOVSX reg32, mreg16

MOVSX reg32, mem16

MOVZX reg16/32, mreg8

MOVZX reg16/32, mem8

MOVZX reg32, mreg16

MOVZX reg32, mem16

MUL AL, mreg8

load, store, alux, alux

long

load, store, alu, alu

long

load, store, alu, alu

BEh

BFh

B6h

B7h

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

short

vector

short

vector

short

vector

short

vector

short

vector

short

long

alu

load, alu

alu

mm-xxx-xxx

11-xxx-xxx

load, alu

alu

mm-xxx-xxx

11-xxx-xxx

load, alu

alu

mm-xxx-xxx

11-100-xxx

mm-100-xxx

11-100-xxx

mm-100-xxx

11-011-xxx

mm-011-xxx

11-011-xxx

mm-011-xxx

load, alu

MUL AL, mem8

MUL EAX, mreg16/32

MUL EAX, mem16/32

NEG mreg8

alux

alu

NEG mem8

NEG mreg16/32

NEG mem16/32

NOP (XCHG EAX, EAX)

NOT mreg8

limm

alux

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-xxx-xxx

NOT mem8

NOT mreg16/32

alu

NOT mem16/32

OR mreg8, reg8

alux

OR mem8, reg8

mm-xxx-xxx

11-xxx-xxx

load, alux, store

alu

OR mreg16/32, reg16/32

OR mem16/32, reg16/32

OR reg8, mreg8

short

long

mm-xxx-xxx

11-xxx-xxx

load, alu, store

alux

short

OR reg8, mem8

mm-xxx-xxx

load, alux

Chapter 3

Software Environment

73

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

long

Operations

OR reg16/32, mreg16/32

OR reg16/32, mem16/32

OR AL, imm8

OR EAX, imm16/32

OR mreg8, imm8

OR mem8, imm8

OR mreg16/32, imm16/32

OR mem16/32, imm16/32

OR mreg16/32, imm8 (signed ext.)

OR mem16/32, imm8 (signed ext.)

OUT imm8, AL

OUT imm8, AX

OUT imm8, EAX

OUT DX, AL

0Bh

0Ch

0Dh

80h

81h

83h

E6h

E7h

EEh

EFh

07h

17h

1Fh

0Fh

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

8Fh

61h

9Dh

06h

0Eh

11-xxx-xxx

alu

mm-xxx-xxx

load, alu

alux

alu

11-001-xxx

mm-001-xxx

11-001-xxx

mm-001-xxx

11-001-xxx

mm-001-xxx

alux

load, alux, store

alu

short

long

load, alu, store

alux

short

long

load, alux, store

vector

short

long

OUT DX, AX

OUT DX, EAX

POP ES

POP SS

POP DS

POP FS

A1h

A9h

POP GS

POP EAX

load, alu

load, store, alu

POP ECX

POP EDX

POP EBX

POP ESP

POP EBP

POP ESI

POP EDI

POP mreg 16/32

POP mem 16/32

POPA/POPAD

POPF/POPFD

PUSH ES

11-000-xxx

mm-000-xxx

vector

long

load, store

PUSH CS

vector

74

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

long

Operations

PUSH FS

0Fh

16h

1Eh

50h

51h

52h

53h

54h

55h

56h

57h

6Ah

68h

FFh

60h

9Ch

C0h

C1h

D0h

D1h

D2h

D3h

C0h

C1h

D0h

A0h

A8h

PUSH GS

PUSH SS

PUSH DS

load, store

store

PUSH EAX

short

PUSH ECX

short

store

PUSH EDX

short

store

PUSH EBX

short

store

PUSH ESP

short

store

PUSH EBP

short

PUSH ESI

short

store

PUSH EDI

short

PUSH imm8

long

store

PUSH imm16/32

PUSH mreg16/32

PUSH mem16/32

PUSHA/PUSHAD

PUSHF/PUSHFD

RCL mreg8, imm8

RCL mem8, imm8

RCL mreg16/32, imm8

RCL mem16/32, imm8

RCL mreg8, 1

long

11-110-xxx

vector

long

mm-110-xxx

load, store

vector

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-010-xxx

mm-010-xxx

11-011-xxx

mm-011-xxx

11-011-xxx

mm-011-xxx

11-011-xxx

RCL mem8, 1

RCL mreg16/32, 1

RCL mem16/32, 1

RCL mreg8, CL

RCL mem8, CL

RCL mreg16/32, CL

RCL mem16/32, CL

RCR mreg8, imm8

RCR mem8, imm8

RCR mreg16/32, imm8

RCR mem16/32, imm8

RCR mreg8, 1

Chapter 3

Software Environment

75

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Operations

Instruction Mnemonic

Type

vector

RCR mem8, 1

D0h

D1h

D2h

D3h

0Fh

mm-011-xxx

11-011-xxx

mm-011-xxx

11-011-xxx

mm-011-xxx

11-011-xxx

mm-011-xxx

RCR mreg16/32, 1

RCR mem16/32, 1

RCR mreg8, CL

RCR mem8, CL

RCR mreg16/32, CL

RCR mem16/32, CL

RDMSR

32h

31h

RDTSC

0Fh

RET near imm16

RET near

C2h

C3h

CAh

CBh

C0h

C1h

D0h

D1h

D2h

D3h

C0h

C1h

D0h

D1h

D2h

RET far imm16

RET far

ROL mreg8, imm8

ROL mem8, imm8

ROL mreg16/32, imm8

ROL mem16/32, imm8

ROL mreg8, 1

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-001-xxx

mm-001-xxx

11-001-xxx

mm-001-xxx

11-001-xxx

mm-001-xxx

11-001-xxx

mm-001-xxx

11-001-xxx

mm-001-xxx

ROL mem8, 1

ROL mreg16/32, 1

ROL mem16/32, 1

ROL mreg8, CL

ROL mem8, CL

ROL mreg16/32, CL

ROL mem16/32, CL

ROR mreg8, imm8

ROR mem8, imm8

ROR mreg16/32, imm8

ROR mem16/32, imm8

ROR mreg8, 1

ROR mem8, 1

ROR mreg16/32, 1

ROR mem16/32, 1

ROR mreg8, CL

ROR mem8, CL

76

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

short

Operations

ROR mreg16/32, CL

ROR mem16/32, CL

RSM

D3h

0Fh

9Eh

C0h

C1h

D0h

D1h

D2h

D3h

18h

19h

1Ah

1Bh

1Ch

1Dh

80h

81h

83h

AEh

AFh

11-001-xxx

mm-001-xxx

AAh

SAHF

SAR mreg8, imm8

SAR mem8, imm8

SAR mreg16/32, imm8

SAR mem16/32, imm8

SAR mreg8, 1

11-111-xxx

mm-111-xxx

11-111-xxx

mm-111-xxx

11-111-xxx

mm-111-xxx

11-111-xxx

mm-111-xxx

11-111-xxx

mm-111-xxx

11-111-xxx

mm-111-xxx

11-xxx-xxx

alux

alu

vector

short

vector

short

alux

alu

SAR mem8, 1

vector

short

SAR mreg16/32, 1

SAR mem16/32, 1

SAR mreg8, CL

vector

short

alux

alu

SAR mem8, CL

vector

short

SAR mreg16/32, CL

SAR mem16/32, CL

SBB mreg8, reg8

vector

SBB mem8, reg8

mm-xxx-xxx

11-xxx-xxx

SBB mreg16/32, reg16/32

SBB mem16/32, reg16/32

SBB reg8, mreg8

mm-xxx-xxx

11-xxx-xxx

SBB reg8, mem8

mm-xxx-xxx

11-xxx-xxx

SBB reg16/32, mreg16/32

SBB reg16/32, mem16/32

SBB AL, imm8

mm-xxx-xxx

SBB EAX, imm16/32

SBB mreg8, imm8

SBB mem8, imm8

SBB mreg16/32, imm16/32

SBB mem16/32, imm16/32

SBB mreg16/32, imm8 (signed ext.)

SBB mem16/32, imm8 (signed ext.)

SCASB AL, mem8

11-011-xxx

mm-011-xxx

11-011-xxx

mm-011-xxx

11-011-xxx

mm-011-xxx

SCASW AX, mem16

SCASD EAX, mem32

Chapter 3

Software Environment

77

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

short

Operations

SETO mreg8

0Fh

C0h

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

01h

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

mm-000-xxx

mm-001-xxx

11-100-xxx

SETO mem8

SETNO mreg8

SETNO mem8

SETB/SETNAE mreg8

SETB/SETNAE mem8

SETNB/SETAE mreg8

SETNB/SETAE mem8

SETZ/SETE mreg8

SETZ/SETE mem8

SETNZ/SETNE mreg8

SETNZ/SETNE mem8

SETBE/SETNA mreg8

SETBE/SETNA mem8

SETNBE/SETA mreg8

SETNBE/SETA mem8

SETS mreg8

SETS mem8

SETNS mreg8

SETNS mem8

SETP/SETPE mreg8

SETP/SETPE mem8

SETNP/SETPO mreg8

SETNP/SETPO mem8

SETL/SETNGE mreg8

SETL/SETNGE mem8

SETNL/SETGE mreg8

SETNL/SETGE mem8

SETLE/SETNG mreg8

SETLE/SETNG mem8

SETNLE/SETG mreg8

SETNLE/SETG mem8

SGDT mem48

SIDT mem48

SHL/SAL mreg8, imm8

alux

78

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

short

Operations

SHL/SAL mem8, imm8

SHL/SAL mreg16/32, imm8

SHL/SAL mem16/32, imm8

SHL/SAL mreg8, 1

C0h

C1h

D0h

D1h

D2h

D3h

C0h

C1h

D0h

D1h

D2h

D3h

0Fh

mm-100-xxx

11-100-xxx

mm-100-xxx

11-100-xxx

mm-100-xxx

11-100-xxx

mm-100-xxx

11-100-xxx

mm-100-xxx

11-100-xxx

mm-100-xxx

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

11-xxx-xxx

alu

vector

short

alux

alu

SHL/SAL mem8, 1

vector

short

SHL/SAL mreg16/32, 1

SHL/SAL mem16/32, 1

SHL/SAL mreg8, CL

vector

short

alux

alu

SHL/SAL mem8, CL

vector

short

SHL/SAL mreg16/32, CL

SHL/SAL mem16/32, CL

SHR mreg8, imm8

vector

short

alux

alu

SHR mem8, imm8

vector

short

SHR mreg16/32, imm8

SHR mem16/32, imm8

SHR mreg8, 1

vector

short

alux

alu

SHR mem8, 1

vector

short

SHR mreg16/32, 1

SHR mem16/32, 1

vector

short

SHR mreg8, CL

alux

alu

SHR mem8, CL

vector

short

SHR mreg16/32, CL

SHR mem16/32, CL

vector

SHLD mreg16/32, reg16/32, imm8

SHLD mem16/32, reg16/32, imm8

SHLD mreg16/32, reg16/32, CL

SHLD mem16/32, reg16/32, CL

SHRD mreg16/32, reg16/32, imm8

SHRD mem16/32, reg16/32, imm8

SHRD mreg16/32, reg16/32, CL

SHRD mem16/32, reg16/32, CL

SLDT mreg16

A4h

A5h

ACh

ADh

00h

01h

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-000-xxx

mm-000-xxx

11-100-xxx

mm-100-xxx

SLDT mem16

SMSW mreg16

SMSW mem16

Chapter 3

Software Environment

79

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

long

Operations

STC

F9h

FDh

FBh

AAh

ABh

0Fh

28h

29h

2Ah

2Bh

2Ch

2Dh

80h

81h

83h

0Fh

84h

85h

A8h

A9h

F6h

F7h

STD

STI

STOSB mem8, AL

STOSW mem16, AX

STOSD mem32, EAX

STR mreg16

store, alux

long

00h

11-001-xxx

mm-001-xxx

11-xxx-xxx

vector

short

long

STR mem16

SUB mreg8, reg8

alux

SUB mem8, reg8

mm-xxx-xxx

11-xxx-xxx

load, alux, store

SUB mreg16/32, reg16/32

SUB mem16/32, reg16/32

SUB reg8, mreg8

short

long

alu

mm-xxx-xxx

11-xxx-xxx

load, alu, store

alux

short

long

SUB reg8, mem8

mm-xxx-xxx

11-xxx-xxx

load, alux

alu

SUB reg16/32, mreg16/32

SUB reg16/32, mem16/32

SUB AL, imm8

mm-xxx-xxx

load, alu

alux

SUB EAX, imm16/32

SUB mreg8, imm8

SUB mem8, imm8

SUB mreg16/32, imm16/32

SUB mem16/32, imm16/32

SUB mreg16/32, imm8 (signed ext.)

SUB mem16/32, imm8 (signed ext.)

SYSCALL

alu

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

11-101-xxx

mm-101-xxx

alux

load, alux, store

alu

short

long

load, alu, store

alux

short

long

load, alux, store

05h

07h

vector

short

vector

short

vector

long

SYSRET

TEST mreg8, reg8

TEST mem8, reg8

TEST mreg16/32, reg16/32

TEST mem16/32, reg16/32

TEST AL, imm8

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

alux

alu

mm-xxx-xxx

alux

TEST EAX, imm16/32

TEST mreg8, imm8

TEST mem8, imm8

TEST mreg16/32, imm16/32

long

alu

11-000-xxx

mm-000-xxx

11-000-xxx

long

alux

long

load, alux

alu

long

80

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

Operations

TEST mem16/32, imm16/32

VERR mreg16

F7h

0Fh

9Bh

0Fh

86h

87h

90h

91h

92h

93h

94h

95h

96h

97h

D7h

30h

31h

32h

33h

34h

35h

mm-000-xxx

11-100-xxx

mm-100-xxx

11-101-xxx

mm-101-xxx

long

load, alu

00h

vector

short

long

VERR mem16

VERW mreg16

VERW mem16

WAIT

WBINVD

09h

30h

C0h

C1h

WRMSR

XADD mreg8, reg8

XADD mem8, reg8

XADD mreg16/32, reg16/32

XADD mem16/32, reg16/32

XCHG reg8, mreg8

XCHG reg8, mem8

XCHG reg16/32, mreg16/32

XCHG reg16/32, mem16/32

XCHG EAX, EAX

11-100-xxx

mm-100-xxx

11-101-xxx

mm-101-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

limm

XCHG EAX, ECX

alu, alu, alu

XCHG EAX, EDX

long

XCHG EAX, EBX

long

XCHG EAX, ESP

long

XCHG EAX, EBP

long

XCHG EAX, ESI

long

XCHG EAX, EDI

long

XLAT

vector

short

long

XOR mreg8, reg8

XOR mem8, reg8

XOR mreg16/32, reg16/32

XOR mem16/32, reg16/32

XOR reg8, mreg8

XOR reg8, mem8

XOR reg16/32, mreg16/32

XOR reg16/32, mem16/32

XOR AL, imm8

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

alux

load, alux, store

short

long

alu

load, alu, store

alux

short

load, alux

alu

load, alu

alux

XOR EAX, imm16/32

alu

Chapter 3

Software Environment

81

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 12. Integer Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

long

Operations

XOR mreg8, imm8

80h

81h

83h

11-110-xxx

mm-110-xxx

11-110-xxx

mm-110-xxx

11-110-xxx

mm-110-xxx

alux

XOR mem8, imm8

load, alux, store

alu

XOR mreg16/32, imm16/32

XOR mem16/32, imm16/32

XOR mreg16/32, imm8 (signed ext.)

XOR mem16/32, imm8 (signed ext.)

short

long

load, alu, store

alux

short

long

load, alux, store

Table 13. Floating-Point Instructions

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Operations

Instruction Mnemonic

Type

short

vector

short

vector

short

F2XM1

FABS

D9h

D8h

DCh

DEh

DFh

D9h

DBh

D8h

DCh

D8h

DCh

DEh

D9h

D8h

F0h

F1h

float

FADD ST(0), ST(i)¹

11-000-xxx

mm-000-xxx

11-000-xxx

mm-000-xxx

11-000-xxx

mm-100-xxx

mm-110-xxx

float

FADD ST(0), mem32real

fload, float

float

FADD ST(i), ST(0)¹

FADD ST(0), mem64real

fload, float

float

FADDP ST(i), ST(0)¹

FBLD

FBSTP

FCHS

FCLEX

E0h

E2h

float

FCOM ST(0), ST(i)¹

11-010-xxx

mm-010-xxx

11-011-xxx

float

FCOM ST(0), mem32real

FCOM ST(0), mem64real

fload, float

float

FCOMP ST(0), ST(i)¹

FCOMP ST(0), mem32real

FCOMP ST(0), mem64real

FCOMPP

mm-011-xxx

11-011-001

fload, float

float

D9h

FFh

F6h

FCOS

float

FDECSTP

float

FDIV ST(0), ST(i) (single precision)¹

FDIV ST(0), ST(i) (double precision)¹

FDIV ST(0), ST(i) (extended precision)¹

11-110-xxx

float

D8h

short

float

82

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 13. Floating-Point Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

Operations

FDIV ST(i), ST(0) (single precision)¹

FDIV ST(i), ST(0) (double precision)¹

DCh

11-111-xxx

float

FDIV ST(i), ST(0) (extended precision)¹

FDIV ST(0), mem32real

DCh

D8h

DCh

DEh

11-111-xxx

mm-110-xxx

11-111-xxx

short

float

fload, float

float

FDIV ST(0), mem64real

FDIVP ST(0), ST(i)¹

FDIVR ST(0), ST(i)¹

D8h

11-110-xxx

short

float

FDIVR ST(i), ST(0)¹

DCh

D8h

DCh

DEh

11-111-xxx

mm-111-xxx

11-110-xxx

short

float

FDIVR ST(0), mem32real

FDIVR ST(0), mem64real

fload, float

float

FDIVRP ST(i), ST(0)¹

FFREE ST(i)¹

DDh

DAh

DEh

DAh

DEh

DAh

DEh

DAh

DEh

DAh

DEh

DFh

DBh

DFh

DAh

DEh

D9h

DBh

DFh

DBh

DFh

DBh

DFh

11-000-xxx

mm-000-xxx

mm-010-xxx

mm-011-xxx

mm-110-xxx

mm-111-xxx

mm-000-xxx

mm-101-xxx

mm-001-xxx

short

vector

short

float

FIADD ST(0), mem32int

FIADD ST(0), mem16int

FICOM ST(0), mem32int

FICOM ST(0), mem16int

FICOMP ST(0), mem32int

FICOMP ST(0), mem16int

FIDIV ST(0), mem32int

FIDIV ST(0), mem16int

FIDIVR ST(0), mem32int

FIDIVR ST(0), mem16int

FILD mem16int

fload, float

FILD mem32int

FILD mem64int

FIMUL ST(0), mem32int

FIMUL ST(0), mem16int

FINCSTP

F7h

E3h

FINIT

FIST mem16int

mm-010-xxx

mm-011-xxx

mm-111-xxx

fload, float

FIST mem32int

FISTP mem16int

FISTP mem32int

FISTP mem64int

Chapter 3

Software Environment

83

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 13. Floating-Point Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

vector

short

vector

short

Operations

fload, float

FISUB ST(0), mem32int

FISUB ST(0), mem16int

FISUBR ST(0), mem32int

FISUBR ST(0), mem16int

DAh

DEh

DAh

DEh

D9h

DDh

DBh

D9h

D8h

mm-100-xxx

mm-101-xxx

11-000-xxx

FLD ST(i)¹

FLD mem32real

FLD mem64real

FLD mem80real

FLD1

mm-000-xxx

mm-101-xxx

E8h

fload, float

FLDCW

mm-101-xxx

mm-100-xxx

FLDENV

fload, float

float

FLDL2E

EAh

E9h

ECh

EDh

EBh

EEh

FLDL2T

float

FLDLG2

float

FLDLN2

float

FLDPI

float

FLDZ

float

FMUL ST(0), ST(i)¹

11-001-xxx

float

FMUL ST(i), ST(0)¹

DCh

D8h

DCh

DEh

D9h

DDh

D9h

11-001-xxx

mm-001-xxx

11-001-xxx

short

vector

short

vector

short

vector

short

float

FMUL ST(0), mem32real

FMUL ST(0), mem64real

fload, float

float

FMULP ST(0), ST(i)¹

FNOP

D0h

F3h

F8h

F5h

F2h

FCh

float

FPATAN

float

FPREM

float

FPREM1

float

FPTAN

FRNDINT

float

FRSTOR

mm-100-xxx

mm-110-xxx

FSAVE

FSCALE

FDh

FEh

FBh

FAh

float

FSIN

FSINCOS

FSQRT (single precision)

FSQRT (double precision)

float

84

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 13. Floating-Point Instructions (continued)

First

Byte

Second

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

vector

short

vector

short

vector

short

Operations

FSQRT (extended precision)

FST mem32real

D9h

DDh

D9h

DDh

D9h

DDh

DFh

DDh

D8h

DCh

D8h

FAh

float

mm-010-xxx

11-010-xxx

fstore

FST mem64real

FST ST(i)¹

FSTCW

mm-111-xxx

mm-110-xxx

mm-011-xxx

mm-111-xxx

11-011-xxx

FSTENV

FSTP mem32real

FSTP mem64real

FSTP mem80real

fstore

FSTP ST(i)¹

float

FSTSW AX

E0h

FSTSW mem16

mm-111-xxx

mm-100-xxx

11-100-xxx

FSUB ST(0), mem32real

FSUB ST(0), mem64real

fload, float

float

FSUB ST(0), ST(i)¹

FSUB ST(i), ST(0)¹

DCh

11-101-xxx

short

float

FSUBP ST(0), ST(i)¹

DEh

D8h

DCh

D8h

11-101-xxx

mm-101-xxx

11-100-xxx

short

float

FSUBR ST(0), mem32real

FSUBR ST(0), mem64real

fload, float

float

FSUBR ST(0), ST(i)¹

FSUBR ST(i), ST(0)¹

DCh

11-101-xxx

11-100-xxx

short

float

FSUBRP ST(i), ST(0)¹

FTST

DEh

D9h

DDh

DAh

D9h

9Bh

short

vector

short

vector

float

E4h

FUCOM

FUCOMP

FUCOMPP

FXAM

11-100-xxx

11-101-xxx

E9h

E5h

FXCH

11-001-xxx

FXTRACT

FYL2X

F4h

F1h

F9h

float

FYL2XP1

FWAIT

Notes:

1. The last three bits of the modR/M byte select the stack entry ST(i).

Chapter 3

Software Environment

85

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 14. MMX™ Instructions

Prefix

Byte(s)

First

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

vector

short

Operations

EMMS

0Fh

77h

6Eh

7Eh

6Fh

7Fh

6Bh

63h

67h

FCh

FEh

ECh

EDh

DCh

DDh

FDh

DBh

DFh

74h

MOVD mmreg, mreg32¹

MOVD mmreg, mem32

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

meu

mload

MOVD mreg32, mmreg¹

MOVD mem32, mmreg

mstore, load

mstore

MOVQ mmreg1, mmreg2

MOVQ mmreg, mem64

meu

mload

MOVQ mmreg2, mmreg1

MOVQ mem64, mmreg

meu

mstore

PACKSSDW mmreg1, mmreg2

PACKSSDW mmreg, mem64

PACKSSWB mmreg1, mmreg2

PACKSSWB mmreg, mem64

PACKUSWB mmreg1, mmreg2

PACKUSWB mmreg, mem64

PADDB mmreg1, mmreg2

PADDB mmreg, mem64

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

PADDD mmreg1, mmreg2

PADDD mmreg, mem64

PADDSB mmreg1, mmreg2

PADDSB mmreg, mem64

PADDSW mmreg1, mmreg2

PADDSW mmreg, mem64

PADDUSB mmreg1, mmreg2

PADDUSB mmreg, mem64

PADDUSW mmreg1, mmreg2

PADDUSW mmreg, mem64

PADDW mmreg1, mmreg2

PADDW mmreg, mem64

PAND mmreg1, mmreg2

PAND mmreg, mem64

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

PANDN mmreg1, mmreg2

PANDN mmreg, mem64

PCMPEQB mmreg1, mmreg2

mload, meu

meu

86

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 14. MMX™ Instructions (continued)

Prefix

Instruction Mnemonic

First

Byte

ModR/M

Byte

Decode RISC86

Operations

Byte(s)

Type

short

PCMPEQB mmreg, mem64

PCMPEQD mmreg1, mmreg2

PCMPEQD mmreg, mem64

PCMPEQW mmreg1, mmreg2

PCMPEQW mmreg, mem64

PCMPGTB mmreg1, mmreg2

PCMPGTB mmreg, mem64

PCMPGTD mmreg1, mmreg2

PCMPGTD mmreg, mem64

PCMPGTW mmreg1, mmreg2

PCMPGTW mmreg, mem64

PMADDWD mmreg1, mmreg2

PMADDWD mmreg, mem64

PMULHW mmreg1, mmreg2

PMULHW mmreg, mem64

PMULLW mmreg1, mmreg2

PMULLW mmreg, mem64

POR mmreg1, mmreg2

0Fh

74h

76h

75h

64h

66h

65h

F5h

E5h

D5h

EBh

F2h

72h

F3h

73h

F1h

71h

E2h

72h

E1h

71h

D2h

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-110-xxx

11-xxx-xxx

mm-xxx-xxx

11-110-xxx

11-xxx-xxx

mm-xxx-xxx

11-110-xxx

11-xxx-xxx

mm-xxx-xxx

11-100-xxx

11-xxx-xxx

mm-xxx-xxx

11-100-xxx

11-xxx-xxx

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

POR mmreg, mem64

mload, meu

meu

PSLLD mmreg1, mmreg2

PSLLD mmreg, mem64

mload, meu

meu

PSLLD mmreg, imm8

PSLLQ mmreg1, mmreg2

PSLLQ mmreg, mem64

meu

mload, meu

meu

PSLLQ mmreg, imm8

PSLLW mmreg1, mmreg2

PSLLW mmreg, mem64

PSLLW mmreg, imm8

meu

mload, meu

meu

PSRAD mmreg1, mmreg2

PSRAD mmreg, mem64

PSRAD mmreg, imm8

meu

mload, meu

meu

PSRAW mmreg1, mmreg2

PSRAW mmreg, mem64

PSRAW mmreg, imm8

meu

mload, meu

meu

PSRLD mmreg1, mmreg2

meu

Chapter 3

Software Environment

87

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 14. MMX™ Instructions (continued)

Prefix

Instruction Mnemonic

First

Byte

ModR/M

Byte

Decode RISC86

Byte(s)

Type

short

Operations

mload, meu

meu

PSRLD mmreg, mem64

0Fh

D2h

72h

D3h

73h

D1h

71h

mm-xxx-xxx

11-010-xxx

11-xxx-xxx

mm-xxx-xxx

11-010-xxx

11-xxx-xxx

mm-xxx-xxx

11-010-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

PSRLD mmreg, imm8

PSRLQ mmreg1, mmreg2

PSRLQ mmreg, mem64

meu

mload, meu

meu

PSRLQ mmreg, imm8

PSRLW mmreg1, mmreg2

PSRLW mmreg, mem64

meu

mload, meu

meu

PSRLW mmreg, imm8

PSUBB mmreg1, mmreg2

PSUBB mmreg, mem64

F8h

FAh

E8h

E9h

D8h

D9h

F9h

68h

6Ah

69h

60h

62h

61h

EFh

meu

mload, meu

meu

PSUBD mmreg1, mmreg2

PSUBD mmreg, mem64

mload, meu

meu

PSUBSB mmreg1, mmreg2

PSUBSB mmreg, mem64

PSUBSW mmreg1, mmreg2

PSUBSW mmreg, mem64

PSUBUSB mmreg1, mmreg2

PSUBUSB mmreg, mem64

PSUBUSW mmreg1, mmreg2

PSUBUSW mmreg, mem64

PSUBW mmreg1, mmreg2

PSUBW mmreg, mem64

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

PUNPCKHBW mmreg1, mmreg2

PUNPCKHBW mmreg, mem64

PUNPCKHDQ mmreg1, mmreg2

PUNPCKHDQ mmreg, mem64

PUNPCKHWD mmreg1, mmreg2

PUNPCKHWD mmreg, mem64

PUNPCKLBW mmreg1, mmreg2

PUNPCKLBW mmreg, mem32

PUNPCKLDQ mmreg1, mmreg2

PUNPCKLDQ mmreg, mem32

PUNPCKLWD mmreg1, mmreg2

PUNPCKLWD mmreg, mem32

PXOR mmreg1, mmreg2

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

88

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 14. MMX™ Instructions (continued)

Prefix

Instruction Mnemonic

First

Byte

ModR/M

Byte

Decode RISC86

Byte(s)

Type

Operations

PXOR mmreg, mem64

0Fh

EFh

mm-xxx-xxx

short

mload, meu

Notes:

1. Bits 2, 1, and 0 of the modR/M byte select the integer register.

Table 15. 3DNow!™ Instructions

Prefix

Byte(s)

Opcode

ModR/M

Byte

Decode RISC86

Operations

Instruction Mnemonic

Byte

0Eh

BFh

1Dh

AEh

9Eh

B0h

90h

A0h

A4h

94h

B4h

96h

A6h

B6h

A7h

Type

vector

short

FEMMS

0Fh

PAVGUSB mmreg1, mmreg2

PAVGUSB mmreg, mem64

PF2ID mmreg1, mmreg2

PF2ID mmreg, mem64

0Fh, 0Fh

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

meu

mload, meu

meu

mload, meu

meu

PFACC mmreg1, mmreg2

PFACC mmreg, mem64

PFADD mmreg1, mmreg2

PFADD mmreg, mem64

PFCMPEQ mmreg1, mmreg2

PFCMPEQ mmreg, mem64

PFCMPGE mmreg1, mmreg2

PFCMPGE mmreg, mem64

PFCMPGT mmreg1, mmreg2

PFCMPGT mmreg, mem64

PFMAX mmreg1, mmreg2

PFMAX mmreg, mem64

PFMIN mmreg1, mmreg2

PFMIN mmreg, mem64

PFMUL mmreg1, mmreg2

PFMUL mmreg, mem64

PFRCP mmreg1, mmreg2

PFRCP mmreg, mem64

PFRCPIT1 mmreg1, mmreg2

PFRCPIT1 mmreg, mem64

PFRCPIT2 mmreg1, mmreg2

PFRCPIT2 mmreg, mem64

PFRSQIT1 mmreg1, mmreg2

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

mload, meu

meu

Chapter 3

Software Environment

89

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 15. 3DNow!™ Instructions (continued)

Prefix

Instruction Mnemonic

Opcode

Byte

ModR/M

Byte

Decode RISC86

Byte(s)

Type

short

vector

Operations

mload, meu

meu

PFRSQIT1 mmreg, mem64

PFRSQRT mmreg1, mmreg2

PFRSQRT mmreg, mem64

PFSUB mmreg1, mmreg2

PFSUB mmreg, mem64

0Fh, 0Fh

0Fh

A7h

97h

9Ah

AAh

0Dh

B7h

0Dh

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mload, meu

meu

mm-xxx-xxx

11-xxx-xxx

mload, meu

meu

PFSUBR mmreg1, mmreg2

PFSUBR mmreg, mem64

PI2FD mmreg1, mmreg2

PI2FD mmreg, mem64

mm-xxx-xxx

11-xxx-xxx

mload, meu

meu

mm-xxx-xxx

11-xxx-xxx

mload, meu

meu

PMULHRW mmreg1, mmreg2

PMULHRW mmreg1, mem64

mm-xxx-xxx

mm-000-xxx

mload, meu

load

PREFETCH mem8¹

PREFETCHW mem8^1,2

Notes:

0Fh

0Dh

mm-001-xxx

vector

load

1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched.

2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2E+ processor, this instruction performs in the same man-

ner as the PREFETCH instruction.

Table 16. 3DNow!™ Technology DSP Extensions

Prefix

Byte(s)

Opcode

Byte

ModR/M

Byte

Decode RISC86

Instruction Mnemonic

Type

short

Operations

PF2IW mmreg1, mmreg2

PF2IW mmreg, mem64

0Fh, 0Fh

1Ch

8Ah

8Eh

0Ch

BBh

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

11-xxx-xxx

mm-xxx-xxx

meu

mload, meu

meu

PFNACC mmreg1, mmreg2

PFNACC mmreg, mem64

PFPNACC mmreg1, mmreg2

PFPNACC mmreg, mem64

PI2FW mmreg1, mmreg2

PI2FW mmreg, mem64

mload, meu

meu

mload, meu

meu

mload, meu

meu

PSWAPD mmreg1, mmreg2

PSWAPD mmreg, mem64

mload, meu

90

Software Environment

Chapter 3

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

4

Logic Symbol Diagram

Voltage Detection²

Clock

VCC2H/L#

VCC2DET

BF[2:0]

VID[4:0]

CLK

AHOLD

BOFF#

BREQ

HLDA

HOLD

BRDY#

BRDYC#

D[63:0]

DP[7:0]

PCHK#

Data

and

Data

Parity

Bus

Arbitration

A20M#

A[31:3]

AP

Address

and

Address

Parity

EADS#

HIT#

HITM#

INV

Inquire

Cycles

ADS#

ADSC#

APCHK#

BE[7:0]#

AMD-K6-2E+

D/C#

FERR#

IGNNE#

Floating-Point

Error Handling

1

EWBE#

LOCK#

M/IO#

NA#

Processor

Cycle

Definition

and

Control

SCYC

W/R#

FLUSH#

INIT

INTR

NMI

RESET

SMI#

External

Interrupts,

SMM, Reset and

Initialization

CACHE#

KEN#

PCD

Cache

Control

PWT

SMIACT#

STPCLK#

WB/WT#

TCK TDI TDO TMS TRST#

JTAG Test

Notes:

1. The signals are grouped by function. The arrows show the direction of the signal, either into or out of the processor. Signals with double-

headed arrows are bidirectional. Signals with pound signs (#) are active Low.

2. The VID[4:0] outputs are supported on low-power versions only. The VCC2DET and VCC2H/L# outputs are supported on the CPGA

package only.

Chapter 4

Logic Symbol Diagram

91

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

92

Logic Symbol Diagram

Chapter 4

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5

Signal Descriptions

This chapter includes a detailed description of each signal

supported on the AMD-K6-2E+ processor. This chapter also

provides tables listing the signals grouped by type, beginning

on page 140.

The logic symbol diagram on page 91 shows the signals grouped

by function.

Connection diagrams and pins listed by high-level function are

included in Chapter 18, “Pin Designations” on page 321.

5.1

Signal Terminology

The following terminology is used in this chapter:

■ Driven—The processor actively pulls the signal up to the

High-voltage state or pulls the signal down to the

Low-voltage state.

■ Floated—The signal is not being driven by the processor

(high-impedance state), which allows another device to

drive this signal.

■ Asserted—For all active High signals, the term asserted

means the signal is in the High-voltage state. For all active

Low signals, the term asserted means the signal is in the

Low-voltage state. See Table 19 on page 140 for information

on asserting signals synchronously and asynchronously.

■ Negated—For all active High signals, the term negated means

the signal is in the Low-voltage state. For all active Low

signals, the term negated means the signal is in the

High-voltage state.

■ Sampled—The processor has measured the state of a signal

at predefined points in time and will take the appropriate

action based on the state of the signal. If a signal is not

sampled by the processor, its assertion or negation has no

effect on the operation of the processor.

Chapter 5

Signal Descriptions

93

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.2

A20M# (Address Bit 20 Mask)

Pin Attribute

Summary

Input

A20M# is used to simulate the behavior of the 8086 when

running in Real mode. The assertion of A20M# causes the

processor to force bit 20 of the physical address to 0 prior to

accessing the caches or driving out a memory bus cycle. The

clearing of address bit 20 maps addresses that extend above the

8086 1-Mbyte limit to below 1 Mbyte.

Sampled

The processor samples A20M# as a level-sensitive input on

every clock edge. The system logic can drive the signal either

synchronously or asynchronously. If it is asserted

asynchronously, it must be asserted for a minimum pulse width

of two clocks.

The following list explains the effects of the processor sampling

A20M# asserted under various conditions:

■ Inquire cycles and writeback cycles are not affected by the

state of A20M#.

■ The assertion of A20M# in System Management Mode

(SMM) is ignored.

■ When A20M# is sampled asserted in Protected mode, it

causes unpredictable processor operation. A20M# is only

defined in Real mode.

■ To ensure that A20M# is recognized before the first ADS#

occurs following the negation of RESET, A20M# must be

sampled asserted on the same clock edge that RESET is

sampled negated or on one of the two subsequent clock

edges.

■ To ensure A20M# is recognized before the execution of an

instruction, a serializing instruction must be executed

between the instruction that asserts A20M# and the

targeted instruction. (A serializing instruction is an

instruction inserted between operations to enforce program

order. It forces the processor to finish all modifications to

flags, registers, and memory before the next instruction is

executed.)

94

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.3

A[31:3] (Address Bus)

Pin Attribute

Summary

A[31:5] Bidirectional, A[4:3] Output

A[31:3] contain the physical address for the current bus cycle.

The processor drives addresses on A[31:3] during memory and

I/O cycles, and cycle definition information during special bus

cycles. The processor samples addresses on A[31:5] during

inquire cycles.

Driven, Sampled, and

Floated

As Outputs: A[31:3] are driven valid off the same clock edge as

ADS# and remain in the same state until the clock edge on

which NA# or the last expected BRDY# of the cycle is sampled

asserted. A[31:3] are driven during memory cycles, I/O cycles,

special bus cycles, and interrupt acknowledge cycles. The

processor continues to drive the address bus while the bus is

idle.

As Inputs: The processor samples A[31:5] during inquire cycles

on the clock edge on which EADS# is sampled asserted. Even

though A4 and A3 are not used during the inquire cycle, they

must be driven to a valid state and must meet the same timings

as A[31:5].

A[31:3] are floated off the clock edge that AHOLD or BOFF# is

sampled asserted and off the clock edge that the processor

asserts HLDA in recognition of HOLD.

The processor resumes driving A[31:3] off the clock edge on

which the processor samples AHOLD or BOFF#negated and off

the clock edge on which the processor negates HLDA.

Chapter 5

Signal Descriptions

95

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.4

ADS# (Address Strobe)

Pin Attribute

Summary

Output

The assertion of ADS# indicates the beginning of a new bus

cycle. The address bus and all cycle definition signals

corresponding to this bus cycle are driven valid off the same

clock edge as ADS#.

Driven and Floated

ADS# is asserted for one clock at the beginning of each bus

cycle. For non-pipelined cycles, ADS# can be asserted as early

as the clock edge after the clock edge on which the last

expected BRDY#of the cycle is sampled asserted, resulting in a

single idle state between cycles. For pipelined cycles if the

processor is prepared to start a new cycle, ADS#can be asserted

as early as one clock edge after NA#is sampled asserted.

If AHOLD is sampled asserted, ADS# is only driven in order to

perform a writeback cycle due to an inquire cycle that hits a

modified cache line.

The processor floats ADS# off the clock edge that BOFF# is

sampled asserted and off the clock edge that the processor

asserts HLDA in recognition of HOLD.

5.5

ADSC# (Address Strobe Copy)

Pin Attribute

Summary

Output

ADSC# has the identical function and timing as ADS#. In the

event ADS# becomes too heavily loaded due to a large fanout in

a system, ADSC# can be used to split the load across two

outputs, which can improve system timing.

96

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.6

AHOLD (Address Hold)

Pin Attribute

Summary

Input

AHOLD can be asserted by the system to initiate one or more

inquire cycles. To allow the system to drive the address bus

during an inquire cycle, the processor floats A[31:3] and AP off

the clock edge on which AHOLD is sampled asserted. The data

bus and all other control and status signals remain under the

control of the processor and are not floated. This allows a bus

cycle that is in progress when AHOLD is sampled asserted to

continue to completion. The processor resumes driving the

address bus off the clock edge on which AHOLD is sampled

negated.

If AHOLD is sampled asserted, ADS# is only asserted in order

to perform a writeback cycle due to an inquire cycle that hits a

modified cache line.

Sampled

The processor samples AHOLD on every clock edge. AHOLD is

recognized while INIT and RESET are sampled asserted.

Chapter 5

Signal Descriptions

97

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.7

AP (Address Parity)

Pin Attribute

Summary

Bidirectional

AP contains the even parity bit for cache line addresses driven

and sampled on A[31:5]. Even parity means that the total

number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not

used for the generation or checking of address parity because

these bits are not required to address a cache line.) AP is driven

by the processor during processor-initiated cycles and is

sampled by the processor during inquire cycles. If AP does not

reflect even parity during an inquire cycle, the processor

asserts APCHK# to indicate an address bus parity check. The

processor does not take an internal exception as the result of

detecting an address bus parity check, and system logic must

respond appropriately to the assertion of this signal.

Driven, Sampled, and

Floated

As an Output: The processor drives AP valid off the clock edge

on which ADS#is asserted until the clock edge on which NA#or

the last expected BRDY# of the cycle is sampled asserted. AP is

driven during memory cycles, I/O cycles, special bus cycles, and

interrupt acknowledge cycles. The processor continues to drive

AP while the bus is idle.

As an Input: The processor samples AP during inquire cycles on

the clock edge on which EADS#is sampled asserted.

The processor floats AP off the clock edge that AHOLD or

BOFF# is sampled asserted and off the clock edge that the

processor asserts HLDA in recognition of HOLD.

The processor resumes driving AP off the clock edge on which

the processor samples AHOLD or BOFF# negated and off the

clock edge on which the processor negates HLDA.

98

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.8

APCHK# (Address Parity Check)

Pin Attribute

Summary

Output

If the processor detects an address parity error during an

inquire cycle, APCHK# is asserted for one clock. The processor

does not take an internal exception as the result of detecting an

address bus parity check, and system logic must respond

appropriately to the assertion of this signal.

The processor is designed so that APCHK# does not glitch,

enabling the signal to be used as a clocking source for system

logic.

Driven

APCHK# is driven valid off the clock edge after the clock edge

on which the processor samples EADS# asserted. It is negated

off the next clock edge.

APCHK# is always driven except in the Three-State Test mode.

Chapter 5

Signal Descriptions

99

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.9

BE[7:0]# (Byte Enables)

Pin Attribute

Summary

Output

BE[7:0]# are used by the processor to indicate the valid data

bytes during a write cycle and the requested data bytes during

a read cycle. The byte enables can be used to derive address bits

A[2:0], which are not physically part of the processor’s address

bus. The processor checks and generates valid data parity for

the data bytes that are valid as defined by the byte enables. The

eight byte enables correspond to the eight bytes of the data bus

as follows:

■ BE7#: D[63:56]

■ BE6#: D[55:48]

■ BE5#: D[47:40]

■ BE4#: D[39:32]

■ BE3#: D[31:24]

■ BE2#: D[23:16]

■ BE1#: D[15:8]

■ BE0#: D[7:0]

The processor expects data to be driven by the system logic on

all eight bytes of the data bus during a burst cache-line read

cycle, independent of the byte enables that are asserted.

The byte enables are also used to distinguish between special

bus cycles as defined in Table 24 on page 142.

Driven and Floated

BE[7:0]# are driven off the same clock edge as ADS# and

remain in the same state until the clock edge on which NA# or

the last expected BRDY# of the cycle is sampled asserted.

BE[7:0]# are driven during memory cycles, I/O cycles, special

bus cycles, and interrupt acknowledge cycles.

The processor floats BE[7:0]# off the clock edge that BOFF# is

sampled asserted and off the clock edge that the processor

asserts HLDA in recognition of HOLD. Unlike the address bus,

BE[7:0]# are not floated in response to AHOLD.

100

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.10

BF[2:0] (Bus Frequency)

Pin Attribute

Summary

Inputs, Internal Pullups

BF[2:0] determine the internal operating frequency of the

processor. The frequency of the CLK input signal is multiplied

internally by a ratio determined by the state of these signals as

defined in Table 17. BF[2:0] have weak internal pullups and

default to the 3.5 multiplier if left unconnected.

Table 17. Processor-to-Bus Clock Ratios

State of BF[2:0] Inputs

Processor-Clock to Bus-Clock Ratio

100b

101b

110b

111b

000b

001b

010b

011b

2.0x

3.0x

6.0x

3.5x

4.5x

5.0x

4.0x

5.5x

Sampled

BF[2:0] are sampled during the falling transition of RESET.

They must meet a minimum setup time of 1.0 ms and a

minimum hold time of two clocks relative to the negation of

RESET.

Chapter 5

Signal Descriptions

101

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.11

BOFF# (Backoff)

Pin Attribute

Summary

Input

If BOFF# is sampled asserted, the processor unconditionally

aborts any cycles in progress and transitions to a bus hold state

by floating the following signals: A[31:3], ADS#, ADSC#, AP,

BE[7:0]#, CACHE#, D[63:0], D/C#, DP[7:0], LOCK#, M/IO#,

PCD, PWT, SCYC, and W/R#. These signals remain floated until

BOFF# is sampled negated. This allows an alternate bus master

or the system to control the bus.

When BOFF# is sampled negated, any processor cycle that was

aborted due to the assertion of BOFF# is restarted from the

beginning of the cycle, regardless of the number of transfers

that were completed. If BOFF# is sampled asserted on the same

clock edge as BRDY# of a bus cycle of any length, then BOFF#

takes precedence over the BRDY#. In this case, the cycle is

aborted and restarted after BOFF#is sampled negated.

Sampled

BOFF# is sampled on every clock edge. The processor floats its

bus signals off the clock edge on which BOFF# is sampled

asserted. These signals remain floated until the clock edge on

which BOFF#is sampled negated.

BOFF# is recognized while INIT and RESET are sampled

asserted.

102

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.12

BRDY# (Burst Ready)

Pin Attribute

Summary

Input, Internal Pullup

BRDY# is asserted to the processor by system logic to indicate

either that the data bus is being driven with valid data during a

read cycle or that the data bus has been latched during a write

cycle. If necessary, the system logic can insert bus cycle wait

states by negating BRDY# until it is ready to continue the data

transfer. BRDY# is also used to indicate the completion of

special bus cycles.

Sampled

BRDY# is sampled every clock edge within a bus cycle starting

with the clock edge after the clock edge that negates ADS#.

BRDY# is ignored while the bus is idle. The processor samples

the following inputs on the clock edge on which BRDY# is

sampled asserted: D[63:0], DP[7:0], and KEN# during read

cycles, EWBE# during write cycles (if not masked off), and

WB/WT# during read and write cycles. If NA# is sampled

asserted prior to BRDY#, then KEN# and WB/WT# are sampled

on the clock edge on which NA#is sampled asserted.

The number of times the processor expects to sample BRDY#

asserted depends on the type of bus cycle, as follows:

■ One time for a single-transfer cycle, a special bus cycle, or

each of two cycles in an interrupt acknowledge sequence

■ Four times for a burst cycle (once for each data transfer)

BRDY# can be held asserted for four consecutive clocks

throughout the four transfers of the burst, or it can be negated

to insert wait states.

Chapter 5

Signal Descriptions

103

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.13

BRDYC# (Burst Ready Copy)

Pin Attribute

Summary

Input, Internal Pullup

BRDYC# has the identical function as BRDY#. In the event

BRDY# becomes too heavily loaded due to a large fanout or

loading in a system, BRDYC# can be used to reduce this

loading, which improves timing.

Sampled

BRDYC#is sampled every clock edge within a bus cycle starting

with the clock edge after the clock edge that negates ADS#.

5.14

BREQ (Bus Request)

Pin Attribute

Summary

Output

BREQ is asserted by the processor to request the bus in order to

complete an internally pending bus cycle. The system logic can

use BREQ to arbitrate among the bus participants. If the

processor does not own the bus, BREQ is asserted until the

processor gains access to the bus in order to begin the pending

cycle or until the processor no longer needs to run the pending

cycle. If the processor currently owns the bus, BREQ is asserted

with ADS#. The processor asserts BREQ for each assertion of

ADS#but does not necessarily assert ADS#for each assertion of

BREQ.

Driven

BREQ is asserted off the same clock edge on which ADS# is

asserted. BREQ can also be asserted off any clock edge,

independent of the assertion of ADS#. BREQ can be negated

one clock edge after it is asserted.

The processor always drives BREQ except in the Three-State

Test mode.

104

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.15

CACHE# (Cacheable Access)

Pin Attribute

Summary

Output

For reads, CACHE# is asserted to indicate the cacheability of

the current bus cycle. In addition, if the processor samples

KEN # asserted, which indicates the driven address is

cacheable, the cycle is a 32-byte burst read cycle. For write

cycles, CACHE#is asserted to indicate the current bus cycle is a

modified cache-line writeback. KEN# is ignored during

writebacks. If CACHE# is not asserted, or if KEN# is sampled

negated during a read cycle, the cycle is not cacheable and

defaults to a single-transfer cycle.

Driven and Floated

CACHE#is driven off the same clock edge as ADS#and remains

in the same state until the clock edge on which NA# or the last

expected BRDY#of the cycle is sampled asserted.

CACHE# is floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in recognition of HOLD.

5.16

CLK (Clock)

Pin Attribute

Summary

Input

The CLK signal is the bus clock for the processor and is the

reference for all signal timings under normal operation (except

for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal

frequency multiplier applied to CLK to obtain the processor’s

core operating frequency. See “BF[2:0] (Bus Frequency)” on

page 101 for a list of the processor-to-bus clock ratios.

Sampled

The CLK signal must be stable a minimum of 1.0 ms prior to the

negation of RESET to ensure the proper operation of the

processor. See “CLK Switching Characteristics” on page 296 for

details regarding the CLK specifications.

Chapter 5

Signal Descriptions

105

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.17

D/C# (Data/Code)

Pin Attribute

Summary

Output

The processor drives D/C# during a memory bus cycle to

indicate whether it is addressing data or executable code. D/C#

is also used to define other bus cycles, including interrupt

acknowledge and special cycles. See Table 23 and Table 24 on

page 142 for more details.

Driven and Floated

D/C# is driven off the same clock edge as ADS# and remains in

the same state until the clock edge on which NA# or the last

expected BRDY# of the cycle is sampled asserted. D/C# is

driven during memory cycles, I/O cycles, special bus cycles, and

interrupt acknowledge cycles.

D/C# is floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in recognition of HOLD.

106

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.18

D[63:0] (Data Bus)

Pin Attribute

Summary

Bidirectional

D[63:0] represent the processor’s 64-bit data bus. Each of the

eight bytes of data that comprise this bus is qualified as valid

by its corresponding byte enable. See “BE[7:0]# (Byte

Enables)” on page 100.

Driven, Sampled, and

Floated

As Outputs: For single-transfer write cycles, the processor drives

D[63:0] with valid data one clock edge after the clock edge on

which ADS# is asserted and D[63:0] remain in the same state

until the clock edge on which BRDY#is sampled asserted. If the

cycle is a writeback—in which case four 8-byte transfers

occur—D[63:0] are driven one clock edge after the clock edge

on which ADS# is asserted and are subsequently changed off

the clock edge on which each BRDY# assertion of the burst

cycle is sampled.

If the assertion of ADS# represents a pipelined write cycle that

follows a read cycle, the processor does not drive D[63:0] until it

is certain that contention on the data bus will not occur. In this

case, D[63:0] are driven the clock edge after the last expected

BRDY#of the previous cycle is sampled asserted.

As Inputs: During read cycles, the processor samples D[63:0] on

the clock edge on which BRDY#is sampled asserted.

The processor always floats D[63:0] except when they are being

driven during a write cycle as described above. In addition,

D[63:0] are floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts

HLDA in recognition of HOLD.

Chapter 5

Signal Descriptions

107

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.19

DP[7:0] (Data Parity)

Pin Attribute

Summary

Bidirectional

DP[7:0] are even parity bits for each valid byte of data—as

defined by BE[7:0]#—driven and sampled on the D[63:0] data

bus. Even parity means that the total number of 1 bits within

each byte of data and its respective data parity bit is an even

number. DP[7:0] are driven by the processor during write cycles

and sampled by the processor during read cycles.

If the processor detects bad parity on any valid byte of data

during a read cycle, PCHK# is asserted for one clock beginning

the clock edge after BRDY# is sampled asserted. The processor

does not take an internal exception as the result of detecting a

data parity check, and system logic must respond appropriately

to the assertion of this signal.

The eight data parity bits correspond to the eight bytes of the

data bus as follows:

■ DP7: D[63:56]

■ DP6: D[55:48]

■ DP5: D[47:40]

■ DP4: D[39:32]

■ DP3: D[31:24]

■ DP2: D[23:16]

■ DP1: D[15:8]

■ DP0: D[7:0]

For systems that do not support data parity, DP[7:0] should be

connected to V through pullup resistors.

CC3

Driven, Sampled, and

Floated

As Outputs: For single-transfer write cycles, the processor drives

DP[7:0] with valid parity one clock edge after the clock edge on

which ADS# is asserted and DP[7:0] remain in the same state

until the clock edge on which BRDY# is sampled asserted. If the

cycle is a writeback, DP[7:0] are driven one clock edge after the

clock edge on which ADS# is asserted and are subsequently

changed off the clock edge on which each BRDY# assertion of

the burst cycle is sampled.

As Inputs: During read cycles, the processor samples DP[7:0] on

the clock edge BRDY# is sampled asserted.

108

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The processor always floats DP[7:0] except when they are being

driven during a write cycle as described above. In addition,

DP[7:0] are floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts

HLDA in recognition of HOLD.

5.20

EADS# (External Address Strobe)

Pin Attribute

Summary

Input

System logic asserts EADS# during a cache inquire cycle to

indicate that the address bus contains a valid address. EADS#

can only be driven after the system logic has taken control of

the address bus by asserting AHOLD or BOFF# or by receiving

HLDA. The processor responds to the sampling of EADS# and

the address bus by driving HIT#, which indicates if the inquired

cache line exists in the processor’s caches, and HITM#, which

indicates if it is in the modified state.

Sampled

If AHOLD or BOFF# is asserted by the system logic in order to

execute a cache inquire cycle, the processor begins sampling

EADS# two clock edges after AHOLD or BOFF# is sampled

asserted. If the system logic asserts HOLD in order to execute a

cache inquire cycle, the processor begins sampling EADS# two

clock edges after the clock edge HLDA is asserted by the

processor.

EADS#is ignored during the following conditions:

■ One clock edge after the clock edge on which EADS# is

sampled asserted

■ Two clock edges after the clock edge on which ADS# is

asserted

■ When the processor is driving the address bus

■ When the processor asserts HITM#

Chapter 5

Signal Descriptions

109

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.21

EWBE# (External Write Buffer Empty)

Pin Attribute

Summary

Input

The system logic can negate EWBE#to the processor to indicate

that its external write buffers are full and that additional data

cannot be stored at this time. This causes the processor to delay

the following activities until EWBE# is sampled asserted:

■ The commitment of write hit cycles to cache lines in the

modified state or exclusive state in the processor’s caches

■ The decode and execution of an instruction that follows a

currently-executing serializing instruction

■ The assertion or negation of SMIACT#

■ The entering of the Halt state and the Stop Grant state

Negating EWBE# does not prevent the completion of any type

of cycle that is currently in progress.

Sampled

The processor samples EWBE# on each clock edge that BRDY#

is sampled asserted during all memory write cycles (except

writeback cycles), I/O write cycles, and special bus cycles.

If EWBE# is sampled negated, it is sampled on every clock edge

until it is asserted, and then it is ignored until BRDY# is

sampled asserted in the next write cycle or special cycle.

If EFER[3] is set to 1, then EWBE# is ignored by the processor.

For more information on the EFER settings and EWBE#, see

“EWBE# Control” on page 229.

110

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.22

FERR# (Floating-Point Error)

Pin Attribute

Summary

Output

The assertion of FERR# indicates the occurrence of an

unmasked floating-point exception resulting from the

execution of a floating-point instruction. This signal is provided

to allow the system logic to handle this exception in a manner

consistent with IBM-compatible PC/AT systems. See “Handling

Floating-Point Exceptions” on page 237 for a system logic

implementation that supports floating-point exceptions.

The state of the numeric error (NE) bit in CR0 does not affect

the FERR# signal.

The processor is designed so that FERR# does not glitch,

enabling the signal to be used as a clocking source for system

logic.

Driven

The processor asserts FERR# on the instruction boundary of

the next floating-point instruction, MMX instruction, 3DNow!

instruction, or WAIT instruction that occurs following the

floating-point instruction that caused the unmasked

floating-point exception—that is, FERR# is not asserted at the

time the exception occurs. The IGNNE# signal does not affect

the assertion of FERR#.

FERR#is negated during the following conditions:

■ Following the successful execution of the floating-point

instructions FCLEX, FINIT, FSAVE, and FSTENV

■ Under certain circumstances, following the successful

execution of the floating-point instructions FLDCW,

FLDENV, and FRSTOR, which load the floating-point status

word or the floating-point control word

■ Following the falling transition of RESET

FERR#is always driven except in the Three-State Test mode.

See “IGNNE# (Ignore Numeric Exception)” on page 116 for

more details on floating-point exceptions.

Chapter 5

Signal Descriptions

111

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.23

FLUSH# (Cache Flush)

Pin Attribute

Summary

Input

In response to sampling FLUSH# asserted, the processor writes

back any cache lines in the L1 data cache or L2 cache that are in

the modified state, invalidates all lines in the L1 and L2 caches,

and then executes a flush acknowledge special cycle. See

Table 24 on page 142 for the bus definition of special cycles.

In addition, FLUSH# is sampled when RESET is negated to

determine if the processor enters the Three-State Test mode. If

FLUSH# is 0 during the falling transition of RESET, the

processor enters the Three-State Test mode instead of

performing the normal RESET functions.

Sampled

FLUSH# is sampled and latched as a falling edge-sensitive

signal. During normal operation (not RESET), FLUSH# is

sampled on every clock edge but is not recognized until the next

instruction boundary.

■ If FLUSH# is asserted synchronously (see Table 19 on

page 140), it can be asserted for a minimum of one clock.

■ If FLUSH# is asserted asynchronously, it must have been

negated for a minimum of two clocks, followed by an

assertion of a minimum of two clocks.

FLUSH#is also sampled during the falling transition of RESET.

If RESET and FLUSH# are driven synchronously, FLUSH# is

sampled on the clock edge prior to the clock edge on which

RESET is sampled negated. If RESET is driven asynchronously,

the minimum setup and hold time for FLUSH#, relative to the

negation of RESET, is two clocks.

112

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.24

HIT# (Inquire Cycle Hit)

Pin Attribute

Summary

Output

The processor asserts HIT# during an inquire cycle to indicate

that the cache line is valid within the processor’s L1 and/or L2

caches (also known as a cache hit). The cache line can be in the

modified, exclusive, or shared state.

Driven

HIT# is always driven—except in the Three-State Test mode—

and only changes state the clock edge after the clock edge on

which EADS# is sampled asserted. It is driven in the same state

until the next inquire cycle.

5.25

HITM# (Inquire Cycle Hit To Modified Line)

Pin Attribute

Summary

Output

The processor asserts HITM# during an inquire cycle to

indicate that the cache line exists in the processor’s L1 data

cache or L2 cache in the modified state. The processor performs

a writeback cycle as a result of this cache hit. If an inquire cycle

hits a cache line that is currently being written back, the

processor asserts HITM# but does not execute another

writeback cycle. The system logic must not expect the processor

to assert ADS# each time HITM# is asserted.

Driven

HITM# is always driven—except in the Three-State Test

mode—and, in particular, is driven to represent the result of an

inquire cycle the clock edge after the clock edge on which

EADS# is sampled asserted. If HITM# is negated in response to

the inquire address, it remains negated until the next inquire

cycle. If HITM#is asserted in response to the inquire address, it

remains asserted throughout the writeback cycle and is negated

one clock edge after the last BRDY# of the writeback is

sampled asserted.

Chapter 5

Signal Descriptions

113

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.26

HLDA (Hold Acknowledge)

Pin Attribute

Summary

Output

When HOLD is sampled asserted, the processor completes the

current bus cycles, floats the processor bus, and asserts HLDA

in an acknowledgment that these events have been completed.

The processor does not assert HLDA until the completion of a

locked sequence of cycles. While HLDA is asserted, another bus

master can drive cycles on the bus, including inquire cycles to

the processor. The following signals are floated when HLDA is

asserted: A[31:3], ADS#, ADSC#, AP, BE[7:0]#, CACHE#,

D[63:0], D/C#, DP[7:0], LOCK#, M/IO#, PCD, PWT, SCYC, and

W/R#.

The processor is designed so that HLDA does not glitch.

Driven

HLDA is always driven except in the Three-State Test mode. If a

processor cycle is in progress while HOLD is sampled asserted,

HLDA is asserted one clock edge after the last BRDY# of the

cycle is sampled asserted. If the bus is idle, HLDA is asserted

one clock edge after HOLD is sampled asserted. HLDA is

negated one clock edge after the clock edge on which HOLD is

sampled negated.

The assertion of HLDA is independent of the sampled state of

BOFF#.

The processor floats the bus every clock in which HLDA is

asserted.

114

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.27

HOLD (Bus Hold Request)

Pin Attribute

Summary

Input

The system logic can assert HOLD to gain control of the

processor’s bus. When HOLD is sampled asserted, the processor

completes the current bus cycles, floats the processor bus, and

asserts HLDA in an acknowledgment that these events have

been completed.

Sampled

The processor samples HOLD on every clock edge. If a

processor cycle is in progress while HOLD is sampled asserted,

HLDA is asserted one clock edge after the last BRDY# of the

cycle is sampled asserted. If the bus is idle, HLDA is asserted

one clock edge after HOLD is sampled asserted. HOLD is

recognized while INIT and RESET are sampled asserted.

Chapter 5

Signal Descriptions

115

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.28

IGNNE# (Ignore Numeric Exception)

Pin Attribute

Summary

Input

IGNNE#, in conjunction with the numeric error (NE) bit in the

CR0 register, is used by the system logic to control the effect of

an unmasked floating-point exception on a previous

floating-point instruction during the execution of a

floating-point instruction, MMX instruction, 3DNow!

instruction, or the WAIT instruction—hereafter referred to as

the target instruction.

If an unmasked floating-point exception is pending and the

target instruction is considered error-sensitive, then the

relationship between NE and IGNNE# is as follows:

■ If NE = 0, then:

•

If IGNNE# is sampled asserted, the processor ignores the

floating-point exception and continues with the

execution of the target instruction.

•

If IGNNE# is sampled negated, the processor waits until

it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted.

•

If IGNNE# is sampled asserted while waiting, the

processor ignores the floating-point exception and

continues with the execution of the target

instruction.

•

If INTR, SMI#, NMI, or INIT is sampled asserted

while waiting, the processor handles its assertion

appropriately.

■ If NE = 1, the processor invokes the INT 10h exception

handler.

If an unmasked floating-point exception is pending and the

target instruction is considered error-insensitive, then the

processor ignores the floating-point exception and continues

with the execution of the target instruction.

FERR# is not affected by the state of the NE bit or IGNNE#.

FERR# is always asserted at the instruction boundary of the

target instruction that follows the floating-point instruction

that caused the unmasked floating-point exception.

116

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

This signal is provided to allow the system logic to handle

exceptions in a manner consistent with IBM-compatible PC/AT

systems.

Sampled

The processor samples IGNNE# as a level-sensitive input on

every clock edge. The system logic can drive the signal either

synchronously or asynchronously. If it is asserted

asynchronously, it must be asserted for a minimum pulse width

of two clocks.

5.29

INIT (Initialization)

Pin Attribute

Summary

Input

The assertion of INIT causes the processor to empty its

pipelines, to initialize most of its internal state, and to branch

to address FFFF_FFF0h—the same instruction execution

starting point used after RESET. Unlike RESET, the processor

preserves the contents of its caches, the floating-point state, the

MMX state, Model-Specific Registers, the CD and NW bits of

the CR0 register, and other specific internal resources.

INIT can be used as an accelerator for 80286 code that requires

a reset to exit from Protected mode back to Real mode.

Sampled

INIT is sampled and latched as a rising edge-sensitive signal.

INIT is sampled on every clock edge but is not recognized until

the next instruction boundary. During an I/O write cycle, it must

be sampled asserted a minimum of three clock edges before

BRDY# is sampled asserted if it is to be recognized on the

boundary between the I/O write instruction and the following

instruction.

■ If INIT is asserted synchronously (see Table 19 on page 140),

it can be asserted for a minimum of one clock.

■ If it is asserted asynchronously, it must have been negated

for a minimum of two clocks, followed by an assertion of a

minimum of two clocks.

Chapter 5

Signal Descriptions

117

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.30

INTR (Maskable Interrupt)

Pin Attribute

Summary

Input

INTR is the system’s maskable interrupt input to the processor.

When the processor samples and recognizes INTR asserted, the

processor executes a pair of interrupt acknowledge bus cycles

and then jumps to the interrupt service routine specified by the

interrupt number that was returned during the interrupt

acknowledge sequence. The processor only recognizes INTR if

the interrupt flag (IF) in the EFLAGS register equals 1.

Sampled

The processor samples INTR as a level-sensitive input on every

clock edge, but the interrupt request is not recognized until the

next instruction boundary. The system logic can drive INTR

either synchronously or asynchronously. If it is asserted

asynchronously, it must be asserted for a minimum pulse width

of two clocks. In order to be recognized, INTR must remain

asserted until an interrupt acknowledge sequence is complete.

5.31

INV (Invalidation Request)

Pin Attribute

Summary

Input

During an inquire cycle, the state of INV determines whether

an addressed cache line that is found in the processor’s L1

and/or L2 caches transitions to the invalid state or the shared

state.

If INV is sampled asserted during an inquire cycle, the

processor transitions the cache line (if found) to the invalid

state, regardless of its previous state. If INV is sampled negated

during an inquire cycle, the processor transitions the cache line

(if found) to the shared state. In either case, if the cache line is

found in the modified state, the processor writes it back to

memory before changing its state.

Sampled

INV is sampled on the clock edge on which EADS# is sampled

asserted.

118

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.32

KEN# (Cache Enable)

Pin Attribute

Summary

Input

If KEN# is sampled asserted, it indicates that the address

presented by the processor is cacheable. If KEN# is sampled

asserted and the processor intends to perform a cache-line fill

(signified by the assertion of CACHE#), the processor executes

a 32-byte burst read cycle and expects to sample BRDY#

asserted a total of four times. If KEN# is sampled negated

during a read cycle, a single-transfer cycle is executed and the

processor does not cache the data. For write cycles, CACHE# is

asserted to indicate the current bus cycle is a modified

cache-line writeback. KEN#is ignored during writebacks.

If PCD is asserted during a bus cycle, the processor does not

cache any data read during that cycle, regardless of the state of

KEN#. See “PCD (Page Cache Disable)” on page 124 for more

details.

If the processor has sampled the state of KEN# during a cycle,

and that cycle is aborted due to the sampling of BOFF#

asserted, the system logic must ensure that KEN# is sampled in

the same state when the processor restarts the aborted cycle.

Sampled

KEN# is sampled on the clock edge on which the first BRDY# or

NA# of a read cycle is sampled asserted. If the read cycle is a

burst, KEN# is ignored during the last three assertions of

BRDY#. KEN# is sampled during read cycles only when

CACHE# is asserted.

Chapter 5

Signal Descriptions

119

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.33

LOCK# (Bus Lock)

Pin Attribute

Summary

Output

The processor asserts LOCK# during a sequence of bus cycles to

ensure that the cycles are completed without allowing other bus

masters to intervene. Locked operations consist of two to five

bus cycles. LOCK# is asserted during the following operations:

■ An interrupt acknowledge sequence

■ Descriptor Table accesses

■ Page Directory and Page Table accesses

■ XCHG instruction

■ An instruction with an allowable LOCK prefix

In order to ensure that locked operations appear on the bus and

are visible to the entire system, any data operands addressed

during a locked cycle that reside in the processor’s caches are

flushed and invalidated from the caches prior to the locked

operation. If the cache line is in the modified state, it is written

back and invalidated prior to the locked operation. Likewise,

any data read during a locked operation is not cached.

The processor is designed so that LOCK# does not glitch.

Driven and Floated

During a locked cycle, LOCK# is asserted off the same clock

edge on which ADS# is asserted and remains asserted until the

last BRDY# of the last bus cycle is sampled asserted. The

processor negates LOCK# for at least one clock between

consecutive sequences of locked operations to allow the system

logic to arbitrate for the bus.

LOCK# is floated off the clock edge on which BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD. When LOCK# is floated due to BOFF#

sampled asserted, the system logic is responsible for preserving

the lock condition while LOCK# is in the high-impedance state.

120

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.34

M/IO# (Memory or I/O)

Pin Attribute

Summary

Output

The processor drives M/IO# during a bus cycle to indicate

whether it is addressing the memory or I/O space. If M/IO# = 1,

the processor is addressing memory or a memory-mapped I/O

port as the result of an instruction fetch or an instruction that

loads or stores data. If M/IO# = 0, the processor is addressing an

I/O port during the execution of an I/O instruction. In addition,

M/IO# is used to define other bus cycles, including interrupt

acknowledge and special cycles. See Table 23 and Table 24 on

page 142 for more details.

Driven and Floated

M/IO# is driven off the same clock edge as ADS# and remains in

the same state until the clock edge on which NA# or the last

expected BRDY# of the cycle is sampled asserted. M/IO# is

driven during memory cycles, I/O cycles, special bus cycles, and

interrupt acknowledge cycles.

M/IO# is floated off the clock edge on which BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD.

Chapter 5

Signal Descriptions

121

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.35

NA# (Next Address)

Pin Attribute

Summary

Input

System logic asserts NA# to indicate to the processor that it is

ready to accept another bus cycle pipelined into the previous

bus cycle. ADS#, along with address and status signals, can be

asserted as early as one clock edge after NA# is sampled

asserted if the processor is prepared to start a new cycle.

Because the processor allows a maximum of two cycles to be in

progress at a time, the assertion of NA# is sampled while two

cycles are in progress, but ADS# is not asserted until the

completion of the first cycle.

Sampled

NA# is sampled every clock edge during bus cycles, starting one

clock edge after the clock edge that negates ADS#, until the last

expected BRDY# of the last executed cycle is sampled asserted

(with the exception of the clock edge after the clock edge that

negates the ADS# for a second pending cycle). Because the

processor latches NA# when sampled, the system logic only

needs to assert NA# for one clock.

122

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.36

NMI (Non-Maskable Interrupt)

Pin Attribute

Summary

Input

When NMI is sampled asserted, the processor jumps to the

interrupt service routine defined by interrupt number 02h.

Unlike the INTR signal, software cannot mask the effect of NMI

if it is sampled asserted by the processor. However, NMI is

temporarily masked upon entering System Management Mode

(SMM). In addition, an interrupt acknowledge cycle is not

executed because the interrupt number is predefined.

If NMI is sampled asserted while the processor is executing the

interrupt service routine for a previous NMI, the subsequent

NMI remains pending until the completion of the execution of

the IRET instruction at the end of the interrupt service routine.

Sampled

NMI is sampled and latched as a rising edge-sensitive signal.

During normal operation, NMI is sampled on every clock edge

but is not recognized until the next instruction boundary.

■ If NMI is asserted synchronously (see Table 19 on page 140),

it can be asserted for a minimum of one clock.

■ If NMI is asserted asynchronously, it must have been

negated for a minimum of two clocks, followed by an

assertion of a minimum of two clocks.

Chapter 5

Signal Descriptions

123

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.37

PCD (Page Cache Disable)

Pin Attribute

Summary

Output

The processor drives PCD to indicate the operating system’s

specification of cacheability for the page being addressed.

System logic can use PCD to control external caching. If PCD is

asserted, the addressed page is not cached. If PCD is negated,

the cacheability of the addressed page depends upon the state

of CACHE# and KEN#.

The state of PCD depends upon the processor’s operating mode

and the state of certain bits in its control registers and TLB as

follows:

■ In Real mode, or in Protected and Virtual-8086 modes while

paging is disabled (PG bit in CR0 set to 0):

PCD output = CD bit in CR0

■ In Protected and Virtual-8086 modes while caching is

enabled (CD bit in CR0 set to 0) and paging is enabled (PG

bit in CR0 set to 1):

•

For accesses to I/O space, page directory entries, and

other non-paged accesses:

PCD output = PCD bit in CR3

For accesses to 4-Kbyte page table entries or 4-Mbyte

pages:

PCD output = PCD bit in page directory entry

For accesses to 4-Kbyte pages:

PCD output = PCD bit in page table entry

Driven and Floated

PCD is driven off the same clock edge as ADS# and remains in

the same state until the clock edge on which NA# or the last

expected BRDY# of the cycle is sampled asserted.

PCD is floated off the clock edge that BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD.

124

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.38

PCHK# (Parity Check)

Pin Attribute

Summary

Output

The processor asserts PCHK# during read cycles if it detects an

even parity error on one or more valid bytes of D[63:0] during a

read cycle. (Even parity means that the total number of 1 bits

within each byte of data and its respective data parity bit is

even.) The processor checks data parity for the data bytes that

are valid, as defined by BE[7:0]#, the byte enables.

PCHK# is always driven but is only asserted for memory and I/O

read bus cycles and the second cycle of an interrupt

acknowledge sequence. PCHK# is not driven during any type of

write cycles or special bus cycles. The processor does not take

an internal exception as the result of detecting a data parity

error, and system logic must respond appropriately to the

assertion of this signal.

The processor is designed so that PCHK# does not glitch,

enabling the signal to be used as a clocking source for system

logic.

Driven

PCHK# is always driven except in the Three-State Test mode.

For each BRDY# returned to the processor during a read cycle

with a parity error detected on the data bus, PCHK# is asserted

for one clock, one clock edge after BRDY# is sampled asserted.

Chapter 5

Signal Descriptions

125

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.39

PWT (Page Writethrough)

Pin Attribute

Summary

Output

The processor drives PWT to indicate the operating system’s

specification of the writeback state or writethrough state for

the page being addressed. PWT, together with WB/WT#,

specifies the data cache-line state during cacheable read misses

and write hits to shared cache lines. See “WB/WT# (Writeback

or Writethrough)” on page 139 for more details.

The state of PWT depends upon the processor’s operating mode

and the state of certain bits in its control registers and TLB as

follows:

■ In Real mode, or in Protected and Virtual-8086 modes while

paging is disabled (PG bit in CR0 set to 0):

PWT output = 0 (writeback state)

■ In Protected and Virtual-8086 modes while paging is

enabled (PG bit in CR0 set to 1):

•

For accesses to I/O space, page directory entries, and

other non-paged accesses:

PWT output = PWT bit in CR3

For accesses to 4-Kbyte page table entries or 4-Mbyte

pages:

PWT output = PWT bit in page directory entry

For accesses to 4-Kbyte pages:

PWT output = PWT bit in page table entry

Driven and Floated

PWT is driven off the same clock edge as ADS# and remains in

the same state until the clock edge on which NA# or the last

expected BRDY# of the cycle is sampled asserted.

PWT is floated off the clock edge on which BOFF# is sampled

asserted and off the clock edge on which the processor asserts

HLDA in response to HOLD.

126

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.40

RESET (Reset)

Pin Attribute

Summary

Input

When the processor samples RESET asserted, it immediately

flushes and initializes all internal resources and its internal

state including its pipelines and caches, the floating-point

state, the MMX state, the 3DNow! state, and all registers, and

then the processor jumps to address FFFF_FFF0h to start

instruction execution.

The FLUSH# signal is sampled during the falling transition of

RESET to invoke the Three-State Test mode.

Sampled

RESET is sampled as a level-sensitive input on every clock

edge. System logic can drive the signal either synchronously or

asynchronously.

During the initial power-on reset of the processor, RESET must

remain asserted for a minimum of 1.0 ms after CLK and V

reach specification before it is negated.

CC

During a warm reset, while CLK and V

are within their

CC

specification, RESET must remain asserted for a minimum of

15 clocks prior to its negation.

Chapter 5

Signal Descriptions

127

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.41

RSVD (Reserved)

Pin Attribute

Summary

Not Applicable

Reserved signals are a special class of pins that can be treated

in one of the following ways:

■ As no-connect (NC) pins, in which case these pins are left

unconnected

■ As pins connected to the system logic as defined by the

industry-standard Super7 and Socket 7 interface

■ Any combination of NC and Socket 7 pins

In any case, if the RSVD pins are treated accordingly, the

normal operation of the AMD-K6-2E+ processor is not adversely

affected in any manner.

128

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.42

SCYC (Split Cycle)

Pin Attribute

Summary

Output

The processor asserts SCYC during misaligned, locked transfers

on the D[63:0] data bus. The processor generates additional bus

cycles to complete the transfer of misaligned data.

For purposes of bus cycles, the term aligned means:

■ Any 1-byte transfers

■ 2-byte and 4-byte transfers that lie within 4-byte address

boundaries

■ 8-byte transfers that lie within 8-byte address boundaries

Driven and Floated

SCYC is asserted off the same clock edge as ADS#, and negated

off the clock edge on which NA# or the last expected BRDY# of

the entire locked sequence is sampled asserted. SCYC is only

valid during locked memory cycles.

SCYC is floated off the clock edge on which BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD.

Chapter 5

Signal Descriptions

129

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.43

SMI# (System Management Interrupt)

Pin Attribute

Summary

Input, Internal Pullup

The assertion of SMI# causes the processor to enter System

Management Mode (SMM). Upon recognizing SMI#, the

processor performs the following actions, in the order shown:

1. Flushes its instruction pipelines

2. Completes all pending and in-progress bus cycles

3. Acknowledges the interrupt by asserting SMIACT# after

sampling EWBE# asserted (if EWBE# is masked off, then

SMIACT# is not affected by EWBE#)

4. Saves the internal processor state in SMM memory

5. Disables interrupts by clearing the interrupt flag (IF) in

EFLAGS and disables NMI interrupts

6. Jumps to the entry point of the SMM service routine at the

SMM base physical address, which defaults to 0003_8000h

in SMM memory

See “System Management Mode (SMM)” on page 241 for more

details regarding SMM.

Sampled

SMI# is sampled and latched as a falling edge-sensitive signal.

SMI# is sampled on every clock edge but is not recognized until

the next instruction boundary. If SMI# is to be recognized on

the instruction boundary associated with a BRDY#, it must be

sampled asserted a minimum of three clock edges before the

BRDY# is sampled asserted.

■ If SMI# is asserted synchronously (see Table 19 on

page 140), it can be asserted for a minimum of one clock.

■ If SMI# is asserted asynchronously, it must have been

negated for a minimum of two clocks followed by an

assertion of a minimum of two clocks.

A second assertion of SMI# while in SMM is latched but is not

recognized until the SMM service routine is exited.

130

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.44

SMIACT# (System Management Interrupt Active)

Pin Attribute

Summary

Output

The processor acknowledges the assertion of SMI# with the

assertion of SMIACT# to indicate that the processor has

entered System Management Mode (SMM). The system logic

can use SMIACT# to enable SMM memory. See “SMI# (System

Management Interrupt)” on page 130 for more details.

See “System Management Mode (SMM)” on page 241 for more

details regarding SMM.

Driven

The processor asserts SMIACT# after the last BRDY# of the last

pending bus cycle is sampled asserted (including all pending

write cycles) and after EWBE# is sampled asserted (if EWBE#

is masked off, then SMIACT# is not affected by EWBE#).

SMIACT# remains asserted until after the last BRDY# of the

last pending bus cycle associated with exiting SMM is sampled

asserted.

SMIACT# remains asserted during any flush, internal snoop, or

writeback cycle due to an inquire cycle.

Chapter 5

Signal Descriptions

131

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.45

STPCLK# (Stop Clock)

Pin Attribute

Summary

Input, Internal Pullup

The assertion of STPCLK# causes the processor to enter the

Stop Grant state, during which the processor’s internal clock is

stopped. From the Stop Grant state, the processor can

subsequently transition to the Stop Clock state, in which the

bus clock CLK is stopped. Upon recognizing STPCLK#, the

processor performs the following actions, in the order shown:

1. Flushes its instruction pipelines

2. Completes all pending and in-progress bus cycles

3. Acknowledges the STPCLK# assertion by executing a Stop

Grant special bus cycle (see Table 24 on page 142)

4. Stops its internal clock after BRDY# of the Stop Grant

special bus cycle is sampled asserted and after EWBE# is

sampled asserted (if EWBE# is masked off, then entry into

the Stop Grant state is not affected by EWBE#)

5. Enters the Stop Clock state if the system logic stops the bus

clock CLK (optional)

See “Clock Control” on page 275 for more details regarding

clock control.

Sampled

STPCLK# is sampled as a level-sensitive input on every clock

edge but is not recognized until the next instruction boundary.

System logic can drive the signal either synchronously or

asynchronously. If it is asserted asynchronously, it must be

asserted for a minimum pulse width of two clocks.

STPCLK# must remain asserted until recognized, which is

indicated by the completion of the Stop Grant special cycle.

132

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.46

TCK (Test Clock)

Pin Attribute

Summary

Input, Internal Pullup

TCK is the clock for boundary-scan testing using the Test

Access Port (TAP). See “Boundary-Scan Test Access Port

(TAP)” on page 253 for details regarding the operation of the

TAP controller.

Sampled

The processor always samples TCK, except while TRST# is

asserted.

5.47

TDI (Test Data Input)

Pin Attribute

Summary

Input, Internal Pullup

TDI is the serial test data and instruction input for

boundary-scan testing using the Test Access Port (TAP). See

“Boundary-Scan Test Access Port (TAP)” on page 253 for

details regarding the operation of the TAP controller.

Sampled

The processor samples TDI on every rising TCK edge, but only

while in the Shift-IR and Shift-DR states.

5.48

TDO (Test Data Output)

Pin Attribute

Summary

Output

TDO is the serial test data and instruction output for

boundary-scan testing using the Test Access Port (TAP). See

“Boundary-Scan Test Access Port (TAP)” on page 253 for

details regarding the operation of the TAP controller.

Driven and Floated

The processor drives TDO on every falling TCK edge, but only

while in the Shift-IR and Shift-DR states. TDO is floated at all

other times.

Chapter 5

Signal Descriptions

133

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.49

TMS (Test Mode Select)

Pin Attribute

Summary

Input, Internal Pullup

TMS specifies the test function and sequence of state changes

for boundary-scan testing using the Test Access Port (TAP). See

“Boundary-Scan Test Access Port (TAP)” on page 253 for

details regarding the operation of the TAP controller.

Sampled

The processor samples TMS on every rising TCK edge. If TMS is

sampled High for five or more consecutive clocks, the TAP

controller enters its Test-Logic-Reset state, regardless of the

controller state. This action is the same as that achieved by

asserting TRST#.

5.50

TRST# (Test Reset)

Pin Attribute

Summary

Input, Internal Pullup

The assertion of TRST# initializes the Test Access Port (TAP) by

resetting its state machine to the Test-Logic-Reset state. See

“Boundary-Scan Test Access Port (TAP)” on page 253 for

details regarding the operation of the TAP controller.

Sampled

TRST# is a completely asynchronous input that does not

require a minimum setup and hold time relative to TCK. See

Table 70 on page 308 for the minimum pulse width

requirement.

134

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.51

VCC2DET (VCC2 Detect)

Pin Attribute

Summary

Output (supported on the CPGA package only)

VCC2DET is internally tied to V (logic level 0) to indicate to

SS

the system logic that it must supply the specified dual-voltage

requirements to the V

and V

pins. The V

pins supply

CC2

CC3

CC2

voltage to the processor core, independent of the voltage

supplied to the I/O buffers on the V pins. Upon sampling

CC3

VCC2DET Low, system logic should sample VCC2H/L# to

identify core voltage requirements

Note that this pin is not supported on the OBGA package.

Driven

VCC2DET always equals 0 and is never floated—even during

the Three-State Test mode.

Chapter 5

Signal Descriptions

135

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.52

VCC2H/L# (VCC2 High/Low)

Pin Attribute

Summary

Output (supported on the CPGA package only)

VCC2H/L# is internally tied to V (logic level 0) to indicate to

SS

the system logic that it must supply the specified processor core

voltage to the V

pins. The V

pins supply voltage to the

CC2

processor core, independent of the voltage supplied to the I/O

buffers on the V pins. Upon sampling VCC2DET Low to

CC3

identify dual-voltage processor requirements, system logic

should sample VCC2H/L# to identify the core voltage

requirements: 2.9-V and 3.2-V products (High) or 2.4-V and

lower products (Low).

■ VCC2H/L# is only driven High on older legacy (0.35-micron

process technology) AMD-K6 processors to indicate core

voltages of 2.9 V and 3.2 V.

■ VCC2H/L# is driven Low for all AMD-K6 processors with a

core voltage requirement of 2.4 V or less. Note that all AMD

products based on the 0.18-micron process technology,

including the AMD-K6-2E+ processor, are 2.0 V or less.

Note that this pin is not supported on the OBGA package.

Driven

VCC2H/L# always equals 0 and is never floated for 2.4-V and

lower products—even during the Three-State Test mode. To

ensure proper operation for 2.9-V and 3.2-V products, system

logic that samples VCC2H/L# should design a weak pullup

resistor for this signal.

Table 18. Output Pin Float Conditions for VCC2 High/Low

Name

Floated At:

Always Driven

VCC2DET¹

VCC2H/L#¹

Notes:

1. All outputs except VCC2DET, VCC2H/L#, and TDO float during the Three-State Test mode.

136

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.53

VID[4:0] (Voltage Identification)

Pin Attribute

Summary

Output

For AMD PowerNow! technology-enabled processors, the

VID[4:0] signals are used to drive the VID inputs of the DC/DC

regulator that generates the core voltage for the processor. The

processor VID[4:0] outputs default to 01010b when RESET is

sampled asserted.

Note that these pins are supported on the low-power versions

only of the AMD-K6-2+ processor. For more information about

these signals, see the Embedded AMD-K6™ Processors BIOS

Design Guide Application Note, order# 23913.

Driven

VID[4:0] are initialized to the default state after RESET is

sampled asserted, the CPU input clock is running, and the core

and I/O voltages are applied. Thereafter, the VID [4:0] outputs

are always driven.

Chapter 5

Signal Descriptions

137

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.54

W/R# (Write/Read)

Pin Attribute

Summary

Output

The processor drives W/R# to indicate whether it is performing

a write or a read cycle on the bus. In addition, W/R# is used to

define other bus cycles, including interrupt acknowledge and

special cycles. See Table 23 and Table 24 on page 142 for more

details.

Driven and Floated

W/R# is driven off the same clock edge as ADS# and remains in

the same state until the clock edge on which NA# or the last

expected BRDY# of the cycle is sampled asserted. W/R# is

driven during memory cycles, I/O cycles, special bus cycles, and

interrupt acknowledge cycles.

W/R# is floated off the clock edge on which BOFF# is sampled

asserted and off the clock edge that the processor asserts HLDA

in response to HOLD.

138

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.55

WB/WT# (Writeback or Writethrough)

Pin Attribute

Summary

Input

WB/WT#, together with PWT, specifies the data cache-line state

during cacheable read misses and write hits to shared cache

lines.

■ If WB/WT# = 0 or PWT = 1 during a cacheable read miss or

write hit to a shared cache line, the accessed line is cached

in the shared state. This is referred to as the writethrough

state because all write cycles to this cache line are driven

externally on the bus.

■ If WB/WT# = 1 and PWT = 0 during a cacheable read miss or

a write hit to a shared cache line, the accessed line is cached

in the exclusive state. Subsequent write hits to the same line

cause its state to transition from exclusive to modified. This

is referred to as the writeback state because the L1 data

cache and the L2 cache can contain modified cache lines

that are subject to be written back—referred to as a

writeback cycle—as the result of an inquire cycle, an

internal snoop, a flush operation, or the WBINVD

instruction.

Sampled

WB/WT# is sampled on the clock edge that the first BRDY# or

NA# of a bus cycle is sampled asserted. If the cycle is a burst

read, WB/WT# is ignored during the last three assertions of

BRDY#. WB/WT# is sampled during memory read and

non-writeback write cycles and is ignored during all other types

of cycles.

Chapter 5

Signal Descriptions

139

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.56

Pin Tables by Type

Table 19. Input Pin Types

Name

A20M#¹

Type

Name

IGNNE#¹

INIT²

Type

Asynchronous

Synchronous

Asynchronous

AHOLD

BF[2:0]³

BOFF#

BRDY#

BRDYC#

CLK

INTR¹

INV

Synchronous

Clock

Asynchronous

Synchronous

Asynchronous

KEN#

NA#

NMI²

RESET^4,5

SMI#²

EADS#

Synchronous

Asynchronous

Synchronous

Asynchronous

Synchronous

EWBE#⁶

FLUSH#^2,7

HOLD

STPCLK#¹

WB/WT#

Notes:

1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold

times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.

2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold

times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain

asserted at least two clocks.

3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time

of two clocks relative to the negation of RESET.

4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V_CCreach spec-

ification before it is negated.

5. During a warm reset, while CLK and V_CCare within their specification, RESET must remain asserted for a minimum of 15 clocks prior to

its negation.

6. When register bit EFER[3] is set to 1, EWBE# is ignored by the processor.

7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sampled on

a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which RESET is sampled

negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the negation of

RESET.

140

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 20. Output Pin Float Conditions

1

Name

Floated At:

A[4:3]^2,3

ADS#²

ADSC#²

APCHK#

LOCK#²

M/IO#²

PCD²

HLDA, AHOLD, BOFF#

HLDA, BOFF#

Always Driven

HLDA, BOFF#

Always Driven

HLDA, BOFF#

Always Driven

HLDA, BOFF#

Always Driven

HLDA, BOFF#

Always Driven

HLDA, BOFF#

PCHK#

PWT²

SCYC²

BE[7:0]#²

BREQ

CACHE#²

SMIACT#

VCC2DET

VCC2H/L#

VID[4:0]⁴

W/R#²

D/C#²

FERR#

HIT#

HITM#

HLDA

Notes:

1. All outputs except VCC2DET, VCC2H/L#, and TDO float during the Three-State Test mode.

2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.

3. Floated off the clock edge that AHOLD is sampled asserted.

4. Supported on the low-power versions only.

Table 21. Input/Output Pin Float Conditions

1

Name

Floated At:

A[31:5]^2,3

AP^2,3

D[63:0]²

DP[7:0]²

Notes:

HLDA, AHOLD, BOFF#

HLDA, BOFF#

1. All outputs except VCC2DET and TDO float during the Three-State Test mode.

2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.

3. Floated off the clock edge that AHOLD is sampled asserted.

Table 22. Test Pin Types

Name

TCK

Type

Clock

Input

Output

Input

Comment

TDI

Sampled on the rising edge of TCK

Driven on the falling edge of TCK

Sampled on the rising edge of TCK

Asynchronous (Independent of TCK)

TDO

TMS

TRST#

Chapter 5

Signal Descriptions

141

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5.57

Bus Cycle Definitions

Table 23. Bus Cycle Definition

Generated

by System Logic

Generated by the CPU

D/C# W/R# CACHE#

Bus Cycle Initiated

M/IO#

KEN#

Code Read, L1 Instruction Cache and L2 Cache Line Fill

Code Read, Noncacheable

1

0

1

0

1

0

1

0

1

0

1

x

0

x¹

1

x

0

1

Code Read, Noncacheable

Encoding for Special Cycle

1

0

1

x

Interrupt Acknowledge

x

I/O Read

x

I/O Write

x

Memory Read, L1 Data Cache and L2 Cache Line Fill

Memory Read, Noncacheable

Memory Write, L1 Data Cache or L2 Cache Writeback

Memory Write, Noncacheable

0

x

1

x

0

1

x

Notes:

1. x means “don’t care”

Table 24. Special Cycles

Special Cycle

x¹

x

Stop Grant

1

0

1

0

1

0

1

0

1

Enhanced Power Management (EPM)

1

2

Stop Grant

Flush Acknowledge

(FLUSH# sampled asserted)

0

1

0

1

0

1

x

Writeback (WBINVD instruction)

0

1

0

1

0

1

0

1

0

1

x

Halt

Flush (INVD, WBINVD instruction)

Shutdown

Notes:

1. x means “don’t care”.

2. Supported on the low-power versions only.

142

Signal Descriptions

Chapter 5

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

6

AMD PowerNow!™ Technology

The AMD PowerNow!™ technology is an advanced second-

generation power management feature that reduces the overall

power consumed by the processor through control of voltage

and frequency. This power saving technology is designed to be

dynamic and flexible by enabling instant “on-the-fly” and

independent control of both the processor’s core voltage and

frequency.

AMD PowerNow! technology can be used in conjunction with

the existing power management schemes in an embedded

system to provide a better combination of performance and

power savings than previously possible.

6.1

Enhanced Power Management Features

AMD PowerNow! technology-enabled processors include two

new features specifically designed to enhance power

management functionality:

■ Dynamic core frequency control

■ Dynamic core voltage control

These enhanced power management features are accessed and

controlled through an I/O block and two registers:

■ An aligned 16-byte block of I/O address space is defined by

the Enhanced Power Management Register (EPMR).

■ The Enhanced Power Management Register (EPMR) is

supported on low-power versions of the processor only.

■ The Processor State Observability Register (PSOR) is

defined differently on the low-power versions of the

AMD-K6-2E+ processor to support AMD PowerNow!

technology features.

The EPMR and PSOR registers and the I/O block are defined in

this section, followed by a discussion of how to implement and

use the AMD PowerNow! technology features (see “Dynamic

Core Frequency and Core Voltage Control” on page 150). The

Embedded AMD-K6™ Processors BIOS Design Guide Application

Note, order# 23913, contains additional information.

Chapter 6

AMD PowerNow!™ Technology

143

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Enhanced Power

ManagementRegister

(EPMR)

The EPMR register allows software to access the aligned

Enhanced Power Management (EPM) 16-byte block of I/O

address space, which contains bits for enabling, controlling,

and monitoring the enhanced power management features. All

accesses to the EPM 16-byte I/O block must be aligned dword

accesses. Valid accesses to the EPM 16-byte block do not

generate I/O cycles on the host bus, while non-aligned and non-

dword accesses are passed to the host bus.

The EPMR is MSR C000_0086h.

Figure 54 and Table 25 define the EPMR register. An assertion

of RESET clears all of the bits of the 16-byte I/O block to zero

(excluding the Voltage ID Output bits which default to

01010b). BIOS must always initialize the EPMR register and

enhanced power management features whenever RESET is

asserted.

For more information about the EPMR register, see the

Embedded AMD-K6™ Processors BIOS Design Guide Application

Note, order# 23913.

3

1

0

4

2

63

16 15

G

S

B

C

E

N

IOBASE

Reserved

Symbol

IOBASE

GSBC

EN

Description

I/O Base Address

Generate Special Bus Cycle

Enable AMD PowerNow! Technology

Management

Bit

15-4

1

0

Figure 54. Enhanced Power Management Register (EPMR)

144

AMD PowerNow!™ Technology

Chapter 6

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 25. Enhanced Power Management Register (EPMR) Definition

1

Bit

Description

R/W

Function

63–16 Reserved

R

All reserved bits are always read as 0.

IOBASE defines a base address for a 16-byte block of I/O address

15-4

3-2

1

I/O BASE Address (IOBASE)

R/W space accessible for enabling, controlling, and monitoring the EPM

features.

Reserved

R

All reserved bits are always read as 0.

This bit controls whether a special bus cycle is generated upon dword

R/W accesses within the EPM 16-byte I/O block. If set to 1, an EPM special

bus cycle is generated, where BE[7:0]# = BFh and A[4:3] = 00b.

Generate Special Bus Cycle (GSBC)

This bit controls access to the I/O-mapped address space for the AMD

R/W PowerNow! technology EPM features. Clearing this bit to zero does

not affect the state of bits defined in the EPM 16-byte I/O block.

Enable AMD PowerNow! Technology

Management (EN)

0

Notes:

1. All bits default to 0 when RESET is asserted.

IOBASE Field. The IOBASE field is initialized during POST to an

I/O address range used by an SMM handler to access the

enhanced power management features. Because the I/O range

is only enabled and accessed by the SMM handler during SMM,

the EPM features are hidden from all other software (OS

included)—BIOS does not need to report the I/O range to the

operating system.

GSBC Bit. If the GSBC bit is enabled (set to 1), a special bus

cycle is generated upon a dword access within the EPM 16-byte

I/O block. The EPM special bus cycle is defined as the

processor driving D/C# = 0, M/IO# = 0, and W/R# = 1, BE[7:0]# =

BFh and A[31:3] = 0000h. The system logic must return BRDY#

in response to all processor special cycles.

EN Bit. The EN bit should only be enabled (set to 1) by an SMM

handler when the SMM handler accesses the EPM features.

Upon exiting, the SMM handler should disable the EN bit and

thereby protect the EPM 16-byte I/O block from unwanted

accesses. When the EN bit is disabled, accesses to the EPM

block 16-byte I/O block are passed to the host bus.

Chapter 6

AMD PowerNow!™ Technology

145

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

EPM 16-Byte I/O

Block

The EPM 16-byte I/O block contains one 4-byte field—Bus

Divisor and Voltage ID Control (BVC)—for enabling,

controlling, and monitoring the enhanced power management

features (see Figure 55). Table 26 defines the function of the

BVC field within the EPM 16-byte I/O block mapped by the

EPMR.

8

7

0

12

15

11

BVC

Reserved

Symbol Description

BVC Bus Divisor and Voltage ID Control

Bytes

11-8

Figure 55. EPM 16-Byte I/O Block

Table 26. EPM 16-Byte I/O Block Definition

Byte Description

1

R/W

Function

All reserved bits are always read as 0.

15-12

11-8

7-0

Reserved

R

The bit fields within the BVC bytes allow software to change the

processor bus divisor and core voltage.

Bus Divisor and Voltage ID Control (BVC) R/W

Reserved

R

All reserved bits are always read as 0.

Notes:

1. All bits default to 0 when RESET is asserted.

BVC. Figure 56 on page 147 shows the format, and Table 27 on

page 147 defines the function of each bit of the BVC field

located within the EPM 16-byte I/O block.

146

AMD PowerNow!™ Technology

Chapter 6

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

11 10 9

7

8

5 4

0

12

31

V

I

D

C

B

V

SGTC

VIDO

BDC IBF[2:0]

C

M

Reserved

Symbol

SGTC

BVCM

VIDC

Description

Bits

31-12

11

Stop Grant Time-out Counter

Bus Divisor and VID Change Mode

Voltage ID Control

10

BDC

IBF[2:0]

VIDO

Bus Divisor Control

Internal BF Divisor

Voltage ID Output

9-8

7-5

4-0

Figure 56. Bus Divisor and Voltage ID Control (BVC) Field

Table 27. Bus Divisor and Voltage ID Control (BVC) Definition

1

Bit

Description

R/W

Function

Writing a non-zero value to this field causes the processor to enter the

EPM Stop Grant state internally. This 20-bit value is multiplied by 4096

to determine the duration of the EPM Stop Grant state, measured in

processor bus clocks.

31-12

Stop Grant Time-Out Counter (SGTC)

W

This bit controls the mode in which the bus-divisor and the voltage

control bits are allowed to change. If BVCM=0, the Bus Divisor and

R/W Voltage ID changes take effect only upon entering the EPM Stop Grant

state as a result of the SGTC field being programmed. BVCM=1 is

reserved.

Bus Divisor and VID Change Mode

(BVCM)

11

10

This bit controls the mode of Voltage ID control. If VIDC=0, the proces-

sor VID[4:0] pins are unchanged upon entering the EPM Stop Grant

R/W state. If VIDC=1, the processor VID[4:0] pins are programmed to the

VIDO value upon entering the EPM Stop Grant state. BIOS should ini-

tialize this bit to 1 during the POST routine.

Voltage ID Control (VIDC)

Bus Divisor Control (BDC)

This 2-bit field controls the mode of Bus Divisor control. If

BDC[1:0]=00b, the BF[2:0] pins are sampled at the falling edge of

R/W RESET. If BDC[1:0]=1xb, the IBF[2:0] field is sampled upon entering the

EPM Stop Grant state. BDC[1:0]=01b is reserved. BIOS should initialize

these bits to 10b during the POST routine.

9-8

If BDC[1:0]=1xb, the processor EBF[2:0] field of the PSOR is pro-

R/W grammed to the IBF[2:0] value upon entering the EPM Stop Grant

state.

7-5

4-0

Internal BF Divisor (IBF[2:0])

Voltage ID Output (VIDO)

This 5-bit value is driven out on the processor VID[4:0] pins upon

R/W entering the EPM Stop Grant state if the VIDC bit=1. These bits are ini-

tialized to 01010b and driven on the processor VID[4:0] pins at RESET.

Notes:

1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b.

Chapter 6

AMD PowerNow!™ Technology

147

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Processor State

Observability

Register (PSOR)

To support AMD PowerNow! technology, all low-power versions

of the AMD-K6-2E+ processor provide a different version of the

Processor State Observability Register (PSOR), as shown in

Figure 57 and fully described in this section. All standard-

power versions of the processor support the PSOR register as

defined on page 49. The PSOR register is MSR C000_0087h.

.

Symbol

PBF

VID

Description

Pin Bus Frequency Divisor

Voltage ID

Bits

23-21

20-16

63

24

23

21 20

16 15

9

8

7

2

4

3

0

N

O

L

STEP

EBF[2:0]

PBF[2:0]

VID

2

Reserved

Symbol

NOL2

STEP

Description

No L2 Functionality

Processor Stepping

Bits

8

7-4

EBF

Effective Bus Frequency Divisor 2-0

Figure 57. Processor State Observability Register (PSOR)—Low-Power Versions of the Processor

PBF[2:0] Field. This read-only field contains the BF divisor values

externally applied to the processor BF[2:0] pins. These input BF

values are sampled by the processor during the falling

transition of RESET.

Note: This BF divisor value may be different than the BF divisor

value supplied to the processor’s internal PLL.

VID Field. This read-only field contains the Voltage ID bits driven

to the processor VID[4:0] pins at RESET. These bits are

initialized to 01010b and driven on the VID[4:0] pins at RESET.

Note: Low-power AMD-K6-2E+ processors support AMD

PowerNow! technology, which enables dynamic alteration of

the processor’s core voltage. See “Enhanced Power

Management Register (EPMR)” on page 144 for

information on programming the VID[4:0] pins.

NOL2 Bit. This read-only bit indicates whether the processor

contains an L2 cache. This bit is always set to 0 for the

AMD-K6-2E+ processor.

148

AMD PowerNow!™ Technology

Chapter 6

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

STEP Field. This read-only field contains the stepping ID. This is

identical to the value returned by CPUID standard function 1 in

EAX[3:0].

EBF[2:0] Field. This read-only field contains the effective value of

the BF divisor supplied to the processor’s internal PLL, which

allows the BIOS to determine the frequency of the host bus. The

core frequency must first be determined using the Time Stamp

Counter (TSC) method (see “Time Stamp Counter” on page 46).

The core frequency is then divided by the processor-to-bus clock

ratio as determined by the EBF field (see Table 28). The result

is the frequency of the processor bus.

Table 28. Processor-to-Bus Clock Ratios

State of EBF[2:0]

Processor-to-Bus Clock Ratio

1

100b

101b

110b

111b

000b

001b

010b

011b

2.0x

3.0x

6.0x

3.5x

4.5x

5.0x

4.0x

5.5x

Notes:

1. The AMD-K6-2E+ processor does not support the 2.5x ratio supported by earlier AMD-K6 proces-

sors. Instead, a ratio of 2.0x is selected when EBF[2:0] equals 100b.

Chapter 6

AMD PowerNow!™ Technology

149

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

6.2

Dynamic Core Frequency and Core Voltage Control

AMD PowerNow! technology-enabled processors support the

ability to change the bus frequency divisor and core voltage

transparently to the user during run-time. These features are

implemented in conjunction with a new clock control state—

the EPM Stop Grant state.

For AMD PowerNow! technology state transitions, the EPMR

register is accessed using an SMM handler.

■ The SMM handler initiates core voltage and frequency

transitions by writing a non-zero value to the Stop Grant

Time-Out Counter (SGTC) field.

■ This action automatically places the processor into the EPM

Stop Grant State and transitions the CPU core voltage and

frequency to the values specified in the Voltage ID Output

(VIDO) and Internal BF Divisor (IBF) fields of the BVC field.

■ Once the timer of the SGTC has expired, the EPM Stop

Grant State is exited and the AMD PowerNow! technology

state transition is completed.

See “Clock Control” on page 275 for more information about

the EPM Stop Grant State.

Effective Bus

Frequency Divisor

(EBF[2:0])

The processor core frequency is controlled by the Effective Bus

Frequency Divisor—EBF[2:0]—which dictates the processor-to-

bus clock ratio supplied to the processor’s internal PLL. This

processor-to-bus clock ratio is multiplied by the external bus

frequency to set the frequency of operation for the processor

core.

■ At the fall of RESET, the EBF[2:0] value is determined by

the state of the processor BF[2:0] input pins.

■ Afterwards, the EBF[2:0] value can be dynamically

controlled through AMD PowerNow! technology state

transitions.

Table 28 on page 149 lists valid EBF[2:0] states and equivalent

processor-to-bus clock ratios.

150

AMD PowerNow!™ Technology

Chapter 6

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Dynamic Core

Frequency Control

For AMD PowerNow! technology core frequency transitions,

the BVC field of the EPM 16-byte I/O block is accessed through

an SMM handler.

■ To change the processor core frequency, the SMM handler

initiates core voltage and frequency transitions by writing a

non-zero value to the SGTC field.

■ This action automatically places the processor into the EPM

Stop Grant state and transitions the CPU core voltage and

frequency to the values specified in the VIDO and IBF fields

of the BVC field.

Note: System-initiated inquire (snoop) cycles are not supported

and must be prevented during the EPM Stop Grant state.

Voltage Identification

(VID) Outputs

AMD PowerNow! technology-enabled processors feature

Voltage ID (VID) outputs to support dynamic control of the

core voltage.

■ These outputs serve as inputs to a DC/DC regulator that

supplies the processor core voltage.

■ Based on its VID[4:0] inputs, the regulator outputs a

corresponding voltage.

■ For those regulators that do not support VID inputs, the

processor VID[4:0] outputs must be used to manipulate the

regulator’s feedback voltage to vary the regulator output

voltage.

Chapter 6

AMD PowerNow!™ Technology

151

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

152

AMD PowerNow!™ Technology

Chapter 6

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7

Bus Cycles

The following sections describe and illustrate the timing and

relationship of bus signals during various types of bus cycles. A

representative set of bus cycles is illustrated.

7.1

Timing Diagrams

The timing diagrams illustrate the signals on the external local

bus as a function of time, as measured by the bus clock (CLK).

Bus Clock (CLK)

Throughout this chapter, the term clock refers to a single

bus-clock cycle. A clock extends from one rising CLK edge to

the next rising CLK edge. The processor samples and drives

most signals relative to the rising edge of CLK. The exceptions

to this rule include the following:

■ BF[2:0]—Sampled on the falling edge of RESET

■ FLUSH#—Sampled on the falling edge of RESET, also

sampled on the rising edge of CLK

■ All inputs and outputs are sampled relative to TCK in

Boundary-Scan Test Mode. Inputs are sampled on the rising

edge of TCK, outputs are driven off of the falling edge of

TCK.

Waveform

Definitions

For each signal in the timing diagrams, the High level

represents 1, the Low level represents 0, and the Middle level

represents the floating (high-impedance) state.

When both the High and Low levels are shown, the meaning

depends on the signal:

■ A single signal indicates ‘don’t care’.

■ In the case of bus activity, if both High and Low levels are

shown, it indicates that the processor, alternate master, or

system logic is driving a value, but this value may or may not

be valid. (For example, the value on the address bus is valid

only during the assertion of ADS#, but addresses are also

driven on the bus at other times.)

Figure 58 on page 154 defines the different waveform

representations.

Chapter 7

Bus Cycles

153

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Active High Signals

Active Low Signals

For all active High signals, the term asserted means the signal is

in the High-voltage state and the term negated means the signal

is in the Low-voltage state.

For all active Low signals, the term asserted means the signal is

in the Low-voltage state and the term negated means the signal

is in the High-voltage state.

Waveform

Description

Don’t care or bus is driven

Signal or bus is changing from Low to High

Signal or bus is changing from High to Low

Bus is changing

Bus is changing from valid to invalid

Signal or bus is floating

Denotes multiple clock periods

Figure 58. Waveform Definitions

154

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7.2

Bus States

The bus states illustrated in Figure 59 are described in this

section.

Bus State

Addr

Branch Condition

Yes

No

Pending

Request?

Address

Data

Idle

Data

Idle

No

Yes

No

Last BRDY#

Asserted?

NA# Sampled

Asserted?

Yes

Data-NA#

Requested

Last BRDY#

Asserted?

No

Yes

No

Pending

Request?

No

NA# Sampled

Asserted?

Yes

Pipe-A

Pipeline

Address

Pipe-D

Trans

Pipeline

Data

No

Yes

Last BRDY#

Asserted?

Yes

No

NA# Sampled

Asserted?

Transition

Bus Transition?

No

Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled asserted.

Figure 59. Bus State Machine Diagram

Chapter 7

Bus Cycles

155

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Idle

The processor does not drive the system bus in the Idle state

and remains in this state until a new bus cycle is requested. The

processor enters this state off the clock edge on which the last

BRDY# of a cycle is sampled asserted during the following

conditions:

■ The processor is in the Data state

■ The processor is in the Data-NA# Requested state and no

internal pending cycle is requested

In addition, the processor is forced into this state when the

system logic asserts RESET or BOFF#. The transition to this

state occurs on the clock edge on which RESET or BOFF# is

sampled asserted.

Address

Data

In this state, the processor drives ADS# to indicate the

beginning of a new bus cycle by validating the address and

control signals. The processor remains in this state for one clock

and unconditionally enters the Data state on the next clock

edge.

In the Data state, the processor drives the data bus during a

write cycle or expects data to be returned during a read cycle.

The processor remains in this state until either NA# or the last

BRDY# is sampled asserted. If the last BRDY# is sampled

asserted or both the last BRDY# and NA# are sampled asserted

on the same clock edge, the processor enters the Idle state. If

NA# is sampled asserted first, the processor enters the

Data-NA# Requested state.

Data-NA# Requested

If the processor samples NA# asserted while in the Data state

and the current bus cycle is not completed (the last BRDY# is

not sampled asserted), it enters the Data-NA# Requested state.

The processor remains in this state until either the last BRDY#

is sampled asserted or an internal pending cycle is requested. If

the last BRDY# is sampled asserted before the processor drives

a new bus cycle, the processor enters the Idle state (no internal

pending cycle is requested) or the Address state (processor has

a internal pending cycle).

In this state, the processor drives ADS#, indicating the

beginning of a new bus cycle and validating the address and

control signals. In this state, the processor is still waiting for the

current bus cycle to be completed (until the last BRDY# is

Pipeline Address

156

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

sampled asserted). If the last BRDY# is not sampled asserted,

the processor enters the Pipeline Data state.

If the processor samples the last BRDY# asserted in this state, it

determines if a bus transition is required between the current

bus cycle and the pipelined bus cycle. A bus transition is

required when the data bus direction changes between bus

cycles, such as a memory write cycle followed by a memory read

cycle. If a bus transition is required, the processor enters the

Transition state for one clock to prevent data bus contention. If

a bus transition is not required, the processor enters the Data

state.

The processor does not transition to the Data-NA# Requested

state from the Pipeline Address state because the processor

does not begin sampling NA# until it has exited the Pipeline

Address state.

Pipeline Data

Two bus cycles are executing concurrently in this state. The

processor cannot issue any additional bus cycles until the

current bus cycle is completed. The processor drives the data

bus during write cycles or expects data to be returned during

read cycles for the current bus cycle until the last BRDY# of the

current bus cycle is sampled asserted.

If the processor samples the last BRDY# asserted in this state, it

determines if a bus transition is required between the current

bus cycle and the pipelined bus cycle. If the bus transition is

required, the processor enters the Transition state for one clock

to prevent data bus contention. If a bus transition is not

required, the processor enters the Data state (NA# was not

sampled asserted) or the Data-NA# Requested state (NA# was

sampled asserted).

Transition

The processor enters this state for one clock during data bus

transitions and enters the Data state on the next clock edge if

NA# is not sampled asserted. The sole purpose of this state is to

avoid bus contention caused by bus transitions during pipeline

operation.

Chapter 7

Bus Cycles

157

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7.3

Memory Reads and Writes

The AMD-K6-2E+ processor performs single or burst-memory

bus cycles.

■ The single-transfer memory bus cycle transfers 1, 2, 4, or 8

bytes and requires a minimum of two clocks.

■ Misaligned instructions or operands result in a split cycle,

which requires multiple transactions on the bus.

■ A burst cycle consists of four back-to-back 8-byte (64-bit)

transfers on the data bus.

Single-Transfer

Memory Read and

Write

Figure 60 on page 159 shows a single-transfer read from

memory, followed by two single-transfer writes to memory. For

the memory read cycle, the processor asserts ADS# for one

clock to validate the bus cycle and also drives A[31:3], BE[7:0]#,

D/C#, W/R#, and M/IO# to the bus. The processor then waits for

the system logic to return the data on D[63:0] (with DP[7:0] for

parity checking) and assert BRDY#. The processor samples

BRDY# on every clock edge starting with the clock edge after

the clock edge that negates ADS#. See “BRDY# (Burst Ready)”

on page 103.

During the read cycle, the processor drives PCD, PWT, and

CACHE# to indicate its caching and cache-coherency intent for

the access. The system logic returns KEN# and WB/WT# to

either confirm or change this intent. If the processor asserts

PCD and negates CACHE#, the accesses are noncacheable, even

though the system logic asserts KEN# during the BRDY# to

indicate its support for cacheability. The processor (which

drives CACHE#) and the system logic (which drives KEN#) must

agree in order for an access to be cacheable.

The processor can drive another cycle (in this example, a write

cycle) by asserting ADS# off the next clock edge after BRDY# is

sampled asserted. Therefore, an idle clock is guaranteed

between any two bus cycles. The processor drives D[63:0] with

valid data one clock edge after the clock edge on which ADS# is

asserted. To minimize processor idle times, the system logic

stores the address and data in write buffers, returns BRDY#,

and performs the store to memory later. If the processor

samples EWBE# negated during a write cycle, it suspends

certain activities until EWBE# is sampled asserted. See

“EWBE# (External Write Buffer Empty)” on page 110. In

158

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 60, the second write cycle occurs during the execution of

a serializing instruction. The processor delays the following

cycle until EWBE# is sampled asserted.

Write Cycle (Next Cycle Delayed by EWBE#)

Write Cycle

Read Cycle

DATA IDLE ADDR DATA

ADDR DATA IDLE ADDR DATA

DATA IDLE

IDLE

IDLE ADDR

IDLE

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

BREQ

D[63:0]

DP[7:0]

CACHE#

EWBE#

KEN#

BRDY#

WB/WT#

Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE#

Chapter 7

Bus Cycles

159

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Misaligned

Figure 61 on page 161 shows a misaligned (split) memory read

followed by a misaligned memory write. Any cycle that is not

aligned as defined in “SCYC (Split Cycle)” on page 129 is

considered misaligned. When the processor encounters a

misaligned access, it determines the appropriate pair of bus

cycles—each with its own ADS# and BRDY#— required to

complete the access.

Single-Transfer

Memory Read and

Write

The AMD-K6-2E+ processor performs misaligned memory reads

and memory writes using least-significant bytes (LSBs) first

followed by most-significant bytes (MSBs). Table 29 shows the

order. In the first memory read cycle in Figure 61, the processor

reads the least-significant bytes. Immediately after the

processor samples BRDY# asserted, it drives the second bus

cycle to read the most-significant bytes to complete the

misaligned transfer.

Table 29. Bus-Cycle Order During Misaligned Memory Transfers

Type of Access

Memory Read

Memory Write

First Cycle

LSBs

Second Cycle

MSBs

LSBs

MSBs

Similarly, the misaligned memory write cycle in Figure 61

transfers the LSBs to the memory bus first. In the next cycle,

after the processor samples BRDY# asserted, the MSBs are

written to the memory bus.

160

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Memory Write (Misaligned)

Memory Read (Misaligned)

DATA IDLE ADDR DATA

DATA IDLE

DATA

ADDR DATA DATA DATA IDLE

DATA IDLE ADDR DATA

ADDR DATA

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

LSB

MSB

LSB

MSB

D[63:0]

BRDY#

Figure 61. Misaligned Single-Transfer Memory Read and Write

Chapter 7

Bus Cycles

161

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Burst Reads and

Pipelined Burst Reads

Figure 62 on page 163 shows normal burst read cycles and a

pipelined burst read cycle. The AMD-K6-2E+ processor drives

CACHE# and ADS# together to specify that the current bus

cycle is a burst cycle. If the processor samples KEN# asserted

with the first BRDY#, it performs burst transfers. During the

burst transfers, the system logic must ignore BE[7:0]# and must

return all eight bytes beginning at the starting address the

processor asserts on A[31:3]. Depending on the starting

address, the system logic must determine the successive

quadword addresses (A[4:3]) for each transfer in a burst, as

shown in Table 30. The processor expects the second, third, and

fourth quadwords to occur in the sequences shown in Table 30.

Table 30. A[4:3] Address-Generation Sequence During Bursts

A[4:3] Addresses of Subsequent

Address Driven By

Processor on A[4:3]

1

Quadwords Generated by System Logic

Quadword 1

Quadword 2

Quadword 3

Quadword 4

00b

01b

10b

11b

01b

00b

11b

10b

11b

00b

01b

11b

10b

01b

00b

Notes:

1. Quadword = 8 bytes.

In Figure 62, the processor drives CACHE# throughout all burst

read cycles. In the first burst read cycle, the processor drives

ADS# and CACHE#, then samples BRDY# on every clock edge

starting with the clock edge after the clock edge that negates

ADS#. The processor samples KEN# asserted on the clock edge

on which the first BRDY# is sampled asserted, executes a

32-byte burst read cycle, and expects a total of four BRDY#

signals. An ideal no-wait state access is shown in Figure 62,

whereas most system logic solutions add wait states between

the transfers.

The second burst read cycle illustrates a similar sequence, but

the processor samples NA# asserted on the same clock edge

that the first BRDY# is sampled asserted. NA# assertion

indicates the system logic is requesting the processor to output

the next address early (also known as a pipeline transfer

request). Without waiting for the current cycle to complete, the

processor drives ADS# and related signals for the next burst

cycle. Pipelining can reduce processor cycle-to-cycle idle times.

162

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Burst Read

Pipelined Burst Read

DATA PIPE

ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA

DATA DATA DATA DATA IDLE

-NA -ADDR

CLK

ADDR1

ADDR2

ADDR3

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

NA#

DATA1

DATA2

DATA3

D[63:0]

CACHE#

KEN#

BRDY#

Figure 62. Burst Reads and Pipelined Burst Reads

Chapter 7

Bus Cycles

163

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Burst Writeback

Figure 63 on page 165 shows a burst read followed by a

writeback transaction. The AMD-K6-2E+ processor initiates

writebacks under the following conditions:

■ Replacement—If a cache-line fill is initiated for a cache line

currently filled with valid entries, the processor selects a

line for replacement based on a least-recently-used (LRU)

algorithm for the L1 instruction cache and the L2 cache, and

a least-recently-allocated (LRA) algorithm for the L1 data

cache. Before a replacement is made to a L1 data cache or L2

cache line that is in the modified state, the modified line is

scheduled to be written back to memory.

■ Internal Snoop—The processor snoops its L1 instruction

cache during read or write misses to its L1 data cache, and it

snoops its L1 data cache during read misses to its L1

instruction cache. This snooping is performed to determine

whether the same address is stored in both caches, a

situation that is taken to imply the occurrence of

self-modifying code. If an internal snoop hits a L1 data cache

line in the modified state, the line is written back to memory

before being invalidated.

■ WBINVD Instruction—When the processor executes a

WBINVD instruction, it writes back all modified lines in the

L1 data cache and L2 cache, and then invalidates all lines in

all caches.

■ Cache Flush—When the processor samples FLUSH#

asserted, it executes a flush acknowledge special cycle and

writes back all modified lines in the L1 data cache and L2

cache, and then invalidates all lines in all caches.

The processor drives writeback cycles during inquire or cache

flush cycles. The writeback shown in Figure 63 is caused by a

cache-line replacement. The processor completes the burst read

cycle that fills the cache line. Immediately following the burst

read cycle is the burst writeback cycle that represents the

modified line to be written back to memory. D[63:0] are driven

one clock edge after the clock edge on which ADS# is asserted

and are subsequently changed off the clock edge on which each

of the four BRDY# signals of the burst cycle are sampled

asserted.

164

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Burst Read

Burst Writeback from L1 Cache

DATA

DATA DATA

DATA

DATA DATA

ADDR

DATA

IDLE

ADDR

DATA

IDLE

CLK

A[31:3]

BE[7:0]#

ADS#

CACHE#

M/IO#

D/C#

W/R#

D[63:0]

KEN#

BRDY#

WB/WT#

Figure 63. Burst Writeback due to Cache-Line Replacement

Chapter 7

Bus Cycles

165

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7.4

I/O Read and Write

Basic I/O Read and

Write

The processor accesses I/O when it executes an I/O instruction

(for example, IN or OUT). Figure 64 shows an I/O read followed

by an I/O write. The processor drives M/IO# Low and D/C# High

during I/O cycles. In this example, the first cycle shows a single

wait state I/O read cycle. It follows the same sequence as a

single-transfer memory read cycle. The processor drives ADS#

to initiate the bus cycle, then it samples BRDY# on every clock

edge starting with the clock edge after the clock edge that

negates ADS#. The system logic must return BRDY# to

complete the cycle. When the processor samples BRDY#

asserted, it can assert ADS# for the next cycle off the next clock

edge. (In this example, an I/O write cycle.)

The I/O write cycle is similar to a memory write cycle, but the

processor drives M/IO# low during an I/O write cycle. The

processor asserts ADS# to initiate the bus cycle. The processor

drives D[63:0] with valid data one clock edge after the clock

edge on which ADS# is asserted. The system logic must assert

BRDY# when the data is properly stored to the I/O destination.

The processor samples BRDY# on every clock edge starting with

the clock edge after the clock edge that negates ADS#. In this

example, two wait states are inserted while the processor waits

for BRDY# to be asserted.

I/O Write Cycle

I/O Read Cycle

DATA

IDLE

DATA

ADDR

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

D[63:0]

BRDY#

Figure 64. Basic I/O Read and Write

166

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Misaligned I/O Read

and Write

Table 31 shows the misaligned I/O read and write cycle order

executed by the AMD-K6-2E+ processor. In Figure 65, the

least-significant bytes (LSBs) are transferred first. Immediately

after the processor samples BRDY# asserted, it drives the

second bus cycle to transfer the most-significant bytes (MSBs)

to complete the misaligned bus cycle.

Table 31. Bus-Cycle Order During Misaligned I/O Transfers

Type of Access

I/O Read

First Cycle

LSBs

Second Cycle

MSBs

I/O Write

LSBs

MSBs

Misaligned I/O Write

Misaligned I/O Read

ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA

DATA

IDLE ADDR DATA DATA DATA IDLE

DATA

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

SCYC

D[63:0]

BRDY#

LSB

MSB

LSB

MSB

Figure 65. Misaligned I/O Transfer

Chapter 7

Bus Cycles

167

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7.5

Inquire and Bus Arbitration Cycles

The AMD-K6-2E+ processor provides built-in level-one (L1)

data and instruction caches, and a unified level-two (L2) cache.

Each L1 cache is 32 Kbytes and two-way set-associative. The L2

cache is 128 Kbytes and four-way set-associative. The system

logic or other bus master devices can initiate an inquire cycle to

maintain cache/memory coherency. In response to the inquire

cycle, the processor compares the inquire address with its cache

tag addresses in all caches, and, if necessary, updates the MESI

state of the cache line and performs writebacks to memory.

An inquire cycle can be initiated by asserting AHOLD, BOFF#,

or HOLD. AHOLD is exclusively used to support inquire cycles.

During AHOLD-initiated inquire cycles, the processor only

floats the address bus. BOFF# provides the fastest access to the

bus because it aborts any processor cycle that is in-progress,

whereas AHOLD and HOLD both permit an in-progress bus

cycle to complete. During HOLD-initiated and BOFF#-initiated

inquire cycles, the processor floats all of its bus-driving signals.

The AMD-K6-2E+ processor does not support system-initiated

inquire cycles during the Enhanced Power Management (EPM)

Stop Grant State. For more information on the EPM Stop Grant

State, see “Clock Control” on page 275.

Hold and Hold

Acknowledge Cycle

The system logic or another bus device can assert HOLD to

initiate an inquire cycle or to gain full control of the bus. When

the AMD-K6-2E+ processor samples HOLD asserted, it

completes any in-progress bus cycle and asserts HLDA to

acknowledge release of the bus. The processor floats the

following signals off the same clock edge on which HLDA is

asserted:

■ A[31:3]

■ ADS#

■ DP[7:0]

■ LOCK#

■ M/IO#

■ PCD

■ AP#

■ BE[7:0]#

■ CACHE#

■ D[63:0]

■ D/C#

■ PWT

■ SCYC

■ W/R#

168

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 66 on page 169 shows a basic HOLD/HLDA operation. In

this example, the processor samples HOLD asserted during the

memory read cycle. It continues the current memory read cycle

until BRDY# is sampled asserted. The processor drives HLDA

and floats its outputs one clock edge after the last BRDY# of the

cycle is sampled asserted. The system logic can assert HOLD for

as long as it needs to utilize the bus. The processor samples

HOLD on every clock edge but does not assert HLDA until any

in-progress cycle or sequence of locked cycles is completed.

When the processor samples HOLD negated during a hold

acknowledge cycle, it negates HLDA off the next clock edge.

The processor regains control of the bus and can assert ADS#

off the same clock edge on which HLDA is negated.

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

D[63:0]

HOLD

HLDA

BRDY#

Figure 66. Basic HOLD/HLDA Operation

Chapter 7

Bus Cycles

169

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

HOLD-Initiated

Inquire Hit to Shared

or Exclusive Line

Figure 67 on page 171 shows a HOLD-initiated inquire cycle. In

this example, the processor samples HOLD asserted during the

burst memory read cycle. The processor completes the current

cycle (until the last expected BRDY# is sampled asserted),

asserts HLDA and floats its outputs as described in “Hold and

Hold Acknowledge Cycle” on page 168.

The system logic drives an inquire cycle within the hold

acknowledge cycle. It asserts EADS#, which validates the

inquire address on A[31:5]. If EADS# is sampled asserted

before HOLD is sampled negated, the processor recognizes it as

a valid inquire cycle.

In Figure 67, the processor asserts HIT# and negates HITM# on

the clock edge after the clock edge on which EADS# is sampled

asserted, indicating the current inquire cycle hit a shared or

exclusive cache line. (Shared and exclusive cache lines have not

been modified and do not need to be written back.) During an

inquire cycle, the processor samples INV to determine whether

the addressed cache line found in the processor’s caches

transitions to the invalid state or the shared state. In this

example, the processor samples INV asserted with EADS#,

which invalidates the cache line.

The system logic can negate HOLD off the same clock edge on

which EADS# is sampled asserted. The processor continues

driving HIT# in the same state until the next inquire cycle.

HITM# is not asserted unless HIT# is asserted.

170

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Burst Memory Read

Inquire

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

HIT#

HITM#

D[63:0]

KEN#

BRDY#

HOLD

HLDA

EADS#

INV

Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line

Chapter 7

Bus Cycles

171

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

HOLD-Initiated

Inquire Hit to

Modified Line

Figure 68 on page 173 shows the same sequence as Figure 67 on

page 171, but in Figure 68 the inquire cycle hits a modified line

and the processor asserts both HIT# and HITM#. In this

example, the processor performs a writeback cycle immediately

after the inquire cycle. It updates the modified cache line to

external memory (normally, external cache or DRAM). The

processor uses the address (A[31:5]) that was latched during the

inquire cycle to perform the writeback cycle. The processor

asserts HITM# throughout the writeback cycle and negates

HITM# one clock edge after the last expected BRDY# of the

writeback is sampled asserted.

When the processor samples EADS# during the inquire cycle, it

also samples INV to determine the cache line MESI state after

the inquire cycle. If INV is sampled asserted during an inquire

cycle, the processor transitions the line (if found) to the invalid

state, regardless of its previous state. The cache line

invalidation operation is not visible on the bus. If INV is

sampled negated during an inquire cycle, the processor

transitions the line (if found) to the shared state. In Figure 68

the processor samples INV asserted during the inquire cycle.

In a HOLD-initiated inquire cycle, the system logic can negate

HOLD off the same clock edge on which EADS# is sampled

asserted. The processor drives HIT# and HITM# on the clock

edge after the clock edge on which EADS# is sampled asserted.

172

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Burst Memory Read

Writeback Cycle

Inquire

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

HIT#

HITM#

D[63:0]

KEN#

BRDY#

HOLD

HLDA

EADS#

INV

Figure 68. HOLD-Initiated Inquire Hit to Modified Line

Chapter 7

Bus Cycles

173

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

AHOLD-Initiated

Inquire Miss

AHOLD can be asserted by the system to initiate one or more

inquire cycles. To allow the system to drive the address bus

during an inquire cycle, the processor floats A[31:3] and AP off

the clock edge on which AHOLD is sampled asserted. The data

bus and all other control and status signals remain under the

control of the processor and are not floated. This functionality

allows a bus cycle in progress when AHOLD is sampled asserted

to continue to completion. The processor resumes driving the

address bus off the clock edge on which AHOLD is sampled

negated.

In Figure 69 on page 175, the processor samples AHOLD

asserted during the memory burst read cycle, and it floats the

address bus off the same clock edge on which it samples

AHOLD asserted. While the processor still controls the bus, it

completes the current cycle until the last expected BRDY# is

sampled asserted. The system logic drives EADS# with an

inquire address on A[31:5] during an inquire cycle. The

processor samples EADS# asserted and compares the inquire

address to its tag address in the L1 instruction and data caches,

and in the L2 cache. In Figure 69, the inquire address misses the

tag address in the processor (both HIT# and HITM# are

negated). Therefore, the processor proceeds to the next cycle

when it samples AHOLD negated. (The processor can drive a

new cycle by asserting ADS# off the same clock edge that it

samples AHOLD negated.)

For an AHOLD-initiated inquire cycle to be recognized, the

processor must sample AHOLD asserted for at least two

consecutive clocks before it samples EADS# asserted. If the

processor detects an address parity error during an inquire

cycle, APCHK# is asserted for one clock. The system logic must

respond appropriately to the assertion of this signal.

174

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Inquire

Read

CLK

A[31:3]

BE[7:0]#

AP

APCHK#

ADS#

HIT#

HITM#

D[63:0]

KEN#

BRDY#

AHOLD

EADS#

INV

Figure 69. AHOLD-Initiated Inquire Miss

Chapter 7

Bus Cycles

175

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

AHOLD-Initiated

Inquire Hit to Shared

or Exclusive Line

In Figure 70 on page 177, the processor asserts HIT# and

negates HITM# off the clock edge after the clock edge on which

EADS# is sampled asserted, indicating the current inquire

cycle hits either a shared or exclusive line. (HIT# is driven in

the same state until the next inquire cycle.) The processor

samples INV asserted during the inquire cycle and transitions

the line to the invalid state regardless of its previous state.

During an AHOLD-initiated inquire cycle, the processor

samples AHOLD on every clock edge until it is negated. In

Figure 70, the processor asserts ADS# off the same clock on

which AHOLD is sampled negated. If the inquire cycle hits a

modified line, the processor performs a writeback cycle before

it drives a new bus cycle. The next section describes the

AHOLD-initiated inquire cycle that hits a modified line.

176

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Inquire

Burst Memory Read

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

HIT#

HITM#

D[63:0]

KEN#

BRDY#

AHOLD

EADS#

INV

Figure 70. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line

Chapter 7

Bus Cycles

177

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

AHOLD-Initiated

Inquire Hit to

Modified Line

Figure 71 on page 179 shows an AHOLD-initiated inquire cycle

that hits a modified line. During the inquire cycle in this

example, the processor asserts both HIT# and HITM# on the

clock edge after the clock edge that it samples EADS# asserted.

This condition indicates that the cache line exists in the

processor’s L1 data cache or L2 cache in the modified state.

If the inquire cycle hits a modified line, the processor performs

a writeback cycle immediately after the inquire cycle to update

the modified cache line to shared memory (normally external

cache or DRAM). In Figure 71, the system logic holds AHOLD

asserted throughout the inquire cycle and the processor

writeback cycle. In this case, the processor is not driving the

address bus during the writeback cycle because AHOLD is

sampled asserted. The system logic writes the data to memory

by using its latched copy of the inquire cycle address. If the

processor samples AHOLD negated before it performs the

writeback cycle, it drives the writeback cycle by using the

address (A[31:5]) that it latched during the inquire cycle.

If INV is sampled asserted during an inquire cycle, the

processor transitions the line (if found) to the invalid state,

regardless of its previous state (the cache invalidation

operation is not visible on the bus). If INV is sampled negated

during an inquire cycle, the processor transitions the line (if

found) to the shared state. In either case, if the line is found in

the modified state, the processor writes it back to memory

before changing its state. Figure 71 shows that the processor

samples INV asserted during the inquire cycle and invalidates

the cache line after the inquire cycle.

178

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Burst Memory Read

Inquire

Writeback

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

HIT#

HITM#

D[63:0]

KEN#

BRDY#

AHOLD

EADS#

INV

Figure 71. AHOLD-Initiated Inquire Hit to Modified Line

Chapter 7

Bus Cycles

179

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

AHOLD Restriction

When the system logic drives an AHOLD-initiated inquire

cycle, it must assert AHOLD for at least two clocks before it

asserts EADS#. This requirement guarantees the processor

recognizes and responds to the inquire cycle properly. The

processor’s 32 address bus drivers turn on almost immediately

after AHOLD is sampled negated. If the processor switches the

data bus (D[63:0] and DP[7:0]) during a write cycle off the same

clock edge that switches the address bus (A[31:3] and AP), the

processor switches 102 drivers simultaneously, which can lead

to ground-bounce spikes. Therefore, before negating AHOLD

the following restrictions must be observed by the system logic:

■ When the system logic negates AHOLD during a write cycle,

it must ensure that AHOLD is not sampled negated on the

clock edge on which BRDY# is sampled asserted (See

Figure 72 on page 181).

■ When the system logic negates AHOLD during a writeback

cycle, it must ensure that AHOLD is not sampled negated on

the clock edge on which ADS# is negated (See Figure 72).

■ When a write cycle is pipelined into a read cycle, AHOLD

must not be sampled negated on the clock edge after the

clock edge on which the last BRDY# of the read cycle is

sampled asserted to avoid the processor simultaneously

driving the data bus (for the pending write cycle) and the

address bus off this same clock edge.

180

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

CLK

ADS#

W/R#

HITM#

EADS#

D[63:0]

BRDY#

Legal AHOLD negation during write cycle

AHOLD

Illegal AHOLD negation during write cycle

The system must ensure that AHOLD is not sampled negated on the clock edge that ADS# is negated.

The system must ensure that AHOLD is not sampled negated on the clock edge on which BRDY# is sampled asserted.

Figure 72. AHOLD Restriction

Chapter 7

Bus Cycles

181

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Bus Backoff (BOFF#)

BOFF# provides the fastest response among bus-hold inputs.

Either the system logic or another bus master can assert BOFF#

to gain control of the bus immediately. BOFF# is also used to

resolve potential deadlock problems that arise as a result of

inquire cycles. The processor samples BOFF# on every clock

edge. If BOFF# is sampled asserted, the processor

unconditionally aborts any cycles in progress and transitions to

a bus hold state. (See “BOFF# (Backoff)” on page 102.)

Figure 73 on page 183 shows a read cycle that is aborted when

the processor samples BOFF# asserted even though BRDY# is

sampled asserted on the same clock edge. The read cycle is

restarted after BOFF# is sampled negated (KEN# must be in

the same state during the restarted cycle as its state during the

aborted cycle).

During a BOFF#-initiated inquire cycle that hits a shared or

exclusive line, the processor samples BOFF# negated and

restarts any bus cycle that was aborted when BOFF# was

asserted. If a BOFF#-initiated inquire cycle hits a modified line,

the processor performs a writeback cycle before it restarts the

aborted cycle.

If the processor samples BOFF# asserted on the same clock

edge that it asserts ADS#, ADS# is floated but the system logic

may erroneously interpret ADS# as asserted. In this case, the

system logic must properly interpret the state of ADS# when

BOFF# is negated.

182

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Read

Restart Read Cycle

Backoff Cycle

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

BOFF#

D[63:0]

BRDY#

Figure 73. BOFF# Timing

Chapter 7

Bus Cycles

183

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Locked Cycles

The processor asserts LOCK# during a sequence of bus cycles to

ensure the cycles are completed without allowing other bus

masters to intervene. Locked operations can consist of two to

five cycles. LOCK# is asserted during the following operations:

■ An interrupt acknowledge sequence

■ Descriptor Table accesses

■ Page Directory and Page Table accesses

■ XCHG instruction

■ An instruction with an allowable LOCK prefix

In order to ensure that locked operations appear on the bus and

are visible to the entire system, any data operands addressed

during a locked cycle that reside in the processor’s caches are

flushed and invalidated from the caches prior to the locked

operation. If the cache line is in the modified state, it is written

back and invalidated prior to the locked operation. Likewise,

any data read during a locked operation is not cached. The

processor negates LOCK# for at least one clock between

consecutive sequences of locked operations to allow the system

logic to arbitrate for the bus.

The processor asserts SCYC during misaligned locked transfers

on the D[63:0] data bus. The processor generates additional bus

cycles to complete the transfer of misaligned data.

Basic Locked

Operation

Figure 74 on page 185 shows a pair of read-write bus cycles. It

represents a typical read-modify-write locked operation. The

processor asserts LOCK# off the same clock edge that it asserts

ADS# of the first bus cycle in the locked operation and holds it

asserted until the last expected BRDY# of the last bus cycle in

the locked operation is sampled asserted. (The processor

negates LOCK# off of the same clock edge.)

184

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Locked Write Cycle

IDLE IDLE

Locked Read Cycle

IDLE IDLE ADDR DATA DATA DATA

ADDR

ADDR DATA DATA DATA

CLK

A[31:3]

BE[7:0]#

ADS#

LOCK#

M/IO#

D/C#

W/R#

SCYC

D[63:0]

BRDY#

Figure 74. Basic Locked Operation

Chapter 7

Bus Cycles

185

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Locked Operation

with BOFF#

Intervention

Figure 75 on page 187 shows BOFF# asserted within a locked

read-write pair of bus cycles. In this example, the processor

asserts LOCK# with ADS# to drive a locked memory read cycle

followed by a locked memory write cycle. During the locked

memory write cycle in this example, the processor samples

BOFF# asserted. The processor immediately aborts the locked

memory write cycle and floats all its bus-driving signals,

including LOCK#. The system logic or another bus master can

initiate an inquire cycle or drive a new bus cycle one clock edge

after the clock edge on which BOFF# is sampled asserted. If the

system logic drives a BOFF#-initiated inquire cycle and hits a

modified line, the processor performs a writeback cycle before

it restarts the locked cycle (the processor asserts LOCK# during

the writeback cycle).

In Figure 75, the processor immediately restarts the aborted

locked write cycle by driving the bus off the clock edge on

which BOFF# is sampled negated. The system logic must ensure

the processor results for interrupted and uninterrupted locked

cycles are consistent. That is, the system logic must guarantee

the memory accessed by the processor is not modified during

the time another bus master controls the bus.

186

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Locked Read Cycle

Restart Write Cycle

Aborted Write Cycle

CLK

A[31:3]

BE[7:0]#

ADS#

LOCK#

M/IO#

D/C#

W/R#

BOFF#

D[63:0]

BRDY#

Figure 75. Locked Operation with BOFF# Intervention

Chapter 7

Bus Cycles

187

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Interrupt

Acknowledge

In response to recognizing the system’s maskable interrupt

(INTR), the processor drives an interrupt acknowledge cycle at

the next instruction boundary. During an interrupt

acknowledge cycle, the processor drives a locked pair of read

cycles as shown in Figure 76 on page 189. The first read cycle is

not functional, and the second read cycle returns the interrupt

number on D[7:0] (00h–FFh). Table 32 shows the state of the

signals during an interrupt acknowledge cycle.

Table 32. Interrupt Acknowledge Operation Definition

Processor Outputs First Bus Cycle

Second Bus Cycle

D/C#

Low

M/IO#

W/R#

Low

BE[7:0]#

A[31:3]

EFh

FEh (low byte enabled)

0000_0000h

Interrupt number expected from interrupt con-

troller on D[7:0]

D[63:0]

(ignored)

The system logic can drive INTR either synchronously or

asynchronously. If it is asserted asynchronously, it must be

asserted for a minimum pulse width of two clocks. To ensure it

is recognized, INTR must remain asserted until an interrupt

acknowledge sequence is complete.

188

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Interrupt Acknowledge Cycles

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

LOCK#

INTR

Interrupt Number

D[63:0]

KEN#

BRDY#

Figure 76. Interrupt Acknowledge Operation

Chapter 7

Bus Cycles

189

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7.6

Special Bus Cycles

The AMD-K6-2E+ processor drives special bus cycles that

include the following:

■ Stop grant

■ Enhanced power management

■ Flush acknowledge

■ Cache writeback invalidation

■ Halt

■ Cache invalidation

■ Shutdown

During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1.

BE[7:0]# and A[31:3] are driven to differentiate among the

special cycles, as shown in Table 33.

Note that the system logic must return BRDY# in response to all

processor special cycles.

Table 33. Encodings for Special Bus Cycles

1

BE[7:0]#

Special Bus Cycle

Cause

A[4:3]

FBh

10b

Stop Grant

STPCLK# sampled asserted

A dword access is made to the EPM 16-byte I/O block and the GSBC bit of the

EPMR register is set to 1

EPM Stop Grant²

BFh

00b

EFh

F7h

FBh

FDh

FEh

00b

Flush Acknowledge

Writeback

Halt

FLUSH# sampled asserted

WBINVD instruction

HLT instruction

Flush

INVD,WBINVD instruction

Triple fault

Shutdown

Notes:

1. A[31:5] = 0

2. Supported on the low-power versions only.

Basic Special Bus

Cycle

Figure 77 on page 191 shows a basic special bus cycle.

The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the

same clock edge that it asserts ADS#.

In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h,

which indicates that the special cycle is a halt special cycle (See

190

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 33). A halt special cycle is generated after the processor

executes the HLT instruction.

If the processor samples FLUSH# asserted, it writes back any

L1 data cache and L2 cache lines that are in the modified state

and invalidates all lines in all caches. The processor then drives

a flush acknowledge special cycle.

If the processor executes a WBINVD instruction, it drives a

writeback special cycle after the processor completes

invalidating and writing back the cache lines.

Halt Cycle

CLK

A[31:3]

A[4:3] = 00b

FBh

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

BRDY#

Figure 77. Basic Special Bus Cycle (Halt Cycle)

Chapter 7

Bus Cycles

191

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Shutdown Cycle

In Figure 78 on page 192, a shutdown (triple fault) occurs in the

first half of the waveform, and a shutdown special cycle follows

in the second half. The processor enters shutdown when an

interrupt or exception occurs during the handling of a double

fault (INT 8), which amounts to a triple fault. When the

processor encounters a triple fault, it stops its activity on the

bus and generates the shutdown special bus cycle (BE[7:0]# =

FEh).

The system logic must assert NMI, INIT, RESET, or SMI# to get

the processor out of the shutdown state.

Shutdown Occurs

(Triple Fault)

Shutdown Special Cycle

CLK

A[4:3] = 00b

FEh

A[31:3]

BE[7:0]#

ADS#

LOCK#

M/IO#

D/C#

W/R#

D[63:0]

KEN#

BRDY#

Figure 78. Shutdown Cycle

192

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Stop Grant and Stop

Clock States

Figure 79 on page 194 and Figure 80 on page 195 show the

processor transition from normal execution to the Stop Grant

state, then to the Stop Clock state, back to the Stop Grant state,

and finally back to normal execution. The series of transitions

begins when the processor samples STPCLK# asserted. On

recognizing a STPCLK# interrupt at the next instruction

retirement boundary, the processor performs the following

actions, in the order shown:

1. Its instruction pipelines are flushed.

2. All pending and in-progress bus cycles are completed.

3. The STPCLK# assertion is acknowledged by executing a

Stop Grant special bus cycle.

4. Its internal clock is stopped after BRDY# of the Stop Grant

special bus cycle is sampled asserted (if EWBE# is masked

off, then entry into the Stop Grant state is not affected by

EWBE#) and after EWBE# is sampled asserted.

5. The Stop Clock state is entered if the system logic stops the

bus clock CLK (optional).

STPCLK# is sampled as a level-sensitive input on every clock

edge but is not recognized until the next instruction boundary.

The system logic drives the signal either synchronously or

asynchronously. If it is asserted asynchronously, it must be

asserted for a minimum pulse width of two clocks. STPCLK#

must remain asserted until recognized, which is indicated by

the completion of the Stop Grant special cycle.

Chapter 7

Bus Cycles

193

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Stop Clock

Stop Grant Special Cycle

STPCLK# Sampled Asserted

CLK

A[4:3] = 10b

FBh

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

CACHE#

STPCLK#

D[63:0]

KEN#

BRDY#

Figure 79. Stop Grant and Stop Clock Modes, Part 1

194

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Stop Clock

STPCLK# Sampled Negated Normal

Stop Grant State

(Re-entered after PLL stabilization)

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

CACHE#

STPCLK#

D[63:0]

KEN#

BRDY#

Figure 80. Stop Grant and Stop Clock Modes, Part 2

Chapter 7

Bus Cycles

195

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

INIT-Initiated

Transition from

Protected Mode to

Real Mode

INIT is typically asserted in response to a BIOS interrupt that

writes to an I/O port. This interrupt is often in response to a

Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar

to port 64h in the keyboard controller) that asserts INIT. INIT is

also used to support 80286 software that must return to Real

mode after accessing extended memory in Protected mode.

The assertion of INIT causes the processor to empty its

pipelines, initialize most of its internal state, and branch to

address FFFF_FFF0h—the same instruction execution starting

point used after RESET. Unlike RESET, the processor

preserves the contents of its caches, the floating-point state, the

MMX state, Model-Specific Registers (MSRs), the CD and NW

bits of the CR0 register, the time stamp counter, and other

specific internal resources.

Figure 81 on page 197 shows an example in which the operating

system writes to an I/O port, causing the system logic to assert

INIT. The sampling of INIT asserted starts an extended

microcode sequence that terminates with a code fetch from

FFFF_FFF0h, the reset location. INIT is sampled on every clock

edge but is not recognized until the next instruction boundary.

During an I/O write cycle, it must be sampled asserted a

minimum of three clock edges before BRDY# is sampled

asserted if it is to be recognized on the boundary between the

I/O write instruction and the following instruction. If INIT is

asserted synchronously, it can be asserted for a minimum of one

clock. If it is asserted asynchronously, it must have been

negated for a minimum of two clocks, followed by an assertion

of a minimum of two clocks.

196

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

INIT Sampled Asserted

Code Fetch

CLK

A[31:3]

BE[7:0]#

ADS#

FFFF_FFF0h

M/IO#

D/C#

W/R#

D[63:0]

KEN#

BRDY#

INIT

Figure 81. INIT-Initiated Transition from Protected Mode to Real Mode

Chapter 7

Bus Cycles

197

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

198

Bus Cycles

Chapter 7

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

8

Power-on Configuration and Initialization

On power-on the system logic must reset the AMD-K6-2E+

processor by asserting the RESET signal. When the processor

samples RESET asserted, it immediately flushes and initializes

all internal resources and its internal state, including its

pipelines and caches, the floating-point state, the MMX and

3DNow! states, and all registers. Then the processor jumps to

address FFFF_FFF0h to start instruction execution.

8.1

Signals Sampled During the Falling Transition of RESET

FLUSH#

FLUSH# is sampled on the falling transition of RESET to

determine if the processor begins normal instruction execution

or enters Three-State Test mode.

■ If FLUSH# is High during the falling transition of RESET,

the processor unconditionally runs its Built-In Self Test

(BIST), performs the normal reset functions, then jumps to

address FFFF_FFF0h to start instruction execution. (See

“Built-In Self-Test (BIST)” on page 251 for more details.)

■ If FLUSH# is Low during the falling transition of RESET,

the processor enters Three-State Test mode. (See

“Three-State Test Mode” on page 252 and “FLUSH# (Cache

Flush)” on page 112 for more details.)

BF[2:0]

The internal operating frequency of the processor is

determined by the state of the bus frequency signals BF[2:0]

when they are sampled during the falling transition of RESET.

The frequency of the CLK input signal is multiplied internally

by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”

on page 101 for the processor-clock to bus-clock ratios.)

Chapter 8

Power-on Configuration and Initialization

199

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

8.2

RESET Requirements

During the initial power-on reset of the processor, RESET must

remain asserted for a minimum of 1.0 ms after CLK and V

CC

reach specification. (See “CLK Switching Characteristics” on

page 296 for clock specifications. “Electrical Data” beginning

on page 285 for V specifications.)

CC

During a warm reset while CLK and V

are within

CC

specification, RESET must remain asserted for a minimum of

15 clocks prior to its negation.

8.3

State of Processor After RESET

Output Signals

Table 34 shows the state of all processor outputs and

bidirectional signals immediately after RESET is sampled

asserted.

Table 34. Output Signal State After RESET

Signal

State

Floating

High

Signal

LOCK#

M/IO#

PCD

State

High

Low

A[31:3], AP

ADS#, ADSC#

APCHK#

BE[7:0]#

BREQ

High

Low

Floating

Low

High

Low

PCHK#

PWT

CACHE#

D/C#

High

SCYC

Low

High

Floating

Low

SMIACT#

TDO

D[63:0], DP[7:0]

FERR#

Floating

High

VCC2DET

VCC2H/L#

HIT#

High

Low

1

HITM#

HLDA

High

Low

01010b

Low

VID[4:0]

W/R#

Notes:

1. Supported on low-power versions only.

Registers

Table 35 on page 201 shows the state of all architecture

registers and Model-Specific Registers (MSRs) after the

processor has completed its initialization due to the recognition

of the assertion of RESET.

200

Power-on Configuration and Initialization

Chapter 8

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 35. Register State After RESET

Register

GDTR

IDTR

State (hex)

base:0000_0000h limit:0FFFFh

0000h

TR

LDTR

EIP

0000h

FFFF_FFF0h

0000_0002h

0000_0000h

0000_059Xh

0000_0000h

F000h

EFLAGS

EAX¹

EBX

ECX

EDX²

ESI

EDI

EBP

ESP

CS

SS

0000h

DS

0000h

ES

0000h

FS

0000h

GS

0000h

FPU Stack R7–R0³

FPU Control Word³

FPU Status Word³

FPU Tag Word³

0000_0000_0000_0000_0000h

0040h

0000h

5555h

FPU Instruction Pointer³

FPU Data Pointer³

FPU Opcode Register³

0000_0000_0000h

000_0000_0000b

CR0⁴

CR2

CR3

CR4

DR7

DR6

DR3

6000_0010h

0000_0000h

0000_0400h

FFFF_0FF0h

0000_0000h

Chapter 8

Power-on Configuration and Initialization

201

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 35. Register State After RESET (continued)

Register

DR2

State (hex)

0000_0000h

DR1

0000_0000h

DR0

MCAR³

MCTR³

TR12³

0000_0000_0000_0000h

0000_0000_0000_0002h

0000_0000_0000_0000h

0000_0000_0000_01SBh

0000_0000_0000_0000h

TSC³

EFER³

STAR³

WHCR³

UWCCR³

PSOR⁵

,

PFIR^{3 5}

,

EPMR^{3 6}

0000_0000_0000_0000h

Notes:

1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.

If EAX is non-zero, BIST failed.

2. EDX contains the AMD-K6-2E+ processor signature, where X indicates the processor Stepping ID.

3. The contents of these registers are preserved following the recognition of INIT.

4. The CD and NW bits of CR0 are preserved following the recognition of INIT.

5. “S” represents the Stepping. “B” represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is

equal to the value of the BF[2:0] signals sampled during the falling transition of RESET.

6. Supported on low-power versions only.

202

Power-on Configuration and Initialization

Chapter 8

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

8.4

State of Processor After INIT

The recognition of the assertion of INIT causes the processor to

empty its pipelines, to initialize most of its internal state, and to

branch to address FFFF_FFF0h—the same instruction

execution starting point used after RESET.

Unlike RESET, the processor preserves the contents of its

caches, the floating-point state, the MMX and 3DNow! states,

MSRs, and the CD and NW bits of the CR0 register.

The edge-sensitive interrupts FLUSH# and SMI# are sampled

and preserved during the INIT process and are handled

accordingly after the initialization is complete. However, the

processor resets any pending NMI interrupt upon sampling

INIT asserted.

INIT can be used as an accelerator for 80286 code that requires

a reset to exit from Protected mode back to Real mode.

Chapter 8

Power-on Configuration and Initialization

203

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

204

Power-on Configuration and Initialization

Chapter 8

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

9

Cache Organization

The following sections describe the basic architecture and

resources of the AMD-K6-2E+ processor internal caches.

The performance of the AMD-K6-2E+ processor is enhanced by

writeback level-one (L1) and level-two (L2) caches.

■ The L1 cache is organized as separate 32-Kbyte instruction

and data caches, each with two-way set associativity.

■ The L2 cache is 128 Kbytes, and is organized as a unified,

four-way set-associative cache (See Figure 82 on page 206).

The cache line size is 32 bytes, and lines are fetched from

external memory using an efficient pipelined burst transaction.

As the L1 instruction cache is filled from the L2 cache or from

external memory, each instruction byte is analyzed for

instruction boundaries using predecode logic. Predecoding

annotates each instruction byte in the L1 instruction cache with

information that later enables the decoders to efficiently

decode multiple instructions simultaneously.

Translation lookaside buffers (TLB) are used in conjunction

with the L1 cache to translate linear addresses to physical

addresses. The L1 instruction cache is associated with a

64-entry TLB, while the L1 data cache is associated with a

128-entry TLB.

Chapter 9

Cache Organization

205

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

32-Kbyte L1 Instruction Cache

Tag

RAM

State Tag

Bit RAM

State

Bit

Way 0

Way 1

64-Entry TLB

System Bus

Interface Unit

Processor

Core

Pre-Decode Instruction Cache

128-Entry TLB

Tag

RAM

MESI Tag

Bits RAM

MESI

Bits

Way 0

Way 1

32-Kbyte L1 Data Cache

Tag

RAM

MESI Tag

Bits RAM

MESI Tag

Bits RAM

MESI Tag

Bits RAM

MESI

Way 0

Way 1

Way 2

Way 3

Bits

128-Kbyte L2 Cache

Figure 82. L1 and L2 Cache Organization for the AMD-K6™-2E+ Processor

The processor cache design takes advantage of a sectored

organization (See Figure 83). Each sector consists of 64 bytes

configured as two 32-byte cache lines. The two cache lines of a

sector share a common tag but have separate MESI (modified,

exclusive, shared, invalid) bits that track the state of each cache

line.

206

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

L1 Instruction Cache Line

Tag

Address

Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit

Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit

L1 Data Cache Line and L2 Cache Line

Tag

Address

Cache Line 0

Cache Line 1

Byte 31

Byte 30

........

Byte 0

2 MESI Bits

Note: L1 instruction-cache lines have only two coherency states

(valid or invalid) rather than the four MESI coherency

states of L1 data-cache and L2 cache lines. Only two states

are needed for the L1 instruction cache because these lines

are read-only.

Figure 83. L1 Cache Sector Organization

9.1

MESI States in the L1 Data Cache and L2 Cache

The state of each line in the caches is tracked by the MESI bits.

The coherency of these states or MESI bits is maintained by

internal processor snoops and external inquire cycles by the

system logic. The following four states are defined for the L1

data cache and the L2 cache:

■ Modified—This line has been modified and is different from

external memory.

■ Exclusive—In general, an exclusive line in the L1 data cache

or the L2 cache is not modified and is the same as external

memory. The exception is the case where a line exists in the

modified state in the L1 data cache and also resides in the

L2 cache. By design, the line in the L2 cache must be in the

exclusive state.

■ Shared—If a cache line is in the shared state it means that

the same line can exist in more than one cache system.

■ Invalid—The information in this line is not valid.

Chapter 9

Cache Organization

207

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

9.2

Predecode Bits

Decoding x86 instructions is particularly difficult because the

instructions vary in length, ranging from 1 to 15 bytes long.

Predecode logic supplies the predecode bits associated with

each instruction byte.

Predecode bits indicate the number of bytes to the start of the

next x86 instruction. The predecode bits are passed with the

instruction bytes to the decoders where they assist with parallel

x86 instruction decoding. The predecode bits use memory

separate from the 32-Kbyte L1 instruction cache. The

predecode bits are stored in an extended L1 instruction cache

alongside each x86 instruction byte as shown in Figure 83 on

page 207.

The L2 cache does not store predecode bits. As an instruction

cache line is fetched from the L2 cache, the predecode bits are

generated and stored alongside the cache line in the L1

instruction cache in the same manner as if the cache line were

fetched from the processor’s system bus.

9.3

Cache Operation

The operating modes for the caches are configured by software

using the not writethrough (NW) and cache disable (CD) bits of

control register 0 (CR0 bits 29 and 30, respectively). These bits

are used in all operating modes.

■ When the CD and NW bits are both set to 0, the cache is fully

enabled. This is the standard operating mode for the cache.

If a L1 cache read miss occurs, the processor determines if

the read hits the L2 cache, in which case the cache line is

supplied from the L2 cache to the L1 cache. If a read misses

both the L1 and the L2 caches, a line fill (32-byte burst read)

on the system bus occurs in order to fetch the cache line. The

cache line is then filled in both the L1 and the L2 caches.

Write hits to the L1 and L2 caches are updated, while write

misses and writes to shared lines cause external memory

updates. Refer to Table 39 on page 221 for a summary of

cache read and write cycles and the effect of these

operations on the cache MESI state.

Note: A write allocate operation can modify the behavior of write

misses to the caches. See “Write Allocate” on page 215.

208

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The AMD-K6-2E+ processor does not enforce any rules of

inclusion or exclusion as part of the protocol defined for the

L1 and L2 caches. However, there are certain restrictions

imposed by design on the allowable MESI states of a cache

line that exists in both the L1 cache and the L2 cache. Refer

to Table 40 on page 225 for a list of the valid cache-line

states allowed.

■ When CD is set to 0 and NW is set to 1, an invalid mode of

operation exists that causes a general protection fault to

occur.

■ When CD is set to 1 (disabled) and NW is set to 0, the cache

fill mechanism is disabled but the contents of the cache are

still valid. The processor reads from the caches if the read

hits the L1 or the L2 cache. If a read misses both the L1 and

the L2 caches, a line fill does not occur on the system bus.

Write hits to the L1 or L2 cache are updated, while write

misses and writes to shared lines cause external memory

updates. If PWT is driven Low and WB/WT# is sampled

High, a write hit to a shared line changes the cache-line state

to exclusive.

■ When the CD and NW bits are both set to 1, the cache is fully

disabled. Even though the cache is disabled, the contents

are not necessarily invalid. The processor reads from the

caches if the read hits the L1 or the L2 cache. If a read

misses both the L1 and the L2 caches, a line fill does not

occur on the system bus. If a write hits the L1 or the L2

cache, the cache is updated but an external memory update

does not occur. If a cache line is in the exclusive state during

a write hit, the cache-line state is changed to modified.

Cache lines in the shared state remain in the shared state

after a write hit. Write misses access external memory

directly.

The operating system can control the cacheability of a page.

The paging mechanism is controlled by CR3, the Page Directory

Entry (PDE), and the Page Table Entry (PTE). Within CR3,

PDE, and PTE are Page Cache Disable (PCD) and Page

Writethrough (PWT) bits. The values of the PCD and PWT bits

used in Table 36 on page 210 and Table 37 on page 210 are

taken from either the PTE or PDE. For more information on

PCD and PWT, see “PCD (Page Cache Disable)” on page 124

and “PWT (Page Writethrough)” on page 126, respectively.

Chapter 9

Cache Organization

209

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 36 describes how the PWT signal is driven based on the

values of the PWT bits and the PG bit of CR0.

Table 36. PWT Signal Generation

1

PG Bit of CR0

PWT Signal

PWT Bit

1

0

1

0

1

0

High

Low

Notes:

1. PWT is taken from PTE or PDE.

Table 37 describes how the PCD signal is driven based on the

values of the CD bit of CR0, the PCD bits, and the PG bit of

CR0.

Table 37. PCD Signal Generation

1

CD Bit of CR0

PG Bit of CR0

PCD Signal

PCD Bit

1

0

X

1

0

1

0

X

1

0

High

Low

Notes:

1. PCD is taken from PTE or PDE.

Table 38 describes how the CACHE# signal is driven based on

the cycle type, the CI bit of TR12, the PCD signal, and the

UWCCR model-specific register.

210

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 38. CACHE# Signal Generation

1

Cycle Type

CI Bit of TR12

PCD Signal

CACHE#

Low

Access Within WC/UC Range

X

0

X

1

X

0

X

1

X

Writebacks

0

X

1

Low

Unlocked Reads

Locked Reads

High

Single Writes

High

Any Cycle Except Writebacks

High

Any Cycle Except Writebacks

Notes:

1. WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR.

Cache-Related Signals

Complete descriptions of the signals that control cacheability

and cache coherency are given on the following pages:

■ CACHE#—page 105

■ EADS#—page 109

■ FLUSH#—page 112

■ HIT#—page 113

■ HITM#—page 113

■ INV—page 118

■ KEN#—page 119

■ PCD—page 124

■ PWT—page 126

■ WB/WT#—page 139

9.4

Cache Disabling and Flushing

L1 and L2 Cache

Disabling

To completely disable all accesses to the L1 and the L2 caches,

the CD bit must be set to 1 and the caches must be completely

flushed. There are three different methods for flushing the

caches. The first method relies on the system logic and the

other two methods rely on software.

■ For the system logic to flush the caches, the processor must

sample FLUSH# asserted. In this method, the processor

writes back any L1 data cache and L2 cache lines that are in

Chapter 9

Cache Organization

211

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

the modified state, invalidates all lines in all caches, and

then executes a flush acknowledge special cycle (See

Table 24 on page 142).

■ The second method for flushing the caches is for software to

execute the WBINVD instruction, which causes all modified

lines to first be written back to memory, then marks all

cache lines as invalid. Alternatively, if writing modified lines

back to memory is not necessary, the INVD instruction can

be used to invalidate all cache lines.

■ The third method for flushing the caches is to make use of

the Page Flush/Invalidate Register (PFIR), which allows

cache invalidation and optional flushing of a specific 4-

Kbyte page from the linear address space (see “Page

Flush/Invalidate Register (PFIR)” on page 223). Unlike the

previous two methods of flushing the caches, this particular

method requires the software to be aware of which specific

pages must be flushed and invalidated.

L2 Cache Disabling

The L2 cache in the AMD-K6-2E+ processor can be completely

disabled by setting the L2 Disable (L2D) bit (EFER[4]) to 1 (see

“Extended Feature Enable Register (EFER)” on page 47). If

disabled in this manner, the processor does not access the L2

cache for any purpose, including allocations, read hits, write

hits, snoops, inquire cycles, flushing, and read/write attempts

by means of the L2AAR. (See “L2 Cache Testing” on page 213.)

The L1 cache operation is not affected by disabling the L2

cache.

The L2D bit is provided for debug and testing purposes only. For

normal operation and maximum performance, this bit must be

set to 0, which is the default setting following reset.

The AMD-K6-2E+ processor does not provide a method for

disabling the L1 cache while the L2 cache remains enabled.

212

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

9.5

9.6

L2 Cache Testing

The AMD-K6-2E+ processor provides the L2AAR MSR that

allows for direct access to the L2 cache and L2 tag arrays. For

more detailed information, refer to “L2 Cache and Tag Array

Testing” on page 264.

Cache-Line Fills

The processor performs a cache-line fill for any area of system

memory defined as cacheable. If an area of system memory is

not explicitly defined as uncacheable by the software or system

logic, or implicitly treated as uncacheable by the processor,

then the memory access is assumed to be cacheable.

Software can prevent caching of certain pages by setting the

PCD bit in the PDE or PTE. Additionally, software can define

regions of memory as uncacheable or write combinable by

programming the MTRRs in the UWCCR MSR (see “Memory

Type Range Registers” on page 231). Write-combinable

memory is defined as uncacheable.

The system logic also has control of the cacheability of bus

cycles. If it determines the address is not cacheable, system

logic negates the KEN# signal when asserting the first BRDY#

or NA# of a cycle.

The processor does not cache certain memory accesses such as

locked operations. In addition, the processor does not cache

PDE or PTE memory reads in the L1 cache (referred to as page

table walks). However, page table walks are cached in the L2

cache if the PDE or PTE is determined to be cacheable.

When the processor needs to read memory, the processor drives

a read cycle onto the bus. If the cycle is cacheable, the

processor asserts CACHE#. If the cycle is not cacheable, a

non-burst, single-transfer read takes place. The processor waits

for the system logic to return the data and assert a single

BRDY# (See Figure 60 on page 159). If the cycle is cacheable,

the processor executes a 32-byte burst read cycle. The processor

expects a total of four BRDY# signals for a burst read cycle to

take place (See Figure 62 on page 163).

Chapter 9

Cache Organization

213

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Cache-line fills initiate 32-byte burst read cycles from memory

on the system bus for the L1 instruction cache and the L1 data

cache. All L1 cache-line fills supplied from the system bus are

also filled in the L2 cache.

9.7

Cache-Line Replacements

As programs execute and task switches occur, some cache lines

eventually require replacement.

When a cache miss occurs in the L1 cache, the required cache

line is filled from either the L2 cache, if the cache line is

present (L2 cache hit), or from external memory, if the cache

line is not present (L2 cache miss). If the cache line is filled

from external memory, the cache line is filled in both the L1

and the L2 caches.

Two forms of cache misses and associated cache fills can take

place—a tag-miss cache fill and a tag-hit cache fill.

■ In the case of a tag-miss cache fill, the level-one cache miss is

due to a tag mismatch, in which case the required cache line

is filled either from the level-two cache or from external

memory, and the level-one cache line within the sector that

was not required is marked as invalid.

■ In the case of a tag-hit cache fill, the address matches the

tag, but the requested cache line is marked as invalid. The

required level-one cache line is filled from the level-two

cache or from external memory, and the level-one cache line

within the sector that is not required remains in the same

cache state.

If a L1 data-cache line being filled replaces a modified line, the

modified line is written back to the L2 cache if the cache line is

present (L2 cache hit). By design, if a cache line is in the

modified state in the L1 cache, this cache line can only exist in

the L2 cache in the exclusive state. During the writeback, the

L2 cache-line state is changed from exclusive to modified, and

the writeback does not occur on the system bus. If the

replacement writeback does not hit the L2 cache (L2 cache

miss), then the modified L1 cache line is written back on the

system bus, and the L2 cache is not updated. If the other cache

line in this sector is in the modified state, it is also written back

in the same manner.

214

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

L1 instruction-cache lines and L2 cache lines are replaced using

a Least Recently Used (LRU) algorithm. If a line replacement is

required, lines are replaced when read cache misses occur.

The L1 data cache uses a slightly different approach to line

replacement. If a miss occurs, and a replacement is required,

lines are replaced by using a Least Recently Allocated (LRA)

algorithm.

9.8

Write Allocate

Write allocate, if enabled, occurs when the processor has a

pending memory write cycle to a cacheable line and the line

does not currently reside in the L1 data cache. If the line does

not exist in the L2 cache, the processor performs a 32-byte burst

read cycle on the system bus to fetch the data-cache line

addressed by the pending write cycle. If the line does exist in

the L2 cache, the data is supplied directly from the L2 cache, in

which case a system bus cycle is not executed. The data

associated with the pending write cycle is merged with the

recently-allocated data-cache line and stored in the processor’s

L1 data cache. If the data-cache line was fetched from memory

(because of a L2 cache miss), the data is stored, without

modification, in the L2 cache. The final MESI state of the cache

lines depends on the state of the WB/WT# and PWT signals

during the burst read cycle and the subsequent L1 data cache

write hit (See Table 39 on page 221 to determine the cache-line

states and the access types following a cache write miss). If the

L1 data cache line is stored in the modified state, then the same

cache line is stored in the L2 cache in the exclusive state. If the

L1 data cache line is stored in the shared state, then the same

cache line is stored in the L2 cache in the shared state.

If a data-cache line fetch from memory is attempted because

the write allocate misses the L2 cache, and KEN# is sampled

negated, the processor does not perform an allocation. In this

case, the pending write cycle is executed as a single write cycle

on the system bus.

During write allocates that miss the L2 cache, a 32-byte burst

read cycle is executed in place of a non-burst write cycle. While

the burst read cycle generally takes longer to execute than the

non-burst write cycle, performance gains are realized on

subsequent write cycle hits to the write-allocated cache line.

Chapter 9

Cache Organization

215

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Due to the nature of software, memory accesses tend to occur in

proximity of each other (principle of locality). The likelihood of

additional write hits to the write-allocated cache line is high.

Write allocates that hit the L2 cache increase performance by

avoiding accesses to the system bus.

The following is a description of three mechanisms by which the

AMD-K6-2E+ processor performs write allocations. A write

allocate is performed when any one or more of these

mechanisms indicates that a pending write is to a cacheable

area of memory.

Write to a Cacheable

Page

Every time the processor completes a L1 cache line fill, the

address of the page in which the cache line resides is saved in

the Cacheability Control Register (CCR). The page address of

subsequent write cycles is compared with the page address

stored in the CCR. If the two addresses are equal, then the

processor performs a write allocate because the page has

already been determined to be cacheable.

When the processor performs a L1 cache line fill from a

different page than the address saved in the CCR, the CCR is

updated with the new page address.

Write to a Sector

If the address of a pending write cycle matches the tag address

of a valid L1 cache sector, but the addressed cache line within

the sector is marked invalid (a sector hit but a cache line miss),

then the processor performs a write allocate. The pending write

cycle is determined to be cacheable because the sector hit

indicates the presence of at least one valid cache line in the

sector. The two cache lines within a sector are guaranteed by

design to be within the same page.

Write Allocate Limit

The AMD-K6-2E+ processor uses two mechanisms that are

programmable within the Write Handling Control Register

(WHCR) to enable write allocations for write cycles that

address a definable area, or a special 1-Mbyte memory area.

The WHCR contains two fields—the Write Allocate Enable

Limit (WAELIM) field, and the Write Allocate Enable

15-to-16-Mbyte (WAE15M) bit (see Figure 84).

216

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

63

32 31

22 21 17 16 15

0

W

A

E

WAELIM

1

5

M

Reserved

Symbol

WAELIM

WAE15M

Description

Write Allocate Enable Limit

Write Allocate Enable 15-to-16-Mbyte 16

Bits

31-22

Notes: Hardware RESET initializes this MSR to all zeros.

Figure 84. Write Handling Control Register (WHCR)

Write Allocate Enable Limit Field. The WAELIM field is 10 bits wide.

This field, multiplied by 4 Mbytes, defines an upper memory

limit. Any pending write cycle that misses the L1 cache and that

addresses memory below this limit causes the processor to

perform a write allocate (assuming the address is not within a

range where write allocates are disallowed). Write allocate is

disabled for memory accesses at and above this limit unless the

processor determines a pending write cycle is cacheable by

means of one of the other write allocate mechanisms—“Write

to a Cacheable Page” and “Write to a Sector.” The maximum

10

value of this limit is ((2 –1) · 4 Mbytes) = 4092 Mbytes. When

all the bits in this field are set to 0, all memory is above this

limit and write allocates due to this mechanism is disabled

(even if all bits in the WAELIM field are set to 0, write allocates

can still occur due to the “Write to a Cacheable Page” and

“Write to a Sector” mechanisms).

Write Allocate Enable 15-to-16-Mbyte Bit. The Write Allocate Enable

15-to-16-Mbyte (WAE15M) bit is used to enable write

allocations for memory write cycles that address the 1 Mbyte of

memory between 15 Mbytes and 16 Mbytes. This bit must be set

to 1 to allow write allocate in this memory area. This bit is

provided to account for a small number of uncommon

memory-mapped I/O adapters that use this particular memory

address space. If the system contains one of these peripherals,

the bit should be set to 0 (even if the WAE15M bit is set to 0,

write allocates can still occur between 15 Mbytes and 16

Mbytes due to the “Write to a Cacheable Page” and “Write to a

Chapter 9

Cache Organization

217

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Sector” mechanisms). The WAE15M bit is ignored if the value

in the WAELIM field is set to less than 16 Mbytes.

By definition a write allocate is not performed in the memory

area between 640 Kbytes and 1 Mbyte unless the processor

determines a pending write cycle is cacheable by means of one

of the other write allocate mechanisms—“Write to a Cacheable

Page” and “Write to a Sector.” It is not considered safe to

perform write allocations between 640 Kbytes and 1 Mbyte

(000A_0000h to 000F_FFFFh) because it is considered a

noncacheable region of memory.

If a memory region is defined as write combinable or

uncacheable by a MTRR, write allocates are not performed in

that region.

Write Allocate Logic

Mechanisms and

Conditions

Figure 85 shows the logic flow for all the mechanisms involved

with write allocate for memory bus cycles. The left side of the

diagram (the text) describes the conditions that need to be true

in order for the value of that line to be a 1. Items 1 to 4 of the

diagram are related to general cache operation and items 5 to

10 are related to the write allocate mechanisms.

For more information about write allocate, see the

Implementation of Write Allocate in the K86™ Processors

Application Note, order# 21326.

Perform

Write Allocate

1) CD Bit of CR0

2) PCD Signal

3) CI Bit of TR12

4) UC or WC

5) Write to Cacheable Page (CCR)

6) Write to a Sector

7) Less Than Limit (WAELIM)

8) Between 640 Kbytes and 1 Mbyte

9) Between 15–16 Mbytes

10) Write Allocate Enable 15–16 Mbyte (WAE15M)

Figure 85. Write Allocate Logic Mechanisms and Conditions

218

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The following list describes the corresponding items in Figure

85:

1. CD Bit of CR0—When the cache disable (CD) bit within con-

trol register 0 (CR0) is set to 1, the cache fill mechanism for

both reads and writes is disabled and write allocate does

not occur.

2. PCD Signal—When the PCD (page cache disable) signal is

driven High, caching for that page is disabled, even if KEN#

is sampled asserted, and write allocate does not occur.

3. CI Bit of TR12—When the cache inhibit bit of Test Register

12 is set to 1, L1 and L2 cache fills are disabled and write

allocate does not occur.

4. UC or WC—If a pending write cycle addresses a region of

memory defined as write combinable or uncacheable by an

MTRR, write allocates are not performed in that region.

5. Write to a Cacheable Page (CCR)—A write allocate is

performed if the processor knows that a page is cacheable.

The CCR is used to store the page address of the last L1

cache fill for a read miss. See “Write to a Cacheable Page”

on page 216 for a detailed description of this condition.

6. Write to a Sector—A write allocate is performed if the

address of a pending write cycle matches the tag address of

a valid L1 cache sector but the addressed cache line within

the sector is invalid. See “Write to a Sector” on page 216 for

a detailed description of this condition.

7. Less Than Limit (WAELIM)—The write allocate limit

mechanism determines if the memory area being addressed

is less than the limit set in the WAELIM field of WHCR. If

the address is less than the limit, write allocate for that

memory address is performed as long as conditions 8

through 10 do not prevent write allocate (even if conditions

8 and 10 attempt to prevent write allocate, condition 5 or 6

allows write allocate to occur).

8. Between 640 Kbytes and 1 Mbyte—Write allocate is not

performed in the memory area between 640 Kbytes and 1

Mbyte. It is not considered safe to perform write allocations

between 640 Kbytes and 1 Mbyte (000A_0000h to

000F_FFFFh) because this area of memory is considered a

noncacheable region of memory (even if condition 8

attempts to prevent write allocate, condition 5 or 6 allows

write allocate to occur).

Chapter 9

Cache Organization

219

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

9. Between 15–16 Mbytes—If the address of a pending write

cycle is in the 1 Mbyte of memory between 15 Mbytes and

16 Mbytes, and the WAE15M bit is set to 1, write allocate

for this cycle is enabled.

10.Write Allocate Enable 15–16 Mbytes (WAE15M)—This

condition is associated with the Write Allocate Limit

mechanism and affects write allocate only if the limit

specified by the WAELIM field is greater than or equal to

16 Mbytes. If the memory address is between 15 Mbytes and

16 Mbytes, and the WAE15M bit in the WHCR is set to 0,

write allocate for this cycle is disabled (even if condition 10

attempts to prevent write allocate, condition 5 or 6 allows

write allocate to occur).

9.9

Prefetching

Hardware

Prefetching

The AMD-K6-2E+ processor conditionally performs cache

prefetching, which results in the filling of the required cache

line first, and a prefetch of the second cache line making up the

other half of the sector. From the perspective of the external

bus, the two cache-line fills typically appear as two 32-byte

burst read cycles occurring back-to-back or, if allowed, as

pipelined cycles. The burst read cycles do not occur

back-to-back (wait states occur) if the processor is not ready to

start a new cycle, if higher priority data read or write requests

exist, or if NA# (next address) was sampled negated. Wait states

can also exist between burst cycles if the processor samples

AHOLD or BOFF# asserted.

Software Prefetching

The 3DNow! technology includes an instruction called

PREFETCH that allows a cache line to be prefetched into the

L1 data cache and the L2 cache. Unlike prefetching under

hardware control, software prefetching only fetches the cache

line specified by the operand of the PREFETCH instruction,

and does not attempt to fetch the other cache line in the sector.

The PREFETCH instruction format is defined in Table 15,

“3DNow!™ Instructions,” on page 89. For more detailed

information, see the 3DNow!™ Technology Manual, order#

21928.

220

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

9.10

Cache States

Table 39 shows all the possible cache-line states before and

after program-generated accesses to individual cache lines.

Table 39. L1 and L2 Cache States for Read and Write Accesses

Cache State After Access

1

Cache State Before Access

2

Type

Access Type

MESI State

L1

I

L2

I

L1

I

S or E⁴

L2

I

S or E⁴

Single read from bus

Burst read from bus, fill L1 and L2³

Read Miss L1,

Read Miss L2

I

E

S

M

I

–

E

S

M

–

E

S

M

E

S

M

–

E

S

E

Read Hit L1

Cache

Read

Fill L1

Read Miss L1,

Read Hit L2

E⁵

M⁵

I

Single write to bus⁶

I

7

M⁸

S⁹

E⁸

S⁹

Write Miss L1

Write Miss L2

Burst read from bus, fill L1 and L2, write to L1

Burst read from bus, fill L1 and L2, write to

L1 and L2, single write to bus⁷

Write to L1,

single write to bus

I

S or E⁴

S

I

Write Hit L1

Write to L1 and L2,

single write to bus

S or E⁴

S

Cache

Write

E or M

–

E

Write to L1

Write to L2⁶

M

I

–

I

M

S or E⁴

Write to L2, single write to bus⁶

Write to L2⁶

Fill L1, write to L1⁷

Write to L2, single write to bus⁷

Fill L1, write to L1⁷

S

I

M

E

I

M

Write Miss L1

Write Hit L2

M

E

S or E⁴

M

S or E⁴

E

S

M

Notes:

1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and

are treated as “valid” states.

2. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line.

3. If CACHE# is driven Low and KEN# is sampled asserted.

4. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or

WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.

Chapter 9

Cache Organization

221

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

5. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in

the modified state in the L2 cache.

6. Assumes the write allocate conditions as specified in “Write Allocate” on page 215 are not met.

7. Assumes the write allocate conditions as specified in “Write Allocate” on page 215 are met.

8. Assumes PWT is driven Low and WB/WT# is sampled High.

9. Assumes PWT is driven High or WB/WT# is sampled Low.

—

Not applicable or none.

9.11

Cache Coherency

Different ways exist to maintain coherency between the system

memory and cache memories. Inquire cycles, internal snoops,

FLUSH#, WBINVD, INVD, and line replacements all prevent

inconsistencies between memories.

Inquire Cycles

Inquire cycles are bus cycles initiated by system logic that

ensure coherency between the caches and main memory. In

systems with multiple bus masters, system logic maintains

cache coherency by driving inquire cycles to the processor.

System logic initiates inquire cycles by asserting AHOLD,

BOFF#, or HOLD to obtain control of the address bus and then

driving EADS#, INV (optional), and an inquire address

(A[31:5]).

This type of bus cycle causes the processor to compare the tags

for its L1 instruction and L1 data caches, and L2 cache, with the

inquire address.

■ If there is a hit to a shared or exclusive line in the L1 data

cache or the L2 cache, or a valid line in the L1 instruction

cache, the processor asserts HIT#.

■ If the compare hits a modified line in the L1 data cache or

the L2 cache, the processor asserts HIT# and HITM#. If

HITM# is asserted, the processor writes the modified line

back to memory.

■ If INV was sampled asserted with EADS#, a hit invalidates

the line.

■ If INV was sampled negated with EADS#, a hit leaves the

line in the shared state or transitions it from the exclusive or

modified state to the shared state.

Table 40 on page 225 lists valid combinations of MESI states

permitted for a cache line in the L1 and L2 caches, and shows

the effects of inquire cycles performed with INV equal to 0

(non-invalidating) and INV equal to 1 (invalidating).

222

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Internal Snooping

Internal snooping is initiated by the processor (rather than

system logic) during certain cache accesses. It is used to

maintain coherency between the L1 instruction cache and the

L1 data cache.

The processor automatically snoops its L1 instruction cache

during read or write misses to its L1 data cache, and it snoops

its L1 data cache during read misses to its L1 instruction cache.

The L2 cache is not snooped during misses to either of the L1

caches. Table 41 on page 226 summarizes the actions taken

during this internal snooping.

If an internal snoop hits its target, the processor does the

following:

■ L1 Data Cache Snoop During an L1 Instruction-cache Read

Miss—If modified, the line in the L1 data cache is written

back. If the writeback hits the L2 cache, the cache line is

stored in the L2 cache in the modified state and no

writeback occurs on the system bus. If the writeback misses

the L2 cache, the cache line is written back on the system

bus to external memory. Regardless of its state, the L1

data-cache line is invalidated and the L1 instruction cache

performs a read from either the L2 cache (if a L2 hit occurs)

or external memory (if a L2 miss occurs).

■ L1 Instruction Cache Snoop During an L1 Data Cache

Miss—The line in the instruction cache is marked invalid,

and the L1 data-cache read or write is performed as defined

in Table 39 on page 221.

FLUSH#

In response to sampling FLUSH# asserted, the processor writes

back any L1 data cache lines and L2 cache lines that are in the

modified state and then marks all lines in the L1 instruction

cache, the L1 data cache, and the L2 cache as invalid.

Page Flush/Invalidate

Register (PFIR)

The AMD-K6-2E+ processor contains the Page Flush/Invalidate

Register (PFIR) that allows cache invalidation and optional

flushing of a specific 4-Kbyte page from the linear address

space (see Figure 86 on page 224). When the PFIR is written to

(using the WRMSR instruction), the invalidation and,

optionally, the flushing begins. The total amount of cache in the

AMD-K6-2E+ processor is 128 Kbytes. Using this register can

result in a much lower cycle count for flushing particular pages

versus flushing the entire cache.

Chapter 9

Cache Organization

223

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

63

32 31

12 11 9 8 7

1 0

F

/

I

P

F

LINPAGE

Reserved

Description

Symbol

Bit

LINPAGE 20-bit Linear Page Address

31-12

PF

F/I

Page Fault Occurred

Flush/Invalidate Command

8

0

Figure 86. Page Flush/Invalidate Register (PFIR)

LINPAGE Field. This 20-bit field must be written with bits 31:12 of

the linear address of the 4-Kbyte page that is to be invalidated

and optionally flushed from the L1 or the L2 cache.

PF Bit. If an attempt to invalidate or flush a page results in a

page fault, the processor sets the PF bit to 1, and the invalidate

or flush operation is not performed (even though invalidate

operations do not normally generate page faults). In this case,

an actual page fault exception is not generated. If the PF bit

equals 0 after an invalidate or flush operation, then the

operation executed successfully. The PF bit must be read after

every write to the PFIR register to determine if the invalidate

or flush operation executed successfully.

F/I Bit. This bit is used to control the type of action that occurs to

the specified linear page. If a 0 is written to this bit, the

operation is a flush, in which case all cache lines in the

modified state within the specified page are written back to

memory, after which the entire page is invalidated. If a 1 is

written to this bit, the operation is an invalidation, in which

case the entire page is invalidated without the occurrence of

any writebacks.

WBINVD and INVD

These x86 instructions cause all cache lines to be marked as

invalid. WBINVD writes back modified lines before marking all

cache lines invalid. INVD does not write back modified lines.

Cache-Line

Replacement

Replacing lines in the L1 cache and the L2 cache, according to

the line replacement algorithms described in “Cache-Line

Fills” on page 213, ensures coherency between external

memory and the caches.

224

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 40 shows all possible cache-line states before and after

inquire cycles.

Table 40. Valid L1 and L2 Cache States and Effect of Inquire Cycles

Cache State After Inquire

INV = 0 INV = 1

1

Cache State Before Inquire

2

Memory Access

L1

L2

M

E

L1

I

L2

S

I

L1

L2

I

Writeback L2 to bus

I

–

I

S

–

I

–

I

E³

E

M³

E

I

Writeback L2 to bus

S

I

–

E

–

M

S

E

I

Writeback L1 to bus

I

Writeback L1 to bus

I

S

I

–

S

I

S

Notes:

1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and

are treated as “valid” states.

2. Writeback cycles to the bus are 32-byte burst writes.

3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in

the modified state in the L2 cache.

Chapter 9

Cache Organization

225

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 41 shows all possible cache-line states before and after

various cache-related operations.

Table 41. L1 and L2 Cache States for Snoops, Flushes, and Invalidation

1

Cache State After Operation

Cache State Before Operation

2

Operation Type

Access Type

L1

L2

M

E

L1

I

L2

M

E

S

I

–

I

S

I

E³

E

M³

E

I

M

E

I

Internal Snoop

I

E

I

M

S

E

I

Writeback L1 to L2

I

M

I

Writeback L1 to bus

I

S

I

–

I

S

I

S

–

I

S or E

–

I

FLUSH# Signal

M

–

Writeback L1 to bus

I

M

Writeback L2 to bus

I

–

I

PFIR (F/I = 0)

M

–

M

–

Writeback L1 to bus

I

Writeback L2 to bus

I

PFIR (F/I = 1)

–

I

S or E

–

I

WBINVD Instruction

M

–

M

–

Writeback L1 to bus

Writeback L2 to bus

–

I

INVD Instruction

–

I

Notes:

1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache

and are treated as “valid” states.

2. Writeback cycles to the bus are 32-byte burst writes.

3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in

the modified state in the L2 cache.

—

Not applicable or none.

226

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

9.12

Writethrough and Writeback Coherency States

The terms writethrough and writeback apply to two related

concepts in a read-write cache like the AMD-K6-2E+ processor

L1 data cache and the L2 cache. The following conditions apply

to both the writethrough and writeback modes:

■ Memory Writes—A relationship exists between external

memory writes and their concurrence with cache updates:

•

An external memory write that occurs concurrently with

a cache update to the same location is a writethrough.

Writethroughs are driven as single cycles on the bus.

•

An external memory write that occurs after the processor

has modified a cache line is a writeback. Writebacks are

driven as burst cycles on the bus.

■ Coherency State—A relationship exists between MESI

coherency states and writethrough-writeback coherency

states of lines in the cache as follows:

•

Shared and invalid MESI lines are in the writethrough

state.

•

Modified and exclusive MESI lines are in the writeback

state.

9.13

A20M# Masking of Cache Accesses

Although the processor samples A20M# as a level-sensitive

input on every clock edge, it should only be asserted in Real

mode. The processor applies the A20M# masking to its tags,

through which all programs access the caches. Therefore,

assertion of A20M# affects all addresses (cache and external

memory), including the following:

■ Cache-line fills (caused by read misses or write allocates)

■ Cache writethroughs (caused by write misses or write hits to

lines in the shared state)

However, A20M# does not mask writebacks or invalidations

caused by the following actions:

■ Internal snoops

■ Inquire cycles

■ The FLUSH# signal

Chapter 9

Cache Organization

227

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ Writing to the Page Flush/Invalidate Register (PFIR)

■ The WBINVD instruction

228

Cache Organization

Chapter 9

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

10

Write Merge Buffer

The AMD-K6-2E+ processor contains an 8-byte write merge

buffer that allows the processor to conditionally combine data

from multiple noncacheable write cycles into this merge buffer.

The merge buffer operates in conjunction with the Memory

Type Range Registers (MTRRs). Refer to “Memory Type Range

Registers” on page 231 for a description of the MTRRs.

Merging multiple write cycles into a single write cycle reduces

processor bus utilization and processor stalls, thereby

increasing the overall system performance.

10.1

EWBE# Control

The presence of the merge buffer creates the potential to

perform out-of-order write cycles relative to the processor’s

caches. In general, the ordering of write cycles that are driven

externally on the system bus and those that hit the processor’s

cache can be controlled by the EWBE# signal. See “EWBE#

(External Write Buffer Empty)” on page 110 for more

information.

If EWBE# is sampled negated, the processor delays the

commitment of write cycles to cache lines in the modified state

or exclusive state in the processor’s caches. Therefore, the

system logic can enforce strong ordering by negating EWBE#

until the external write cycle is complete, thereby ensuring that

a subsequent write cycle that hits a cache does not complete

ahead of the external write cycle.

However, the addition of the write merge buffer introduces the

potential for out-of-order write cycles to occur between writes

to the merge buffer and writes to the processor’s caches.

Because these writes occur entirely within the processor and

are not sent out to the processor bus, the system logic is not able

to enforce strong ordering with the EWBE# signal.

The EWBE# control (EWBEC) bits in the EFER register provide

a mechanism for enforcing three different levels of write

ordering in the presence of the write merge buffer:

Chapter 10

Write Merge Buffer

229

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ EFER[3] is defined as the Global EWBE# Disable

(GEWBED). When GEWBED equals 1, the processor does

not attempt to enforce any write ordering internally or

externally (the EWBE# signal is ignored). This is the

maximum performance setting.

■ EFER[2] is defined as the Speculative EWBE# Disable

(SEWBED). SEWBED only affects the processor when

GEWBED equals 0. If GEWBED equals 0 and SEWBED

equals 1, the processor enforces strong ordering for all

internal write cycles with the exception of write cycles

addressed to a range of memory defined as uncacheable

(UC) or write-combining (WC) by the MTRRs. In addition,

the processor samples the EWBE# signal. If EWBE# is

sampled negated, the processor delays the commitment of

write cycles to processor cache lines in the modified state or

exclusive state until EWBE# is sampled asserted.

This setting provides performance comparable to, but

slightly less than, the performance obtained when

GEWBED equals 1 because some degree of write ordering is

maintained.

■ If GEWBED equals 0 and SEWBED equals 0, the processor

enforces strong ordering for all internal and external write

cycles. In this setting, the processor assumes, or speculates,

that strong order must be maintained between writes to the

merge buffer and writes that hit the processor’s caches.

Once the merge buffer is written out to the processor’s bus,

the EWBE# signal is sampled. If EWBE# is sampled negated,

the processor delays the commitment of write cycles to

processor cache lines in the modified state or exclusive state

until EWBE# is sampled asserted.

This setting is the default after RESET and provides the

lowest performance of the three settings because full write

ordering is maintained.

230

Write Merge Buffer

Chapter 10

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 42 summarizes the three settings of the EWBEC field for

the EFER register, along with the effect of write ordering and

performance. For more information on the EFER register, see

“Extended Feature Enable Register (EFER)” on page 47.

Table 42. EWBEC Settings and Performance

EFER[3]

EFER[2]

Write

Performance

(GEWBED) (SEWBED) Ordering

1

0

0 or 1

None

Best

1

0

All except UC/WC

All

Close-to-Best

Slowest

10.2

Memory Type Range Registers

The AMD-K6-2E+ processor provides two variable-range

Memory Type Range Registers (MTRRs)—MTRR0 and

MTRR1—that each specify a range of memory. Each range can

be defined as one of the following memory types:

■ Uncacheable (UC) Memory—Memory read cycles are

sourced directly from the specified memory address and the

processor does not allocate a cache line. Memory write

cycles are targeted at the specified memory address and a

write allocation does not occur.

■ Write-Combining (WC) Memory—Memory read cycles are

sourced directly from the specified memory address and the

processor does not allocate a cache line. The processor

conditionally combines data from multiple noncacheable

write cycles that are addressed within this range into a

merge buffer. Merging multiple write cycles into a single

write cycle reduces processor bus utilization and processor

stalls, thereby increasing the overall system performance.

This memory type is applicable for linear video frame

buffers.

Chapter 10

Write Merge Buffer

231

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

UC/WC Cacheability

Control Register

(UWCCR)

The MTRRs are accessed by addressing the 64-bit MSR known

as the UC/WC Cacheability Control Register (UWCCR). The

MSR address of the UWCCR is C000_0085h. Following reset, all

bits in the UWCCR register are set to 0. MTRR0 (lower 32 bits

of the UWCCR register) defines the size and memory type of

range 0 and MTRR1 (upper 32 bits) defines the size and

memory type of range 1 (see Figure 87).

.

Symbol Description

Bits

32

Symbol Description

Bits

0

UC1

Uncacheable Memory Type

UC0

Uncacheable Memory Type

WC1

Write-Combining Memory Type 33

WC0

Write-Combining Memory Type

1

63

49 48

34 33 32 31

17 16

2

1

0

W

C

1

U

C

1

W

C

0

U

C

0

Physical Base Address 1

Physical Address Mask 1

Physical Base Address 0

Physical Address Mask 0

MTRR1

MTRR0

Figure 87. UC/WC Cacheability Control Register (UWCCR)

Physical Base Address n (n=0, 1). This address is the 15 most-

significant bits of the physical base address of the memory

range. The least-significant 17 bits of the base address are not

needed because the base address is by definition always aligned

on a 128-Kbyte boundary.

Physical Address Mask n (n=0, 1). This value is the 15 most-

significant bits of a physical address mask that is used to define

the size of the memory range. This mask is logically ANDed

with both the physical base address field of the UWCCR

register and the physical address generated by the processor. If

the results of the two AND operations are equal, then the

generated physical address is considered within the range.

That is, if:

Mask & Physical Base Address = Mask & Physical Address Generated

then, the physical address generated by the processor is in the

range.

232

Write Merge Buffer

Chapter 10

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

WCn (n=0, 1). When set to 1, this memory range is defined as

write combinable (see Table 43). Write-combinable memory is

uncacheable.

UCn (n=0, 1). When set to 1, this memory range is defined as

uncacheable (see Table 43).

Table 43. WC/UC Memory Type

WCn

0

UCn

Memory Type

0

1

No effect on cacheability or write combining

Write-combining memory range (uncacheable)

Uncacheable memory range

1

0 or 1

10.3

Memory-Range Restrictions

The following rules regarding the address alignment and size of

each range must be adhered to when programming the physical

base address and physical address mask fields of the UWCCR

register:

■ The minimum size of each range is 128 Kbytes.

■ The physical base address must be aligned on a 128-Kbyte

boundary.

■ The physical base address must be range-size aligned. For

example, if the size of the range is 1 Mbyte, then the

physical base address must be aligned on a 1-Mbyte

boundary.

■ All bits set to 1 in the physical address mask must be

contiguous. Likewise, all bits set to 0 in the physical address

mask must be contiguous. For example:

111_1111_1100_0000b is a valid physical address mask.

111_1111_1101_0000b is invalid.

Chapter 10

Write Merge Buffer

233

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 44 lists the valid physical address masks and the resulting

range sizes that can be programmed in the UWCCR register.

Table 44. Valid Masks and Range Sizes for UWCCR Register

Masks

Size

111_1111_1111_1111b

111_1111_1111_1110b

111_1111_1111_1100b

111_1111_1111_1000b

111_1111_1111_0000b

111_1111_1110_0000b

111_1111_1100_0000b

111_1111_1000_0000b

111_1111_0000_0000b

111_1110_0000_0000b

111_1100_0000_0000b

111_1000_0000_0000b

111_0000_0000_0000b

110_0000_0000_0000b

100_0000_0000_0000b

000_0000_0000_0000b

128 Kbytes

256 Kbytes

512 Kbytes

1 Mbyte

2 Mbytes

4 Mbytes

8 Mbytes

16 Mbytes

32 Mbytes

64 Mbytes

128 Mbytes

256 Mbytes

512 Mbytes

1 Gbyte

2 Gbytes

4 Gbytes

234

Write Merge Buffer

Chapter 10

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

10.4

Examples

Suppose that the range of memory from 16 Mbytes to 32 Mbytes

is uncacheable, and the 8-Mbyte range of memory on top of 1

Gbyte is write-combinable. Range 0 is defined as the

uncacheable range, and range 1 is defined as the write-

combining range.

■ Extracting the 15 most-significant bits of the 32-bit physical

base address that corresponds to 16 Mbytes (0100_0000h)

yields

a

physical

base

address

0

field

of

000_0000_1000_0000b. Because the uncacheable range size

is 16 Mbytes, the physical mask value 0 field is

111_1111_1000_0000b, according to Table 44 on page 234.

Bit 1 of the UWCCR register (WC0) is set to 0 and bit 0 of the

UWCCR register is set to 1 (UC0).

■ Extracting the 15 most-significant bits of the 32-bit physical

base address that corresponds to 1 Gbyte (4000_0000h)

yields

a

physical

base

address

1

field

of

010_0000_0000_0000b. Because the write-combining range

size is 8 Mbytes, the physical mask value 1 field is

111_1111_1100_0000b, according to Table 44 on page 234.

Bit 33 of the UWCCR register (WC1) is set to 1 and bit 32 of

the UWCCR register is set to 0 (UC1).

Chapter 10

Write Merge Buffer

235

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

236

Write Merge Buffer

Chapter 10

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

11

Floating-Point and Multimedia Execution Units

11.1

Floating-Point Execution Unit

The AMD-K6-2E+ processor contains an IEEE 754-compatible

and 854-compatible floating-point execution unit designed to

accelerate the performance of software that utilizes the x86

floating-point instruction set.

Floating-point software is typically written to manipulate

numbers that are very large or very small, that require a high

degree of precision, or that result from complex mathematical

operations such as transcendentals. Applications that take

advantage of floating-point operations include geometric

calculations for graphics acceleration, scientific, statistical, and

engineering applications, and business applications that use

large amounts of high-precision data.

The high-performance floating-point execution unit contains an

adder unit, a multiplier unit, and a divide/square root unit.

These low-latency units can execute floating-point instructions

in as few as two processor clocks. To increase performance, the

processor is designed to simultaneously decode most

floating-point instructions with most short-decodeable

instructions.

See “Software Environment” on page 27 for a description of the

floating-point data types, registers, and instructions.

Handling

Floating-Point

Exceptions

The AMD-K6-2E+ processor provides the following two types of

exception handling for floating-point exceptions:

■ If the numeric error (NE) bit in CR0 is set to 1, the processor

invokes the interrupt 10h handler. In this manner, the

floating-point exception is completely handled by software.

■ If the NE bit in CR0 is set to 0, the processor requires

external logic to generate an interrupt on the INTR signal in

order to handle the exception.

Chapter 11

Floating-Point and Multimedia Execution Units

237

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

External Logic

Support of

Floating-Point

Exceptions

The processor provides the FERR# (Floating-Point Error) and

IGNNE# (Ignore Numeric Error) signals to allow the external

logic to generate the interrupt in a manner consistent with

IBM-compatible PC/AT systems. The assertion of FERR#

indicates the occurrence of an unmasked floating-point

exception resulting from the execution of a floating-point

instruction. IGNNE# is used by the external hardware to control

the effect of an unmasked floating-point exception. Under

certain circumstances, if IGNNE# is sampled asserted, the

processor ignores the floating-point exception.

Figure 88 on page 239 illustrates an implementation of external

logic for supporting floating-point exceptions. The following

example explains the operation of the external logic in Figure

88:

1. As the result of a floating-point exception, the processor

asserts FERR#.

2. The assertion of FERR# and the sampling of IGNNE#

negated indicates the processor has stopped instruction

execution and is waiting for an interrupt.

3. The assertion of FERR# leads to the assertion of INTR by

the interrupt controller.

4. The processor acknowledges the interrupt and jumps to the

corresponding interrupt service routine in which an I/O

write cycle to address port F0h leads to the assertion of

IGNNE#.

5. When IGNNE# is sampled asserted, the processor ignores

the floating-point exception and continues instruction

execution.

6. When the processor negates FERR#, the external logic

negates IGNNE#.

See “FERR# (Floating-Point Error)” on page 111 and “IGNNE#

(Ignore Numeric Exception)” on page 116 for more details.

238

Floating-Point and Multimedia Execution Units

Chapter 11

Preliminary Information

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

I/O Address

Port F0h

AMD-K6-2E+

Processor

IGNNE#

Flip-Flop

CLOCK

Q

RESET

“1”

DATA

CLEAR

FERR#

Interrupt

Controller

FERR#

Flip-Flop

CLOCK

Q

IRQ13

DATA

CLEAR

INTR

IGNNE#

Figure 88. External Logic for Supporting Floating-Point Exceptions

11.2

Multimedia and 3DNow!™ Execution Units

The multimedia and 3DNow! execution units of the

AMD-K6-2E+ processor are designed to accelerate the

performance of software written using the industry-standard

MMX instructions and the new 3DNow! instructions.

Applications that can take advantage of the MMX and 3DNow!

instructions include graphics, video and audio compression and

decompression, speech recognition, and telephony

applications.

3DNow! technology enables fast frame rates on high-resolution

3D-rendered scenes, realistic physical modeling of real-world

environments, sharp and detailed 3D imaging, smooth video

playback, and theater-quality audio.

The AMD-K6-2E+ processor supports five new digital signal

processing (DSP) instructions, developed to enhance the

performance of communications applications, including soft

xDSL modems, MP3 recording, and Dolby Digital and Surround

Sound processing.

®

For more information on MMX instructions, see the AMD-K6

Processor Multimedia Technology Manual, order# 20726. For

Chapter 11

Floating-Point and Multimedia Execution Units

239

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

more information on 3DNow! instructions, see the 3DNow!™

Technology Manual, order# 21928. For more information on the

3DNow! technology DSP extensions, see the AMD Extensions to

the 3DNow!™ and MMX™ Instructions Sets Manual, order#

22466.

The multimedia execution unit can execute MMX instructions

in a single processor clock. All MMX and 3DNow! arithmetic

instructions are pipelined for higher performance. To increase

performance, the processor is designed to simultaneously

decode all MMX and 3DNow! instructions with most other

instructions.

11.3

Floating-Point and MMX™/3DNow!™ Instruction Compatibility

Registers

The eight 64-bit MMX registers (which are also utilized by

3DNow! instructions) are mapped on the floating-point stack.

This enables backward compatibility with all existing software.

For example, the register saving event that is performed by

operating systems during task switching requires no changes to

the operating system. The same support provided in an

operating system’s interrupt 7 handler (Device Not Available)

for saving and restoring the floating-point registers also

supports saving and restoring the MMX registers.

Exceptions

There are no new exceptions defined for supporting the MMX

and 3DNow! instructions. All exceptions that occur while

decoding or executing an MMX or 3DNow! instruction are

handled in existing exception handlers without modification.

FERR# and IGNNE#

MMX instructions and 3DNow! instructions do not generate

floating-point exceptions. However, if an unmasked

floating-point exception is pending, the processor asserts

FERR# at the instruction boundary of the next floating-point

instruction, MMX instruction, 3DNow! instruction or WAIT

instruction.

The sampling of IGNNE# asserted only affects processor

operation during the execution of an error-sensitive

floating-point instruction, MMX instruction, 3DNow!

instruction or WAIT instruction when the NE bit in CR0 is set

to 0.

240

Floating-Point and Multimedia Execution Units

Chapter 11

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

12

System Management Mode (SMM)

SMM is an alternate operating mode entered by way of a system

management interrupt (SMI#) and handled by an interrupt

service routine. SMM is designed for system control activities

such as power management. These activities appear

transparent to conventional operating systems like DOS and

Windows. SMM is targeted for use by the Basic Input Output

System (BIOS), specialized low-level device drivers, and the

operating system. The code and data for SMM are stored in the

SMM memory area, which is isolated from main memory.

The processor enters SMM by the assertion of the SMI#

interrupt and the processor’s acknowledgment by the assertion

of SMIACT#. At this point the processor saves its state into the

SMM memory state-save area and jumps to the SMM service

routine. The processor returns from SMM when it executes the

resume (RSM) instruction from within the SMM service

routine. Subsequently, the processor restores its state from the

SMM save area, negates SMIACT#, and resumes execution with

the instruction following the point where it entered SMM.

The following sections summarize the SMM state-save area,

entry into and exit from SMM, exceptions and interrupts in

SMM, memory allocation and addressing in SMM, and the SMI#

and SMIACT# signals.

12.1

SMM Operating Mode and Default Register Values

The software environment within SMM has the following

characteristics:

■ Addressing and operation in real mode

■ 4-Gbyte segment limits

■ Default 16-bit operand, address, and stack sizes, although

instruction prefixes can override these defaults

■ Control transfers that do not override the default operand

size truncate the EIP to 16 bits

■ Far jumps or calls cannot transfer control to a segment with

a base address requiring more than 20 bits, as in real mode

segment-base addressing

Chapter 12

System Management Mode (SMM)

241

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ A20M# is masked

■ Interrupt vectors use the real-mode interrupt vector table

■ The IF flag in EFLAGS is cleared (INTR not recognized)

■ The TF flag in EFLAGS is cleared

■ The NMI and INIT interrupts are disabled

■ Debug register DR7 is cleared (debug traps disabled)

Figure 89 shows the default map of the SMM memory area. It

consists of a 64-Kbyte area, between 0003_0000h and

0003_FFFFh, of which the top 32 Kbytes (0003_8000h to

0003_FFFFh) must be populated with RAM. The default

code-segment (CS) base address for the area—called the SMM

base address — is at 0003_0000h. The top 512 bytes

(0003_FE00h to 0003_FFFFh) contain a fill-down SMM

state-save area. The default entry point for the SMM service

routine is 0003_8000h.

Fill Down

0003_FFFFh

0003_FE00h

SMM

State-Save

Area

32-Kbyte

Minimum RAM

SMM

Service Routine

Service Routine Entry Point

0003_8000h

0003_0000h

SMM Base Address (CS)

Figure 89. SMM Memory

242

System Management Mode (SMM)

Chapter 12

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 45 shows the initial state of registers when entering SMM.

Table 45. Initial State of Registers in SMM

Registers

SMM Initial State

unmodified

General Purpose Registers

EFLAGS

0000_0002h

PE, EM, TS, and PG are cleared (bits 0, 2, 3, and

31). The other bits are unmodified.

CR0

DR7

0000_0400h

unmodified

0000_8000h

0003_0000h

0000_0000h

GDTR, LDTR, IDTR, TSSR, DR6

EIP

CS

DS, ES, FS, GS, SS

12.2

SMM State-Save Area

When the processor acknowledges an SMI# interrupt by

asserting SMIACT#, it saves its state in a 512-byte SMM

state-save area shown in Table 46. The save begins at the top of

the SMM memory area (SMM base address + FFFFh) and fills

down to SMM base address + FE00h.

Table 46 shows the offsets in the SMM state-save area relative

to the SMM base address. The SMM service routine can alter

any of the read/write values in the state-save area.

Table 46. SMM State-Save Area Map

Address Offset

FFFCh

Contents Saved

CR0

CR3

EFLAGS

EIP

FFF8h

FFF4h

FFF0h

FFECh

EDI

FFE8h

ESI

FFE4h

EBP

ESP

FFE0h

FFDCh

FFD8h

FFD4h

FFD0h

EBX

EDX

ECX

EAX

Chapter 12

System Management Mode (SMM)

243

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 46. SMM State-Save Area Map (continued)

Address Offset

FFCCh

Contents Saved

DR6

FFC8h

DR7

FFC4h

TR

FFC0h

LDTR Base

FFBCh

GS

FFB8h

FS

FFB4h

DS

FFB0h

SS

FFACh

CS

ES

FFA8h

FFA4h

I/O Trap Doubleword

FFA0h

FF9Ch

FF98h

FF94h

FF90h

FF8Ch

FF88h

FF84h

FF80h

FF7Ch

FF78h

FF74h

FF70h

FF6Ch

FF68h

FF64h

FF60h

FF5Ch

FF58h

FF54h

FF50h

FF4Ch

FF48h

FF44h

FF40h

No data dump at this address

I/O Trap EIP¹

No data dump at this address

IDT Base

IDT Limit

GDT Base

GDT Limit

TSS Attr

TSS Base

TSS Limit

No data dump at this address

LDT High

LDT Low

GS Attr

GS Base

GS Limit

FS Attr

FS Base

FS Limit

DS Attr

DS Base

DS Limit

SS Attr

SS Base

244

System Management Mode (SMM)

Chapter 12

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 46. SMM State-Save Area Map (continued)

Address Offset

FF3Ch

Contents Saved

SS Limit

FF38h

CS Attr

FF34h

CS Base

FF30h

CS Limit

ES Attr

FF2Ch

FF28h

ES Base

FF24h

ES Limit

FF20h

FF1Ch

FF18h

FF14h

FF10h

FF0Ch

No data dump at this address

CR2

CR4

I/O Restart ESI¹

I/O Restart ECX¹

FF08h

I/O Restart EDI¹

HALT Restart Slot

I/O Trap Restart Slot

SMM RevID

FF04h

FF02h

FF00h

FEFCh

FEF8h

SMM Base

FEF7h–FE00h

No data dump at this address

Notes:

1. Only contains information if SMI# is asserted during a valid I/O bus cycle.

12.3

SMM Revision Identifier

The SMM revision identifier at offset FEFCh in the SMM

state-save area specifies the version of SMM and the extensions

that are available on the processor. The SMM revision identifier

fields are as follows:

■ Bits 31–18—Reserved

■ Bit 17—SMM base address relocation (1 = enabled)

■ Bit 16—I/O trap restart (1 = enabled)

■ Bits 15–0—SMM revision level for the AMD-K6-2E+ proces-

sor= 0002h

Chapter 12

System Management Mode (SMM)

245

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 47 shows the format of the SMM Revision Identifier.

Table 47. SMM Revision Identifier

31–18

Reserved

0

17

16

15–0

SMM Revision Level

0002h

SMM Base Relocation

1

I/O Trap Extension

1

12.4

SMM Base Address

During RESET, the processor sets the base address of the

code-segment (CS) for the SMM memory area—the SMM base

address—to its default, 0003_0000h. The SMM base address at

offset FEF8h in the SMM state-save area can be changed by the

SMM service routine to any address that is aligned to a

32-Kbyte boundary. (Locations not aligned to a 32-Kbyte

boundary cause the processor to enter the Shutdown state when

executing the RSM instruction.)

In some operating environments it may be desirable to relocate

the 64-Kbyte SMM memory area to a high memory area in order

to provide more low memory for legacy software. During system

initialization, the base of the 64-Kbyte SMM memory area is

relocated by the BIOS. To relocate the SMM base address, the

system enters the SMM handler at the default address. This

handler changes the SMM base address location in the SMM

state-save area, copies the SMM handler to the new location,

and exits SMM.

The next time SMM is entered, the processor saves its state at

the new base address. This new address is used for every SMM

entry until the SMM base address in the SMM state-save area is

changed or a hardware reset occurs.

12.5

Halt Restart Slot

During entry into SMM, the halt restart slot at offset FF02h in

the SMM state-save area indicates if SMM was entered from the

Halt state. Before returning from SMM, the halt restart slot

(offset FF02h) can be written to by the SMM service routine to

specify whether the return from SMM takes the processor back

to the Halt state or to the next instruction after the HLT

instruction.

246

System Management Mode (SMM)

Chapter 12

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Upon entry into SMM, the halt restart slot is defined as follows:

■ Bits 15–1—Reserved

■ Bit 0—Point of entry to SMM:

1 = entered from Halt state

0 = not entered from Halt state

After entry into the SMI handler and before returning from

SMM, the halt restart slot can be written using the following

definition:

■ Bits 15–1—Reserved

■ Bit 0—Point of return when exiting from SMM:

1 = return to Halt state

0 = return to next instruction after the HLT instruction

If the return from SMM takes the processor back to the Halt

state, the HLT instruction is not re-executed, but the Halt

special bus cycle is driven on the bus after the return.

12.6

I/O Trap Doubleword

If the assertion of SMI# is recognized during the execution of an

I/O instruction, the I/O trap doubleword at offset FFA4h in the

SMM state-save area contains information about the

instruction. The fields of the I/O trap doubleword are

configured as follows:

■ Bits 31–16—I/O port address

■ Bits 15–4—Reserved

■ Bit 3—REP (repeat) string operation

(1 = REP string, 0 = not a REP string)

■ Bit 2—I/O string operation

(1 = I/O string, 0 = not an I/O string)

■ Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)

■ Bit 0—Input or output instruction (1 = INx, 0 = OUTx)

Chapter 12

System Management Mode (SMM)

247

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 48 shows the format of the I/O trap doubleword.

Table 48. I/O Trap Doubleword Configuration

31—16

15—4

3

2

1

0

I/O Port

Address

REP String

Operation

I/O String

Operation

Valid I/O

Instruction

Input or

Output

Reserved

The I/O trap doubleword is related to the I/O trap restart slot

(see “I/O Trap Restart Slot”). If bit 1 of the I/O trap doubleword

is set by the processor, it means that SMI# was asserted during

the execution of an I/O instruction. The SMI handler tests bit 1

to see if there is a valid I/O instruction trapped. If the I/O

instruction is valid, the SMI handler is required to ensure the

I/O trap restart slot is set properly. The I/O trap restart slot

informs the processor whether it should re-execute the I/O

instruction after the RSM or execute the instruction following

the trapped I/O instruction.

Note: If SMI# is sampled asserted during an I/O bus cycle a

minimum of three clock edges before BRDY# is sampled

asserted, the associated I/O instruction is guaranteed to be

trapped by the SMI handler.

12.7

I/O Trap Restart Slot

The I/O trap restart slot at offset FF00h in the SMM state-save

area specifies whether the trapped I/O instruction should be

re-executed on return from SMM. This slot in the state-save area

is called the I/O instruction restart function. Re-executing a

trapped I/O instruction is useful, for example, if an I/O write

occurs to a disk that is powered down. The system logic

monitoring such an access can assert SMI#. Then the SMM

service routine would query the system logic, detect a failed I/O

write, take action to power-up the I/O device, enable the I/O

trap restart slot feature, and return from SMM.

The fields of the I/O trap restart slot are defined as follows:

■ Bits 31–16—Reserved

■ Bits 15–0—I/O instruction restart on return from SMM:

0000h = execute the next instruction after the trapped

I/O instruction

00FFh = re-execute the trapped I/O instruction

248

System Management Mode (SMM)

Chapter 12

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 49 shows the format of the I/O trap restart slot.

Table 49. I/O Trap Restart Slot

31–16

15–0

Reserved

I/O Instruction restart on return from SMM:

0000h = execute the next instruction after the trapped I/O

00FFh = re-execute the trapped I/O instruction

The processor initializes the I/O trap restart slot to 0000h upon

entry into SMM. If SMM was entered due to a trapped I/O

instruction, the processor indicates the validity of the I/O

instruction by setting or clearing bit 1 of the I/O trap

doubleword at offset FFA4h in the SMM state-save area. The

SMM service routine should test bit 1 of the I/O trap

doubleword to determine if a valid I/O instruction was being

executed when entering SMM and before writing the I/O trap

restart slot. If the I/O instruction is valid, the SMM service

routine can safely rewrite the I/O trap restart slot with the value

00FFh, which causes the processor to re-execute the trapped I/O

instruction when the RSM instruction is executed. If the I/O

instruction is invalid, writing the I/O trap restart slot has

undefined results.

If a second SMI# is asserted and a valid I/O instruction was

trapped by the first SMM handler, the processor services the

second SMI# prior to re-executing the trapped I/O instruction.

The second entry into SMM never has bit 1 of the I/O trap

doubleword set, and the second SMM service routine must not

rewrite the I/O trap restart slot.

During a simultaneous SMI# I/O instruction trap and debug

breakpoint trap, the AMD-K6-2E+ processor first responds to

the SMI# and postpones recognizing the debug exception until

after returning from SMM via the RSM instruction. If the debug

registers DR3–DR0 are used while in SMM, they must be saved

and restored by the SMM handler. The processor automatically

saves and restores DR7–DR6. If the I/O trap restart slot in the

SMM state-save area contains the value 00FFh when the RSM

instruction is executed, the debug trap does not occur until

after the I/O instruction is re-executed.

Chapter 12

System Management Mode (SMM)

249

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

12.8

Exceptions, Interrupts, and Debug in SMM

During an SMI# I/O trap, the exception/interrupt priority of the

AMD-K6-2E+ processor changes from its normal priority. The

normal priority places the debug traps at a priority higher than

the sampling of the FLUSH# or SMI# signals. However, during

an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals

takes precedence over debug traps.

The processor recognizes the assertion of NMI within SMM

immediately after the completion of an IRET instruction. Once

NMI is recognized within SMM, NMI recognition remains

enabled until SMM is exited, at which point NMI masking is

restored to the state it was in before entering SMM.

250

System Management Mode (SMM)

Chapter 12

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

13

Test and Debug

The AMD-K6-2E+ processor implements various test and debug

modes to enable the functional and manufacturing testing of

systems and boards that use the processor. In addition, the

debug features of the processor allow designers to debug the

instruction execution of software components. This chapter

describes the following test and debug features:

■ Built-In Self-Test (BIST)—The BIST, which is invoked after

the falling transition of RESET, runs internal tests that

exercise most on-chip RAM structures.

■ Three-State Test Mode—A test mode that causes the

processor to float its output and bidirectional pins.

■ Boundary-Scan Test Access Port (TAP)—The Joint Test

Action Group (JTAG) test access function defined by the

IEEE Standard Test Access Port and Boundary-Scan

Architecture (IEEE 1149.1-1990) specification.

■ Cache Inhibit—A feature that disables the processor’s

internal L1 and L2 caches.

■ Level-2 Cache Array Access Register (L2AAR)—The

AMD-K6-2E+ processor provides the L2AAR that allows for

direct access to the L2 cache and L2 tag arrays.

■ Debug Support—Consists of all x86-compatible software

debug features, including the debug extensions.

13.1

Built-In Self-Test (BIST)

Following the falling transition of RESET, the processor

unconditionally runs its built-in self test (BIST). The internal

resources tested during BIST include the following:

■ L1 instruction and data caches

■ L2 cache

■ Instruction and Data Translation Lookaside Buffers (TLBs)

Chapter 13

Test and Debug

251

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The contents of the EAX general-purpose register after the

completion of reset indicate if the BIST was successful.

■ If EAX contains 0000_0000h, then BIST was successful.

■ If EAX is non-zero, the BIST failed.

Following the completion of the BIST, the processor jumps to

address FFFF_FFF0h to start instruction execution, regardless

of the outcome of the BIST.

The BIST takes approximately 5,000,000 processor clocks to

complete.

13.2

Three-State Test Mode

The Three-State Test mode causes the processor to float its

output and bidirectional pins, which is useful for board-level

manufacturing testing. In this mode, the processor is

electrically isolated from other components on a system board,

allowing automated test equipment (ATE) to test components

that drive the same signals as those the processor floats.

If the FLUSH# signal is sampled Low during the falling

transition of RESET, the processor enters the Three-State Test

mode. (See “FLUSH# (Cache Flush)” on page 112 for the

specific sampling requirements.) The signals floated in the

Three-State Test mode are as follows:

■ A[31:3]

■ ADS#

■ D/C#

■ M/IO#

■ PCD

■ D[63:0]

■ DP[7:0]

■ FERR#

■ HIT#

■ ADSC#

■ AP

■ PCHK#

■ PWT

■ APCHK#

■ BE[7:0]#

■ BREQ

■ CACHE#

■ SCYC

■ SMIACT#

■ VID[4:0]

■ W/R#

■ HITM#

■ HLDA

■ LOCK#

The VCC2DET, VCC2H/L#, and TDO signals are the only

outputs not floated in the Three-State Test mode.

■ VCC2DET and VCC2H/L# must remain Low to ensure the

system continues to supply the specified processor core

voltage to the V

pins.

CC2

252

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ TDO is never floated because the Boundary-Scan Test

Access Port must remain enabled at all times, including

during the Three-State Test mode.

The Three-State Test mode is exited when the processor

samples RESET asserted.

13.3

Boundary-Scan Test Access Port (TAP)

The boundary-scan Test Access Port (TAP) is an IEEE standard

that defines synchronous scanning test methods for complex

logic circuits, such as boards containing a processor. The

AMD-K6-2E+ processor supports the TAP standard defined in

the IEEE Standard Test Access Port and Boundary-Scan

Architecture (IEEE 1149.1-1990) specification.

Boundary scan testing uses a shift register consisting of the

serial interconnection of boundary-scan cells that correspond to

each I/O buffer of the processor. This non-inverting register

chain, called a Boundary Scan Register (BSR), can be used to

capture the state of every processor pin and to drive every

processor output and bidirectional pin to a known state.

Each BSR of every component on a board that implements the

boundary-scan architecture can be serially interconnected to

enable component interconnect testing.

Test Access Port

The TAP consists of the following:

■ Test Access Port (TAP) Controller—The TAP controller is a

synchronous, finite state machine that uses the TMS and

TDI input signals to control a sequence of test operations.

See “TAP Controller State Machine” on page 260 for a list of

TAP states and their definition.

■ Instruction Register (IR)—The IR contains the instructions

that select the test operation to be performed and the Test

Data Register (TDR) to be selected. See “TAP Registers” on

page 255 for more details on the IR.

■ Test Data Registers (TDR)—The three TDRs are used to

process the test data. Each TDR is selected by an instruction

in the Instruction Register (IR). See “TAP Registers” on

page 255 for a list of these registers and their functions.

Chapter 13

Test and Debug

253

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

TAP Signals

The test signals associated with the TAP controller are as

follows:

■ TCK—The Test Clock for all TAP operations. The rising

edge of TCK is used for sampling TAP signals, and the

falling edge of TCK is used for asserting TAP signals. The

state of the TMS signal sampled on the rising edge of TCK

causes the state transitions of the TAP controller to occur.

TCK can be stopped in the logic 0 or 1 state.

■ TDI—The Test Data Input represents the input to the most

significant bit of all TAP registers, including the IR and all

test data registers. Test data and instructions are serially

shifted by one bit into their respective registers on the rising

edge of TCK.

■ TDO—The Test Data Output represents the output of the

least significant bit of all TAP registers, including the IR and

all test data registers. Test data and instructions are serially

shifted by one bit out of their respective registers on the

falling edge of TCK.

■ TMS—The Test Mode Select input specifies the test

function and sequence of state changes for boundary-scan

testing. If TMS is sampled High for five or more consecutive

clocks, the TAP controller enters its reset state.

■ TRST#—The Test Reset signal is an asynchronous reset that

unconditionally causes the TAP controller to enter its reset

state.

Refer to “Electrical Data” on page 285 and “Signal Switching

Characteristics” on page 295 to obtain the electrical

specifications of the test signals.

254

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

TAP Registers

The AMD-K6-2E+ processor provides an Instruction Register

(IR) and three Test Data Registers (TDR) to support the

boundary-scan architecture. The IR and one of the TDRs—the

Boundary-Scan Register (BSR)—consist of a shift register and

an output register. The shift register is loaded in parallel in the

Capture states. (See “TAP Controller State Machine” on

page 260 for a description of the TAP controller states.) In

addition, the shift register is loaded and shifted serially in the

Shift states. The output register is loaded in parallel from its

corresponding shift register in the Update states.

Instruction Register (IR). The IR is a 5-bit register, without parity,

that determines which instruction to run and which test data

register to select. When the TAP controller enters the

Capture-IR state, the processor loads the following bits into the

IR shift register:

■ 01b—Loaded into the two least significant bits, as specified

by the IEEE 1149.1 standard

■ 000b—Loaded into the three most significant bits

Loading 00001b into the IR shift register during the Capture-IR

state results in loading the SAMPLE/PRELOAD instruction.

For each entry into the Shift-IR state, the IR shift register is

serially shifted by one bit toward the TDO pin. During the shift,

the most significant bit of the IR shift register is loaded from

the TDI pin.

The IR output register is loaded from the IR shift register in the

Update-IR state, and the current instruction is defined by the

IR output register. See “TAP Instructions” on page 259 for a list

and definition of the instructions supported by the

AMD-K6-2E+ processor.

Boundary Scan Register (BSR). The Boundary Scan Register is a Test

Data Register consisting of the interconnection of 152

boundary-scan cells. Each output and bidirectional pin of the

processor requires a two-bit cell, where one bit corresponds to

the pin and the other bit is the output enable for the pin. When

a 0 is shifted into the enable bit of a cell, the corresponding pin

is floated, and when a 1 is shifted into the enable bit, the pin is

driven valid. Each input pin requires a one-bit cell that

corresponds to the pin. The last cell of the BSR is reserved and

does not correspond to any processor pin.

Chapter 13

Test and Debug

255

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The total number of bits that comprise the BSR is 297. Table 50

on page 257 lists the order of these bits, where TDI is the input

to bit 296, and TDO is driven from the output of bit 0. The

entries listed as pin_E (where pin is an output or bidirectional

signal) are the enable bits.

If the BSR is the register selected by the current instruction

and the TAP controller is in the Capture-DR state, the processor

loads the BSR shift register as follows:

■ If the current instruction is SAMPLE/PRELOAD, then the

current state of each input, output, and bidirectional pin is

loaded. A bidirectional pin is treated as an output if its

enable bit equals 1, and it is treated as an input if its enable

bit equals 0.

■ If the current instruction is EXTEST, then the current state

of each input pin is loaded. A bidirectional pin is treated as

an input, regardless of the state of its enable.

While in the Shift-DR state, the BSR shift register is serially

shifted toward the TDO pin. During the shift, bit 280 of the BSR

is loaded from the TDI pin.

The BSR output register is loaded with the contents of the BSR

shift register in the Update-DR state. If the current instruction

is EXTEST, the processor’s output pins, as well as those

bidirectional pins that are enabled as outputs, are driven with

their corresponding values from the BSR output register.

256

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

1

Table 50. Boundary Scan Bit Definitions

Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable

296 A6_E

295 A6

294

263 A28_E

262 A28

230 HIT#

229 A27_E

228 A27

197 AP

164 RSVD

163 RSVD

162 RSVD

131 D40_E

130 D40

196 A20_E

195 A20

VID1_E²

261 ADS_E

129 D59_E

VID1²

293

260 ADS#

259 A17_E

258 A17

227 A4_E

226 A4

194 BREQ_E

193 BREQ

192 A11_E

191 A11

161 RSVD

160 AHOLD

159 INV

128 D59

127 D9_E

126 D9

292 A22_E

291 A22

225 A7_E

224 A7

290 PCHK_E

289 PCHK#

257 A25_E

256 A25

158 CLK

125 D28_E

124 D28

VID2_E²

157

223 A8_E

190 A10_E

VID2²

156

288 A14_E

287 A14

255 PWT_E

254 PWT

253 A12_E

252 A12

222 A8

189 A10

123 D56_E

122 D56

221 A15_E

220 A15

188 APCHK_E

187 APCHK#

186 SMIACT_E

185 SMIACT#

184 RSVD

183 A5_E

182 A5

155 CACHE_E

154 CACHE#

153 MIO_E

152 M/IO#

151 FERR_E

150 FERR#

149 D0_E

148 D0

286 A13_E

285 A13

121 D44_E

120 D44

219 DC_E

218 D/C#

217 A16_E

216 A16

284 A24_E

283 A24

251 A9_E

250 A9

119 D11_E

118 D11

282 RESET

281 A18_E

280 A18

249 A26_E

248 A26

117 DP3_E

116 DP3

215 A19_E

214 A19

247 A30_E

246 A30

181 INTR

115 D39_E

114 D39

279 A21_E

278 A21

213 SCYC_E

212 SCYC

180 NMI

147 D1_E

146 D1

VID0_E²

245

179 INIT

113 DP6_E

VID0²

244

277 PCD_E

276 PCD

211 ADSC_E

210 ADSC#

209 BE6_E

208 BE6

178 HOLD

177 IGNNE#

176 SMI#

175 WB/WT#

174 BF0

145 D61_E

144 D61

112 DP6

111 D8_E

110 D8

243 HITM_E

242 HITM#

241 A20M#

240 FLUSH#

239 A3_E

238 A3

275 BE4_E

274 BE4#

273 BE7_E

272 BE7#

271 A23_E

270 A23

143 D62_E

142 D62

141 DP0_E

140 DP0

139 D21_E

138 D21

109 D32_E

108 D32

107 D36_E

106 D36

105 D51_E

104 D51

207 BE3_E

206 BE3

173 BOFF#

172 NA#

205 HLDA_E

204 HLDA

203 BE1_E

202 BE1#

201 EADS#

200 BE2_E

199 BE2#

198 AP_E

237 A31_E

236 A31

171 BF1

269 LOCK_E

268 LOCK#

267 BE0_E

266 BE0#

265 BE5_E

264 BE5#

170 BRDYC#

169 BRDY#

168 STPCLK#

167 BF2

137 D57_E

136 D57

235 A29_E

234 A29

103 D15_E

102 D15

135 D5_E

134 D5

233 WR_E

232 W/R#

231 HIT_E

101 D37_E

100 D37

99 D41_E

166 KEN#

165 EWBE#

133 D24_E

132 D24

Chapter 13

Test and Debug

257

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

1

Table 50. Boundary Scan Bit Definitions (continued)

Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable

98 D41

81 D49

64 D20_E

63 D20

47 D35

30 D43_E

29 D43

28 D58_E

27 D58

26 D26_E

25 D26

24 D3_E

23 D3

13 D45

97 D52_E

96 D52

80 D17_E

79 D17

46 D10_E

45 D10

12 D60_E

11 D60

62 D13_E

61 D13

95 D14_E

94 D14

78 D19_E

77 D19

44 D53_E

43 D53

10 D22_E

60 DP5_E

59 DP5

9

8

7

6

D22

93 D29_E

92 D29

76 D48_E

75 D48

42 D34_E

41 D34

D63_E

D63

58 D31_E

57 D31

VID4_E²

40

91 D33_E

74 D47_E

DP7_E

VID4²

39

90 D33

73 D47

56 D27_E

55 D27

22 D55_E

21 D55

5

4

3

2

1

DP7

D4_E

D4

89 RSVD

88 D18_E

87 D18

72 D16_E

71 D16

38 D7_E

37 D7

54 D12_E

53 D12

20 D42_E

19 D42

70 DP1_E

69 DP1

36 DP4_E

35 DP4

D2_E

D2

VID3_E²

18

86 D23_E

52 D50_E

VID3²

17

85 D23

68 D46_E

67 D46

51 D50

34 D54_E

33 D54

0

Reserved

84 D25_E

83 D25

50 D38_E

49 D38

16 D6_E

15 D6

66 DP2_E

65 DP2

32 D30_E

31 D30

82 D49_E

48 D35_E

14 D45_E

Notes:

1. TDI is the input to bit 296, and TDO is driven from the output of bit 0. The entries listed as pin_E (where pin is an output or

bidirectional signal) are the enable bits.

2. Supported on low-power versions only.

Device Identification Register (DIR). The DIR is a 32-bit Test Data

Register selected during the execution of the IDCODE

instruction. The fields of the DIR and their values are shown in

Table 51 on page 259 and are defined as follows:

■ Version Code—This 4-bit field is incremented by AMD

manufacturing for each major revision of silicon.

■ Part Number—This 16-bit field identifies the specific

processor model.

■ Manufacturer—This 11-bit field identifies the manufacturer

of the component (AMD).

258

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

■ LSB—The least significant bit (LSB) of the DIR is always set

to 1, as specified by the IEEE 1149.1 standard.

Table 51. Device Identification Register

Version Code

(Bits 31–28)

Part Number

(Bits 27–12)

Manufacturer

(Bits 11–1)

LSB

(Bit 0)

Xh

05D0h

00000000001b

1b

Bypass Register (BR). The BR is a Test Data Register consisting of

a 1-bit shift register that provides the shortest path between

TDI and TDO. When the processor is not involved in a test

operation, the BR can be selected by an instruction to allow the

transfer of test data through the processor without having to

serially scan the test data through the BSR. This functionality

preserves the state of the BSR and significantly reduces test

time.

The BR register is selected by the BYPASS and HIGHZ

instructions as well as by any instructions not supported by the

AMD-K6-2E+ processor.

TAP Instructions

The processor supports the three instructions required by the

IEEE 1149.1 standard—EXTEST, SAMPLE/PRELOAD, and

BYPASS—as well as two additional optional instructions—

IDCODE and HIGHZ.

Table 52 shows the complete set of TAP instructions supported

by the processor along with the 5-bit Instruction Register

encoding and the register selected by each instruction.

Table 52. Supported TAP Instructions

Instruction

Encoding

Register

Description

EXTEST¹

00000b

00001b

BSR

DIR

BR

Sample inputs and drive outputs

Sample inputs and outputs, then load the BSR

Read DIR

SAMPLE / PRELOAD

IDCODE

00010b

HIGHZ

00011b

Float outputs and bidirectional pins

Undefined instruction, execute the BYPASS instruction

BYPASS²

BYPASS³

Notes:

00100b–11110b

BR

11111b

BR

Connect TDI to TDO to bypass the BSR

1. Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal, non-test operation.

2. These instruction encodings are undefined on the AMD-K6-2E+ processor and default to the BYPASS instruction.

3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open during

an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.

Chapter 13

Test and Debug

259

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

EXTEST Instruction. When the EXTEST instruction is executed,

the processor loads the BSR shift register with the current state

of the input and bidirectional pins in the Capture-DR state and

drives the output and bidirectional pins with the corresponding

values from the BSR output register in the Update-DR state.

SAMPLE/PRELOAD Instruction. The SAMPLE/PRELOAD instruction

performs two functions. These functions are as follows:

■ During the Capture-DR state, the processor loads the BSR

shift register with the current state of every input, output,

and bidirectional pin.

■ During the Update-DR state, the BSR output register is

loaded from the BSR shift register in preparation for the

next EXTEST instruction.

The SAMPLE/PRELOAD instruction does not affect the normal

operational state of the processor.

BYPASS Instruction. The BYPASS instruction selects the BR

register, which reduces the boundary-scan length through the

processor from 297 to one (TDI to BR to TDO). The BYPASS

instruction does not affect the normal operational state of the

processor.

IDCODE Instruction. The IDCODE instruction selects the DIR

register, allowing the device identification code to be shifted

out of the processor. This instruction is loaded into the IR when

the TAP controller is reset. The IDCODE instruction does not

affect the normal operational state of the processor.

HIGHZ Instruction. The HIGHZ instruction forces all output and

bidirectional pins to be floated. During this instruction, the BR

is selected and the normal operational state of the processor is

not affected.

TAP Controller State

Machine

The TAP controller state diagram is shown in Figure 90 on page

261. State transitions occur on the rising edge of TCK. The logic

0 or 1 next to the states represents the value of the TMS signal

sampled by the processor on the rising edge of TCK.

260

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Test-Logic-Reset

1

0

1

Run-Test/Idle

0

Select-DR-Scan

Select-IR-Scan

0

Capture-DR

0

Capture-IR

0

1

Shift-DR

Shift-IR

0

1

Exit1-DR

Exit1-IR

0

Pause-DR

Pause-IR

0

1

Exit2-DR

Exit2-IR

0

1

Update-DR

0

Update-IR

1

0

Figure 90. TAP State Diagram

Chapter 13

Test and Debug

261

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The states of the TAP controller are described as follows:

Test-Logic-Reset. This state represents the initial reset state of the

TAP controller and is entered when the processor samples

RESET asserted, when TRST# is asynchronously asserted, and

when TMS is sampled High for five or more consecutive clocks.

In addition, this state can be entered from the Select-IR-Scan

state. The IR is initialized with the IDCODE instruction, and

the processor’s normal operation is not affected in this state.

Capture-DR. During the SAMPLE/PRELOAD instruction, the

processor loads the BSR shift register with the current state of

every input, output, and bidirectional pin. During the EXTEST

instruction, the processor loads the BSR shift register with the

current state of every input and bidirectional pin.

Capture-IR. When the TAP controller enters the Capture-IR state,

the processor loads 01b into the two least significant bits of the

IR shift register and loads 000b into the three most significant

bits of the IR shift register.

Shift-DR. While in the Shift-DR state, the selected TDR shift

register is serially shifted toward the TDO pin. During the shift,

the most significant bit of the TDR is loaded from the TDI pin.

Shift-IR. While in the Shift-IR state, the IR shift register is

serially shifted toward the TDO pin. During the shift, the most

significant bit of the IR is loaded from the TDI pin.

Update-DR. During the SAMPLE/PRELOAD instruction, the BSR

output register is loaded with the contents of the BSR shift

register. During the EXTEST instruction, the output pins, as

well as those bidirectional pins defined as outputs, are driven

with their corresponding values from the BSR output register.

Update-IR. In this state, the IR output register is loaded from the

IR shift register, and the current instruction is defined by the

IR output register.

262

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The following states have no effect on the normal or test

operation of the processor other than as shown in Figure 90 on

page 261:

■ Run-Test/Idle—This state is an idle state between scan

operations.

■ Select-DR-Scan—This is the initial state of the test data

register state transitions.

■ Select-IR-Scan—This is the initial state of the Instruction

Register state transitions.

■ Exit1-DR—This state is entered to terminate the shifting

process and enter the Update-DR state.

■ Exit1-IR—This state is entered to terminate the shifting

process and enter the Update-IR state.

■ Pause-DR—This state is entered to temporarily stop the

shifting process of a Test Data Register.

■ Pause-IR—This state is entered to temporarily stop the

shifting process of the Instruction Register.

■ Exit2-DR—This state is entered in order to either terminate

the shifting process and enter the Update-DR state or to

resume shifting following the exit from the Pause-DR state.

■ Exit2-IR—This state is entered in order to either terminate

the shifting process and enter the Update-IR state or to

resume shifting following the exit from the Pause-IR state.

13.4

Cache Inhibit

The AMD-K6-2E+ processor provides a means for inhibiting the

normal operation of its internal L1 and L2 caches while still

supporting an external cache. This capability allows system

designers to disable the L1 and L2 caches during the testing

and debug of an L3 cache.

If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set

to 0, the processor’s L1 and L2 caches are enabled and operate

as described in “Cache Organization” on page 205. If the Cache

Inhibit bit is set to 1, the L1 and L2 caches are disabled and no

new cache lines are allocated. Even though new allocations do

not occur, valid L1 and L2 cache lines remain valid and are read

by the processor when a requested address hits a cache line. In

addition, the processor continues to support inquire cycles

Chapter 13

Test and Debug

263

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

initiated by the system logic, including the execution of

writeback cycles when a modified cache line is hit.

While the L1 and L2 are inhibited, the processor continues to

drive the PCD output signal appropriately, which system logic

can use to control external L3 caching.

In order to completely disable the L1 and L2 caches so that no

valid lines exist in the cache, the Cache Inhibit bit must be set

to 1 and the cache must be flushed in one of the following ways:

■ Asserting the FLUSH# input signal

■ Executing the WBINVD instruction

■ Executing the INVD instruction (modified cache lines are

not written back to memory)

■ Using the Page Flush/Invalidate Register (PFIR) (see “Page

Flush/Invalidate Register (PFIR)” on page 223)

13.5

L2 Cache and Tag Array Testing

Level-2 Cache Array

Access Register

(L2AAR)

The AMD-K6-2E+ processor provides the Level-2 Cache Array

Access Register (L2AAR) that allows for direct access to the L2

cache and L2 tag arrays. The 128-Kbyte L2 cache in the

AMD-K6-2E+ is organized as shown in Figure 91 on page 265:

■ Four 32-Kbyte ways

■ Each way contains 512sets

■ Each set contains four 64-byte sectors (one sector in each

way)

■ Each sector contains two 32-byte cache lines

■ Each cache line contains four 8-byte octets

■ Each octet contains an upper and lower dword (4 bytes)

Each line within a sector contains its own MESI state bits, and

associated with each sector is a tag and LRU (least recently

used) information.

264

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

64 bytes

Line0/MESI

Line1/MESI

Line0/MESI

Tag/LRU

Line1/MESI

Tag/LRU

Line1/MESI

Tag/LRU

Set 0

Way 0

Way 1

Way 2

Way 3

Set 511

Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor

Figure 92 shows the L2 cache sector and line organization. If bit

5 of the address of a cache line equals 1, then this cache line is

stored in Line 1 of a sector. Similarly, if bit 5 of the address of a

cache line equals 0, then this cache line is stored in Line 0 of a

sector.

Octet 0

Octet 1

Octet 2

Octet 3

Upper Dword

Lower Dword

Upper Dword

Lower Dword

Line 1

Line 0

Sector

Figure 92. L2 Cache Sector and Line Organization

The L2AAR register is MSR C000_0089h. The operation that is

performed on the L2 cache is a function of the instruction

executed—RDMSR or WRMSR—and the contents of the EDX

register. The EDX register specifies the location of the access,

and whether the access is to the L2 cache data or tags (refer to

Figure 93 on page 266). Bit 20 of EDX (T/D) determines

whether the access is to the L2 cache data or tag. Table 53 on

Chapter 13

Test and Debug

265

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

page 266 describes the operation that is performed based on

the instruction and the T/D bit.

Symbol Description

Bit

T/D

Way

Selects Tag (1) or Data (0) access

Selects desired cache way

20

17-16

31

21 20 19 18

6

5

4

3 2

1

0

17 16 15 14

Way

D

w

L

i

n

e

T

/

D

Octet

Set

o

r

d

Reserved

Symbol Description

Bit

14-6

5

Set

Selects the desired cache set

Line

Octet

Selects Line1 (1) or Line0 (0)

Selects one of four octets

4-3

Dword Selects upper (1) or lower (0) dword

2

Figure 93. L2 Tag or Data Location for the AMD-K6™-2E+ Processor—EDX

Table 53. Tag versus Data Selector

T/D

(EDX[20])

Instruction

RDMSR

Operation

Read dword from L2 data array into EAX. Dword location

is specified by EDX.

0

Read tag, line state and LRU information from L2 tag array

into EAX. Location of tag is specified by EDX.

RDMSR

1

0

1

Write dword to the L2 data array using data in EAX. Dword

location is specified by EDX.

WRMSR

Write tag, line state and LRU information into L2 tag array

from EAX. Location of tag is specified by EDX.

When the L2AAR is read or written, EDX is left unchanged.

This facilitates multiple accesses when testing the entire

cache/tag array.

L2 Cache Data Reads

If the L2 cache data is read (as opposed to reading the tag

information), the result (dword) is placed in EAX in the format

266

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

as illustrated in Figure 94. Similarly, if the L2 cache data is

written, the write data is taken from EAX.

31

0

Data

Figure 94. L2 Data - EAX

L2 Tag Reads

If the L2 tag is read (as opposed to reading the cache data), the

result is placed in EAX in the format as illustrated in Figure 95

on page 267. Similarly, if the L2 tag is written, the write data is

taken from EAX. When accessing the L2 tag, the Line, Octet,

and Dword fields of the EDX register are ignored.

.

31

14 13 12 11 10

9

8

7

0

C

M

D

Line1ST Line0ST

Tag

LRU

Reserved

Symbol Description

Bit

Tag

Tag data read or written

31-14

Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10

Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8

LRU

Two bits of LRU for each way

7-0

Figure 95. L2 Tag Information for the AMD-K6™-2E+ Processor—EAX

LRU (Least Recently Used). For the 4-way set associative L2 cache,

each way has a 2-bit LRU field for each sector. Values for the

LRU field are 00b, 01b, 10b, and 11b, where 00b indicates that

the sector is “most recently used,” and 11b indicates that the

sector is “least recently used” (see Figure 96 on page 268).

EAX[7:6] indicate LRU information for Way 0, EAX[5:4] for

Way 1, EAX[3:2] for Way 2, and EAX[1:0] for Way 3.

Chapter 13

Test and Debug

267

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

7

6

5

4

3

2

1

0

Way 0

Way 1

Way 2

Way 3

LRU Values

00b Most Recently Used

01b Used More Recent Than 10b, But Less Recent Than 00b

10b Used More Recent Than 11b, But Less Recent Than 01b

11b Least Recently Used

Figure 96. LRU Byte

13.6

Debug

The AMD-K6-2E+ processor implements the standard x86

debug functions, registers, and exceptions. In addition, the

processor supports the I/O breakpoint debug extension. The

debug feature assists programmers and system designers

during software execution tracing by generating exceptions

when one or more events occur during processor execution. The

exception handler, or debugger, can be written to perform

various tasks, such as displaying the conditions that caused the

breakpoint to occur, displaying and modifying register or

memory contents, or single-stepping through program

execution.

The following sections describe the debug registers and the

various types of breakpoints and exceptions that the processor

supports.

268

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Debug Registers

Figures 97 through 100 show the 32-bit debug registers

supported by the processor.

Symbol

LEN 3

R/W 3

LEN 2

R/W 2

LEN 1

R/W 1

LEN 0

R/W 0

Description

Length of Breakpoint #3

Bits

31–30

Type of Transaction(s) to Trap 29–28

Length of Breakpoint #2 27–26

Type of Transaction(s) to Trap 25–24

Length of Breakpoint #1 23–22

Type of Transaction(s) to Trap 21–20

Length of Breakpoint #0 19–18

Type of Transaction(s) to Trap 17–16

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

G

D

G

E

L

E

G

3

L

3

G

2

L

2

G

1

L

1

G

0

L

0

LEN

3

R/W LEN R/W

LEN

1

R/W LEN

R/W

0

3

2

1

0

Reserved

Symbol

GD

GE

LE

Description

General Detect Enabled

Global Exact Breakpoint Enabled

Local Exact Breakpoint Enabled

Bit

13

9

8

G3

L3

G2

L2

G1

L1

G0

L0

Global Exact Breakpoint # 3 Enabled

Local Exact Breakpoint # 3 Enabled

Global Exact Breakpoint # 2 Enabled

Local Exact Breakpoint # 2 Enabled

Global Exact Breakpoint # 1 Enabled

Local Exact Breakpoint # 1 Enabled

Global Exact Breakpoint # 0 Enabled

Local Exact Breakpoint # 0 Enabled

7

6

5

4

3

2

1

0

Figure 97. Debug Register DR7

Chapter 13

Test and Debug

269

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

B

D

B

1

B

S

B

2

B

0

B

T

B

3

Reserved

Symbol

BT

BS

Description

Breakpoint Task Switch

Breakpoint Single Step

Bit

15

14

BD

B3

B2

B1

B0

Breakpoint Debug Access Detected 13

Breakpoint #3 Condition Detected

Breakpoint #2 Condition Detected

Breakpoint #1 Condition Detected

Breakpoint #0 Condition Detected

3

2

1

0

Figure 98. Debug Register DR6

DR5

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reserved

DR4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Reserved

9

8

7

6

5

4

3

2

1

0

Figure 99. Debug Registers DR5 and DR4

270

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

DR3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 3 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

DR2

DR1

DR0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 2 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 1 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Breakpoint 0 32-bit Linear Address

9

8

7

6

5

4

3

2

1

0

Figure 100. Debug Registers DR3, DR2, DR1, and DR0

DR3–DR0. The processor allows the setting of up to four

breakpoints. DR3–DR0 contain the linear addresses for

breakpoint 3 through breakpoint 0, respectively, and are

compared to the linear addresses of processor cycles to

determine if a breakpoint occurs. Debug register DR7 defines

the specific type of cycle that must occur in order for the

breakpoint to occur.

DR5–DR4. When debugging extensions are disabled (bit 3 of CR4

is set to 0), the DR5 and DR4 registers are mapped to DR7 and

DR6, respectively, in order to be software compatible with

previous generations of x86 processors. When debugging

Chapter 13

Test and Debug

271

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

extensions are enabled (bit 3 of CR4 is set to 1), any attempt to

load DR5 or DR4 results in an undefined opcode exception.

Likewise, any attempt to store DR5 or DR4 also results in an

undefined opcode exception.

DR6. If a breakpoint is enabled in DR7, and the breakpoint

conditions as defined in DR7 occur, then the corresponding B

bit (B3–B0) in DR6 is set to 1. In addition, any other breakpoints

defined using these particular breakpoint conditions are

reported by the processor by setting the appropriate B-bits in

DR6, regardless of whether these breakpoints are enabled or

disabled. However, if a breakpoint is not enabled, a debug

exception does not occur for that breakpoint.

If the processor decodes an instruction that writes or reads DR7

through DR0, the BD bit (bit 13) in DR6 is set to 1 (if enabled in

DR7) and the processor generates a debug exception. This

operation allows control to pass to the debugger prior to debug

register access by software.

If the Trap Flag (bit 8) of the EFLAGS register is set to 1, the

processor generates a debug exception after the successful

execution of every instruction (single-step operation) and sets

the BS bit (bit 14) in DR6 to indicate the source of the

exception.

When the processor switches to a new task and the debug trap

bit (T bit) in the corresponding Task State Segment (TSS) is set

to 1, the processor sets the BT bit (bit 15) in DR6 and generates

a debug exception.

DR7. When set to 1, L3–L0 locally enable breakpoints 3 through

0, respectively. L3–L0 are set to 0 whenever the processor

executes a task switch. Setting L3–L0 to 0 disables the

breakpoints and ensures that these particular debug exceptions

are only generated for a specific task.

When set to 1, G3–G0 globally enable breakpoints 3 through 0,

respectively. Unlike L3–L0, G3–G0 are not set to 0 whenever the

processor executes a task switch. Not setting G3–G0 to 0 allows

breakpoints to remain enabled across all tasks. If a breakpoint

is enabled globally but disabled locally, the global enable

overrides the local enable.

272

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the

operation of the processor and are provided in order to be

software-compatible with previous generations of x86

processors.

When set to 1, the GD bit in DR7 (bit 13) enables the debug

exception associated with the BD bit (bit 13) in DR6. This bit is

set to 0 when a debug exception is generated.

LEN3–LEN0 and RW3–RW0 are two-bit fields in DR7 that

specify the length and type of each breakpoint as defined in

Table 54.

Table 54. DR7 LEN and RW Definitions

1

RW Bits

Breakpoint

LEN Bits

00b²

00b

01b

11b

00b

01b

11b

00b

01b

11b

Instruction Execution

One-byte Data Write

01b

Two-byte Data Write

Four-byte Data Write

One-byte I/O Read or Write

Two-byte I/O Read or Write

Four-byte I/O Read or Write

One-byte Data Read or Write

Two-byte Data Read or Write

Four-byte Data Read or Write

10b³

11b

Notes:

1. LEN bits equal to 10b is undefined.

2. When RW equals 00b, LEN must be equal to 00b.

3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set to 1).

If DE is set to 0, then RW equal to 10b is undefined.

Debug Exceptions

A debug exception is categorized as either a debug trap or a

debug fault.

■ A debug trap calls the debugger following the execution of

the instruction that caused the trap.

■ A debug fault calls the debugger prior to the execution of the

instruction that caused the fault.

All debug traps and faults generate either an Interrupt 01h or

an Interrupt 03h exception.

Chapter 13

Test and Debug

273

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Interrupt 01h. The following events are considered debug traps

that cause the processor to generate an Interrupt 01h

exception:

■ Enabled breakpoints for data and I/O cycles

■ Single Step Trap

■ Task Switch Trap

The following events are considered debug faults that cause the

processor to generate an Interrupt 01h exception:

■ Enabled breakpoints for instruction execution

■ BD bit in DR6 set to 1

Interrupt 03h. The INT 3 instruction is defined in the x86

architecture as a breakpoint instruction. This instruction

causes the processor to generate an Interrupt 03h exception.

This exception is a debug trap because the debugger is called

following the execution of the INT 3 instruction.

The INT 3 instruction is a one-byte instruction (opcode CCh)

typically used to insert a breakpoint in software by writing CCh

to the address of the first byte of the instruction to be trapped

(the target instruction). Following the trap, if the target

instruction is to be executed, the debugger must replace the

INT 3 instruction with the first byte of the target instruction.

274

Test and Debug

Chapter 13

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

14

Clock Control

14.1

Clock Control States

The standard-power versions of the AMD-K6-2E+ processor

support five modes of clock control. The low-power versions of

the AMD-K6-2E+ processor support six modes of clock control.

The processor can transition between these modes to maximize

performance, to minimize power dissipation, or to provide a

balance between performance and power. (See “Power

Dissipation” on page 289 for the maximum power dissipation of

the AMD-K6-2E+ processor within the normal and

reduced-power states.) The clock-control states supported are:

■ Normal State—The processor is running in Real Mode,

Virtual-8086 Mode, Protected Mode, or System Management

Mode (SMM). In this state, all clocks are running—including

the external bus clock CLK and the internal processor

clock—and the full features and functions of the processor

are available.

■ Halt State—This low-power state is entered following the

successful execution of the HLT instruction. During this

state, the internal processor clock is stopped.

■ Stop Grant State—This low-power state is entered following

the recognition of the assertion of the STPCLK# signal.

During this state, the internal processor clock is stopped.

■ Stop Grant Inquire State—This state is entered from the

Halt state and the Stop Grant state as the result of a

system-initiated inquire cycle.

■ Enhanced Power Management (EPM) Stop Grant State: This

low-power state is available on low--power versions of the

processor. It is entered following the write of a non-zero

value to the SGTC field of the EPM 16-byte I/O block for the

purpose of performing dynamic processor core frequency

and voltage ID state transitions using AMD PowerNow!

technology. During this state, the internal processor clock is

stopped.

■ Stop Clock State—This low-power state is entered from the

Stop Grant state when the CLK signal is stopped.

Chapter 14

Clock Control

275

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 101 and Figure 102 illustrate the clock control state

transitions on the standard-power and low-power versions,

respectively, of the AMD-K6-2E+ processor. Each of the

reduced-power states are described in the following sections.

STPCLK# Asserted

HLT Instruction

Normal Mode

- Real

- Virtual-8086

- Protected

- SMM

STPCLK# Negated,

or RESET Asserted

RESET, SMI#, INIT,

or INTR Asserted

EADS# Asserted

Stop Grant

Inquire

State

Halt

State

Stop Grant

State

Writeback

Completed

Writeback

Completed

CLK

Stopped

CLK

Started

Stop Clock

State

Figure 101. Clock Control State Transitions for Standard-Power Versions of the AMD-K6™-2E+

Processor

276

Clock Control

Chapter 14

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Non-zero value written to SGTC

SGTC timer expires

HLT Instruction

Normal Mode

– Real

– Virtual-8086

– Protected

– SMM

RESET, SMI#, INIT,

or INTR Asserted

STPCLK# Negated,

or RESET Asserted

STPCLK# Asserted

EPM Stop Grant

State

Stop Grant

State

CLK

Started

CLK

Stopped

CLK

Started

CLK

Stopped

EADS# Asserted

Writeback

Completed

EADS# Asserted

Stop Grant

Halt

State

Stop Clock

State

Inquire

State

Writeback

Completed

Figure 102. Clock Control State Transitions for Low-Power Versions of the AMD-K6™-2E+ Processor

Chapter 14

Clock Control

277

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

14.2

Halt State

Enter Halt State

During the execution of the HLT instruction, the AMD-K6-2E+

processor executes a Halt special cycle. After BRDY# is

sampled asserted during this cycle, and then EWBE# is also

sampled asserted (if not masked off), the processor enters the

Halt state in which the processor disables most of its internal

clock distribution. In order to support the following operations,

the internal phase-lock loop (PLL) still runs, and some internal

resources are still clocked in the Halt state:

■ Inquire Cycles—The processor continues to sample AHOLD,

BOFF#, and HOLD in order to support inquire cycles that

are initiated by the system logic. The processor transitions to

the Stop Grant Inquire state during the inquire cycle. After

returning to the Halt state following the inquire cycle, the

processor does not execute another Halt special cycle.

■ Flush Cycles—The processor continues to sample FLUSH#.

If FLUSH# is sampled asserted, the processor performs the

flush operation in the same manner as it is performed in the

Normal state. Upon completing the flush operation, the

processor executes the Halt special cycle, which indicates

the processor is in the Halt state.

■ Time Stamp Counter (TSC)—The TSC continues to count in

the Halt state.

■ Signal Sampling—The processor continues to sample INIT,

INTR, NMI, RESET, and SMI#.

After entering the Halt state, all signals driven by the processor

retain their state as they existed following the completion of

the Halt special cycle.

Exit Halt State

The AMD-K6-2E+ processor remains in the Halt state until it

samples INIT, INTR (if interrupts are enabled), NMI, RESET, or

SMI# asserted. If any of these signals is sampled asserted, the

processor returns to the Normal state and performs the

corresponding operation. All of the normal requirements for

recognition of these input signals apply within the Halt state.

14.3

Stop Grant State

Enter Stop Grant

State

After recognizing the assertion of STPCLK#, the AMD-K6-2E+

processor flushes its instruction pipelines, completes all

pending and in-progress bus cycles, and acknowledges the

278

Clock Control

Chapter 14

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

STPCLK# assertion by executing a Stop Grant special bus cycle.

After BRDY# is sampled asserted during this cycle, and then

EWBE# is also sampled asserted (if not masked off), the

processor enters the Stop Grant state.

The Stop Grant state is like the Halt state in that the processor

disables most of its internal clock distribution in the Stop Grant

state.

In order to support the following operations, the internal PLL

still runs, and some internal resources are still clocked in the

Stop Grant state:

■ Inquire cycles—The processor transitions to the Stop Grant

Inquire state during an inquire cycle. After returning to the

Stop Grant state following the inquire cycle, the processor

does not execute another Stop Grant special cycle.

■ Time Stamp Counter (TSC)—The TSC continues to count in

the Stop Grant state.

■ Signal Sampling—The processor continues to sample INIT,

INTR, NMI, RESET, and SMI#.

FLUSH# is not recognized in the Stop Grant state (unlike while

in the Halt state).

Upon entering the Stop Grant state, all signals driven by the

processor retain their state as they existed following the

completion of the Stop Grant special cycle.

Exit Stop Grant State

The AMD-K6-2E+ processor remains in the Stop Grant state

until it samples STPCLK# negated or RESET asserted. If

STPCLK# is sampled negated, the processor returns to the

Normal state in less than 10 bus clock (CLK) periods. After the

transition to the Normal state, the processor resumes execution

at the instruction boundary on which STPCLK# was initially

recognized.

If STPCLK# is recognized as negated in the Stop Grant state

and subsequently sampled asserted prior to returning to the

Normal state, the AMD-K6-2E+ processor guarantees that a

minimum of one instruction is executed prior to re-entering the

Stop Grant state.

If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or

SMI# are sampled asserted in the Stop Grant state, the

Chapter 14

Clock Control

279

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

processor latches the edge-sensitive signals (INIT, FLUSH#,

NMI, and SMI#), but otherwise does not exit the Stop Grant

state to service the interrupt. When the processor returns to the

Normal state due to sampling STPCLK# negated, any pending

interrupts are recognized after returning to the Normal state.

To ensure their recognition, all of the normal requirements for

these input signals apply within the Stop Grant state.

If RESET is sampled asserted in the Stop Grant state, the

processor immediately returns to the Normal state and the

reset process begins.

14.4

Stop Grant Inquire State

Enter Stop Grant

Inquire State

The Stop Grant Inquire state is entered from the Stop Grant

state or the Halt state when EADS# is sampled asserted during

an inquire cycle initiated by the system logic. The AMD-K6-2E+

processor responds to an inquire cycle in the same manner as in

the Normal state by driving HIT# and HITM#. If the inquire

cycle hits a modified cache line, the processor performs a

writeback cycle.

Exit Stop Grant

Inquire State

Following the completion of any writeback, the processor

returns to the state from which it entered the Stop Grant

Inquire state.

280

Clock Control

Chapter 14

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

14.5

EPM Stop Grant State

Enter EPM Stop Grant

State

This state is supported on the low-power versions of the

AMD-K6-2E+ processor. After receiving a write of a non-zero

value to the SGTC (Stop Grant Time-out Counter) field located

within the EPM 16-byte I/O block, the processor flushes its

instruction pipelines, completes all pending and in-progress

bus cycles, and performs the following:

■ Drives the processor VID[4:0] output pins to the value stored

in the VIDO field of the EPM 16-byte I/O block (see “EPM

16-Byte I/O Block” on page 146) if the VIDC bit is set to 1.

■ Forwards the processor-to-bus clock ratio stored in the

IBF[2:0] field of the EPM 16-byte I/O block to the internal

PLL if the BDC[1:0] value is set to 1xb.

The EPM Stop Grant state is like the Halt state in that the

processor disables most of its internal clock distribution in the

EPM Stop Grant state. In order to support the following

operations, the internal PLL still runs, and some internal

resources are still clocked in the EPM Stop Grant state.

■ Time Stamp Counter (TSC): The TSC continues to count in

the EPM Stop Grant state.

■ Signal Sampling: The processor continues to sample INIT,

INTR, NMI, RESET, and SMI#.

Unlike the Halt and Stop Grant states, system-initiated inquire

cycles are not supported and must be prevented during the

EPM Stop Grant state.

FLUSH# is not recognized in the EPM Stop Grant state (unlike

while in the Halt state).

Upon entering the EPM Stop Grant state, all signals driven by

the processor retain their state as they existed following the

completion of the EPM Stop Grant special cycle.

Exit EPM Stop Grant

State

The processor remains in the EPM Stop Grant state until the

allotted time expires, as determined by the value written to the

SGTC field, or until RESET is sampled asserted. Once the

allotted time expires, the processor returns to the Normal state.

After the transition to the Normal state, the processor resumes

execution at the instruction boundary on which the EPM Stop

Grant state was entered.

Chapter 14

Clock Control

281

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or

SMI# are sampled asserted in the EPM Stop Grant state, the

processor latches the edge-sensitive signals (INIT, FLUSH#,

NMI, and SMI#), but otherwise does not exit the EPM Stop

Grant state to service the interrupt. When the processor returns

to the Normal state, any pending interrupts are recognized. To

ensure their recognition, all of the normal requirements for

these input signals apply within the EPM Stop Grant state.

If RESET is sampled asserted in the EPM Stop Grant state, the

processor immediately returns to the Normal state and the

reset process begins.

282

Clock Control

Chapter 14

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

14.6

Stop Clock State

Enter Stop Clock

State

If the CLK signal is stopped while the AMD-K6-2E+ processor is

in the Stop Grant state, the processor enters the Stop Clock

state. Because all internal clocks and the PLL are not running

in the Stop Clock state, the Stop Clock state represents the

minimum-power state of all clock control states. The CLK signal

must be held Low while it is stopped.

The Stop Clock state cannot be entered from the Halt state.

INTR is the only input signal that is allowed to change states

while the processor is in the Stop Clock state. However, INTR is

not sampled until the processor returns to the Stop Grant state.

All other input signals must remain unchanged in the Stop

Clock state.

Exit Stop Clock State

The AMD-K6-2E+ processor returns to the Stop Grant state

from the Stop Clock state after the CLK signal is started and

the internal PLL has stabilized. PLL stabilization is achieved

after the CLK signal has been running within its specification

for a minimum of 1.0 ms.

The frequency of CLK when exiting the Stop Clock state can be

different than the frequency of CLK when entering the Stop

Clock state.

The state of the BF[2:0] signals when exiting the Stop Clock

state is ignored because the BF[2:0] signals are only sampled

during the falling transition of RESET.

Chapter 14

Clock Control

283

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

284

Clock Control

Chapter 14

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

15

Electrical Data

This chapter includes specifications for the operating ranges,

absolute ratings, and DC characteristics of the AMD-K6-2E+

embedded processor. Nominal and maximum power dissipation

values for the AMD-K6-2E+ processor during normal and

reduced power states are listed. The chapter concludes with a

discussion of power and grounding requirements.

Chapter 15

Electrical Data

285

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

15.1

Operating Ranges

The AMD-K6-2E+ processor is designed to provide functional

operation if the voltage and temperature parameters are within

the limits defined in Table 55 and Table 56.

Table 55. Operating Ranges for Low-Power AMD-K6™-2E+ Devices

Parameter Parameter Description

350 MHz

1.4 V²

400 MHz

1.5 V³

450 MHz

1.6 V⁴

1

Core Supply Voltage (Minimum)

Core Supply Voltage (Nominal)

Core Supply Voltage (Maximum)

I/O Supply Voltage (Minimum)

I/O Supply Voltage (Nominal)

I/O Supply Voltage (Maximum)

V_CC2

1

1.5 V²

1.6 V³

1.7 V⁴

V_CC2

V_CC3

1

1.6 V²

1.7 V³

1.8 V⁴

3.135 V

3.30 V

3.6 V

0C

Case Temperature (Minimum)⁵

Case Temperature (Maximum)⁵

T_CASE

Notes:

85C

1. V_CC2and V_CC3are referenced from V_SS.

2. V_CC2specification for 1.5-V component.

3. V_CC2specification for 1.6-V component.

4. V_CC2specification for 1.7-V component.

5. Case temperature range required for AMD-K6-2E+/350xUZ, AMD-K6-2E+/400xTZ, and AMD-K6-2E+/450xPZ valid ordering part num-

ber combinations, where x represents the package type. See Table 79 on page 334 for a complete list of valid OPNs.

Table 56. Operating Ranges for Standard-Power AMD-K6™-2E+ Devices

Parameter Parameter Description

400 MHz

450 MHz

500 MHz

1

Core Supply Voltage (Minimum)²

Core Supply Voltage (Nominal)²

Core Supply Voltage (Maximum)²

I/O Supply Voltage (Minimum)

I/O Supply Voltage (Nominal)

I/O Supply Voltage (Maximum)

1.9 V

V_CC2

1

2.0 V

2.1 V

V_CC2

V_CC3

1

3.135 V

3.30 V

3.6 V

0C

Case Temperature (Minimum)³

Case Temperature (Maximum)⁵

T_CASE

Notes:

70C

1. V_CC2and V_CC3are referenced from V_SS.

2. V_CC2specification for 2.0-V component

3. Case temperature range required for AMD-K6-2E+/xxxyACR valid ordering part number combinations, where xxx represents the pro-

cessor core frequency and y represents the package type, as defined in Table 79 on page 334.

286

Electrical Data

Chapter 15

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

15.2

Absolute Ratings

The AMD-K6-2E+ processor is not designed to be operated

beyond the operating ranges listed in Table 55 and Table 56.

Exposure to conditions outside these operating ranges for

extended periods of time can affect long-term reliability.

Permanent damage can occur if the absolute ratings listed in

Table 57 are exceeded.

Table 57. Absolute Ratings

Parameter

V_CC2

Description

Minimum

–0.5 V

Maximum

2.2 V

Core Supply Voltage

I/O Supply Voltage

Voltage on Any I/O Pin

Case Temperature

V_CC3

–0.5 V

3.6 V

1

V

_CC3+ 0.4 V and 3.8 V

–0.5 V

–65C

V_PIN

T_CASE(under bias)

T_STORAGE

+110C

+150C

Storage Temperature

Notes:

1. V_PIN(the voltage on any I/O pin) must not be greater than 0.4 V above the voltage being applied to V_CC3. In addition, the V_PINvoltage

must never exceed 3.8 V.

15.3

DC Characteristics

The DC characteristics of the AMD-K6-2E+ processor are shown

in Table 58.

Table 58. DC Characteristics for the AMD-K6™-2E+ Processor

Preliminary Data

Symbol Parameter Description

Comments

Min

Max

V_IL

Input Low Voltage

–0.3 V

+0.8 V

1

Input High Voltage

2.0 V

VCC3+0.3 V

0.4 V

V_IH

V_OL

V_OH

I_OL= 4.0-mA load

I_OH= 3.0-mA load

Output Low Voltage

Output High Voltage

2.4 V

350 MHz^2,3

400 MHz^2,3,4

450 MHz^2,3

1.5-V Power Supply Current

1.6-V Power Supply Current

1.7-V Power Supply Current

5.30 A

6.15 A

7.60 A

I_CC2

Low Power

Chapter 15

Electrical Data

287

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 58. DC Characteristics for the AMD-K6™-2E+ Processor (continued)

Preliminary Data

Symbol Parameter Description

Comments

Min

Max

8.70 A

9.25 A

9.75 A

0.64 A

0.65 A

0.66 A

0.68 A

400 MHz^3,4,5

450 MHz^3,5

500 MHz^3,5

350 MHz^3,6

400 MHz^3,4,6

450 MHz^3,6

500 MHz^3,6

I_CC2

2.0 V Power Supply Current

3.3 V Power Supply Current

Standard

Power

I_CC3

Standard

and Low

Power

7

Input Leakage Current

15 mA

–500 mA

I_LI

7

Output Leakage Current

I_LO

8

Input Leakage Current Bias with Pullup

I_IL

9

Input Leakage Current Bias with Pulldown

Input Capacitance

500 mA

10 pF

15 pF

20 pF

10 pF

15 pF

10 pF

I_IH

C_IN

C_OUT

C_CLK

C_TIN

Output Capacitance

I/O Capacitance

CLK Capacitance

Test Input Capacitance (TDI, TMS, TRST#)

Test Output Capacitance (TDO)

TCK Capacitance

C_TOUT

C_TCK

Notes:

1. V_CC3refers to the voltage being applied to V_CC3during functional operation.

2. V_CC2= Maximum V_CC2as listed in Table 55 on page 286— The maximum power supply current must be taken into account when

designing a power supply.

3. This specification applies to components using a CLK frequency of 100 MHz.

4. This specification applies to components using a CLK frequency of 66 MHz (66-MHz bus applies to 400-MHz part only).

5. V_CC2= 2.1 V — The maximum power supply current must be taken into account when designing a power supply.

6. V_CC3= 3.6 V—The maximum power supply current must be taken into account when designing a power supply.

7. Refers to inputs and I/O without an internal pullup resistor and 0 V_IN V_CC3.

8. Refers to inputs with an internal pullup and V_IL= 0.4 V.

9. Refers to inputs with an internal pulldown and V_IH= 2.4 V.

288

Electrical Data

Chapter 15

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

15.4

Power Dissipation

Table 59 and Table 60 contain the application power dissipation

of the low-power and standard-power AMD-K6-2E+ processor

during normal and reduced power states. Table 61 on page 290

shows the supported voltages and operating frequencies for

low-power versions of AMD-K6-2E+ processors enabled with

AMD PowerNow! technology.

Table 59. Power Dissipation for Low-Power AMD-K6™-2E+ Devices

1

1,2

1

Power Dissipation

350 MHz

400 MHz

450 MHz

Active³

5.60 W

6.90 W

8.70 W

Application Power

AMD PowerNow! Technology

Power Saving Mode⁴

2.95 W

Thermal Design Power (Maximum)^5,6

Stop Grant/Halt (Maximum)^6,7

7.50 W

9.50 W

2.50 W

12.00 W

1.90 W

V

_CCNominal

1.60 W

Stop Clock (Maximum)^6,8

9

1.30 W

Lowest Operating V_CC

Notes:

1. This specification applies to components using a CLK frequency of 100 MHz.

2. This specification applies to components using a CLK frequency of 66 MHz.

3. The active application power measurements were taken by running a suite of embedded benchmarks covering four major

embedded market segments: automotive, office automation, networking, and telecommunications.

4. AMD PowerNow! technology Power Saving Mode represents averaged values measured while running the processor in the lowest

settings supported by AMD PowerNow! technology.

5. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal

dissipation for the AMD-K6-2E+ processor.

6. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with

V_CC2= Nominal V_CC2as listed in Table 55 on page 286 and V_CC3= 3.3 V.

7. The CLK signal and the internal PLL are still running, but most internal clocking has stopped.

8. The CLK signal, the internal PLL, and all internal clocking has stopped.

9. The lowest operating V_CCis 1.4 V.

Chapter 15

Electrical Data

289

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 60. Power Dissipation for Standard-Power AMD-K6™-2E+ Devices

1,2

1

Power Dissipation

400 MHz

11.40 W

450 MHz

12.65 W

17.50 W

4.50 W

500 MHz

13.90 W

18.50 W

Active³

Application Power

Thermal Design Power (Maximum)^4,5

Stop Grant/Halt (Maximum)^5,6

Stop Clock (Maximum)^5,7

Notes:

16.50 W

4.00 W

1. This specification applies to components using a CLK frequency of 100 MHz.

2. This specification applies to components using a CLK frequency of 66 MHz.

3. The active application power measurements were taken by running a suite of embedded benchmarks covering four major

embedded market segments: automotive, office automation, networking, and telecommunications.

4. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal

dissipation for the AMD-K6-2E+ processor.

5. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with

V_CC2= 2.0 V and V_CC3= 3.3 V.

6. The CLK signal and the internal PLL are still running, but most internal clocking has stopped.

7. The CLK signal, the internal PLL, and all internal clocking has stopped.

Table 61. Supported Voltages and Operating Frequencies for Low-Power AMD-K6™-2E+ Processors

Enabled with AMD PowerNow!™ Technology

Range of Supported

1

3

Core Voltage

Ordering Part Number

Active Power

2

Operating Frequencies

450–200 MHz

400–200 MHz

350–200 MHz

300–200 MHz

400–200 MHz

350–200 MHz

300–200 MHz

350–200 MHz

300–200 MHz

1.7 V

1.6 V

1.5 V

1.4 V

1.6 V

1.5 V

1.4 V

1.5 V

1.4 V

8.70–4.90 W

6.90–4.20 W

5.60–3.70 W

4.30–2.95 W

6.90–4.20 W

5.60–3.70 W

4.30–2.95 W

5.60–3.70 W

4.30–2.95 W

AMD-K6-2E+/450APZ

AMD-K6-2E+/400xTZ

AMD-K6-2E+/350xUZ

Notes:

1. An x in this column represents the package type. See Table 79, “AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Com-

binations,” on page 334.

2. AMD PowerNow! technology enables the operating frequency to step down in increments corresponding to the available bus frequency

multipliers. Note that 250-MHz operation is not supported due to exclusion of 2.5 bus frequency multiplier.

3. Active application power dissipation for highest and lowest supported frequency at specified voltage.

290

Electrical Data

Chapter 15

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

15.5

Power and Grounding

Power Connections

The AMD-K6-2E+ processor is a dual voltage device. Two

separate supply voltages are required: V and V

.

CC3

CC2

■ V

provides the core voltage for the processor.

CC2

CC3

provides the I/O voltage.

See “Operating Ranges” on page 286 for the value and range of

and V

V

.

CC3

CC2

The power and ground pins for each package are listed in

Table 76 on page 325 and Table 78 on page 329. Table 74 on

page 321 lists the pin differences between the two packages.

The large number of power and ground pins are provided to

ensure that the processor and package maintain a clean and

stable power distribution network.

For proper operation and functionality, all V

, V

, and V

CC3 SS

CC2

pins must be connected to the appropriate planes in the circuit

board. The power planes have been arranged in a pattern to

simplify routing and minimize crosstalk on the circuit board.

The isolation region between two voltage planes must be at

least 0.254mm if they are in the same layer of the circuit board.

(See Figure 103 on page 292.) In order to maintain a

low-impedance current sink and reference, the ground plane

must never be split.

Although the AMD-K6-2E+ processor has two separate supply

voltages, there are no special power sequencing requirements.

The best procedure is to minimize the time between which V

CC2

and V

are either both on or both off.

CC3

Chapter 15

Electrical Data

291

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

0.254mm (min.) for

isolation region

C20

C21

C22

C23

C24

C25

C18

C17

C19

C5

C6

C7

CC3

+

C27

C28

C1

C2

CC4

CC5

CC6

+

C11

C12

C13

C29

C30

C31

C26

V_CC3(I/O) Plane

V_CC2(Core) Plane

CC1

CC2

Figure 103. Suggested Component Placement for CPGA Package

Decoupling

Recommendations

In addition to the isolation region mentioned in “Power

Connections” on page 291, adequate decoupling capacitance is

required between the two system power planes and the ground

plane to minimize ringing and to provide a low-impedance path

for return currents. Suggested decoupling capacitor placement

is shown in Figure 103.

Surface-mounted capacitors should be used under the

processor’s ZIF socket to minimize resistance and inductance in

the lead lengths while maintaining minimal height. For

information and recommendations about the specific value,

®

quantity, and location of the capacitors, see the AMD-K6

Processor Power Supply Design Application Note, order# 21103.

292

Electrical Data

Chapter 15

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Pin Connection

Requirements

For proper operation, the following requirements for signal pin

connections must be met:

■ Do not drive address and data signals into large capacitive

loads at high frequencies. If necessary, use buffer chips to

drive large capacitive loads.

■ Leave all NC (no-connect) pins unconnected.

■ Unused inputs should always be connected to an

appropriate signal level.

•

Active Low inputs that are not being used should be

connected to V through a 20-kW pullup resistor.

CC3

•

Active High inputs that are not being used should be

connected to GND through a pulldown resistor.

■ Reserved signals can be treated in one of the following ways:

•

As no-connect (NC) pins, in which case these pins are left

unconnected

As pins connected to the system logic as defined by the

industry-standard Super7 and Socket 7 interface

Any combination of NC and Socket 7 pins

■ Keep trace lengths to a minimum.

Chapter 15

Electrical Data

293

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

294

Electrical Data

Chapter 15

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16

Signal Switching Characteristics

The AMD-K6-2E+ processor signal switching characteristics are

presented in Table 62 through Table 71 on the following pages.

Valid delay, float, setup, and hold timing specifications are

listed. These specifications are provided for the system

designer to determine if the timings necessary for the processor

to interface with the system logic are met.

■ Table 62 on page 296 and Table 63 on page 297 contain the

switching characteristics of the CLK input.

■ Table 64 on page 298 through Table 67 on page 304 contain

the timings for the normal operation signals.

■ Table 68 on page 306 and Table 69 on page 307 contain the

timings for RESET and the configuration signals.

■ Table 70 on page 308 and Table 71 on page 308 contain the

timings for the test operation signals.

All signal timings provided are:

■ Measured between CLK, TCK, or RESET at 1.5 V and the

corresponding signal at 1.5 V—this applies to input and

output signals that are switching from Low to High, or from

High to Low

■ Based on input signals applied at a slew rate of 1 V/ns

between 0 V and 3 V (rising) and 3 V to 0 V (falling)

■ Valid within the operating ranges given in “Operating

Ranges” on page 286

■ Based on a load capacitance (C ) of 0 pF

L

Chapter 16

Signal Switching Characteristics

295

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.1

CLK Switching Characteristics

Table 62 and Table 63 on page 297 contain the switching

characteristics of the CLK input to the AMD-K6-2E+ processor

for 100-MHz and 66-MHz bus operation, respectively, as

measured at the voltage levels indicated by Figure 104 on page

297.

The CLK Period Stability parameter specifies the variance

(jitter) allowed between successive periods of the CLK input

measured at 1.5 V. This parameter must be considered as one of

the elements of clock skew between the AMD-K6-2E+ processor

and the system logic.

16.2

Clock Switching Characteristics for 100-MHz Bus Operation

Table 62. CLK Switching Characteristics for 100-MHz Bus Operation

Preliminary Data

Symbol Parameter Description

Figure

Comments

Min

33.3 MHz

10.0 ns

3.0 ns

Max

Frequency

100 MHz

In Normal Mode

t₁

t₂

t₃

t₄

t₅

CLK Period

104

CLK High Time

CLK Low Time

CLK Fall Time

CLK Rise Time

3.0 ns

0.15 ns

1.5 ns

CLK Period Stability¹

250 ps

Notes:

1. The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.

296

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.3

Clock Switching Characteristics for 66-MHz Bus Operation

Table 63. CLK Switching Characteristics for 66-MHz Bus Operation

Preliminary Data

Symbol Parameter Description

Figure

Comments

Min

33.3 MHz

15.0 ns

4.0 ns

Max

Frequency

66.6 MHz

30.0 ns

In Normal Mode

t₁

t₂

t₃

t₄

t₅

CLK Period

104

CLK High Time

CLK Low Time

CLK Fall Time

CLK Rise Time

4.0 ns

0.15 ns

1.5 ns

CLK Period Stability¹

250 ps

Notes:

1. The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.

t₂

2.0 V

1.5 V

t₃

0.8 V

t₄

t₅

t₁

Figure 104. CLK Waveform

Chapter 16

Signal Switching Characteristics

297

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.4

Valid Delay, Float, Setup, and Hold Timings

Valid Delay and Float

Timing

The maximum valid delay timings are provided to allow a

system designer to determine if setup times to the system logic

can be met. Likewise, the minimum valid delay timings are used

to analyze hold times to the system logic.

■ Valid delay and float timings are given for output signals

during functional operation and are given relative to the

rising edge of CLK.

■ During boundary-scan testing, valid delay and float timings

for output signals are with respect to the falling edge of

TCK.

Setup and Hold

Timing

The setup and hold time requirements for the AMD-K6-2E+

processor input signals must be met by the system logic to

assure the proper operation of the AMD-K6-2E+ processor.

■ The setup and hold timings during functional and

boundary-scan test mode are given relative to the rising

edge of CLK and TCK, respectively.

16.5

Output Delay Timings for 100-MHz Bus Operation

Table 64. Output Delay Timings for 100-MHz Bus Operation

Preliminary Data

Min

Symbol Parameter Description

Figure

Max

4.0 ns

7.0 ns

4.0 ns

7.0 ns

4.0 ns

7.0 ns

5.5 ns

7.0 ns

4.5 ns

4.0 ns

7.0 ns

4.0 ns

t₆

t₇

A[31:3] Valid Delay

A[31:3] Float Delay

ADS# Valid Delay

ADS# Float Delay

ADSC# Valid Delay

ADSC# Float Delay

AP Valid Delay

1.1 ns

1.0 ns

106

107

106

107

106

107

106

107

106

107

106

t₈

t₉

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

AP Float Delay

APCHK# Valid Delay

BE[7:0]# Valid Delay

BE[7:0]# Float Delay

BREQ Valid Delay

CACHE# Valid Delay

1.0 ns

298

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 64. Output Delay Timings for 100-MHz Bus Operation (continued)

Preliminary Data

Symbol Parameter Description

Figure

Min

1.0 ns

1.3 ns

Max

7.0 ns

4.0 ns

7.0 ns

4.5 ns

7.0 ns

4.5 ns

7.0 ns

4.5 ns

4.0 ns

7.0 ns

4.0 ns

7.0 ns

4.0 ns

7.0 ns

4.5 ns

4.0 ns

7.0 ns

4.0 ns

7.0 ns

4.0 ns

7.0 ns

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

t₃₀

t₃₁

t₃₂

t₃₃

t₃₄

t₃₅

t₃₆

t₃₇

t₃₈

t₃₉

t₄₀

t₄₁

t₄₂

t₄₃

CACHE# Float Delay

D/C# Valid Delay

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

D/C# Float Delay

D[63:0] Write Data Valid Delay

D[63:0] Write Data Float Delay

DP[7:0] Write Data Valid Delay

DP[7:0] Write Data Float Delay

FERR# Valid Delay

HIT# Valid Delay

1.0 ns

1.1 ns

1.0 ns

1.1 ns

HITM# Valid Delay

HLDA Valid Delay

LOCK# Valid Delay

LOCK# Float Delay

M/IO# Valid Delay

M/IO# Float Delay

PCD Valid Delay

1.0 ns

PCD Float Delay

PCHK# Valid Delay

PWT Valid Delay

1.0 ns

PWT Float Delay

SCYC Valid Delay

1.0 ns

SCYC Float Delay

SMIACT# Valid Delay

W/R# Valid Delay

1.0 ns

W/R# Float Delay

Chapter 16

Signal Switching Characteristics

299

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.6

Input Setup and Hold Timings for 100-MHz Bus Operation

Table 65. Input Setup and Hold Timings for 100-MHz Bus Operation

Preliminary Data

Min Max

3.0 ns

Symbol Parameter Description

Figure

t₄₄

t₄₅

A[31:5] Setup Time

A[31:5] Hold Time

A20M# Setup Time

108

1.0 ns

3.0 ns

1

t₄₆

1

A20M# Hold Time

1.0 ns

3.5 ns

1.0 ns

1.7 ns

1.0 ns

3.5 ns

1.0 ns

3.0 ns

1.0 ns

3.0 ns

1.0 ns

1.7 ns

1.5 ns

1.7 ns

1.5 ns

3.0 ns

1.0 ns

1.7 ns

1.0 ns

1.7 ns

108

t₄₇

t₄₈

t₄₉

t₅₀

t₅₁

t₅₂

t₅₃

t₅₄

t₅₅

t₅₆

t₅₇

t₅₈

t₅₉

t₆₀

t₆₁

t₆₂

t₆₃

t₆₄

t₆₅

AHOLD Setup Time

AHOLD Hold Time

AP Setup Time

AP Hold Time

BOFF# Setup Time

BOFF# Hold Time

BRDY# Setup Time

BRDY# Hold Time

BRDYC# Setup Time

BRDYC# Hold Time

D[63:0] Read Data Setup Time

D[63:0] Read Data Hold Time

DP[7:0] Read Data Setup Time

DP[7:0] Read Data Hold Time

EADS# Setup Time

EADS# Hold Time

EWBE# Setup Time

EWBE# Hold Time

2

FLUSH# Setup Time

t₆₆

2

FLUSH# Hold Time

HOLD Setup Time

HOLD Hold Time

IGNNE# Setup Time

1.0 ns

1.7 ns

1.5 ns

1.7 ns

108

t₆₇

t₆₈

t₆₉

1

t₇₀

1

IGNNE# Hold Time

INIT Setup Time

1.0 ns

1.7 ns

108

t₇₁

2

t₇₂

300

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 65. Input Setup and Hold Timings for 100-MHz Bus Operation (continued)

Preliminary Data

Symbol Parameter Description

Figure

Min

Max

2

1

INIT Hold Time

1.0 ns

108

t₇₃

t₇₄

t₇₅

INTR Setup Time

1.7 ns

INTR Hold Time

INV Setup Time

INV Hold Time

1.0 ns

1.7 ns

1.0 ns

3.0 ns

1.0 ns

1.7 ns

1.0 ns

1.7 ns

108

t₇₆

t₇₇

t₇₈

t₇₉

t₈₀

t₈₁

KEN# Setup Time

KEN# Hold Time

NA# Setup Time

NA# Hold Time

NMI Setup Time

2

t₈₂

t₈₃

t₈₄

t₈₅

t₈₆

t₈₇

2

1

NMI Hold Time

1.0 ns

1.7 ns

1.0 ns

1.7 ns

108

SMI# Setup Time

SMI# Hold Time

STPCLK# Setup Time

STPCLK# Hold Time

WB/WT# Setup Time

WB/WT# Hold Time

1.0 ns

1.7 ns

1.0 ns

108

t₈₈

t₈₉

Notes:

1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold

times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.

2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold

times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain

asserted at least two clocks.

Chapter 16

Signal Switching Characteristics

301

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.7

Output Delay Timings for 66-MHz Bus Operation

Table 66. Output Delay Timings for 66-MHz Bus Operation

Preliminary Data

Min

Symbol Parameter Description

Figure

Max

6.3 ns

10.0 ns

6.0 ns

10.0 ns

7.0 ns

t₆

A[31:3] Valid Delay

A[31:3] Float Delay

ADS# Valid Delay

1.1 ns

1.0 ns

106

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

106

107

t₇

t₈

t₉

ADS# Float Delay

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

t₃₀

t₃₁

t₃₂

t₃₃

t₃₄

t₃₅

ADSC# Valid Delay

ADSC# Float Delay

AP Valid Delay

10.0 ns

8.5 ns

10.0 ns

8.3 ns

7.0 ns

AP Float Delay

APCHK# Valid Delay

BE[7:0]# Valid Delay

BE[7:0]# Float Delay

BREQ Valid Delay

1.0 ns

10.0 ns

8.0 ns

7.0 ns

1.0 ns

CACHE# Valid Delay

CACHE# Float Delay

D/C# Valid Delay

10.0 ns

7.0 ns

1.0 ns

1.3 ns

D/C# Float Delay

10.0 ns

7.5 ns

D[63:0] Write Data Valid Delay

D[63:0] Write Data Float Delay

DP[7:0] Write Data Valid Delay

DP[7:0] Write Data Float Delay

FERR# Valid Delay

HIT# Valid Delay

10.0 ns

7.5 ns

10.0 ns

8.3 ns

6.8 ns

6.0 ns

6.8 ns

7.0 ns

1.0 ns

1.1 ns

1.0 ns

1.1 ns

HITM# Valid Delay

HLDA Valid Delay

LOCK# Valid Delay

LOCK# Float Delay

M/IO# Valid Delay

M/IO# Float Delay

PCD Valid Delay

10.0 ns

5.9 ns

10.0 ns

7.0 ns

1.0 ns

PCD Float Delay

10.0 ns

302

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 66. Output Delay Timings for 66-MHz Bus Operation (continued)

Preliminary Data

Symbol Parameter Description

Figure

Min

1.0 ns

Max

7.0 ns

10.0 ns

7.0 ns

10.0 ns

7.3 ns

7.0 ns

10.0 ns

t₃₆

t₃₇

t₃₈

t₃₉

t₄₀

t₄₁

t₄₂

t₄₃

PCHK# Valid Delay

PWT Valid Delay

PWT Float Delay

SCYC Valid Delay

SCYC Float Delay

SMIACT# Valid Delay

W/R# Valid Delay

W/R# Float Delay

106

107

106

107

106

107

1.0 ns

Chapter 16

Signal Switching Characteristics

303

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.8

Input Setup and Hold Timings for 66-MHz Bus Operation

Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation

Preliminary Data

Symbol Parameter Description

Figure

Min

6.0 ns

1.0 ns

Max

t₄₄

t₄₅

A[31:5] Setup Time

A[31:5] Hold Time

A20M# Setup Time

108

1

5.0 ns

t₄₆

1

A20M# Hold Time

1.0 ns

5.5 ns

1.0 ns

5.0 ns

1.0 ns

5.5 ns

1.0 ns

5.0 ns

1.0 ns

5.0 ns

1.0 ns

2.8 ns

1.5 ns

2.8 ns

1.5 ns

5.0 ns

1.0 ns

5.0 ns

1.0 ns

5.0 ns

108

t₄₇

t₄₈

t₄₉

t₅₀

t₅₁

t₅₂

t₅₃

t₅₄

t₅₅

t₅₆

t₅₇

t₅₈

t₅₉

t₆₀

t₆₁

t₆₂

t₆₃

t₆₄

t₆₅

AHOLD Setup Time

AHOLD Hold Time

AP Setup Time

AP Hold Time

BOFF# Setup Time

BOFF# Hold Time

BRDY# Setup Time

BRDY# Hold Time

BRDYC# Setup Time

BRDYC# Hold Time

D[63:0] Read Data Setup Time

D[63:0] Read Data Hold Time

DP[7:0] Read Data Setup Time

DP[7:0] Read Data Hold Time

EADS# Setup Time

EADS# Hold Time

EWBE# Setup Time

EWBE# Hold Time

2

FLUSH# Setup Time

t₆₆

2

FLUSH# Hold Time

HOLD Setup Time

HOLD Hold Time

IGNNE# Setup Time

1.0 ns

5.0 ns

1.5 ns

5.0 ns

108

t₆₇

t₆₈

t₆₉

1

t₇₀

1

IGNNE# Hold Time

INIT Setup Time

1.0 ns

5.0 ns

108

t₇₁

2

t₇₂

304

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)

Preliminary Data

Symbol Parameter Description

Figure

Min

Max

2

1

INIT Hold Time

1.0 ns

108

t₇₃

t₇₄

t₇₅

INTR Setup Time

5.0 ns

INTR Hold Time

INV Setup Time

INV Hold Time

1.0 ns

5.0 ns

1.0 ns

5.0 ns

1.0 ns

4.5 ns

1.0 ns

5.0 ns

108

t₇₆

t₇₇

t₇₈

t₇₉

t₈₀

t₈₁

KEN# Setup Time

KEN# Hold Time

NA# Setup Time

NA# Hold Time

NMI Setup Time

2

t₈₂

t₈₃

t₈₄

t₈₅

t₈₆

t₈₇

2

1

NMI Hold Time

1.0 ns

5.0 ns

1.0 ns

5.0 ns

108

SMI# Setup Time

SMI# Hold Time

STPCLK# Setup Time

STPCLK# Hold Time

WB/WT# Setup Time

WB/WT# Hold Time

1.0 ns

4.5 ns

1.0 ns

108

t₈₈

t₈₉

Notes:

1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold

times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.

2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold

times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain

asserted at least two clocks.

Chapter 16

Signal Switching Characteristics

305

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.9

RESET and Test Signal Timing

Table 68. RESET and Configuration Signals for 100-MHz Bus Operation

Preliminary Data

Symbol Parameter Description

Min

Figure

Max

t₉₀

t₉₁

t₉₂

t₉₃

RESET Setup Time

1.7 ns

1.0 ns

109

RESET Hold Time

RESET Pulse Width, V_CCand CLK Stable

RESET Active After V_CCand CLK Stable

15 clocks

1.0 ms

1

BF[2:0] Setup Time

t₉₄

1

BF[2:0] Hold Time

2 clocks

109

t₉₅

t₉₆

t₉₇

t₉₈

Intentionally left blank

FLUSH# Setup Time

2

1.7 ns

1.0 ns

109

t₉₉

2

FLUSH# Hold Time

FLUSH# Setup Time

FLUSH# Hold Time

t₁₀₀

3

2 clocks

t₁₀₁

3

t₁₀₂

Notes:

1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.

2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is

sampled negated.

3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET.

306

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 69. RESET and Configuration Signals for 66-MHz Bus Operation

Preliminary Data

Symbol Parameter Description

Figure

Min

5.0 ns

Max

t₉₀

t₉₁

t₉₂

t₉₃

RESET Setup Time

109

RESET Hold Time

1.0 ns

RESET Pulse Width, V_CCand CLK Stable

RESET Active After V_CCand CLK Stable

15 clocks

1.0 ms

1

BF[2:0] Setup Time

1.0 ms

t₉₄

1

BF[2:0] Hold Time

2 clocks

109

t₉₅

t₉₆

t₉₇

t₉₈

Intentionally left blank

FLUSH# Setup Time

2

5.0 ns

1.0 ns

109

t₉₉

2

FLUSH# Hold Time

FLUSH# Setup Time

FLUSH# Hold Time

t₁₀₀

3

2 clocks

t₁₀₁

3

t₁₀₂

Notes:

1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.

2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is sam-

pled negated.

3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET.

Chapter 16

Signal Switching Characteristics

307

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 70. TCK Waveform and TRST# Timing at 25 MHz

Preliminary Data

Max

Symbol

Parameter Description

Figure

Min

TCK Frequency

TCK Period

25 MHz

110

t₁₀₃

t₁₀₄

t₁₀₅

40.0 ns

14.0 ns

TCK High Time

TCK Low Time

1,2

TCK Fall Time

5.0 ns

110

111

t₁₀₆

t₁₀₇

TCK Rise Time

TRST# Pulse Width

3

30.0 ns

t₁₀₈

Notes:

1. Rise/Fall times can be increased by 1.0 ns for each 10 MHz that TCK is run below its maximum frequency of 25 MHz.

2. Rise/Fall times are measured between 0.8 V and 2.0 V.

3. Asynchronous.

Table 71. Test Signal Timing at 25 MHz

Preliminary Data

Symbol Parameter Description

Figure

Min

Max

1

TDI Setup Time

5.0 ns

112

t₁₀₉

1

2

1

TDI Hold Time

9.0 ns

5.0 ns

9.0 ns

3.0 ns

t₁₁₀

t₁₁₁

t₁₁₂

t₁₁₃

t₁₁₄

t₁₁₅

t₁₁₆

t₁₁₇

t₁₁₈

TMS Setup Time

TMS Hold Time

TDO Valid Delay

13.0 ns

16.0 ns

13.0 ns

16.0 ns

TDO Float Delay

All Outputs (Non-Test) Valid Delay

All Outputs (Non-Test) Float Delay

All Inputs (Non-Test) Setup Time

All Inputs (Non-Test) Hold Time

3.0 ns

5.0 ns

9.0 ns

Notes:

1. Parameter is measured from the TCK rising edge.

2. Parameter is measured from the TCK falling edge.

308

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

16.10

Timing Diagrams

WAVEFORM

INPUTS

OUTPUTS

Must be steady

Steady

Can change from

High to Low

Changing from High to Low

Changing from Low to High

Changing, State Unknown

Can change

from Low to High

Don’t care, any

change permitted

(Does not apply)

Center line is high

impedance state

Figure 105. Key to Timing Diagrams

Chapter 16

Signal Switching Characteristics

309

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

T_x

1.5 V

CLK

Max

t_v

Min

Output Signal

Valid n

Valid n +1

Note: For symbols t_vlisted in Table 64 on page 298 and Table 66 on page 302, where:

v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42

Figure 106. Output Valid Delay Timing

T_x

1.5 V

CLK

t_f

Output Signal

Valid

t_v

Min

Note: For symbols t_vand t_flisted in Table 64 on page 298 and Table 66 on page 302, where:

v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42

f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43

Figure 107. Maximum Float Delay Timing

T_x

1.5 V

CLK

t_s

t_h

Input Signal

Note: For symbols t_sand t_hlisted in Table 65 on page 300 and Table 67 on page 304, where:

s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88

h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89

Figure 108. Input Setup and Hold Timing

310

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

T_x

1.5 V

CLK

• • •

t₉₀

t₉₁

RESET

1.5 V

t_{92, 93}

t₉₉

t₁₀₀

FLUSH#

(Synchronous)

• • •

FLUSH#

(Asynchronous)

• • •

t₁₀₁

t₁₀₂

BF[2:0]

(Asynchronous)

• • •

t₉₄

t₉₅

Figure 109. Reset and Configuration Timing

Chapter 16

Signal Switching Characteristics

311

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

t₁₀₄

2.0 V

1.5 V

t₁₀₅

0.8 V

t₁₀₆

t₁₀₇

t₁₀₃

Figure 110. TCK Waveform

t₁₀₈

1.5 V

Figure 111. TRST# Timing

t₁₀₃

1.5 V

TCK

TDI, TMS

TDO

t_{109, 111}t_{110, 112}

t₁₁₄

t₁₁₃

t₁₁₆

t₁₁₅

Output

Signals

Input

Signals

t₁₁₇

t₁₁₈

Figure 112. Test Signal Timing Diagram

312

Signal Switching Characteristics

Chapter 16

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

17

Thermal Design

17.1

Package Thermal Specifications

The AMD-K6-2E+ processor operating specification calls for the

case temperature (T ) to be in the range of 0°C to 70°C for

C

standard-power devices and 0°C to 85°C for low-power devices.

The ambient temperature (T ) is not specified as long as the

A

case temperature is not violated. The case temperature must be

measured on the top center of the package.

Table 72 on page 314 and Table 73 on page 314 show the pro-

cessor thermal specifications for the low-power and standard

power AMD-K6-2E+ devices, respectively.

Chapter 17

Thermal Design

313

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 72. Package Thermal Specification for Low-Power AMD-K6™-2E+

Devices

Maximum Thermal Power

q

JC

Junction-Case

350 MHz

400 MHz

450 MHz

7.50 W

9.50 W

12.00 W

1.0° C/W

2.50 W

Stop Grant Mode

Stop Clock Mode

1.60 W

1.90 W

0°C–85°C

T Case Temperature

C

Table 73. Package Thermal Specification for Standard-Power AMD-K6™-2E+

Devices

Maximum Thermal Power

q

JC

Junction-Case

400 MHz

450 MHz

500 MHz

16.50 W

17.50 W

18.50 W

1.0°C/W

4.50 W

4.00 W

Stop Grant Mode

Stop Clock Mode

0°C–70°C

T Case Temperature

C

Figure 113 on page 315 shows the thermal model of a processor

with a passive thermal solution. The case-to-ambient

temperature (T ) can be calculated from the following

CA

equation:

T_CA

= P_MAX• q_CA

= P_MAX• ( q_IF+ q_SA

)

Where:

P_MAX

q_CA

q_IF

q_SA

= Maximum Power Consumption

= Case-to-Ambient Thermal Resistance

= Interface Material Thermal Resistance

= Sink-to-Ambient Thermal Resistance

314

Thermal Design

Chapter 17

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Thermal

Resistance

(°C/W)

Temperature

(Ambient)

T_CA

q_SA

q_CA

Sink

Case

q_IF

Figure 113. Thermal Model (CPGA Package)

Figure 114 illustrates the case-to-ambient temperature (T ) in

CA

relation to the power consumption (X-axis) and the thermal

resistance (Y-axis). If the power consumption and case

temperature are known, the thermal resistance (q

)

CA

requirement can be calculated for a given ambient temperature

(T ) value.

A

T_CA= T_C- T_A

Case-to-Ambient Temperature

(T_C- T_A)

Power Consumption (Watts)

Figure 114. Power Consumption and Thermal Resistance (CPGA Package)

Chapter 17

Thermal Design

315

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

The thermal resistance of a heatsink is determined by the heat

dissipation surface area, the material and shape of the

heatsink, and the airflow volume across the heatsink. In

general, the larger the surface area the lower the thermal

resistance.

The required thermal resistance of a heatsink (q_SA) can be

calculated using the following example:

If:

T

P

= 70°C

= 45°C

MAX

C

A

= 19.50W

Then:

T_C– T_A

25C

q_CA ------------------- = ------------------ = 1.28C W

Ë

Û

Í

Ý

19.50W

P_MAX

Thermal grease is recommended as interface material because

it provides the lowest thermal resistance (@ 0.20°C/W). The

required thermal resistance (q ) of the heatsink in this

SA

example is calculated as follows:

q_SA= q_CA– q_IF= 1.28 – 0.20 = 1.08°C/W

Heat Dissipation Path

Figure 115 illustrates the heat dissipation path of the processor.

Due to the lower thermal resistance between the processor die

junction and case, most of the heat generated by the processor

is transferred from the top surface of the case. The small

amount of heat generated from the bottom side of the processor

where the processor socket blocks the convection can be safely

ignored.

Ambient Temperature

Thin Lid

Case temperature

Figure 115. Processor Heat Dissipation Path

316

Thermal Design

Chapter 17

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

17.2

Measuring Case Temperature

The processor case temperature is measured to ensure that the

thermal solution meets the processor’s operational

specification. This temperature should be measured on the top

center of the package, where most of the heat is dissipated.

Figure 116 shows the correct location for measuring the case

temperature. The tip of the thermocouple should be secured to

the package surface with a small amount of thermally

conductive epoxy. It is also recommended to secure a second

location along the thermocouple to avoid any movement during

testing.

If a heatsink is installed while measuring, the thermocouple

must be installed into the heatsink via a small hole drilled

through the heatsink base (for example, 1/16 of an inch). Secure

the thermocouple to the base of the heatsink by filling the

small hole with thermal epoxy, allowing the tip of the

thermocouple to protrude the epoxy and touch the top of the

processor case.

Thermally Conductive Epoxy

Thermocouple

Figure 116. Measuring Case Temperature

17.3

Layout and Airflow Considerations

Voltage Regulator

A voltage regulator is required to support the lower voltage

(3.3 V and lower) to the processor. In most applications, the

voltage regulator is designed with power transistors. As a

result, additional heatsinks are required to dissipate the heat

from the power transistors. Figure 117 on page 318 shows the

Chapter 17

Thermal Design

317

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

voltage regulator placed parallel to the processor with the

airflow aligned with the devices. With this alignment, the heat

generated by the voltage regulator has minimal effect on the

processor.

Voltage Regulator

Airflow

Processor

Figure 117. Voltage Regulator Placement

A heatsink and fan combination can deliver much better

thermal performance than a heatsink alone. More importantly,

with a fan/sink the airflow requirements in a system design are

not as critical. A unidirectional heatsink with a fan moves air

from the top of the heatsink to the side. In this case, the best

location for the voltage regulator is on the side of the processor

in the path of the airflow exiting the fan sink (see Figure 118 on

page 319). This location guarantees that the heatsinks on both

the processor and the regulator receive adequate air

circulation.

318

Thermal Design

Chapter 17

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Airflow

Ideal areas for voltage regulator

Figure 118. Airflow for a Heatsink with Fan

Airflow Management

in a System Design

Complete airflow management in a system is important. In

addition to the volume of air, the path of the air is also

important. Figure 119 shows the airflow in a dual-fan system.

The fan in the front end pulls cool air into the system through

intake slots in the chassis. The power supply fan forces the hot

air out of the chassis. The thermal performance of the heatsink

can be maximized if it is located in the shaded area, where it

receives greatest benefit from this air exchange system.

Fan

P/S

Main Board

V

e

n

t

Drive Bays

s

Fan

Vents

Front

Figure 119. Airflow Path in a Dual-Fan System

Chapter 17

Thermal Design

319

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Figure 120 shows the airflow management in a system using the

ATX form-factor. The orientation of the power supply fan and

the motherboard are modified in the ATX platform design. The

power supply fan pulls cool air through the chassis and across

the processor. The processor is located near the power supply

fan, where it can receive adequate airflow without an auxiliary

fan. The arrangement significantly improves the airflow across

the processor with minimum installation cost.

Main Board

F

P/S

a

n

Drive Bays

Figure 120. Airflow Path in an ATX Form-Factor System

For more information about thermal design considerations, see

®

the AMD-K6 Processor Thermal Solution Design Application

Note, order# 21085.

320

Thermal Design

Chapter 17

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

18

Pin Designations

This chapter includes pin connection diagrams and pin

designation tables for each of two packages, the Ceramic Pin

Grid Array (CPGA) and the Organic Ball Grid Array (OBGA).

The pin designation diagrams include the following

annotations:

Control/Parity Pins

V_SSPins

Address Pins

T

Test Pins

V_CC2Pins

NC, INC (Internal No Connect) Pins

RSVD (Reserved) Pins

V_CC3Pins

Data Pins

Note that the OBGA package includes additional pins not

supported on the CPGA package. Table 74 shows the pin

differences between the two packages.

Table 74. Pin Differences Between the CPGA and OBGA Packages

CPGA Package

Supported

OGBA Package

Not supported

Comment

VCC2DET

VCC2H/L#

Supported

These pins are no-connects

(NC) on standard-power

versions for both packages.

Supported on low-

power versions only

Supported on low-

power versions only

VID[4:0]

V_CC2

V_CC3

V_SS

28

32

68

37

26

99

13¹

8²

13¹

8²

No Connects

Internal

No Connects

7

1

Reserved

14

16

Notes:

1. Standard-power versions only, since the VID[4:0] outputs are not supported.

2. Low-power versions only.

Chapter 18

Pin Designations

321

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

18.1

Pins Designations for CPGA Package

B

D

F

H

K

M

P

R

T

V

X

Z

AB AD AF AH AK AM

AA AC AE AG AJ AL AN

A

C

E

G

J

L

N

Q

S

U

W

Y

37

36

35

V

ss

V

ss

NC

D9

V

cc3

V

cc3

A22

V

cc

3

ss

cc

3

cc

3

cc

3

cc

3

cc

3

cc

3

cc3

cc

3

cc

3

cc

3

36

35

V

D11

D13

D16

D20

DP0

V

ss

V

A28

A29

A5

D4

D5

A30

A4

ss

IGNNE# INC

INTR

ss

RSVD

TRST#

NC

TDI

D6

D2

ss

D15

D10

D14

D17

D21

INC

BF0

A25

A31

D1

A24

A27

VID1

BF2

STPCLK#

RSVD

A3

A7

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

TMS

A21

INC

VID2

V

cc3

D8

A26

TCK

D0

BF1

INC

SMI#

INIT

V

NC

A23

D18

D22

D7

TDO

A6

A10

V

RSVD

NMI

D3

cc

3

cc

3

D12

DP1

D19

D23

D26

VID0

A8

V

ss

A11

A12

ss

V

ss

A9

V

ss

V

cc3

V

cc

3

cc

3

V

ss

V

ss

A13

A15

A17

A19

V

ss

V

cc3

D24

A14

A16

cc

3

cc

3

V

ss

V

ss

VID3

V

cc3

V

DP2

D25

cc

3

V

ss

V

ss

V

NC

A18

A20

V

cc

3

cc

3

V

ss

D28

D30

DP3

ss

V

ss

D27

D29

V

cc3

V

cc

3

cc

3

Top

View

V

ss

RESET

ss

V

ss

V

NC

V

cc2

cc

3

cc

3

V

ss

CLK

ss

VID4

V

D31

D32

D34

D36

SCYC

V

cc

2

cc

2

V

BE7#

D33

ss

NC

V

cc2

BE6#

V

cc

2

cc

2

V

ss

BE5#

D35

ss

V

ss

V

cc2

ss

BE4#

cc

2

V

BE3#

BE1#

D37

D39

D40

ss

V

BE2#

V

cc2

ss

cc

2

cc

2

V

ss

V

ss

BE0#

V

D38

DP4

D45

D42

V

cc

2

cc

2

V

A20M#

V

ss

FLUSH#

W/R#

VCC2H/L#

V

ss

D46

D49

INC

cc

2

V

HIT#

ss

D44

D48

D50

DP5

D51

DP6

D

D41

D53

D55

D58

ADS#

D60

D61

V

PCD

RSVD APCHK#

FERR# RSVD

INV

KEN#

NA# WB/WT#

HITM#

DP7

D56

D43

V

RSVD M/IO# AHOLD#

LOCK#

D62

BRDY# BOFF# HOLD

PCHK#

D/C#

D59

RSVD

EADS#

V

ss

D47

NC

D52

D54

D57

RSVD

CACHE#

RSVD

EWBE#

SMIACT# HLDA

V

ss

D63

RSVD

BRDYC#

V

ss

RSVD

PWT

INC

RSVD

V

ss

V

ss

V

ss

ADSC#

VCC2DET

ss

cc2

AP

ss

INC

V

cc2

V

cc2

V

cc2

BREQ

cc

2

cc

2

cc

2

cc

2

cc

2

cc

2

cc

2

cc

2

cc

2

cc

2

B

D

F

H

K

M

P

R

T

V

X

Z

AB AD AF AH AK AM

AA AC AE AG AJ AL AN

A

C

E

G

J

L

N

Q

S

U

W

Y

Notes:

The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

Figure 121. CPGA Connection Diagram (Top-Side View)

322

Pin Designations

Chapter 18

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

AN

AM

AL

AK

AJ

AH

AG

AF

AN

AM

AL

V

VID1

INC

INC VCC2H/L# FLUSH#

V

cc2

A10

A11

A6

V

cc3

V

cc3

ss

cc2

cc3

V

A8

A30

ADSC# EADS# W/R#

ss

BE2# BE4#

D/C# HIT# A20M# BE1# BE3# BE5#

ss

A4

A29

A26

BE0#

PWT

INC

VCC2DET

AP

V

ss

SCYC

NC

HITM#

BE6#

A20

A12

A16

A14

A3

A25

A24

A7

A18

AK

AJ

BE7# CLK

V

RESET A19

V

A17

A15

A13

A9

A5

A28

A22

BREQ HLDA ADS#

V

ss

V

ss

V

ss

NC

A31

NC

ss

cc2

ss

cc3

ss

cc3

AH

AG

AF

AE

AD

AC

V

LOCK#

VID0

ss

SMIACT#

V

PCD

A27

cc2

cc3

V

PCHK#

V

ss

A21

A23 RSVD

AE

AD

V

APCHK#

cc2

RSVD

cc3

V

ss

V

INTR

INC

RSVD

ss

V

AC

AB

AA

Z

Y

X

W

V

cc2

NMI

RSVD

WB/WT#

NA#

cc3

AB

AA

Z

Y

X

W

V

SMI#

ss

HOLD

V

INIT

V

cc3

IGNNE#

V

INC

cc2

RSVD

V

BOFF#

ss

V

BRDYC#

INC

V

cc3

BF0

NC

cc2

V

ss

BRDY#

BF1

ss

V

EWBE#

BF2

KEN#

V

cc3

cc2

V

U

V

U

V

AHOLD

V

ss

STPCLK#

V

ss

Bottom

View

CACHE#

V

cc3

INV

ss

cc2

cc3

T

S

R

Q

P

N

T

S

R

Q

P

N

V

M/IO#

ss

V

cc3

V

cc3

NC

cc2

RSVD RSVD

RSVD

V

VID2

ss

V

TRST#

TDO

V

cc3

FERR#

RSVD

cc2

V

ss

RSVD

TMS

TDI

ss

V

cc2

DP7

D60

D58

D53

D49

D63

V

cc3

M

L

K

M

L

K

J

H

G

V

ss

D62

ss

TCK

V

cc2

D61

cc3

RSVD

cc3

V

ss

D59

D56

D51

D0

ss

J

H

G

V

cc2

RSVD

INC

D2

V

cc3

D57

D55

V

ss

V

D3

D1

cc2

V

cc3

F

E

D

C

F

E

D

C

DP6

D5

D4

DP5

D46

D40

DP4

D54

D52

D42

D39

V

VID4

DP3

V

VID3

D23

V

ss

V

ss

D7

D6

D10

D15

V

ss

cc2

D33

D32

ss

cc3

ss

cc3

D48

D47

D43

D44

D37

D36

D35

D30

D28

D27

D26

D19

DP1

D20

D12

D16

D8

DP0

D11

NC

D45

D38

D34

D31 D29

D25

DP2 D24

D21

D17

D22

D14

D18

D9

B

A

B

A

V

ss

V

ss

V

ss

V

ss

V

ss

D13

cc2

ss

V

D41

V

cc3

NC

ss

cc2

cc3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Notes:

The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

Figure 122. CPGA Connection Diagram (Bottom-Side View)

Chapter 18

Pin Designations

323

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 75. CPGA Pin Designations by Functional Grouping

Pin Name

Pin Number

Pin Name

Pin Number

Pin Name

Pin Number

Data

Pin Name

Pin Number

Data

Control

Address

A20M#

ADS#

ADSC#

AHOLD

APCHK#

BE0#

BE1#

BE2#

BE3#

BE4#

BE5#

BE6#

BE7#

BF0

BF1

BF2

AK-08

AJ-05

AM-02

V-04

A3

A4

A5

A6

A7

A8

A9

AL-35

AM-34

AK-32

AN-33

AL-33

AM-32

AK-30

AN-31

AL-31

AL-29

AK-28

AL-27

AK-26

AL-25

AK-24

AL-23

AK-22

AL-21

AF-34

AH-36

AE-33

AG-35

AJ-35

AH-34

AG-33

AK-36

AK-34

AM-36

D0

D1

D2

D3

D4

D5

D6

D7

K-34

G-35

J-35

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

E-03

G-05

E-01

G-03

H-04

J-03

G-33

F-36

F-34

E-35

E-33

D-34

C-37

C-35

B-36

D-32

B-34

C-33

A-35

B-32

C-31

A-33

D-28

B-30

C-29

A-31

D-26

C-27

C-23

D-24

C-21

AE-05

AL-09

AK-10

AL-11

AK-12

AL-13

AK-14

AL-15

AK-16

Y-33

X-34

W-35

Z-04

X-04

Y-03

J-05

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

K-04

L-05

L-03

M-04

N-03

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

Test

TCK

TDI

TDO

TMS

TRST#

M-34

N-35

N-33

P-34

Q-33

BOFF#

BRDY#

BRDYC#

BREQ

CACHE#

CLK

Parity

AJ-01

U-03

AP

AK-02

D-36

D-30

C-25

D-18

C-07

F-06

F-02

N-05

DP0

DP1

DP2

DP3

DP4

DP5

DP6

DP7

AK-18

AK-04

AM-04

W-03

Q-05

AN-07

AK-06

D/C#

EADS#

EWBE#

FERR#

FLUSH#

HIT#

HITM#

HLDA

HOLD

IGNNE#

INIT

INTR

INV

KEN#

LOCK#

M/IO#

NA#

NMI

PCD

PCHK#

PWT

RESET

SCYC

Voltage ID¹

AL-05

A31

AJ-33

D28

D-22

AJ-03

AB-04

AA-35

AA-33

AD-34

U-05

W-05

AH-04

T-04

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D50

D51

C-19

D-20

C-17

C-15

D-16

C-13

D-14

C-11

D-12

C-09

D-10

D-08

A-05

E-09

B-04

D-06

C-05

E-07

C-03

D-04

E-05

D-02

F-04

VID4

VID3

VID2

VID1

VID0

E-17

E-25

R-34

AN-35

AH-32

Y-05

AC-33

AG-05

AF-04

AL-03

AK-20

AL-17

AB-34

AG-03

V-34

AL-01

AN-05

AM-06

AA-05

SMI#

SMIACT#

STPCLK#

VCC2DET

VCC2H/L#

W/R#

WB/WT#

Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

324

Pin Designations

Chapter 18

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 76. CPGA Pin Designations for No Connect, Reserved, Power, and Ground Pins

Pin Numbers

V_CC2

V_CC3

V_SS

No Connect (NC)

AJ-27

AJ-31

AJ-37

AL-37

AM-08

AM-10

AM-12

AM-14

AM-16

AM-18

AM-20

AM-22

AM-24

A-37

C-01

A-07

A-09

A-11

A-19

A-21

A-23

A-03

B-06

B-08

E-17¹

E-25¹

A-13

A-25

B-10

R-34¹

S-33

S-35

W-33

AH-32¹

AJ-15

AJ-23

AL-19

AN-35¹

A-15

A-17

B-02

E-15

G-01

J-01

L-01

N-01

Q-01

A-27

A-29

E-21

E-27

E-37

G-37

J-37

B-12

B-14

B-16

B-18

B-20

B-22

B-24

B-26

B-28

L-33

L-37

S-01

U-01

N-37

E-11

AM-26

Internal No Connect (INC)

H-34

Q-37

S-37

T-34

U-33

U-37

W-37

Y-37

E-13

E-19

E-23

E-29

E-31

H-02

H-36

AM-28

AM-30

AN-37

Y-35

Z-34

AC-35

AL-07

AN-01

AN-03

W-01

Y-01

AA-01

AC-01

AE-01

AG-01

AJ-11

AA-37

K-02

K-36

M-02

M-36

P-02

P-36

R-02

R-36

T-02

T-36

U-35

V-02

V-36

X-02

Reserved (RSVD)

J-33

L-35

P-04

Q-03

Q-35

R-04

S-03

S-05

AA-03

AC-03

AC-05

AD-04

AE-03

AE-35

AN-09

AN-11

AN-13

AN-15

AN-17

AN-19

AC-37

AE-37

AG-37

AJ-19

AJ-29

AN-21

AN-23

AN-25

AN-27

AN-29

X-36

Z-02

Z-36

AB-02

AB-36

AD-02

AD-36

AF-02

AF-36

AH-02

AJ-07

AJ-09

AJ-13

AJ-17

AJ-21

AJ-25

Notes: 1. These pins are no-connects on standard-power versions only. They are defined as VID[4:0] on low-power versions. See page 324.

Chapter 18

Pin Designations

325

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

18.2

Pins Designations for OBGA Package

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

D52

DP5

NC

D47

D45

D40

D39

D37

D33

VID4

D29

D28

D26

D23

D20

D16

A

B

C

D

E

A

B

C

D

E

V

D51

D44

D46

D48

D41

DP4

D32

D35

D34

D30

D27

DP2

D24

D13

D19

D22

D17

CC3

DP1

D14

D8

SS

V

DP6

D59

D54

D58

D50

D49

D53

D43

D42

D38

D36

DP3

D31

D25

D21

VID3

D15

D18

D10

D9

CC2

SS

V

D56

D12

CC2

SS

V

D60

D55

D57

D63

D7

D11

CC3

SS

CC2

SS

V

DP7

D62

D61

D3

D5

D6

CC3

F

CC2

F

SS

V

RSVD

V

RSVD

V

RSVD

V

FERR#

DP0

D4

D1

CC3

G

H

J

CC2

G

H

J

SS

V

RSVD

V

D0

D2

CC3

CC2

SS

CC2

SS

T

V

TDO

RSVD

TCK

INV

M/IO# CACHE#

CC3

SS

CC2

SS

T

V

RSVD

TRST#

TMS

TDI

BRDY# KEN# EWBE# AHOLD

CC3

K

CC2

K

L

SS

V

BRDYC#

BOFF#

NA#

NC

BF1

BF0

INIT

NMI

A21

A26

VID2

NC

CC3

L

M

N

P

CC2

SS

V

RSVD

V

WB/WT# HOLD

NC

INC

INTR

A28

STPCLK#

CC3

CC2

SS

CC2

SS

M

N

P

R

T

V

RSVD

V

BF2

CC3

SS

CC2

SS

V

RSVD

V

RSVD

V

SMIACT# PCHK# BREQ

SMI# IGNNE#

CC3

SS

CC2

SS

V

SS

RSVD

A22

APCHK#

AP

PCD

CC3

R

CC2

SS

V

A20

A19

A18

A16

NC

A8

A4

A3

A7

A6

A27

A31

V

A24

LOCK# HLDA ADSC#

NC

FLUSH# BE5#

NC

T

CC2

SS

V

A15

A10

A13

A29

A30

A23

ADS#

D/C#

HITM#

EADS#

W/R#

BE0#

BE2#

BE4#

BE6#

BE7#

CLK

CC3

U

V

U

V

W

SS

V

A25

PWT

CC3

CC2

SS

CC2

SS

A17

A14

A12

A11

A9

A5

HIT#

A20M#

BE1#

BE3#

NC

SCYC

RESET

VID1

VID0

W

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

Notes:

There are three pads missing on each corner of the OBGA package due to manufacturing requirements.

The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

Figure 123. OBGA Connection Diagram (Top-Side View)

326

Pin Designations

Chapter 18

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

RSVD

D59

D60

DP6

DP7

D62

D61

D63

INV

BRDY# BRDYC#

APCHK# LOCK# ADS#

1

2

1

2

V

RSVD

V

KEN#

V

SS

D51

D56

D58

WB/WT#

SMIACT#

PCHK#

BREQ

HLDA

PWT

CC2

SS

CC2

SS

CC2

SS

CC2

RSVD

V

D52

DP5

D47

D45

D40

D39

D37

D33

VID4

D29

D28

D26

D23

D20

D16

V

D54

D50

D49

D46

D43

DP4

D38

D35

DP3

D27

D25

D24

VID3

D22

DP1

D55

D57

M/IO# EWBE# BOFF# HOLD

AP

ADSC#

D/C#

HIT#

3

SS

CC2

V

NC

FERR#

CACHE# AHOLD

NA#

PCD

HITM# EADS# A20M#

4

CC2

V

D53

D48

D42

V

NC

W/R#

BE0#

BE1#

BE3#

NC

5

SS

CC2

SS

CC2

SS

CC2

SS

CC2

SS

CC2

SS

CC2

SS

V

D44

V

BE2#

6

SS

CC2

SS

CC2

SS

CC2

SS

CC2

SS

CC2

SS

V

FLUSH# BE4#

7

SS

CC2

SS

CC2

SS

CC2

V

RSVD

D41

BE5#

NC

BE6#

CLK

A19

NC

BE7#

SCYC

RESET

A17

8

SS

CC2

SS

V

D36

D34

D31

V

9

SS

CC2

SS

V

A20

A16

A8

A18

D32

V

CC3

10

11

12

13

14

15

16

17

18

19

10

11

12

13

14

15

16

17

18

19

SS

CC2

SS

V

A14

CC3

SS

CC2

SS

V

D30

V

A15

A13

A7

A10

A12

CC3

SS

V

D21

D13

D15

V

A4

V

A11

CC3

SS

V

A3

A6

A9

DP2

CC3

SS

V

A27

A31

A29

A26

A5

CC3

SS

T

V

RSVD

DP0

RSVD

D19

V

D7

D8

D11

D3

TDO

V

A28

V

A30

NC

BF1

INC

BF0

INTR

INIT

VID1

VID0

CC3

SS

T

V

RSVD

D14

D12

D4

D0

TRST#

A21

A24

V

NC

NMI

CC3

SS

T

V

D17

V

D5

V

TMS

V

A25

STPCLK#

SMI#

CC3

SS

T

RSVD

D18

D10

D9

D6

D1

D2

TCK

TDI

A22

A23

VID2

NC

BF2

IGNNE#

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Notes:

There are three pads missing on each corner of the OBGA package due to manufacturing requirements.

The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

Figure 124. OBGA Connection Diagram (Bottom-Side View)

Chapter 18

Pin Designations

327

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 77. OBGA Pin Designations by Functional Grouping

Pin Name

Pin Number

Pin Name

Pin Number

Pin Name

Pin Number

Data

Pin Name

Pin Number

Data

Control

Address

A20M#

ADS#

ADSC#

AHOLD

APCHK#

BE0#

W4

U1

T3

K4

R1

U6

W5

V6

W6

U7

T8

U8

V8

N17

M17

N19

L3

K1

L1

P4

A3

T14

T13

W15

V14

U14

T12

W14

V12

W13

W12

U13

W11

U12

T11

W10

V10

U10

T10

T17

T19

U19

T18

V18

U17

T15

R16

U16

V16

D0

D1

D2

D3

D4

D5

D6

D7

H18

G19

H19

F17

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

A3

D5

C3

E3

D2

E4

D3

D1

E1

F3

F2

F4

A4

A5

A6

A7

A8

A9

H17

F18

F19

E16

E17

E19

D19

F16

D18

D14

D17

D15

A17

B18

C19

B16

A16

D13

C16

A15

C14

C13

A14

C12

BE1#

BE2#

BE3#

BE4#

BE5#

BE6#

BE7#

BF0

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

Test

TCK

TDI

TDO

TMS

TRST#

J19

K19

J16

K18

K17

BF1

BF2

BOFF#

BRDY#

BRDYC#

BREQ

CACHE#

CLK

Parity

AP

R3

J4

DP0

DP1

DP2

DP3

DP4

DP5

DP6

DP7

G17

C17

B14

C11

C8

A4

C1

U9

U3

V4

K3

G4

T7

W3

U4

T2

M3

P19

P17

P16

J1

K2

T1

J3

L4

R17

R4

P3

D/C#

EADS#

EWBE#

FERR#

FLUSH#

HIT#

F1

Voltage ID¹

HITM#

A31

U15

D28

A13

HLDA

HOLD

IGNNE#

INIT

INTR

INV

KEN#

LOCK#

M/IO#

NA#

NMI

PCD

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D50

D51

A12

B12

D11

B10

A10

D10

C10

D9

A9

C9

A8

A7

B8

D7

C7

B6

A6

C6

A5

D6

C5

C4

B2

VID0

VID1

VID2

VID3

VID4

W17

W16

L19

C15

A11

PCHK#

PWT

RESET

SCYC

V2

W9

W8

P18

P2

M18

U5

M2

SMI#

SMIACT#

STPCLK#

W/R#

WB/WT#

Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

328

Pin Designations

Chapter 18

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 78. OBGA Pin Designations for No Connect, Reserved, Power, and Ground Pins

Pin Numbers

V_CC2

V_CC3

V_SS

B3

B5

B7

V_SS

No Connect (NC)

A11¹

B4

C2

D4

E5

F6

F7

B13

B17

E18

F14

G15

H10

H11

H12

H13

H14

H16

J15

K13

K15

L6

L7

L8

C15¹

L17

L19¹

M16

M19

T5

T9

U11

W7

W16¹

W17¹

B9

B11

B15

C18

D8

D12

D16

E2

F8

F9

L9

L10

L11

L12

L13

L14

L16

F10

F11

G2

G5

H4

H6

H7

J5

K6

K7

K8

K9

E6

E7

J18

L18

K14

L15

M14

E8

E9

E10

E11

E12

E13

E14

E15

F5

F12

F13

F15

G6

G7

G8

G9

G10

G11

G12

G13

G14

G18

H5

H8

H9

H15

J2

M5

M12

M13

M15

N2

N6

N7

N8

N9

N10

N11

N12

N13

N14

P5

P7

P9

P10

P13

P15

R6

Internal No Connect (INC)

N16

Reserved (RSVD)

G1

G3

G16

H1

H2

H3

J17

K16

M1

N1

N3

N4

P1

N15

N18

P11

P12

P14

R10

R13

U18

V11

V15

K10

K11

L2

L5

M4

M6

M7

M8

M9

M10

M11

N5

P6

R2

R5

T4

V3

P8

R8

R19

R7

R9

V7

R11

R12

R14

R15

R18

T6

J6

J7

J8

J9

T16

U2

J10

J11

J12

J13

J14

K5

V5

V9

V13

V17

K12

Notes: 1. These pins are no-connects on standard-power versions only. They are defined as VID[4:0] on low-power versions. See page 328.

Chapter 18

Pin Designations

329

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

330

Pin Designations

Chapter 18

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

19

Package Specifications

19.1

321-Pin Staggered CPGA Package Specification

Figure 125. 321-Pin Staggered CPGA Package Specification

Chapter 19 Package Specifications

331

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

19.2

349-Ball OBGA Package Specification

Dwg rev. AA.04; 08/00

Figure 126. 349-Ball OBGA Package Specification

332

Package Specifications

Chapter 19

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

20

Ordering Information

Standard AMD-K6-2E+ Embedded Processor Products

AMD standard products are available in several operating ranges. The ordering part

number (OPN) is formed by a combination of the elements below. See Table 79 on

page 334 for valid ordering part number combinations.

AMD-K6-2E+ /500

A C R

Case Temperature

R = 0°C–70°C

Z = 0°C–85°C

Operating Voltage

U = 1.4 V–1.6 V (Core)/ 3.135 V–3.6 V (I/O)

T = 1.5 V–1.7 V (Core)/ 3.135 V–3.6 V (I/O)

P = 1.6 V–1.8 V (Core)/ 3.135 V–3.6 V (I/O)

C = 1.9 V–2.1 V (Core)/ 3.135 V–3.6 V (I/O)

Package Type

A = 321-pin CPGA

I = 349-ball OBGA

Performance Rating

/500

/450

/400

/350

Family/Core

AMD-K6-2E+

Chapter 20

Ordering Information

333

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Table 79. AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Combinations

Device

Type

Case

Temperature

Maximum CPU/Bus

Frequency

1

Package Type

321-pin CPGA

349-ball OBGA

321-pin CPGA

349-ball OBGA

Operating Voltage

OPN

1.4 V–1.6 V (Core)

3.135 V–3.6 V (I/O)

AMD-K6-2E+/350AUZ

AMD-K6-2E+/400ATZ

AMD-K6-2E+/450APZ

AMD-K6-2E+/350IUZ

AMD-K6-2E+/400ITZ

AMD-K6-2E+/400ACR

AMD-K6-2E+/450ACR

AMD-K6-2E+/500ACR

AMD-K6-2E+/400ICR

AMD-K6-2E+/450ICR

0°C–85°C

0°C–70°C

350 MHz/100 MHz

400 MHz/100 MHz

450 MHz/100 MHz

350 MHz/100 MHz

400 MHz/100 MHz

450 MHz/100 MHz

500 MHz/100 MHz

400 MHz/100 MHz

450 MHz/100 MHz

1.5 V–1.7 V (Core)

3.135 V–3.6 V (I/O)

Low

Power

1.6 V–1.8 V (Core)

3.135 V–3.6 V (I/O)

1.4 V–1.6 V (Core)

3.135 V–3.6 V (I/O)

1.5 V–1.7 V (Core)

3.135 V–3.6 V (I/O)

1.9 V–2.1 V (Core)

3.135 V–3.6 V (I/O)

1.9 V–2.1 V (Core)

3.135 V–3.6 V (I/O)

Standard

Power

1.9 V–2.1V (Core)

3.135 V–3.6 V (I/O)

1.9 V–2.1 V (Core)

3.135 V–3.6 V (I/O)

1.9 V–2.1 V (Core)

3.135 V–3.6 V (I/O)

Notes:

1. This table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly-released combinations.

334

Ordering Information

Chapter 20

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Index

Airflow

consideration in layout . . . . . . . . . . . . . . . . . . . . . . . . . . .317

Numerics

0.18-Micron Process Technology . . . . . . . . . . . . . . . . . . . . . . . 7

100-MHz Bus

heatsink with fan (figure). . . . . . . . . . . . . . . . . . . . . . . . .319

management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

path in a dual-fan system (figure) . . . . . . . . . . . . . . . . . .319

path in an ATX form-factor system (figure) . . . . . . . . . .320

Aligned Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Allocate, Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

clock switching characteristics . . . . . . . . . . . . . . . . . . . . 296

frontside. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 8

input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 300

output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

AMD PowerNow!™ Technology . . . . . . . . . . . 6, 143, 151, 275

disabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

dynamic core voltage control . . . . . . . . . . . . . . . . . . . . . .151

enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

enhanced power management register (EPMR) . . . . . .144

EPM 16-byte I/O block . . . . . . . . . . . . . . . . . . . . . . . . . . .146

EPM stop grant state. . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

I/O base address definition. . . . . . . . . . . . . . . . . . . . . . . .145

processor state observability register (PSOR) . . . . . . . .148

SMM handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . .1, 8

321-Pin Staggered CPGA Package . . . . . . . . . . . . . . . . . . . . . 2

specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

349-Ball OBGA Package

specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

3DNow!™ Technology. . . . . . . 2, 5, 7, 15, 17, 19, 21–24, 127

data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

INIT state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

instruction compatibility, floating-point and. . . . . . . . . 240

voltage identification signals . . . . . . . . . . . . . . . . . 137, 151

AP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

APCHK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Asserted signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89–90, 240

PREFETCH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 220

register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

RESET state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

software prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

66-MHz Bus

clock switching characteristics . . . . . . . . . . . . . . . . . . . . 297

input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 304

output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

B

Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

BDC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

BE[7:0]# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 199, 283

BIOS, enhanced power management. . . . . . . . . . . . . . . . . .145

BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

A

A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

BOFF# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 182

locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Boundary-Scan

bit definitions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

test access port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

BR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

Branch

A20M# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94, 242

masking cache accesses with. . . . . . . . . . . . . . . . . . . . . . 227

Absolute Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Accelerated Graphic Port (AGP). . . . . . . . . . . . . . . . . . . . . . . 8

Acknowledge, Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Address

bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100, 109

A[31:3] signals] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

address hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

address strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

AHOLD restriction . . . . . . . . . . . . . . . . . . . 174, 178, 180

coherencey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98–99

generation sequence during bursts (table) . . . . . . . . . . 162

hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

parity check signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

parity signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

ADS# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

ADSC# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

AGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

AHOLD

execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 7, 15, 23, 26

target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

BRDY# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

BRDYC# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

BREQ Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

BSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Burst

pipelined burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

ready copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104, 200

writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

writeback due to cache-line replacement . . . . . . . .164–165

Bus

-initiated inquire hit to modified line. . . . . . . . . . . . . . . 178

-initiated inquire hit to shared or exclusive line . . . . . . 176

-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

100-MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 8

address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

A[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

AHOLD restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

AHOLD Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97, 278

Index

335

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

external address strobe signal. . . . . . . . . . . . . . . . . . . 109

hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . .100, 174

parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98–99

strobe copy signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 168

backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

byte enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153–197

aligned transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

definitions (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

order during misaligned I/O transfers (table) . . . . . . 167

order during misaligned memory transfers (table). . 160

special . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142, 190

data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 103, 174

AHOLD restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

aligned transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

byte enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

memory reads and writes. . . . . . . . . . . . . . . . . . . . . . . 158

misaligned transfers. . . . . . . . . . . . . . . . . . . . . . .129, 184

parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108, 125

state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

frequency signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

hold request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

lock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

states

address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

data-NA# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

state machine (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 155

transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

BVC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

definition (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

BVCM Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Bypass Register (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

instruction fetch and decode . . . . . . . . . . . . . . . . . . . . . . .17

instruction prefetch. . . . . . . . . . . . . . . . . . . . . . . 16–17, 220

L1 cache

cache-line replacement. . . . . . . . . . . . . . . . . . . . . . . . .214

coherency states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

data cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . .207

instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

instruction cache line (figure) . . . . . . . . . . . . . . . . . . .207

internal snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

L2 cache

cache line (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

cache-line replacement. . . . . . . . . . . . . . . . . . . . . . . . .214

data reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

direct access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

disabling for debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

EDX register content . . . . . . . . . . . . . . . . . . . . . . . . . .265

Level-2 Cache Array Access Register (L2AAR). . . . . .50

organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

RDMSR instruction effect . . . . . . . . . . . . . . . . . . . . . .265

sector and line organization (figure). . . . . . . . . . . . . .265

tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . 213, 264

tag information (figure) . . . . . . . . . . . . . . . . . . . . . . . . .52

tag or data location (figure) . . . . . . . . . . . . . . . . . . . . . .51

testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

WRMSR instruction effect . . . . . . . . . . . . . . . . . . . . . .265

L3 cache

debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

PCD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

Level-2 Cache Array Access Register (L2AAR) . . . . . . .264

-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213, 264

-line replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . 214, 224

masking cache accesses with A20M# . . . . . . . . . . . . . . .227

MESI states in the data. . . . . . . . . . . . . . . . . . . . . . . . . . .207

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17, 208

prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17, 220

sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . .16

signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . . .8

total internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

TR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

translation lookaside buffers (TLBs). . . . . . . . . . . . . . . .205

write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

write cycle order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

write to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . .216

C

Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

branch target. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

burst writeback cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

cacheable access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 16

writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

CACHE# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

capacitor placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

large capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

disabling . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 211, 251, 263

enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112, 191

inhibiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251, 263

inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . 168, 174, 178

inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

336

Index

Preliminary Information

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

Capture-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Capture-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

measuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

CLK

writeback . . . . . . 94, 96–97, 110, 113, 139, 164, 172, 176,

. . . . . . . . . . . . . . . . . . . . . 178, 180, 186, 210, 264, 277, 280

D

D/C# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

D[63:0] Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Data

switching characteristics

100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 296

60-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 297

CLK Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

bus

AHOLD restriction . . . . . . . . . . . . . . . . . . . . . . . . 97, 180

AHOLD timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

aligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

BRDY# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

byte enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

D[63:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

data state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

memory reads and writes . . . . . . . . . . . . . . . . . . . . . . .158

misaligned transfers . . . . . . . . . . . . . . . . . . . . . . 129, 184

parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 125

split cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

MESI states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

types

3DNow!™ Technology. . . . . . . . . . . . . . . . . . . . . . . . . . .37

floating-point register. . . . . . . . . . . . . . . . . . . . . . . . . . .34

integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Data/Code Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Data-NA# Requested State. . . . . . . . . . . . . . . . . . . . . . . . . .156

DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105, 275

states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

enhanced power management stop grant . . . . . . . . . 275

halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

state transitions (figure) . . . . . . . . . . . . . . . . . . . 276–277

stop clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193, 283

stop grant. . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 278, 281

stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

switching characteristics

100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 296

66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 297

Coherency

cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Compatibility, Floating-Point, MMX, and 3DNow!

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Configuration

power-on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

signal timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

signal timing for 100-MHz bus operation (table). . . . . . 306

signal timing for 66-MHz bus operation . . . . . . . . . . . . . 307

VCC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Connections

pin requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Counter, Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

pin designations (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 322

pin designations by function (table). . . . . . . . . . . . . . . . 324

pin differences (table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

CR4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Cycles

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 269

DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

System Management Mode (SMM) . . . . . . . . . . . . .249–250

Decoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . .292

Descriptors and Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Device Identification Register (DIR) . . . . . . . . . . . . . . . . .258

Diagrams

key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153, 309–312

waveform definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Digital Signal Processing Instructions . . . . . . . . . . . . . . . . .90

DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

Dissipation, Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

DP[7:0] Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

Driven signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

hold and hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . 168

inquire . . . 94–99, 109, 113–114, 131, 139, 164, 168, 170,

. . . .172, 174, 176–178, 182, 186, 222, 263, 275, 278–280

inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 168

interrupt acknowledge . . . . . . . .95, 98, 100, 106, 123, 138

locked. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17, 96

pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

DSP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 239

Dual Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

Index

337

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 24

E

throughput (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

EADS# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

EAS Register

Extended Feature Enable Register (EFER) . 44, 47, 202, 229

External

address strobe signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

write buffer empty signal. . . . . . . . . . . . . . . . . . . . . . . . .110

EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . 46

EAX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

BIST results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

cache accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

EBF Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

EBP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EBX Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ECX Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28, 46

EDI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

F

FEMMS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

FERR# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 111, 238, 240

Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136, 141

Floated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Floating-Point

and MMX/3DNow! instruction compatibility . . . . . . . . .240

and multimedia execution units . . . . . . . . . . . . . . . . . . .237

error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

register data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

cache accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50–51

stepping ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . 46

EFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 47, 202, 229

Effective Bus Frequency Divisor Field . . . . . . . . . . . . . . . . 150

EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38, 242

EIP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Embedded Processor Features . . . . . . . . . . . . . . . . . . . . . . . . 1

EMMS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

EN Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Enhanced Power Management

FLUSH# Signal . . . . . . . . . . . . . . . . . .112, 199, 223, 252, 278

FPU

control word register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

status word register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

tag word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 283, 296–297, 308

control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

special bus cycle (table). . . . . . . . . . . . . . . . . . . . . . . . . . 142

special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Enhanced Power Management Register (EPMR) . . . . . . . 144

EPM 16-Byte I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . .142, 150

control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

voltage identification output state . . . . . . . . . . . . . . . . . 147

EPMR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 144

ESI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ESP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EWBE# Control (EWBEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 229

operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 105, 199

G

Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59, 62

General-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .28

Generate Special Bus Cycle Bit . . . . . . . . . . . . . . . . . . . . . .145

Global EWBE# Disable (GEWBED). . . . . . . . . . . . . . . . . . .230

Ground

pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329

plane capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

pulldown resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

split planes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

unused active high inputs. . . . . . . . . . . . . . . . . . . . . . . . .293

GSBC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

EWBE# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 229, 278

Exception. . . . 98–99, 108, 125, 192, 240, 249–250, 272–274

debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32–33

floating-point. . . . . . . . . . . . . . . . . . 111, 116, 237–238, 240

handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

handling floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . 237

machine check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

MMX technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

summary (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

System Management Mode (SMM). . . . . . . . . . . . . . . . . 250

Execution

latency (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 26

execution latency (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 23

floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 21, 237

H

Halt

restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278

Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

Hit to

modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

modified line, AHOLD-initiated inquire. . . . . . . . . . . . .178

modified line, HOLD-initiated inquire . . . . . . . . . . . . . .172

shared or exclusive line, AHOLD-initiated inquire . . . .176

shared or exclusive line, HOLD-initiated inquire . . . . .170

HIT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

HITM# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

HLDA Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 23–24, 239

register X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 24

338

Index

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Hold

MMX technology (table) . . . . . . . . . . . . . . . . . . . . . . . . . . .86

pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

acknowledge signal. . . . . . . . . . . . . . . . . . . . . .114, 168–170

HOLD Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

-initiated inquire hit to modified line. . . . . . . . . . . . . . . 172

-initiated inquire hit to shared or exclusive line . . . . . . 170

PREFETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 220

RSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241

serializing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

supported by the processor (table) . . . . . . . . . . . . . . . . . .63

Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . .259

WBINVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295, 310

Integer

data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Interrupts . . . . . . . . . 130, 188, 192, 196, 237–238, 240, 242,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250, 273, 280

01h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

03h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

acknowledge. . . . . . . 95, 103, 106, 118, 120, 125, 184, 188

acknowledge cycle definition (table) . . . . . . . . . . . . . . .188

acknowledge cycles . . . . . . . . . . 95, 98, 100, 106, 123, 138

clock grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

descriptor table register . . . . . . . . . . . . . . . . . . . . . . . . . . .54

flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 118, 130

I

I/O

misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . . 167

read and write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

IBF Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

IEEE 1149.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 253

IEEE 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 31, 237

IEEE 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

IGNNE# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 116, 238, 240

Ignore Numeric Exception. . . . . . . . . . . . . . . . . . . . . . . . . . 116

INIT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117, 242, 278

-initiated transition from protected mode to real mode 196

processor state after. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

output signal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

power-on configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 199

processor state after INIT . . . . . . . . . . . . . . . . . . . . . . . . 203

processor state after RESET . . . . . . . . . . . . . . . . . . . . . . 200

register state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

signals sampled during RESET. . . . . . . . . . . . . . . . . . . . 199

Input

floating-point exceptions . . . . . . . . . . . . . . . . . . . . .237–238

gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196, 242

INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

IRQ13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

MMX instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 203, 242

redirection bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

service routine . . . . . . . . . . . . . . . . . . . . . 118, 123, 238, 241

STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

summary (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241

type of. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

INTR Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 278

INV Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Invalidation Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

INVD Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

IOBASE Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

pin float conditions (table) . . . . . . . . . . . . . . . . . . . . . . . 141

pin types (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

setup and hold timing

100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 300

66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 304

Input/Output (I/O)

capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171, 173, 175, 275

bus arbitration cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

cycle hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

cycle hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . 113

K

KEN# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

cycles . . . . . . . . .94–99, 109, 113–114, 131, 139, 164, 168,

. . . . . . . . . . . 170, 172, 174, 176–178, 180, 182, 186, 222,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263, 275, 278–280

miss, AHOLD-initiated. . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

L

L1 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

cache line (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

cache-line replacements . . . . . . . . . . . . . . . . . . . . . . . . . .214

coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222, 227

data cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . . .207

disabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 211–212

flushing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

instruction cache line (figure) . . . . . . . . . . . . . . . . . . . . .207

internal snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

MESI states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . .16

3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . .89–90, 239

3DNow!™ technology (table). . . . . . . . . . . . . . . . . . . . 89–90

cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

digital signal processing. . . . . . . . . . . . . . . . . . . . . . . . . . 239

digital signal processing (table) . . . . . . . . . . . . . . . . . . . . 90

EMMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FEMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

floating-point (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

integer (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

MMX technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . .86, 239

Index

339

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Memory

states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . .221, 225–226

write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

management registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

or I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

read and write, misaligned single-transfer. . . . . . . . . . .160

read and write, single-transfer. . . . . . . . . . . . . . . . . . . . .158

reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

type range registers (MTRR) . . . . . . . . . . . . . . . . . . 49, 231

MESI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 168, 172, 206, 227

L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . 112–113, 139, 142

access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

built-in self test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

cache sector and line organization (figure) . . . . . . . . . . 265

cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

cache-line replacements. . . . . . . . . . . . . . . . . . . . . . . . . . 214

coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

data location (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

data reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

direct access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211–212

disabling for debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

least recently used (LRU) algorithm . . . . . . . . . . . . . . . 215

Level-2 Cache Array Access Register (L2AAR). . . . . . . . 50

LRU field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

MESI states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 207, 209

states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . .207

Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 11–26

branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

enhanced RISC86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

instruction fetching and decode . . . . . . . . . . . . . . . . . . . .17

instruction prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

predecode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Misaligned

I/O read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

I/O transfers (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

memory transfers (table) . . . . . . . . . . . . . . . . . . . . . . . . .160

single-transfer memory read and write. . . . . . . . . . . . . .160

transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

organization (figure). . . . . . . . . . . . . . . . . . . . . . . . .206, 265

predecode bits not stored. . . . . . . . . . . . . . . . . . . . . . . . . 208

prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . 16

states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . .221, 225–226

Super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

T/D bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . . . .213, 264

tag information (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

tag location (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

MMX Technology. . . . . . . . . . . . . . . . . . . . . . . . 19, 21–24, 127

3DNow!™ registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

INIT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

instruction compatibility, floating-point and . . . . . . . . .240

instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

RESET state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . .44

MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

MTRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49, 231

Multimedia

and 3DNow!™ execution units. . . . . . . . . . . . . . . . . . . . .239

execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 239

functional unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

L2AAR . . . . . . . . . . . . . . . . . . . . . . . 44, 50, 212–213, 264–266

L3 Cache

debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

PCD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Latency, execution (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . 317

Level-2 Cache Array Access Register (L2AAR). . . . . 264–266

Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

LOCK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Locked

cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

operation with BOFF# intervention . . . . . . . . . . . . . . . . 186

operation, basic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Logic

branch-prediction . . . . . . . . . . . . . . . . . . . . . . 15, 23, 25–26

external support of floating-point exceptions . . . . . . . . 238

symbol (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

N

NA# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Negated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Next Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

NMI Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 242, 278

No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128, 293

Non-Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Non-Pipelined Single-Transfer Memory Read/Write and

Write Delayed by EWBE#. . . . . . . . . . . . . . . . . . . . .159

Normal State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

Low-Power Devices . . . . . . . . . . . . . . . . . . . . . 4, 286, 289, 334

M

M/IO# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Machine Check Address Register (MCAR) . . . . . .44–45, 202

Machine Check Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Machine Check Type Register (MCTR) . . . . . . . . .44–45, 202

Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44–45, 202

O

OBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2–3

pin designations (figure) . . . . . . . . . . . . . . . . . . . . . . . . .326

pin designations by function (table) . . . . . . . . . . . . . . . .328

pin differences (table) . . . . . . . . . . . . . . . . . . . . . . . . . . .321

specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332

MCTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44–45, 202

340

Index

Preliminary Information

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

OPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Ordering Part Number (OPN) . . . . . . . . . . . . . . . . . . . . . . . 333

Output

management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

management, enhanced . . . . . . . . . . . . . . . . . . . . . . . . . .143

plane capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

PowerNow! Technology. See AMD PowerNow!™ Technology.

Power-on Configuration and Initialization . . . . . . . . . . . . .199

Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . .34

Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17, 208

PREFETCH Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

PREFETCH instruction . . . . . . . . . . . . . . . . . . . . . . . . . .220

software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Processor

absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

AMD PowerNow!™ technology. . . . . . . . . . . . . . . . . . . . .143

block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

cache organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 205

clock control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

logic symbol (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

delay timings

100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 298

66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 302

leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

pin float conditions (table) . . . . . . . . . . . . . . . . . . . . . . . 141

signal state after RESET (table). . . . . . . . . . . . . . . . . . . 200

P

Package

Socket 7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Super7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . 34

Page

cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

directory entry (PDE). . . . . . . . . . . . . . . . . . . . . .57–58, 209

flush/invalidate register (PFIR) . . . . . . . . . . . . . . . . . . . 223

table entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 57, 59, 209

writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

low-power devices . . . . . . . . . . . . . . . . . . . . . . 286, 289, 334

microarchitecture overview . . . . . . . . . . . . . . . . . . . . . . . .11

multimedia execution unit . . . . . . . . . . . . . . . . . . . . . . . .239

operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .331

pin connection requirements . . . . . . . . . . . . . . . . . . . . . .293

power-on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .199

process technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

signal switching characteristics . . . . . . . . . . . . . . . . . . . .295

Socket 7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 100, 108, 125, 158

bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 108, 125

check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98–99, 108, 125

error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99, 125, 174, 255

flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

PCD Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 209, 219

generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

PCHK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49–50, 202, 223

Pins

connection requirements . . . . . . . . . . . . . . . . . . . . . . . . . 293

designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321–329

float conditions (table). . . . . . . . . . . . . . . . . . . . . . . . . . . 141

I/O voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

input pin types (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

logic symbol (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

no-connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 93–139

Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156–157, 162

address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24–25

data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

register X and Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Pipelined . . . . . . . . . . . . . . . .23, 122, 157, 162–163, 180, 220

burst reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 96, 107

design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Platform

Socket 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Super7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pointer, Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power

standard-power devices. . . . . . . . . . . . . . . . . . . . . . 286, 334

state observability register (PSOR). . . . . . . . . . . . . 49, 202

Super7 platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

System Management Mode (SMM) . . . . . . . . . . . . . . . . .241

test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

thermal design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

Processor State Observability Register (PSOR)

low-power version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Protected Mode

INIT-Initiated transition . . . . . . . . . . . . . . . . . . . . . . . . . .196

real mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

PSOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49, 148, 202

PWT Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

R

RDMSR Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

RDTSC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Read and Write

and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

consumption and thermal resistance (figure) . . . . . . . . 315

dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

isolation region between planes . . . . . . . . . . . . . . . . . . . 291

basic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

misaligned I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Reads, Burst Reads and Pipelined Burst . . . . . . . . . . . . . .162

Index

341

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Real Mode

UWCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

INIT-initiated transition. . . . . . . . . . . . . . . . . . . . . . . . . . 196

protected mode transition . . . . . . . . . . . . . . . . . . . . . . . . 196

Register X and Y

functional unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21–22, 24

Regulator, Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

Reserved (RSVD) Pins

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14, 27, 240

3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

boundary scan (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

control 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

control 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

control 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

control 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

control 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

data types, floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . 34

RESET Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 127, 200, 278

signals sampled during reset . . . . . . . . . . . . . . . . . . . . . .199

state of processor after reset . . . . . . . . . . . . . . . . . . . . . .200

timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

timing for 100-MHz bus operation . . . . . . . . . . . . . . . . . .306

timing for 66-MHz bus operation . . . . . . . . . . . . . . . . . . .307

Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . .12

RSM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246, 249

RSVD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41, 269

descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

device identification (DIR) . . . . . . . . . . . . . . . . . . . . . . . 258

DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

DR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

DR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EBP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EBX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

enhanced power management (EPMR) . . . . . . . . . . . . . 144

EPMR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

ESI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ESP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

extended feature enable (EFER) . . . . . . . 44, 47, 202, 229

floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FPU control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FPU status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FPU tag word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

instruction (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

level-2 cache array access (L2AAR) . . . . . . . . . . . . . . . . 264

S

SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . .260

Sampled signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Scheduler/Instruction Control Unit. . . . . . . . . . . . . . . . 14, 21

SCYC Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Sector, Write to a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216, 220

Segment

descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 59–61

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

task state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Serializing Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

SGTC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147, 281

Shift-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

Shift-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Signals

A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

A20M#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 242

ADS#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

ADSC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

AHOLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 278

AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

APCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

machine check address (MCAR) . . . . . . . . . . . . .44–45, 202

machine check type (MCTR) . . . . . . . . . . . . . . . .44–45, 202

MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

memory type range (MTRR) . . . . . . . . . . . . . . . . . . . . . . 231

MMX technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

model-specific (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

packed decimal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

precision real data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

processor state observability (PSOR) . . . . . . . . . . . . . . . 148

BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 283

BOFF#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 182

BRDY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

BREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

CACHE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105, 210

cache-related . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

D/C# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93–139

DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

EADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

processor state observability register (PSOR). . . . .49, 202

PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 148

reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

segment (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SYSCALL/SYSRET target address (STAR) . . . 44, 48, 202

System Management Mode (SMM) initial state (table) 243

test (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

time stamp counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . 46

TR12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 229, 278

FERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111, 240

floated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

FLUSH# . . . . . . . . . . . . . 112, 199, 223, 252, 278, 281–282

HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

342

Index

Preliminary Information

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116, 240

INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117, 278, 281

INTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 278, 281

INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

logic symbol (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

NA#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

negated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 278, 281

output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

PWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127, 278, 281

RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

sampled during RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 199

SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 241, 278, 281

SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131, 241

STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132, 278

switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 295

TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

timing (figures) . . . . . . . . . . . . . . . . . . . . .159–197, 309–312

TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

VCC2H/L# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

VID[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137, 151

W/R#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

SIMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Single Instruction Multiple Data (SIMD) operations . . . . . 15

Single-Transfer Memory Read and Write. . . . . . . . . . . . . . 158

SMI# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 241, 278

SMIACT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131, 241

SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131, 139, 164

cache states (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

instruction cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

internal cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

processor-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

exceptions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

instructions supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

interrupts (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

memory management registers . . . . . . . . . . . . . . . . . . . . . 54

model-specific registers (MSR) . . . . . . . . . . . . . . . . . . . . . 44

paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Software Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Special Bus Cycles

cache writeback invalidation . . . . . . . . . . . . . . . . . . . . . .190

definition (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

differentiating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 190

encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142, 190

enhanced power management . . . . . . . . . . . . . . . . . . . . .145

EPM stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

EWBE# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

flush acknowledge. . . . . . . . . . . . . . . . . . 112, 164, 190, 212

halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190–191, 278

shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190, 192

signal states (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

stop grant . . . . . . . . . . . . . . . . . . . . . . . . . 132, 190, 193, 279

System Management Mode (SMM) . . . . . . . . . . . . . . . . .247

Speculative EWBE# Disable (SEWBED). . . . . . . . . . . . . . .230

Split Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Standard-Power Devices . . . . . . . . . . . . . . . . . . . . . 4, 286, 334

STAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 48, 202

State

bus machine (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

processor

after INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

after RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Stepping ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Stop

clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

power dissipation . . . . . . . . . . . . . . . . . . . . . . . . .289–290

clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 283

grant

inquire state. . . . . . . . . . . . . . . . . . . . . . . . . 275, 278–280

state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 278, 280

grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

Stop Grant Time-Out Counter Field . . . . . . . . . . . . . . . . . .150

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

STPCLK# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132, 278

Super7 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .296

100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . .296

66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

input setup and hold timings for 100-MHz bus. . . . . . . .300

input setup and hold timings for 66-MHz bus. . . . . . . . .304

output delay timings for 100-MHz bus . . . . . . . . . . . . . .298

output delay timings for 66-MHz bus . . . . . . . . . . . . . . .302

signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

valid delay, float, setup, and hold timings . . . . . . . . . . .298

SYSCALL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

SYSCALL/SYSRET Target Address Register (STAR) . 44, 48,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

SYSRET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

System

management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .130

management interrupt active. . . . . . . . . . . . . . . . . . . . . .131

System Design

airflow management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

ATX form factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

component placement. . . . . . . . . . . . . . . . . . . . . . . . . . . .292

decoupling recommendations . . . . . . . . . . . . . . . . . . . . .292

heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

pin connection requirements . . . . . . . . . . . . . . . . . . . . . .293

power connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

BRDY# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

cache invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Index

343

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

System Management Mode (SMM). . . . . . . . . . . . . . . . . . . 241

AMD PowerNow!™ features . . . . . . . . . . . . . . . . . . . . . . 145

base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

debugging in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

default register values . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

enhanced power management. . . . . . . . . . . . . . . . . . . . . 145

entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

exceptions in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

I/O trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

I/O trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

initial register state (table) . . . . . . . . . . . . . . . . . . . . . . . 243

interrupts in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

memory (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

RSM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

SMI# interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

SMIACT# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

state-save area (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

system management interrupt active signal . . . . . . . . . 131

system management interrupt signal . . . . . . . . . . . . . . . 130

IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . .260

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

boundary scan (BSR). . . . . . . . . . . . . . . . . . . . . . . . . . .255

bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

device identification (DIR) . . . . . . . . . . . . . . . . . . . . .258

instruction register (IR) . . . . . . . . . . . . . . . . . . . . . . . .255

signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

states

capture-DR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

capture-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

shift-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

shift-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

update-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

update-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315, 318–319

design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

extended temperature rating . . . . . . . . . . . . . . . . . . . . . .313

heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

layout and airflow consideration . . . . . . . . . . . . . . . . . . .317

measuring case temperature (figure) . . . . . . . . . . . . . . .317

model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .313

Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Three-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Time Stamp Counter Register (TSC). . . . . . . . . . . . . . . . . . .46

Timing

bus cycles (figures) . . . . . . . . . . . . . . . . . . . . . . . . . .159–197

switching characteristics (figures). . . . . . . . . . . . . .309–312

TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

TMS Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

TR12 . . . . . . . . . . . . . . . . . . . . . . . . 44, 46, 202, 210, 218, 263

Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . .205

TRST# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

TSC . . . . . . . . . . . . . . . . . . . . . . . . . .44, 46, 202, 278–279, 281

TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 61–62, 244, 272

T

TAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

TCK Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

TDI Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

TDO Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286, 313, 315

ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

case-to-ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

extended for low-power devices . . . . . . . . . . . . . . . . . . . 313

storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Terminology, Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Test

boundary-scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

built-in self-test (BIST). . . . . . . . . . . . . . . . . . . . . . . . . . . 251

cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

data input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

data output signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

L2 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

-logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

scan chain (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

signal timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

signal timing (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

test access port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

three-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Test Access Port (TAP)

U

UC Memory Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

UC/WC Cacheability Control Register (UWCCR) . . 200, 202,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Uncacheable Memory . . . . . . . . . . . . . . . . . . . . . . 49, 230–231

UWCCR . . . . . . . . . . . . . . . . . . . . . . . . .49, 200, 202, 210, 232

V

VCC2 Pins

absolute ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329

power connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

processor voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

VCC2DET Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

VCC2H/L# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

VCC3 Pins

instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

EXTEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

HIGHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

absolute ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

I/O voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

pin designations (table) . . . . . . . . . . . . . . . . . . . . . 325, 329

344

Index

Preliminary Information

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

unused active low inputs . . . . . . . . . . . . . . . . . . . . . . . . . 293

VID[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137, 151

VID[4:0] Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

VIDC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

VIDO Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Voltage

active high signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

active low signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

bus divisor (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

CLK switching characteristics . . . . . . . . . . . . . . . . . . . . . 296

control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

dual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

cycles . . . . . 94, 96–97, 110, 113, 139, 164, 172, 176, 178,

. . . . . . . . . . . . . . . . . . . . . 180, 182, 186, 210, 264, 277, 280

L1 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

L2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

or writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Write-Combining Memory . . . . . . . . . . . . . . . . . . 49, 230–231

Writethrough

coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287, 291

input low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

plane isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317–318

supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

VCC2 detect signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

VCC2 High/Low Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . 136

VCC2DET signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

voltage identification control (table) . . . . . . . . . . . . . . . 147

VSS Pins

connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

pin designations (table) . . . . . . . . . . . . . . . . . . . . . .325, 329

unused active high inputs . . . . . . . . . . . . . . . . . . . . . . . . 293

W

W/R# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

WB/WT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

WBINVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

WC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 48, 202, 219

Write

allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . 208, 215–216, 219

conditions (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

logic mechanisms and conditions (figure) . . . . . . . . . 219

handling control register (WHCR) . . . . . . . . . . . . .202, 219

to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216, 220

Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

EWBE# control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

EWBEC settings (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 231

memory type range registers (MTRRs) . . . . . . . . . . . . . 231

memory-range restrictions . . . . . . . . . . . . . . . . . . . . . . . . 233

examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

valid masks and range sizes (table) . . . . . . . . . . . . . . 234

performance (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

UC/WC Cacheability Control Register (UWCCR). . . . . 232

uncacheable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

write cycle order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

write-combining memory . . . . . . . . . . . . . . . . . . . . . . . . . 231

Write/Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Writeback . . . . . . . . .105, 107–108, 119, 126, 131, 139, 142,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164–165, 190, 276

burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12, 16

coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Index

345

Preliminary Information

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

346

Index


型号：	AMD-K6-2E+
厂家：	ETC
描述：	AMD-K6-2E+ Processor Data Sheet? 5.53MB (PDF) AMD- K6-2E +处理器数据手册？ 5.53MB （ PDF ）\n 光电二极管
文件：	总368页 (文件大小：5316K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMD-K6-2E+ [ETC]

相关型号：

AMD-K6-2E/233AFR

AMD-K6-2E/233AFZ

AMD-K6-2E/233AMR

AMD-K6-2E/233AMZ

AMD-K6-2E/266AFR

AMD-K6-2E/266AFZ

AMD-K6-2E/266AMR

AMD-K6-2E/266AMZ

AMD-K6-2E/300AFR

AMD-K6-2E/300AFZ

AMD-K6-2E/300AMR

AMD-K6-2E/300AMZ