AMP374P6453BT1-C1H [ETC]
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs; 基于32M ×8 ， 4银行， 8K刷新， 3.3V同步DRAM 64M X 72 SDRAM DIMM支持ECC
| 型号： | AMP374P6453BT1-C1H |
| 厂家： | 
ETC |
| 描述： | 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs |
| 文件： | 总12页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AVED MEMORY PRODUCTS
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DESCRIPTION
AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density
memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit
with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a
168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM.
The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mount-
ing into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system
clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
• Performance Ranges
PIN NAMES
• Part Identification
Pin Name
Function
Address Input (multiplexed)
Select Bank
Data Input/Output
Check Bit (Data-in/out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
- AMP374P6453BT1-C1H/S
8k cycles/64ms Ref, TSOP, Gold Contact Plating
- PC100 Compliant
A0 - A12
BA0 - BA1
DQ0 - DQ63
CB0 - 7
CLK0 - CLK3
CKE0 - CKE1
CS0 - CS3
RAS
CAS
WE
DQM0 - 7
VDD
Part #
Maximum Frequency/Speed
AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2)
•
•
•
•
•
Burst Mode Operation
Auto & Self Refresh capability (8k cycles/64ms)
LVTTL compatible inputs and outputs
DQM
Power Supply(3.3V)
Ground
Power Supply for Reference
Serial Address Data I/O
Serial Clock
Vss
*VREF
SDA
SCL
SA0 - 2
WP
Single 3.3V 0.3V power supply
±
MRS cycle with address key programs
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full Page)
Data Scramble (Sequential & Interleave)
All inputs are sampled at the positive
going edge of the system clock
Address in EEPROM
Write Protect
DU
NC
Don’t Use
No Connection
•
•
Serial Presence Detect with EEPROM
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 1 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATIONS (FRONT SIDE / BACK SIDE)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
Vss
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ18
DQ19
VDD
85
86
Vss
DQ32
DQ33
DQ34
DQ35
VDD
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
VDD
2
CS0
DU
CS1
3
87
RAS
Vss
4
Vss
A0
DQ20
NC
88
DQ52
NC
5
89
A1
A3
6
A2
*VREF
CKE1
Vss
90
*VREF
NC
7
A4
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
A5
8
A6
92
A7
Vss
9
A8
DQ21
DQ22
DQ23
Vss
93
A9
DQ53
DQ54
DQ55
Vss
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10/AP
BA1
VDD
VDD
CLK0
Vss
DU
94
BA0
A11
VDD
CLK1
A12
Vss
CKE0
95
96
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
Vss
DQ24
DQ25
DQ26
DQ27
VDD
97
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ56
DQ57
DQ58
DQ59
VDD
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
CS2
DQM2
CS3
DQM6
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
DQM3
DU
DQ46
DQ47
CB4
DQM7
*A13
VDD
NC
VDD
NC
CB5
NC
CLK2
NC
Vss
NC
CLK3
NC
NC
CB2
CB3
Vss
NC
CB6
CB7
Vss
NC
WP
NC
**SA0
**SA1
**SA2
VDD
VDD
**SDA
**SCL
VDD
VDD
DQ16
DQ17
DQ48
DQ49
CAS
WE
DQM0
DQM4
Pins marked * are not used in this module.
Pins marked ** should be NC in the system which does not support SPD.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 2 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATION DESCRIPTION
Pin Name
Input Function
CLK
System Clock
Active on the positive going edge to sample all inputs.
Chip Select
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE, and DQM.
CS
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least one cycle prior to new command. Disable
input buffers for power down in standby.
CKE should be enabled 1CLK+t ss prior to valid command.
A0 - A12
Address
Row/Column addresses are multiplexed on the same pins.
Row Address: RA0 – RA12, Column address: CA0 – CA9
BA0 - BA1
Bank Select Address
Row Address Strobe
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS
low.
RAS
Enables row access & precharge.
Column Address Strobe
Write Enable
Latches column addresses on the positive going edge of the CLK with
CAS
WE
low.
C A S
Enables column access.
Enables write operation and row precharge.
WE
active.
Latches data in starting from
,
CAS
DQM0 - DQM7
DQ0 - DQ63
CB0 - 7
Data Input/Output Mask
Data Input/Output
Check bit
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP
Write Protect
WP pin is connected to Vss through 47KΩ Resistor. When WP is “high”
EEPROM programming will be inhibited, and the entire memory will be
write-protected.
VDD/Vss
Power Supply/Ground
Power and ground for the input buffers and the core logic.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 3 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage Temperature
Symbol
VIN, VOUT
VDD,VDDQ
Tstg
Rating
Unit
V
V
-1.0
-1.0
-
-
4.6
4.6
-55 to + 150
ºC
Power Dissipation
Short Circuit Current
Pd
IOS
18
50
W
mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to higher than recommended voltage for
extended periods may affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions
(Voltage referenced to Vss=OV, Ta = 0 to 70ºC)
Item
Supply voltage
Symbol
VDD, VDDQ
VIH
VIL
VOH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
-
Max
3.6
VDDQ+0.3
0.8
-
Unit
V
V
V
V
Notes
-
1
2
IOH = -2mA
IOL = 2mA
3
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current (Inputs)
VOL
ILI
-
-
0.4
10
V
µA
-10
Note:1. VIH(max) = 5.6V AC. Pulse width≤3ns.
2. VIL(min) = -2.0V AC. Pulse width≤3ns
3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, Ta = 23ºC, f=1MHz, VREF = 1.4V 200mV)
±
Item
Symbol
Min
Max
Unit
Input capacitance [A0 - A12, BA0 - BA1]
CADD
50
95
pF
Input capacitance [
,
,
]
CIN
50
28
18
18
13
13
13
95
50
25
30
20
18
18
pF
pF
pF
pF
pF
pF
pF
RAS CAS WE
Input capacitance [CKE0 - CKE1]
Input capacitance [CLK0 - CLK3]
Input capacitance [CS0 - CS3]
CCKE
CCLK
CCS
Input capacitance [DQM0 - DQM7]
Data input/output capacitance[DQ0 - DQ63]
Check bit [CB0 - 7]
CDQM
COUT1
2
COUT
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 4 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) T A = 0 to 70ºC
Symbol Test Condition
Version
-1H
Unit
mA
ICC1*
Burst Length = 1
tRC tRC (min)
1,260
≥
IOL = 0mA
ICC2P
ICC2PS
ICC2N
CKE≤ VIL (max), tCC = 10ns
CKE & CLK≤ VIL (max), tCC =
36
36
mA
∞
CKE VIH (min),
VIH (min), tCC = 10ns
≥
≥
CS
Input signals are changed one time during 20ns
288
mA
mA
mA
mA
ICC2NS
CKE VIH (min), CLK≤ VIL (max), tCC =
∞
≥
Input signals are stable
252
108
108
ICC3P
ICC3PS
ICC3N
CKE≤ VIL (max), tCC = 10ns
CKE & CLK≤ VIL(max), tCC =
∞
CKE VIH(min),
VIH(min), tCC = 10ns
≥
≥
CS
Input signals are changed one time during 20ns
540
450
ICC3NS
ICC4
CKE VIH(min), CLK≤ VIL(max), tCC =
∞
≥
Input signals are stable
IOL = 0mA
Page Burst
1,305
4 Banks activated
tCCD = 2CLKS
ICC5
ICC6
tRC tRC (min)
2,070
90
mA
mA
≥
CKE≤ 0.2V
ICC1:
Operating Current (one bank active)
ICC2P:
ICC2PS:
ICC2N:
ICC2NS:
ICC3P:
ICC3PS:
ICC3N:
ICC3NS:
ICC4:
Precharge Standby Current in power-down mode
Precharge Standby Current in power-down mode.
Precharge Standby Current in non power-down mode.
Precharge Standby Current in non power-down mode.
Active Standby Current in power-down mode.
Active Standby Current in power-down mode.
Active Standby Current in non power-down mode (One Bank Active).
Active Standby Current in non power-down mode (One Bank Active).
Operating Current (Burst Mode)
ICC5
Refresh Current
ICC6:
Self Refresh Current
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 5 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
AC OPERATING TEST CONDITIONS ( VDD = 3.3V ± 0.3V, TA = 0 to 70ºC)
Parameter
Value
AC input levels
VIH/VIL= 2.4V / 0.4V
Input timing measurement reference level
Input rise and fall time
Output measurement reference level
Output load condition
1.4V
tr / tf = 1ns / 1ns
1.4V
See Fig. 2
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Refer to the individual component not the whole module.
Parameter
Symbol
Version
-1H
Unit
Note
Row active to row active delay
tRRD (min)
tRCD (min)
tRP (min)
20
ns
1
1
1
1
to
delay
CAS
20
ns
RAS
Row precharge time
Row active time
20
ns
tRAS (min)
tRAS (max)
tRC (min)
50
ns
100
us
Row cycle time
70
ns
1
Last data in to row precharge
Last data in to active delay
Last data in to new col. add. delay
Last data in to burst stop
Column address to col. add. delay
Number of valid output data
tRDL (min)
tDAL (min)
tCDL (min)
tBDL (min)
tCCD (min)
CAS latency = 2
2
CLK
-
2,5
5
2CLK + 20 ns
1
1
1
1
CLK
CLK
CLK
ea
2
2
3
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time
required with clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -80/1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 6 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
AC CHARACTERISTICS (AC Operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
-
Parameter
CLK cycle time
Symbol
tCC
1H
Unit
Note
Min
10
-
Max
1000
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1,2
2
CLK to valid output delay
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
tSAC
tOH
tCH
tCL
6
-
3
3
-
3
3
-
3
tSS
2
3
Input hold time
tSH
1
-
-
3
CLK to output in Low-Z
CLK to output in Hi-Z
tSLZ
tSHZ
1
2
6
Note: 1.
Parameters depend on programmed CAS latency.
2.
3.
If clock rising time is no longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2 - 1] ns should be added to the parameter.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 7 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1
CKEn
CS
L
RAS
L
CAS
L
WE
L
DQM
X
B0,1 A10/AP A12-11,A9-0 Note
Mode Register Set
Auto Refresh
H
H
X
H
L
OPCODE
X
1, 2
3
L
L
L
H
X
Refresh
Self
Entry
Exit
3
Refresh
L
H
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
X
3
3
Bank Active & Row Address
Read &
Column Address Auto Precharge Enable
H
H
X
X
V
V
Row Address
Auto Precharge Disable
L
Column
Address
(A0-A9)
Column
Address
(A0-A9)
4
L
L
H
H
L
L
H
L
H
4, 5
Write &
Auto Precharge Disable
L
4
Column Address Auto Precharge Enable
H
X
X
V
H
4, 5
Burst Stop
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
L
6
Precharge
Bank Selection
All Banks
Entry
V
X
X
H
Clock Suspend or
H
L
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
Active Power Down
X
Exit
L
H
L
X
H
L
X
X
Precharge Power Down
Mode
Entry
H
X
Exit
L
H
X
H
L
X
DQM
H
H
X
V
X
X
X
7
No Operation Command
H
L
X
H
X
H
X
H
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note: 1. OP Code: Operand Code
A0 - A12, BA0 - BA1: Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are same as CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 - BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 8 of 12
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64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
FUNCTIONAL BLOCK DIAGRAM
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
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64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PACKAGE DIMENSIONS
Units: Inches(Millimeters)
Tolerances: .005(.13) unless otherwise specified
±
AVED Memory Products reserves the right to
change products and specifications without notice
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
SERIAL PRESENCE DETECT
•
•
•
•
•
Organization: 64M x 72
Composition: 32M x 8*18
# of rows in module: 2
# of banks in component: 4
Refresh: 8K/64ms
Byte#
Function Description
Function Supported
-1H
Hex Value
-1H
Note
0
# of bytes written into serial memory at module
manufacturer
128 bytes
80h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Total # of bytes of SPD memory devices
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module rows on this assembly
Data width of this assembly
256 bytes (2K-bit)
08h
04h
0Dh
0Ah
02h
48h
00h
01h
A0h
60h
02h
82h
08h
08h
01h
SDRAM
13
10
2
1
1
72 bits
Data width of this assembly
-
Voltage interface standard of this assembly
SDRAM cycle time @ CAS latency 3
SDRAM access time from clock @ CAS latency 3
DIMM configuration type
Refresh rate and type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column
address
LVTTL
10ns
6ns
ECC
2
2
7.8 µs, support self refresh
x8
x8
tCCD = 1CLK
16
17
SDRAM device attributes: Burst lengths supported
SDRAM device attributes: # of banks on SDRAM
device
1,2,4,8 & Full page
4 banks
8Fh
04h
18
19
20
21
SDRAM device attributes: CAS latency
SDRAM device attributes: CS latency
SDRAM device attributes: Write latency
SDRAM module attributes
2 & 3
0 CLK
0 CLK
06h
01h
01h
00h
Non-buffered, Non-
registered & redundant
addressing
22
SDRAM device attributes: General
±10% voltage tolerance,
OEh
Burst read, Single bit Write,
precharge all, auto
precharge
23
24
25
26
27
28
29
30
31
32
33
34
35
SDRAM cycle time @ CAS latency 2
SDRAM access time from clock @ CAS latency 2
SDRAM cycle time @ CAS latency 1
SDRAM access time from clock @ CAS latency 1
Minimum row precharge time (=tRP)
Minimum row active to row active delay(tRRD)
Minimum RAS to CAS delay (=tRCD)
Minimum activate precharge time(=tRAS)
Module row density
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
Data signal input hold time
Superset information (may be used in the future)
10ns
6ns
-
-
20ns
20ns
20ns
50ns
A0h
60h
00h
00h
14h
14h
14h
32h
40h
20h
10h
20h
10h
00h
2
2
2 rows of 256MB
2ns
1ns
2ns
1ns
-
36-61
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 11 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
SERIAL PRESENCE DETECT
(CONTINUED FROM PRESIOUS PAGE)
Byte#
Function Description
SPD data revision code
Function Supported
-1H
Hex Value
-1H
Note
62
63
64
65-71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PC100 SPD Spec. Ver. 1.2A
12h
4Ch
67h
00h
01h
41h
4Dh
50h
33h
37h
34h
50h
36h
34h
35h
33h
42h
54h
31h
2Dh
43h
31h
48h
2Fh
53h
31h
48h
20h
30h
42h
-
Check sum for bytes 0-62
Manufacturer JEDEC ID code
Manufacturer JEDEC ID code
Manufacturing location
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
-
AVED Memory Products
AVED Memory Products
Tustin
A
M
P
3
7
4
P
6
4
5
3
B
T
1
“-“
C
1
H
/
S
1
H
-
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer revision code (for PCB)
Manufacturer revision code (for component)
Manufacturer part #
Manufacturer part #
Manufacturer part #
Manufacturer revision code (for PCB)
Manufacturer revision code (for component)
Manufacturing date (Week)
Manufacturing date (Year)
0
B-die (3RD Gen.)
-
-
-
3
3
4
5
-
-
-
100-103 Assembly serial #
104-130 Manufacturer specific data (for future use)
131
132
Undefined
100MHz
Detailed 100MHz
information
Undefined
System frequency for 100MHz
PC100 specification details
64h
FFh
133+
Unused storage locations
-
5
Notes:
1. The bank select address is excluded in counting the total # of Addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date, Week & Date, Year with BCD format.
4. These bytes are programmed by AVED’s own assembly serial # system. All modules may have different unique serial #s.
5. These bytes are Undefined and can be used for AVED’s own purpose.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 12 of 12
相关型号：
AMP374P6453BT1-C1HS
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs
ETC
AMP374P6453BT1C1H
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs
ETC
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