ART7015D [ETC]
Hi-Rel DC-DC Rad-Hard Dual Converter in a ART package ; 高可靠DC-DC抗辐射双转换器，采用ART包\n
| 型号： | ART7015D |
| 厂家： | 
ETC |
| 描述： | Hi-Rel DC-DC Rad-Hard Dual Converter in a ART package
|
| 文件： | 总13页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94529
ART28XXT SERIES
28V Input,Three Output
ADVANCED ANALOG
HYBRID - HIGH RELIABILITY
RADIATION HARDENED DC/DC CONVERTER
Description
The ART Series of three output DC/DC converters are
designed specifically for use in the hostile radiation
environments characteristic of space and weapon sys-
tems. The extremely high level of radiation tolerance
inherent in the ART design is the culmination of exten-
sive research, thorough analysis and testing and of
careful component specification. Many of the best cir-
cuit design features characterizing the Advanced Ana-
log standard product line were adapted for incorpora-
ART
tion into the ART topology. Capable of uniformly high
performance over long term exposures in radiation in-
Features
n Total Dose > 100KRad (Si), 2:1margin
tense environments, this series sets the standard for
distributed power systems demanding high perfor-
mance and reliability.
n SEE hard to LET = 83 Mev.cm2 /mg
n Designed to MIL-PRF-38534 for Class K
n Derated per MIL-STD-975 & MIL-STD-1547
n Output Power Range 3 to 30 Watts
n 19 to 50 Volt Input Range
The ART converters are hermetically sealed in a rug-
ged, low profile package utilizing copper core pins to
minimize resistive DC losses. Long-term hermeticity is
assured through use of parallel seam welded lid at-
tachment along with Advanced Analog’s rugged ce-
ramic pin-to-package seal. Axial orentation of the leads
facilitates preferred bulkhead mounting to the principal
heat-dissipating surface.
n Input Undervoltage Lockout
n High Electrical Efficiency > 80%
n Full Performance from -55°C to +125°C
n Continuous Short Circuit Protection
n 12.8 W / in3 Output Power Density
n True Hermetic Package
n External Inhibit Port
n Externally Synchronizable
n Fault Tolerant Design
Manufactured in a facility fully qualified to MIL-PRF-
38534, these converters are fabricated utilizing DSSC
qualified processes, and are fully compliant to Class H
while being fully processed to the requirements of Class
K. Complete PI & CI testing has been completed in-
cluding Group C life test. Variations in electrical, me-
chanical and screening specifications can be accom-
modated. Contact Advanced Analog for special require-
ments.
n 5V, ±12 or ±15 Volts Outputs Available
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1
08/20/02
ART28XXT Series
SPECIFICATIONS
Absolute Maximum/Minimum Ratings Note1 Recommended Operating Conditions Note 2
Input Voltage
-0.5V to 80V
Input Voltage Range
19V to 60V
Minimum Output Current
5% maximum rated
current, any output
300°C for 10 seconds
-65°C to +135°C
19V to 50V for full derating
to MIL-STD-975
3W to 30 W
Soldering Temperature
Storage Temperature
Output Power Range
Operating Temperature -55°C to +125°C
-55°C to +85°C for full
derating to MIL-STD-975
Electrical Performance -55°C < TCASE < +125°C, VIN=28V, CL=0 unless otherwise specified.
Parameter
Symbol
Conditions
OUT = 1.5Adc, TC = +25°C
IOUT = ±250mAdc, TC = +25°C ART2812(dual)
Min
Max
Units
4.95
5.05
I
(main)
Output voltage accuracy
VOUT
Vdc
±11.50
±14.50
±12.50
±15.15
°
IOUT = ±250mAdc, TC = +25 C ART2815(dual)
Output power Note 5
Output current Note 5
POUT
IOUT
19 Vdc< VIN < 50Vdc
3
30
W
(main)
150
3000
19 Vdc< VIN < 50Vdc
mAdc
75
750
+15
(dual)
-15
150 mAdc < IOUT < 3000 mAdc
19 Vdc< VIN < 50Vdc
(main)
Line regulation Note 3
Load regulation Note 4
VRLINE
mV
mV
-60
+60
±75 mAdc < IOUT < ±750 mAdc
(dual)
-180
+180
150 mAdc < IOUT < 3000 mAdc
19 Vdc< VIN < 50Vdc
(main)
VRLOAD
-300
-10
+300
+10
±75 mAdc < IOUT < ±750 mAdc
(dual)
(main)
Cross regulation Note 8
Total regulation
VRCROSS
mV
V
19 Vdc< VIN < 50Vdc
-500
4.8
+500
5.2
(dual)
All conditions of Line, Load,
Cross Regulation, Aging,
(main)
VR
Temperature and Radiation ART2812(dual)
ART2815(dual)
±11.1
±13.9
±12.9
±16.0
IOUT = minimum rated, Pin 3 open
250
Input current
IIN
mA
Pin 3 shorted to pin 2 (disabled)
19 Vdc< VIN < 50Vdc
8
Output ripple voltage Note 6
Input ripple current Note 6
VRIP
IRIP
100
mVp.p
mAp.p
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
19 Vdc< VIN < 50Vdc
150
275
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
Switching frequency
Efficiency
FS
Sychronization input open. (pin 6)
225
80
KHz
%
Eff
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
For Notes to SPECIFICATIONS, refer to page 3
2
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ART28XXT Series
Electrical Performance (Continued)
Parameter
Enable Input
Symbol
Conditions
Min
Max
Units
open circuit voltage
drive current (sink)
voltage range
3.0
5.0
0.1
50.0
V
mA
V
-0.5
Synchronization Input
frequency range
pulse high level
pulse low level
External clock signal on Sync. input (pin 4)
225
4.5
-0.5
40
310
10.0
0.25
KHz
V
V
V/µS
%
pulse rise time
pulse duty cycle
20
80
7.5
200
Power dissipation, load fault
PD
Short circuit, any output
W
Output response to step load
changes Notes 7, 11
10% Load to/from 50% load
-200
-200
VTLD
mVPK
50% Load to/from 100% load
10% Load to/from 50% load
200
200
Recovery time from step load
changes Notes 11, 12
TTLD
VTLN
TTLN
µS
50% Load to/from 100% load
200
350
Output response to step line
changes Notes 10, 11
IOUT = 3000 mAdc
(main)
-350
VIN = 19 V to/from 50 V
IOUT = ±500 mAdc
mVPK
(dual)
-1050
1050
500
Recovery time from step line
changes Notes 10, 11,13
IOUT = 3000 mAdc
(main)
VIN = 19 V to/from 50 V
IOUT = ±500 mAdc
µS
(dual)
500
500
(main)
Turn on overshoot
VOS
TDLY
CL
IOUT = minimum and full rated
IOUT = minimum and full rated
No effect on DC performance
mV
mS
µF
(dual)
1500
20
Turn on delay Note 14
Capacitive load Notes 9, 10
Isolation
5
(main)
(dual)
500
100
ISO
500VDC Input to Output or any pin to case
(except pin 12)
100
MΩ
Notes to SPECIFICATIONS
1.
Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently
degrade performance and affect reliability.
2.
Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside
recommended limits is not specified.
3.
4.
5.
6.
7.
8.
9.
Parameter measured from 28V to 19 V or to 50V while loads remain fixed.
Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.
Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.
Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.
A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the
maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.
10. Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits
specified in the table.
11. Load transient rate of change, di/dt ≤ 2 A/µSec.
12. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
13. Line transient rate of change, dv/dt 50 V/µSec.
≤
14. Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the
input.
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3
ART28XXT Series
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Group A
Test
Symbol
Conditions unless otherwise specified
Subgroups
Min
Max
Units
IOUT = 1.5 Adc
(main)
1, 2, 3
4.95
5.05
Output voltage accuracy
VOUT
V
I
OUT = ±250mAdc
ART2812(dual)
ART2815(dual)
1, 2, 3
1, 2, 3
±11.70
±14.50
±12.30
±15.15
IOUT = ±250mAdc
Output power Note 1
POUT
IOUT
VIN = 19 V, 28V, 50 V
1, 2, 3
1, 2, 3
3
30
W
(main)
150
3000
Output current
Note 1
VIN 19 V, 28V, 50 V
mA
(dual)
1, 2, 3
1, 2, 3
75
500
5.2
I
V
I
OUT = 150, 1500, 3000mAdc
IN = 19 V, 28V, 50 V
OUT = ±75, ±310, ±625mAdc
IOUT = ±75, ±250, ±500mAdc
(main)
4.8
Output regulation Note
4
VR
V
2812(dual)
2815(dual)
1, 2, 3
1, 2, 3
±11.1
±14.0
±12.9
±15.8
IOUT = minimum rated, Pin 3 open
1, 2, 3
250
Input current
IIN
mA
Pin 3 shorted to pin 2 (disabled)
VIN = 19 V, 28V, 50 V
1, 2, 3
1, 2, 3
8
Output ripple Note 2
Input ripple Note 2
VRIP
IRIP
100
mVP-P
mAP-P
IOUT = 3000mA main, ±500mA dual
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
1, 2, 3
4, 5, 6
150
275
Switching frequency
Efficiency
FS
Synchronization pin (pin 6) open
IOUT = 800mA main, ±500mA dual
225
KHz
%
Eff
1
2, 3
80
78
Power dissipation,
load fault
PD
VTL
TTL
VOS
Short circuit, any output
1, 2, 3
7.5
W
mVPK
µS
Output response to step
load changes Notes 3,
5
10% Load to/from 50% load
4, 5, 6
-200
-200
200
50% Load to/from 100% load
10% Load to/from 50% load
4, 5, 6
4, 5, 6
200
200
Recovery time from
step load changes
Notes 5, 6
50% Load to/from 100% load
IOUT = minimum and full rated
IOUT = minimum and full rated
4, 5, 6
4, 5, 6
200
500
(main)
(dual)
Turn on overshoot
mV
4, 5, 6
4, 5, 6
1
1500
20
Turn on delay Note 7
Isolation
TDLY
5
mS
ISO
500VDC Input to output or any pin to case
(except pin 12)
100
MΩ
Notes to Group A Test Table
1.
2.
3.
4.
5.
6.
7.
8.
Parameter verified during dynamic load regulation tests.
Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
Load step transition time 10µS.
≥
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
Subgroups 1 and 4 are performed at +25ºC, subgroups 2 and 5 at -55ºC and subgroups 3 and 6 at +125ºC.
4
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ART28XXT Series
Radiation Performance
The radiation tolerance characteristics inherent in the
ART28XXT converter are the direct result of a carefully
planned ground-up design program with specific radiation
design goals. After identification of the general circuit to-
pology, a primary task of the design effort was selection of
appropriate elements from the list of devices for which
extensive radiation effects data was available. By impos-
ing sufficiently large margins on those electrical param-
eters subject to the degrading effects of radiation, design-
ers were able to select appropriate elements for incorpo-
ration into the circuit. Known radiation data was utilized for
input to PSPICE and RadSPICE in the generation of circuit
performance verification analyses. Thus, electrical per-
formance capability under all environmental conditions in-
cluding radiation was well understood before first applica-
tion of power to the inputs.
performance variations. In the few instances where such
margins were not assured, element lots were selected
from which die were fabricated (and characterized) as
radiation hard devices so that realization of the design
goals could be assured.
Completion of first article fabrication, screening and stan-
dard environmental testing was followed by radiation test-
ing to confirm design goals. All design goals were met
handily and in most cases exceeded by large margin.
These test samples were built with elements that, with the
foregoing exceptions, were not screened for radiation char-
acteristics. Additional radiation tests on subsequent
ART28XXT manufacturing lots provide continued confir-
mation of the soundness of the design goals as well as
justification for the element selection criteria.
The following table specifies guaranteed minimum radia-
tion exposure levels tolerated while maintaining specifica-
tion limits.
A principal design goal was a converter topology that, be-
cause of large design margins, had radiation performance
essentially independent of normal elemental lot radiation
Radiation Specification T
= 25°C
case
Test
Conditions
Min
Typ
Max
Unit
Total Ionizing Dose
(2:1 Margin)
MIL-STD-883, Method 1019.4
Operating bias applied during exposure
100
500
KRads
(Si)
Dose Rate
MIL-STD-883, Method 1021
Temporary Saturation
1E8
Rads
Survival
1E11
(Si)/sec
Neutron Fluence
MIL-STD-883, Method 1017.2
3E12
83
Neutron
/cm²
Heavy Ions
BNL Tandem Van de Graaff Generator
MeV•
(Single event effects)
cm²/mg
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5
ART28XXT Series
ART28XXT Circuit Description
Figure I. ART Block Diagram
EMI
Filter
+Vout
Dual
+Input
Under-Voltage
Detector
Return
-Vout
Dual
Primary Bias
&
Reference
+5
Enable
Short
Circuit
Return
Sample
Hold
Pulse Width
Modulator
Sync
Input
Return
Operating Guidelines
Circuit Description and Application Information
The ART28XXT series of converters have been designed
using a single ended forward switched mode converter
topology. (refer to Figure I.) Single ended topologies enjoy
some advantage in radiation hardened designs in that they
eliminate the possibility of simultaneous turn on of both
switching elements during a radiation induced upset; in
addition, single ended topologies are not subject to trans-
former saturation problems often associated with double
ended implementations.
The circuit topology used for regulating output voltages in
the ART28XXT series of converters was selected for a
number of reasons. Significant among these is the ability
to simultaneously provide adequate regulation to each
output voltage while maintaining modest circuit complexity.
These attributes were fundamental in retaining the high
reliability and insensitivity to radiation that characterizes
device performance. Use of this topology dictates that the
user maintain a minimum load on each output as specified
in the electrical tables. Attempts to operate any output
without a load will result in peak charging to a voltage level
well above the specified voltage regulation limits, poten-
tially in excess of ratings, and should be avoided. In most
practical applications, this lower bound on the load range
does not present a serious constraint. Output loads that
are lighter than the specified minimums will result in regu-
lation performance exceeding the limits presented in the
specification tables. Regulation curves illustrating repre-
sentative performance characteristics are shown in Fig-
The design incorporates an LC input filter to attenuate
input ripple current. A low overhead linear bias regulator is
used to provide bias voltage for the converter primary
control logic and a stable, well regulated reference for the
error amplifier. Output control is realized using a wide
band discrete pulse width modulator control circuit incor-
porating a unique non-linear ramp generator circuit. This
circuit helps stabilize loop gain over variations in line volt-
age for superior output transient response. Nominal con-
version frequency has been selected as 250 KHz to maxi-
mize efficiency and minimize magnetic element size.
ures VII, VIII and IX.
Thermal Considerations
Output voltages are sensed using a coupled inductor and
a patented magnetic feedback circuit. This circuit is rela-
tively insensitive to variations in temperature, aging, ra-
diation and manufacturing tolerances making it particu-
larly well suited to radiation hardened designs. The control
logic has been designed to use only radiation tolerant com-
ponents, and all current paths are limited with series re-
sistance to limit photo currents.
The ART series of converters is capable of providing rela-
tively high output power from a package of modest vol-
ume. The power density exhibited by these devices is
obtained by combining high circuit efficiency with effective
methods of heat removal from the die junctions. Good
design practices have effectively addressed this require-
ment inside the device. However when operating at maxi-
mum loads, significant heat generated at the die junctions
must be carried away by conduction from the base. To
maintain case temperature at or below the specified maxi-
mum of 125°C, this heat can be transferred by attachment
Other key circuit design features include short circuit pro-
tection, undervoltage lockout and an external synchroni-
zation port permitting operation at an externally set clock
rate.
6
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ART28XXT Series
Thus, a total heat sink surface area (including fins, if any)
of approximately 32 in in this example, would limit case
to an appropriate heat dissipater held in intimate contact
with the converter base-plate.
2
rise to 35°C above ambient. A flat aluminum plate, 0.25"
thick and of approximate dimension 4" by 4" (16 in per
side) would suffice for this application in a still air environ-
ment. Note that to meet the criteria, both sides of the plate
require unrestricted exposure to the ambient air.
2
Effectiveness of this heat transfer is dependent on the
intimacy of the baseplate-heatsink interface. It is there-
fore suggested that a heat transferring medium possess-
ing good thermal conductivity is inserted between the
baseplate and heatsink. A material utilized at the factory
during testing and burn-in processes is sold under the
Inhibiting Converter Output
1
trade name of Sil-Pad 400 . This particular product is an
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing an input referenced, TTL compatible,
logic signal to the enable pin 3. This port is internally pulled
“high” so that when not used, an open connection on the
pin permits normal converter operation. When inhibited
outputs are desired, a logical “low” on this port will shut the
converter down. An open collector device capable of sink-
ing at least 100 µA connected to enable pin 3 will work well
in this application.
insulator but electrically conductive versions are also avail-
able. Use of these materials assures optimum surface
contact with the heat dissipater by compensating for mi-
nor surface variations. While other available types of heat
conducting materials and thermal compounds provide simi-
lar effectiveness, these alternatives are often less conve-
nient and are frequently messy to use.
A conservative aid to estimating the total heat sink surface
area (A
) required to set the maximum case tem-
HEAT SINK
perature rise (∆T) above ambient temperature is given by
the following expression:
A benefit of utilization of the enable input is that following
initial charge of the input capacitor, subsequent turn-on
commands will induce no uncontrolled current inrush.
−1.43
∆T
A
HEAT SINK
≈
−5.94
80P0.85
Figure II. Enable Input Equivalent Circuit
where
Vin
∆T = Case temperature rise above ambient
5K
1
P = Device dissipation in Watts = POUT
−1
Eff
2N2907A
As an example, assume that it is desired to maintain the
case temperature of an ART2815T at +65°C or less while
operating in an open area whose ambient temperature
does not exceed +35°C; then
64K
150K
150K
Enable
Input
5.6
V
2N2222A
2N2222A
186K
150K
∆T = 65 - 35 = 35°C
Input
Return
Converter inhibit is initiated when
this transistor is turned off
From the Specification Table, the worst case full load effi-
ciency for this device is 80%; therefore the maximum power
dissipation at full load is given by
1
P = 30•
−1 = 30• 0.25 = 7.5W
(
)
.80
and the required heat sink area is
−1.43
35
A
HEAT SINK
=
− 5.94 = 31.8 in2
80• 7.50.85
1
Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN
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7
ART28XXT Series
Synchronization
Parallel Operation
When using multiple converters, system requirements may
dictate operating several converters at a common sys-
tem frequency. To accommodate this requirement, the
ART28XXT type converter provides a synchronization
input port (pin 4). Circuit topology is as illustrated in Figure
III.
Although no special provision for forced current sharing
has been incorporated in the ART28XXT series, multiple
units may be operated in parallel for increased output power
applications. The 5 volt outputs will typically share to within
approximately 10% of their full load capability and the dual
(±15 volt) outputs will typically share to within 50% of their
full load. Load sharing is a function of the individual imped-
ance of each output and the converter with the highest
nominal set voltage will furnish the predominant load cur-
rent.
The sync input port permits synchronization of an ART
converter to any compatible external frequency source
operating in the band of 225 to 310 KHz. The synchroniza-
tion input is edge triggered with synchronization initiated
on the negative transition. This input signal should be a
negative going pulse referenced to the input return and
have a 20% to 80% duty cycle. Compatibility requires the
negative transition time to be less than 100 ns with a mini-
mum pulse amplitude of +4.25 volts referred to the input
return. In the event of failure of an external synchroniza-
tion source, the converter will revert to its own internally
set frequency. When external synchronization is not de-
sired, the sync in port may be left open (unconnected)
permitting the converter to operate at its’ own internally set
frequency.
Input Undervoltage Protection
A minimum voltage is required at the input of the converter
to initiate operation. This voltage is set to a nominal value
of 16.8 volts. To preclude the possibility of noise or other
variations at the input falsely initiating and halting con-
verter operation, a hysteresis of approximately 1.0 volts
is incorporated in this circuit. The converter is guaranteed
to operate at 19 Volts input under all specified conditions.
Input Filter
Figure III. Synchronization Input Equivalent Circuit
To attenuate input ripple current, the ART28XXT series
converters incorporate a single stage LC input filter. The
elements of this filter comprise the dominant input load
impedance characteristic, and therefore determine the
nature of the current inrush at turn-on. The input filter
+10V
5K
circuit elements are as shown in Figure IV.
Sync
Input
2N2907A
Figure IV. Input Filter Circuit
47pf
10
Ω
5K
Input
Return
+ Input
3.6 µH
5.4 µfd
Output Short Circuit Protection
Protection against accidental short circuits on any output
is provided in the ART28XXT converters. This protection
is implemented by sensing primary switching current and,
when an over-current condition is detected, switching ac-
tion is terminated and a restart cycle is initiated. If the
short circuit condition has not been cleared by the time the
restart cycle has completed, another restart cycle is initi-
ated. The sequence will repeat until the short circuit con-
dition is cleared at which time the converter will resume
normal operation. The effect is that during a shorted con-
dition, a series of narrow pulses are generated at approxi-
mately 5% duty cycle which periodically sample the state
of the load. Thus device power dissipation is greatly re-
Input
Return
duced during this mode of operation.
8
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ART28XXT Series
It is important to be aware that when filtering high fre-
quency noise, parasitic circuit elements can easily domi-
nate filter performance. Therefore, it is incumbent on the
designer to exercise care when preparing a circuit layout
for such devices. Wire runs and lengths should be mini-
mized, high frequency loops should be avoided and care-
ful attention paid to the construction details of magnetic
circuit elements. Tight magnetic coupling will improve overall
magnetic performance and reduce stray magnetic fields.
Additional Filtering
Although internal filtering is provided at both input and out-
put terminals, some applications may require additional
filtering in order to accommodate system requirements.
While the internal input filter of Figure IV. keeps input ripple
current below 100 mA , an external filter may be applied
p-p
to further attenuate this ripple to a level below the CE03
limits imposed by MIL-STD-461B. Figure V. describes a
filter providing that attenuation.
Figure VI. External Output Filter
Figure V. External Input EMI Filter
L1
+5
V
+5V Out
L3
C1
C2
C6
5V
+5V
Return
Return
+15V
Out
L2
L4
+15V
C3
C7
C8
This circuit shown in Figure V has been constructed on
copper clad board using the materials listed and tested in
15V
Return
15V
Return
the laboratory.
C4
C5
An external filter may also be added to the output where
circuit requirements dictate extremely low output ripple
noise. The output filter described by Figure VI has been
characterized with the ART2815T using the values shown
in the associated material list.
-15V
Out
-15V
L1
L2
L3
L4
7
7
4
5
tu rn s AWG 21 b ifila r o n Ma g In c . c o re PN YJ -41305-TC o r e q u iva le n t.
tu rn s AWG 24 trifila r o n Ma g In c . c o re PN YJ -41305-TC o r e q u iva le n t.
t u rn s AWG 21 o n Ma g In c . c o re PN MPP55048 o r e q u iva le n t .
tu rn s AWG 21 b ifila r o n Ma g In c . c o re PN MPP55048 o r e q u iva le n t.
C 1 -C 5 2 2 0 0 p F t yp e C KR c e ra m ic c a p a c it o r.
C 6 170µF, 15V M39006/ 22-0514 Ta n t a lu m .
C 7, C 8 25µF, 50V M39006/ 22-0568 Ta n t a lu m .
Measurement techniques can impose a significant influ-
ence on results. All noise measurements should be mea-
sured with test leads as close to the device output pins as
physically possible. Probe ground leads should be kept to
a minimum length.
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9
ART28XXT Series
Performance Characteristics (Typical @ 25°C)
Figure VII. Efficiency vs Output Power
for Three Line Voltages.
85
80
75
70
65
60
55
50
18V
28V
50V
0
5
10
15
20
25
30
35
Output Power (Watts)
FigureVIII. 5V Output Regulation Limits
Including all conditions of Line, Load and Cross Regulation.
5.2
5.1
5.0
4.9
4.8
4.7
Upper Limit
Lower Limit
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Output Current (Amps)
10
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ART28XXT Series
Performance Characteristics (Typical @ 25°C) (Continued)
Figure IX. ±15 V Regulation Curves
For Three conditions of Load on the 5 Volt Output.
17.0
16.0
15.0
14.0
5V Load = 3.0A
5V Load = 1.5A
5V Load = 150 mA
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Output Current (Each Output)
Figure X. Cross Regulation Curves
5 Volt Output as a function of 15 Volt Load Current for Three 5 Volt Loads.
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
5V Load = 150mA
5V Load = 1.5A
5V Load = 3.0A
0
0.1
0.2
0.3
0.4
0.5
0.6
±15 Volt Load Current
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11
ART28XXT Series
ART28XXT Physical & Interface Characteristics
ART28XXT Case Outline
Ø 0.136 - 6 Holes
0.040
Pin Dia.
6 x 0.200
= 1.200
1.675 2.200
1.950
0.375
0.263
0.138
0.300
1.400
0.150
2.400
2.700
0.275
0.240
3.25 Ref.
Max
Mounting
Plane
0.050
Flange
0.500
Max
Note:
1. Dimensions are in inches.
2. Base Plate Mounting Plane Flatness 0.003 maximum.
3. Unless otherwise specified, tolerances are
= ± 2°
.XX
= ± .01
.XXX
= ± .005
4. Device Weight - 120 grams maximum.
Pin Designation
Part Numbering
ART 28 15 T / EM
Pin #
1
2
3
4
5
8
9
10
11
12
13
14
Signal
+ V input
Input return
Enable
Sync In
Model
Screening Level
No Suffix = Flight
Input Voltage
28 = 28V
/EM = Engineering
No connection
No connection
- 15 Vdc output
15 Vdc output return
+ 15 Vdc output
Chassis
100 = 100V
Outputs
T = Triple
Output Voltages
15 = 5V, ± 15V
12 = 5V, ± 12V
Note:
+ 5 Vdc output
5 Vdc output return
Radiation performance not specified for /EM screened device type.
12
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ART28XXT Series
Standard Process Screening for ART28XXT Series
MIL-STD-883
/EM Limits
Flight Limits
Requirement
Method
(Class K)
Temperature Range
Element Evaluation
Non-destructive Bond Pull
Internal Visual
-55°C to +125°C
-55°C to +125°C
MIL-PRF-38534
100%
N/A
N/A
✓
2023
2017
1010
2001,
2020
1015
✓
Temperature Cycle
Constant Acceleration
PIND
✓
Cond C
500 g
N/A
Cond A
Cond A
Burn-in
160 hrs @ 125°C 320 hrs @ 125°C
(2 × 160 hrs)
Interim Electrical @ 160 hrs
Final Electrical (Group A)
Read & Record Data
MIL-PRF-38534
& Specification
-55, +25, +125°C -55, +25, +125°C
PDA (25°C, interim to final)
Radiographic Inspection
Seal, Fine & Gross
N/A
N/A
✓
2%
✓
2012
1014
2009
Cond A, C
✓
External Visual
✓
Standard Periodic & Conformance Inspections on ART28XXT Series
Inspection
Group A
Group B
Group C
Application
Part of Screening on Each Unit
Each Inspection Lot
Quantity
100%
*5 units
10 Units
First Inspection Lot or
Following Class 1 Change
Group D
In Line (Part of Element Evaluation)
* Group B quantity for Option 2 End of Line QCI. No Group B samples reuired for Option 1, In-line.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
ADVANCED ANALOG: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 08/02
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13
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