概述
数据手册AS4LC1M16E5-50JC 概述
3V 1M X 6 CMOS DRAM (EDO) 3V 1M X 6 CMOS DRAM （ EDO ）
AS4LC1M16E5-50JC 数据手册
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PDF下载AS4LC1M16E5
®
3V 1M×16 CMOS DRAM (EDO)
Features
• Organization: 1,048,576 words × 16 bits
• Read-modify-write
• High speed
- 50/60 ns RAS access time
- 20/25 ns hyper page cycle time
- 12/15 ns CAS access time
• TTL-compatible, three-state DQ
• JEDEC standard package and pinout
- 400 mil, 42-pin SOJ
- 400 mil, 44/50-pin TSOP II
• Low power consumption
- Active: 500 mW max (-60)
- Standby: 3.6 mW max, CMOS DQ
• Extended data out
• 3V power supply (AS4LC1M16E5)
• 5V tolerant I/Os; 5.5V maximum V
• Industrial and commercial temperature available
IH
• 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh
Pin arrangement
Pin designation
TSOP II
50
SOJ
Pin(s)
A0 to A9
RAS
Description
VCC
DQ1
DQ2
DQ3
DQ4
VCC
VSS
1
2
3
4
5
6
7
8
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
Address inputs
49
48
47
46
45
44
43
42
41
40
DQ16
DQ15
DQ14
DQ13
VSS
DQ12
DQ11
DQ10
DQ9
2
DQ16
DQ15
DQ14
DQ13
VSS
3
Row address strobe
Input/output
4
5
DQ1 to DQ16
OE
6
DQ5
7
DQ12
DQ11
DQ10
DQ9
NC
8
DQ6
DQ7
DQ8
Output enable
9
9
10
11
12
13
14
15
16
17
18
19
20
21
10
11
WE
Write enable
NC
NC
NC
WE
LCAS
UCAS
OE
UCAS
LCAS
Column address strobe, upper byte
Column address strobe, lower byte
Power
RAS
NC
A9
NC
A8
NC
NC
WE
RAS
NC
NC
A0
15
16
17
18
19
20
21
22
36
35
34
33
32
31
30
29
NC
LCAS
UCAS
OE
A9
A8
A0
A7
VCC
A1
A6
A2
A5
VSS
Ground
A3
A4
Vcc
VSS
A7
A6
A1
A2
A3
VCC
23
24
25
A5
A4
VSS
28
27
26
Selection guide
Symbol
tRAC
tAA
-50
-60
60
Unit
ns
Maximum RAS access time
50
25
Maximum column address access time
Maximum CAS access time
30
ns
tCAC
tOEA
tRC
10
12
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum hyper page mode cycle time
Maximum operating current
10
12
ns
80
100
25
ns
tHPC
ICC1
ICC5
20
ns
140
1.0
120
1.0
mA
mA
Maximum CMOS standby current
Shaded areas indicate advance information.
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
AS4LC1M16E5
®
Functional description
The AS4LC1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16
bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power
and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in
personal and portable PCs, workstations, and multimedia and router switch applications.
The AS4LC1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at very
high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling
edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of column
addresses prior to xCAS assertion. The AS4LC1M16E5 provides dual UCAS and LCAS for independent byte control of read and write access.
Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data remains
active on outputs after xCAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance
and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS and xCAS going high.
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:
• RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.
• CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The AS4LC1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP II packages, respectively. The AS4LC1M16E5 device
operates with a single power supply of 3V 0.3V and provides TTL compatible inputs and outputs.
Logic block diagram
Data
DQ
buffers
VCC
Column decoder
Sense amp
DQ1 to DQ16
GND
RAS clock
generator
RAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
OE
1024 × 1024 × 16
Array
CAS clock
generator
UCAS
LCAS
(16,777,216)
Substrate bias
generator
WE clock
generator
WE
Recommended operating conditions
Parameter
Symbol
VCC
Min
3.0
0.0
2.0
–0.5†
0
Nominal
Max
3.6
0.0
5.5
0.8
70
Unit
V
3.3
0.0
–
Supply voltage
Input voltage
GND
VIH
V
V
VIL
–
V
Commercial
Industrial
–
Ambient operating temperature
TA
°C
-40
–
85
†
V
min -3.0V for pulse widths less than 5 ns.
IL
Recommended operating conditions apply throughout this document unless otherwise specified.
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AS4LC1M16E5
®
Absolute maximum ratings
Parameter
Symbol
VDQ
Min
-1.0
-1.0
-65
–
Max
Unit
V
Input voltage
+5.5
+4.0
+150
260 × 10
0.6
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
VCC
V
TSTG
°C
oC × sec
TSOLDER
PD
–
W
Short circuit output current
Iout
–
50
mA
Truth table
Addresses
Operation
Standby
RAS
LCAS
H to X
L
UCAS
H to X
L
WE
X
OE
X
tR
tC
X
DQ0 to DQ15
High-Z
Notes
H
L
X
Word read
H
L
ROW
COL
Data out
Lower byte
read
Lower byte,
Upper byte, Data out
L
L
L
L
L
L
H
L
H
L
H
H
L
L
L
ROW
ROW
ROW
ROW
ROW
COL
COL
COL
COL
COL
Upper byte
read
Lower byte,
Data out, Upper byte
Word
(early) write
L
X
X
X
Data in
Lower byte
(early) write
Lower byte, Data in,
Upper byte, High-Z
L
H
L
L
Upper byte
(early) write
Lower byte, High-Z,
Upper byte, Data in
H
L
Read write
EDO read
L
L
L
L
L
L
L
L
L
L
H to L L to H ROW
COL
COL
COL
n/a
Data out, Data in
Data out
1,2
2
1st cycle
2nd cycle
Any cycle
1st cycle
2nd cycle
1st cycle
2nd cycle
H to L
H to L
L to H
H to L
H to L
H to L
H to L
H to L
H to L
L to H
H to L
H to L
H
H
H
L
L
L
ROW
n/a
Data out
2
L
n/a
Data out
2
X
X
ROW
n/a
COL
COL
COL
COL
Data in
1
EDO write
L
Data in
1
H to L H to L L to H ROW
Data out, Data in
Data out, Data in
1,2
1,2
EDO
read write
H to L H to L L to H
n/a
RAS only
refresh
L
H
H
X
X
ROW
n/a
High Z
CBR refresh
Self refresh
H to L
H to L
L
L
L
L
H
H
X
X
X
X
X
X
High Z
High Z
3
3
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AS4LC1M16E5
®
DC electrical characteristics
-50
-60
Parameter
Symbol Test conditions
Min Max Min Max Unit Notes
0V ≤ Vin ≤ VCC (max)
Pins not under test = 0V
Input leakage current
IIL
IOL
-2
-2
–
+2
+2
-2
-2
–
+2
+2
µA
µA
Output leakage current
DOUT disabled, 0V ≤ Vout ≤ VCC (max)
Operating power
supply current
RAS, UCAS, LCAS, Address cycling;
ICC1
140
130 mA
4,5
t
RC=min
TTL standby power
supply current
RAS = UCAS = LCAS ≥ VIH,
all other inputs at VIH or VIL
ICC2
–
–
2.0
80
–
–
2.0
70
mA
mA
Average power supply
current, RAS refresh
mode or CBR
RAS cycling, UCAS = LCAS ≥ VIH,
ICC3
4
t
RC = min of RAS low after XCAS low.
EDO page mode average
power supply current
RAS = VIL, UCAS or LCAS,
address cycling: tHPC = min
ICC4
ICC5
–
–
85
1
–
–
75
1
mA
mA
4, 5
CMOS standby power
supply current
RAS = UCAS = LCAS = VCC - 0.2V,
F = 0
VOH
VOL
IOUT = -5.0 mA
IOUT = 4.2 mA
2.4
–
–
2.4
–
–
V
V
Output voltage
0.4
0.4
CAS before RAS refresh
current
mA
ICC6
RAS, UCAS or LCAS cycling, tRC = min
–
80
–
70
RAS = UCAS = LCAS ≤ 0.2V,
WE = OE ≥ VCC - 0.2V,
all other inputs at 0.2V or
Self refresh current
ICC7
–
0.5
–
0.5
mA
V
CC - 0.2V
Shaded areas indicate advance information.
4/11/01
Alliance Semiconductor
4
AS4LC1M16E5
®
AC parameters common to all waveforms
-50
-60
Symbol
tRC
Parameter
Min
80
30
50
8
Max
–
Min
100
40
60
10
15
10
10
50
5
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
Notes
Random read or write cycle time
RAS precharge time
tRP
–
–
tRAS
tCAS
tRCD
tRAD
tRSH
tCSH
tCRP
tASR
tRAH
tT
RAS pulse width
10K
10K
35
25
–
10K
10K
43
30
–
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
15
9
9
10
10
40
5
–
–
–
–
0
–
0
–
8
–
10
1
–
1
50
16
–
50
16
–
7,8
6
tREF
tCP
–
–
CAS precharge time
8
10
30
0
tRAL
tASC
tCAH
Column address to RAS lead time
Column address setup time
Column address hold time
25
0
–
–
–
–
8
–
10
–
Shaded areas indicate advance information.
Read cycle
-50
-60
Symbol
tRAC
Parameter
Min
–
Max
50
12
25
–
Min
–
Max
60
15
30
–
Unit Notes
Access time from RAS
ns
ns
ns
ns
ns
ns
9
tCAC
Access time from CAS
–
–
9,16
10,16
tAA
Access time from address
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
–
–
tRCS
0
0
tRCH
tRRH
0
–
0
–
12
12
0
–
0
–
Shaded areas indicate advance information.
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Alliance Semiconductor
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AS4LC1M16E5
®
Write cycle
-50
-60
Symbol
tWCS
tWCH
tWP
Parameter
Min
0
Max
–
Min
0
Max
–
Unit
ns
Notes
14
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
10
10
10
8
–
10
10
10
10
0
–
ns
14
–
–
ns
tRWL
tCWL
tDS
–
–
ns
–
–
ns
0
–
–
ns
15
15
tDH
Data-in hold time
8
–
10
–
ns
Shaded areas indicate advance information.
Read-modify-write cycle
-50
-60
Symbol
tRWC
Parameter
Min
113
67
Max
–
Min
135
77
Max
–
Unit
ns
Notes
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
tRWD
–
–
ns
14
14
14
tCWD
tAWD
32
–
35
–
ns
42
–
47
–
ns
Shaded areas indicate advance information.
Refresh cycle
-50
-60
Symbol
tCSR
Parameter
Min
5
Max
–
Min
5
Max
–
Unit
ns
Notes
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
6
6
tCHR
8
–
10
0
–
ns
tRPC
0
–
–
ns
CAS precharge time
(CBR counter test)
tCPT
10
–
10
–
ns
Shaded areas indicate advance information.
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Alliance Semiconductor
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AS4LC1M16E5
®
Hyper page mode cycle
-50
-60
Symbol
tCPWD
tCPA
Parameter
Min
45
–
Max
–
Min
52
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
16
CAS precharge to WE delay time
Access time from CAS precharge
RAS pulse width
28
100K
–
35
100K
–
tRASP
tDOH
tREZ
50
5
60
5
Previous data hold time from CAS
Output buffer turn off delay from RAS
Output buffer turn off delay from WE
Output buffer turn off delay from OE
Hyper page mode cycle time
Hyper page mode RMW cycle
RAS hold time from CAS
0
13
13
13
–
0
15
15
15
–
tWEZ
0
0
tOEZ
0
0
tHPC
20
47
30
25
56
35
tHPRWC
tRHCP
–
–
–
–
Shaded areas indicate advance information.
Output enable
-50
-60
Symbol
tCLZ
Parameter
Min
0
Max
–
Min
0
Max
–
Unit
ns
Notes
11
CAS to output in Low Z
RAS hold time referenced to OE
OE access time
tROH
tOEA
tOED
tOEZ
8
–
10
–
–
ns
–
13
–
15
–
ns
OE to data delay
13
0
15
0
ns
Output buffer turnoff delay from OE
OE command hold time
OE to output in Low Z
Output buffer turn-off time
13
–
15
–
ns
11
tOEH
tOLZ
10
0
10
0
ns
–
–
ns
tOFF
0
13
0
15
ns
11,13
Shaded areas indicate advance information.
Self refresh cycle
-50
-60
Std Symbol Parameter
Min
100
Max
–
Min
100
Max
–
Unit
µs
Notes
RAS pulse width
tRASS
(CBR self refresh)
RAS precharge time
(CBR self refresh)
tRPS
90
8
–
–
105
10
–
–
ns
ns
CAS hold time
tCHS
(CBR self refresh)
Shaded areas indicate advance information.
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AS4LC1M16E5
®
Notes
1
2
3
4
5
6
Write cycles may be byte write cycles (either LCAS or UCAS active).
Read cycles may be byte read cycles (either LCAS or UCAS active).
One CAS must be active (either LCAS or UCAS).
I
I
, I , I , and I
are dependent on frequency.
CC6
CC1 CC3 CC4
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
7
8
9
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load as described in AC test conditions below.
T
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
IH
IL
IH
IL
Operation within the t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
is greater than the
RCD
RAC
RCD
RCD
specified t
(max) limit, then access time is controlled exclusively by t
.
CAC
RCD
10 Operation within the t
(max) limit insures that t
(max) can be met. t (max) is specified as a reference point only. If t
RAD
is greater than the
RAD
RAC
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
11 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
12 Either t or t must be satisfied for a read cycle.
RCH
RRH
13
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
is referenced from
OFF
OFF
rising edge of RAS or CAS, whichever occurs last.
, t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
14
t
WCS WCH RWD CWD
AWD
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
WS
WH
cycle. If tRWD ≥ t
(min), t
≥ t
(min) and tAWD ≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the
RWD
CWD
CWD
AWD
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
15 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
16 Access time is determined by the longest of t or t or t
CAA
CAC
CPA
17
tASC ≥ t to achieve t (min) and t (max) values.
CP PC CPA
18 These parameters are sampled and not 100% tested.
AC test conditions
- Access times are measured with output reference levels of
V
OH = 2.4V and VOL = 0.4V,
+3.3V
VIH = 2.0V and VIL = 0.8V
- Input rise and fall times: 2 ns
R1 = 828Ω
Dout
*including scope
and jig capacitance
50 pF*
R2 = 295Ω
GND
Figure B: Equivalent output load
(AS4LC1M16E5)
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
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AS4LC1M16E5
®
Read waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tCAH
tCAS
tCRP
tASC
tRCS
UCAS
LCAS
tRAD
tRAL
tRAH
tASR
Row address
Address
Column address
tRRH
tRCH
tWEZ
WE
OE
tROH
tROH
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC
tREZ
tCLZ
Data out
DQ
tOLZ
Upper byte read waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
UCAS
tRPC
tCRP
LCAS
tRAH
tRAD
tRAL
tASR
tASC
tCAH
Row
Column
Address
tRCH
tRRH
tRCS
WE
OE
tROH
tWEZ
tOEA
tREZ
tOLZ
tRAC
tOEZ
tAA
tCAC
tCLZ
tOFF
Upper DQ
Lower DQ
Data out
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Alliance Semiconductor
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AS4LC1M16E5
®
Lower byte read waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
LCAS
tCRP
tRPC
UCAS
tRAH
tRAD
tASC
tRAL
tASR
tCAH
Row
Column
Address
WE
tRCH
tRRH
tRCS
tROH
tWEZ
OE
Upper DQ
tREZ
tOEA
tOLZ
tRAC
tOEZ
tAA
tCAC
tOFF
tCLZ
Data out
Lower DQ
Early write waveform
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
UCAS,
tRAD
tRAL
LCAS
tASC
tASR
tRAH
tCAH
Row address
Column address
Address
tCWL
tRW L
tWP
tWCS
tWCH
WE
OE
tDH
Data in
tDS
DQ
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Alliance Semiconductor
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AS4LC1M16E5
®
Upper byte early write waveform
tRC
tRAS
tRP
RAS
tASR
tRAD
tRAL
tRAH
Row address
Column address
Address
tCAH
tRSH
tASC
tRCD
tCSH
tCAS
tCRP
tCRP
UCAS
tCRP
tRPC
LCAS
tCWL
tWCH
tRWL
tWCS
tWP
WE
OE
tDS
tDH
Data in
Upper DQ
Lower DQ
Lower byte early write waveform
tRC
tRAS
tRP
RAS
tRAD
tRAL
tASR
Row address
tCRP
tRAH
Address
UCAS
Column address
tRPC
tASC
tRCD
tCAH
tCAS
tCSH
tRSH
tCRP
tCRP
LCAS
tRWL
tCWL
tWCH
tWP
tWCS
WE
OE
Upper DQ
tDS
tDH
Data in
Lower DQ
4/11/01
Alliance Semiconductor
11
AS4LC1M16E5
®
Write waveform
OE controlled
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
tRAL
UCAS,
LCAS
tRAD
tRAH
tASC
tASR
Row address
tCAH
Column address
Address
tRWL
tCWL
tWP
WE
OE
tOEH
tDS
tOED
tDH
Data in
DQ
Upper byte write waveform
OE controlled
tRC
tRAS
tRP
RAS
tRAD
tRAH
tRAL
tASR
Row address
Column address
tCSH
Address
tRCD
tASC
tRSH
tCAH
tCRP
tCAS
tCRP
UCAS
tCRP
tRPC
LCAS
tCWL
tRWL
tWP
WE
OE
tOEH
tDS
tDH
Upper DQ
Lower DQ
Data in
tOED
4/11/01
Alliance Semiconductor
12
AS4LC1M16E5
®
Lower byte write waveform
OE controlled
tRC
tRAS
tRP
RAS
tRAD
tASR
tRAL
tRAH
Address
Row address
Column address
tCAH
tCAS
tRCD
tCSH
tCRP
tACS
tRSH
tCRP
LCAS
tCRP
tRPC
UCAS
tCWL
tRWL
tWP
WE
tOEH
OE
Upper DQ
tDH
tDS
Data in
Lower DQ
Read-modify-write waveform
tRWC
tRAS
tRP
RAS
tCAS
tRSH
tCRP
tRCD
tCSH
UCAS
LCAS
tAR
tRAL
tRAD
tRAH
tASC
tCAH
tASR
Row address
Column address
tRWD
Address
tRWL
tAWD
tCWL
tWP
tRCS
tCWD
WE
OE
tOEA
tOED
tOEZ
tRAC
tAA
tCAC
tCLZ
tDS
tDH
Data out
Data in
DQ
tOLZ
4/11/01
Alliance Semiconductor
13
AS4LC1M16E5
®
Upper byte read-modify-write waveform
tRWC
tRAS
tCSH
tRP
RAS
tRCD
tCAS
tRSH
tCRP
tRPC
tCRP
UCAS
tCRP
LCAS
tRAD
tACS
tASR
tRAL
tCAH
tRAH
Column address
tRWD
Address
Row
tCWL
tRWL
tWP
tAWD
tCWD
tOEA
tRCS
WE
OE
tDH
tDS
tOED
tOLZ
Upper input
tCLZ
tCAC
tAA
Data in
tOEZ
tRAC
Upper output
Data out
tOED
Lower input
Lower output
Lower byte read-modify-write waveform
tRWC
tRAS
tRP
tRPC
RAS
tCRP
UCAS
tCSH
tCAS
tRSH
tRCD
tCRP
tCRP
LCAS
tRAD
tRAL
tASR
tACS
tCAH
tRAH
Row
Column address
tRWD
Address
tCWL
tRWL
tWP
tAWD
tRCS
tCWD
tOEA
WE
OE
tOED
tOLZ
Upper input
Upper output
tDH
tDS
tOED
Lower input
tRAC
Data in
tAA
tCAC
tCLZ
tOEZ
Data out
Lower output
4/11/01
Alliance Semiconductor
14
AS4LC1M16E5
®
Hyper page mode read waveform
tRASP
tRP
RAS
tRHCP
tHPC
tCSH
tRSH
tCRP
tRCD
tCAS
tCP
UCAS,
LCAS
tAR
tRAD
tRAL
tRAH
Row
tASC
Col address
tCAH
tASR
Col address
tRCS
Address
Col address
tRRH
tRCH
WE
OE
tOEA
tOEA
tRAC
tCPA
tOEZ
tOFF
tCLZ
tCAC
tAA
tOEZ
tCPA
Data out
tCLZ
Data out
Data out
DQ
tCLZ
tOLZ
Hyper page mode byte write waveform
tRASP
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
tCAS
tCRP
UCAS
tCP
tHPC
tHPC
tCRP
tCAS
tRPC
tCP
tRAL
tASC
LCAS
tCAH
tRAH
tCAH
tRAD
tASC
tASR
tASC
tCAH
Row
Column 1
Column 2
Column n
Address
tRCH
tRCS
WE
OE
tOEA
tRRH
tOEA
tOEA
tCAC
tOLZ
tCLZ
tAA
tCPA
tOEZ
Data out 2
Lower DQ
Upper DQ
tAA
tOLZ
tAA
tRAC
tCAC
tCLZ
tCPA
tOFF
tOEZ
tCAC
tCLZ
tOEZ
Data out 1
Data out n
tOLZ
4/11/01
Alliance Semiconductor
15
AS4LC1M16E5
®
Hyper page mode early write waveform
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCSH
tCAH
tASC
tCAS
tCP
tRSH
tWCS
UCAS,
LCAS
tRAL
tAR
tASR
tRAD
Row address
Col address
Address
Col address
Col address
tCWL
tWP
tOEH
tWCH
WE
OE
tHDR
tOED
tDH
tDS
DQ
Data in
Data In
Data in
Hyper page mode byte early write waveform
tRASP
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tCRP
tRCD
tCAS
UCAS
LCAS
tCP
tCP
tPC
tPC
tCAS
tCRP
tRPC
tRAD
tRAH
tRAL
tCAH
tCAH
tCAH
tASC
Column 2
tASC
tASR
tASC
Column 1
Address
Row
Column n
tRWL
tWCS
tCWL
tWCH
tWCH
tWP
tWCH
tWCS
tWCS
tWP
tWP
tCWL
tCWL
WE
OE
tDS
tDH
Data In 2
Lower DQ
Upper DQ
tDH
tDS
tDH
tDS
Data in n
Data in 1
4/11/01
Alliance Semiconductor
16
AS4LC1M16E5
®
Hyper page mode read-modify-write waveform
tRASP
tRP
RAS
tHPRWC
tCAS
tCSH
tRCD
tCP
tCRP
UCAS,
LCAS
tRAD
tRAL
tCAH
tASR
tRAH
tASC
tASC
tASC
tCAH
tCAH
Row ad
Col ad
tRWD
Col ad
Col address
tCPWD
Address
tCWL
tRWL
tCWL
tRCS
tCWD
tCWD
tCWD
tAWD
tAWD
tWP
WE
OE
tOEA
tOEZ
tOED
tOEA
tAA
tRAC
tCLZ
tCAC
tDH
tCPA
tCLZ
tCAC
tDS
tDS
tCLZ
tCAC
Data in
Data in
Data out
Data in
DQ
Data out
Data out
CAS before RAS refresh waveform
WE = VIH
tRC
tRP
tRAS
RAS
tRPC
tCHR
tCP
tCSR
UCAS,
LCAS
OPEN
DQ
RAS only refresh waveform
WE = OE = VIH or VIL
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS,
LCAS
tASR
tRAH
Address
Row address
4/11/01
Alliance Semiconductor
17
AS4LC1M16E5
®
Hyper page mode byte read-modify-write waveform
tRASP
tRP
RAS
UCAS
LCAS
tCSH
tRCD
tRSH
tCAS
tCRP
tCRP
tCAS
tCP
tCP
tCAS
tRAL
tCAH
tAWD
tASC
tRAD
tRAH
tASR
tCAH
tCAH
tAWD
tASC
C 1
tASC
C n
Address
R
C 2
tCPWD
tAWD
tCWD
tRWL
tAWD
tCWD
tRWD
tCPWD
tCWD
tAWD
tCAH
tCWL
tCWL
tCWL
tWP
tWP
tWP
WE
OE
tOEA
tOEA
tOEA
tDH
tOED
tDH
tOED
tDS
tDS
Upper input
Data in 1
tOEZ
tCPA
Data in n
tRAC
tAA
tCAC
tOEZ
tAA
tCAC
tCLZ
tCLZ
Upper output
Lower input
Data out n
Data out 1
tDH
tOED
tDS
Data in 2
tCPA
tOEZ
tAA
tCAC
tCLZ
Lower output
Data out 2
4/11/01
Alliance Semiconductor
18
AS4LC1M16E5
®
Hidden refresh waveform (read)
tRC
tRC
tRAS
tRP
tRAS
tRP
RAS
tCRP
tCHR
tRCD
tRSH
tCRP
CAS
tAR
tRAD
tCAH
tRAH
tASC
Col address
tASR
Row
Address
tRCS
tRRH
WE
OE
tOEA
tRAC
tOFF
tAA
tCAC
tCLZ
tOEZ
Data out
DQ
Hidden refresh waveform (write)
tRC
tRAS
tRP
RAS
tCHR
tCRP
tRCD
tRSH
UCAS,
LCAS
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Row address
Col address
Address
WE
tRWL
tWCR
tWP
tWCS
tWCH
tDS
tDH
tDHR
Data in
DQ
OE
4/11/01
Alliance Semiconductor
19
AS4LC1M16E5
®
CAS before RAS refresh counter test waveform
tRAS
tRSH
tRP
RAS
tCSR
tCPT
tCAS
tCHR
UCAS,
LCAS
tRAL
tASC
tCAH
Address
Col address
tAA
tCAC
tCLZ
tOFF
tOEZ
DQ
WE
OE
Data out
tRRH
tRCH
tRCS
tROH
tOEA
tRWL
tCWL
tWP
tWCH
tWCS
WE
tDH
tDS
DQ
OE
Data in
tRW L
tWP
tRCS
tCWD
tAWD
tCWL
WE
OE
tOEA
tOED
t AA
tDH
tCLZ
tCAC
tOEZ
tDS
Data in
DQ
Data out
4/11/01
Alliance Semiconductor
20
AS4LC1M16E5
®
CAS-before-RAS self refresh cycle
tRP
tRASS
tRPS
RAS
tRPC
tCP
tRPC
tCSR
tCHS
UCAS,
LCAS
tCEZ
DQ
Package dimensions
D
42-pin SOJ
e
Min
Max
0.148
-
0.115
0.032
0.020
0.013
1.080
c
A
A1
A2
B
b
c
0.128
0.025
0.105
0.026
0.015
0.007
1.070
SOJ
E1 E2
Pin 1
E
D
B
E
0.370 NOM
A2
A
E1
E2
e
0.395
0.435
0.405
0.445
A1
Seating
Plane
b
0.050 NOM
c
50 49 48 47 46 45 44 43 42 41 40
36 35 34 33 32 31 30 29 28 27 26
50-pin TSOP II
Min
Max
(mm)
(mm)
A
A1
A2
b
1.2
TSOP II
E He
0.05
0.95
1.05
0.45
0.30
c
0.12
0.21
1
2
3
4
5
6
7
8
9
10 11
15 16 17 18 19 20 21 22 23 24 25
d
20.85
10.03
11.56
21.05
10.29
11.96
E
d
He
e
l
0.80 (typical)
0.40 0.60
l
A2
A
0–5°
A1
b
e
4/11/01
Alliance Semiconductor
21
AS4LC1M16E5
®
Capacitance 15
ƒ = 1 MHz, Ta = Room temperature
Parameter
Symbol
CIN1
Signals
Test conditions
Vin = 0V
Max
5
Unit
pF
A0 to A9
Input capacitance
DQ capacitance
CIN2
RAS, UCAS, LCAS, WE, OE
DQ0 to DQ15
Vin = 0V
7
pF
CDQ
Vin = Vout = 0V
7
pF
AS4LC1M16E5 ordering information
Package \ RAS access time
50 ns
60 ns
AS4LC1M16E5-50JC
AS4LC1M16E5-50JI
AS4LC1M16E5-60JC
AS4LC1M16E5-60JI
Plastic SOJ, 400 mil, 42-pin
AS4LC1M16E5-50TC
AS4LC1M16E5-50TI
AS4LC1M16E5-60TC
AS4LC1M16E5-60TI
TSOP II, 400 mil, 44/50-pin
Shaded areas indicate advance information.
AS4LC1M16E5 part numbering system
AS4
LC
1M16E5
–XX
X
X
C = 5V CMOS
DRAM prefix LC = 3.3V CMOS
Package:
Temperature range
C=Commercial, 0°C to 70°C
T = 44/50-pin TSOP II 400 mil I=Industrial, -40°C to 85°C
Device number RAS access time J = 42-pin SOJ 400 mil
Alliance Semiconductor
4/11/01; v.1.0
P. 22 of 22
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may
be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If
the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use
of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made
exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected
to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against
all claims arising from such use.
AS4LC1M16E5-50JC 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AS4LC1M16E5-50JI | ETC | 3V 1M X 6 CMOS DRAM (EDO) | 获取价格 |
|
| AS4LC1M16E5-50TC | ETC | 3V 1M X 6 CMOS DRAM (EDO) | 获取价格 |
|
| AS4LC1M16E5-50TI | ETC | 3V 1M X 6 CMOS DRAM (EDO) | 获取价格 |
|
| AS4LC1M16E5-60JC | ETC | 3V 1M X 6 CMOS DRAM (EDO) | 获取价格 |
|
| AS4LC1M16E5-60JI | ETC | 3V 1M X 6 CMOS DRAM (EDO) | 获取价格 |
|
| AS4LC1M16E5-60TC | ETC | 3V 1M X 6 CMOS DRAM (EDO) | 获取价格 |
|
| AS4LC1M16E5-60TI | ETC | 3V 1M X 6 CMOS DRAM (EDO) | 获取价格 |
|
| AS4LC1M16EC-6 | MICROSS | DRAM | 获取价格 |
|
| AS4LC1M16EC-6/883C | MICROSS | EDO DRAM, 1MX16, 60ns, CMOS, CDSO44, 0.450 INCH, CERAMIC, LCC-50/44 | 获取价格 |
|
| AS4LC1M16EC-7 | MICROSS | DRAM | 获取价格 |
|
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