概述
数据手册AS5SS128K36DQ-11XT 概述
x36 Fast Synchronous SRAM
X36高速同步SRAM
AS5SS128K36DQ-11XT 数据手册
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PDF下载SRAM
AS5SS128K36
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. Zero Bus Latency SRAM
family employs high-speed, low-power CMOS designs using an ad-
vanced CMOS process.
128K x 36 SSRAM
SYNCHRONOUS ZBL SRAM
FLOW-THRU OUTPUT
ASI’s 4Mb ZBL SRAMs integrate a 128K x 36 SRAM core
with advanced synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMS are optimized for 100 percent bus utilization,
eliminating any turnaround cycles for READ to WRITE, or WRITE
to READ, transitions. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input (CLK). The
synchronous inputs include all addresses, all data inputs, chip enable
(CE\), two additional chip enables for easy depth expansion (CE2,
CE2\), cycle start input (ADV/LD\), synchronous clock enable (CKE\),
byte write enables (BWa\, BWb\, BWc\, and BWd\) and read/write (R/
W\).
Asynchronous inputs include the output enable (OE\, which
may be tied LOW for control signal minimization), clock (CLK) and
snooze enable (ZZ, which may be tied LOW if unused). There is also
a burst mode pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left unconnected if
burst is unused. The flow-through data-out (Q) is enabled by OE\.
WRITE cycles can be from one to four bytes wide as controlled by the
write control inputs.
FEATURES
• High frequency and 100% bus utilization
• Fast cycle times: 11ns & 12ns
• Single +3.3V +5% power supply (VDD
)
• Advanced control logic for minimum control signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W\ (READ/WRITE) control pin
• CKE\ pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data I/Os and
control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to eliminate the
need to control OE\
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 8Mb, and 16Mb ZBL
SRAM
All READ, WRITE and DESELECT cycles are initiated by
the ADV/LD\ input. Subsequent burst addresses can be internally
generated as controlled by the burst advance pin (ADV/LD\). Use of
burst mode is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.
• Automatic power-down
To allow for continuous, 100 percent use of the data bus,
the flow-through ZBL SRAM uses a LATE WRITE cycle. For ex-
ample, if a WRITE cycle begins in clock cycle one, the address is
present on rising edge one. BYTE WRITEs need to be asserted on the
same cycle as the address. The write data associated with the address
is required one cycle later, or on the rising edge of clock cycle two.
Address and write control are registered on-chip to simplify
WRITE cycles. This allows self-timed WRITE cycles. Individual
byte enables allow individual bytes to be written. During a BYTE
WRITE cycle, BWa\ controls DQa pins; BWb\ controls DQb pins;
BWc\ controls DQc pins; and BWd\ controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e., when ADV/LD\ is
LOW. Parity/ECC bits are available on this device.
OPTIONS
MARKING
• Timing (Access/Cycle/MHz)
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
-11
-12
• Packages
100-pin TQFP
DQ No. 1001
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
Austin’s 4Mb ZBL SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are LVTTL-compatible.
The device is ideally suited for systems requiring high bandwidth and
zero bus turnaround delays.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
1
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
PIN ASSIGNMENT
(Top View)
100-pinTQFP (DQ)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQc
DQc
DQc
1
2
3
DQb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
VSS
4
5
6
7
8
9
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
DQb
DQb
DQb
DQb
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
Q
VDD
DQb
DQb
VSS
VSS
VDD
ZZ
Q
DQc
DQc
VSS
VDD
VDD
VSS
DQd
DQd
DQa
DQa
VDDQ
VDD
Q
VSS
VSS
DQd
DQd
DQd
DQd
VSS
DQa
DQa
DQa
DQa
VSS
VDD
Q
VDD
Q
DQd
DQd
DQd
DQa
DQa
DQa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PIN DESCRIPTIONS
TQFP PINS
37
SYMBOL
SA0
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as
address bits for the higher-density 8Mb and 16Mb ZBL SRAMs, respectively. SA0 and
SA1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
36
SA1
32-35, 44-50,
81, 82, 99, 100
SA
93
94
95
96
BWa\
BWb\
BWc\
BWd\
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to
be written when a WRITE cycle is active and must meet the setup and hold times
around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle
as the address. BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls
DQc pins; BWd\ controls DQd pins.
87
CKE\
Input
Input
Synchronous Clock Enable: This active LOW input permits CLK to propagate
throughout the device. When CKE is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This input must meet setup and
hold times around the rising edge of CLK.
Read/Write: This input determines the cycle type when ADV/LD\ is LOW and is the
only means for determining READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin
permits BYTE WRITE operations and must meet the setup and hold times around the
rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW.
88
R/W\
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
2
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
PIN DESCRIPTIONS (continued)
TQFP PINS
SYMBOL
TYPE
DESCRIPTION
64
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a
low-power standby mode in which all data in the memory array is retained. When ZZ
is active, all other inputs are ignored.
89
CLK
Input
Clock: This signal registers the address, data, chip enables, byte write enables and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock's rising edge.
98, 92
97
CE\, CE2\
CE2
Input
Input
Synchronous Chip Enable: These active LOW inputs are used to enable the device
and are sampled only when a new external address is loaded (ADV/LD\ LOW). CE2\
can be used for memory depth expansion.
Synchronous Enable: This active HIGH input is used to enable the device and is
sampled only when a new external address is loaded (ADV/LD\ LOW). This input can
be used for memory depth expansion.
86
85
OE\
(G\)
ADV/LD\
Input
Input
Output Enable: This active LOW, asynchronous inputs enables the data I/O output
drivers. G\ is the JEDEC-standard term for OE\.
Synchronous Address Advance/Load: When HIGH, this input is used to advance the
internal burst counter, controlling burst access after the external address is loaded.
When ADV/LD\ is HIGH, R/W\ is ignored. A LOW on ADV/LD\ clocks a new address
at the CLK rising edge.
31
MODE
(LBO\)
Input
Mode: This inputs selects the burst sequence. A LOW on this pin selects linear burst.
NC or HIGH on this pin selects interleaved burst. Do not alter input state while device
is operating. LBO\ is the JEDEC-standard term for MODE.
(a) 51, 52, 53, 56-59,
62, 63
(b) 68, 69, 72-75, 78,
79, 80
DQa
DQb
DQc
DQd
Input/Output SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins;
Byte "d" is DQd pins. Input data must meet setup and hold times around the rising
edge CLK.
(c)1, 2, 3, 6-9, 12, 13
(d) 18, 19, 22-25, 28,
29, 30
15, 16, 41, 65, 91
Supply
Ground
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
Ground: GND
V
DD
5, 10, 14, 17, 21, 26
40, 55, 60, 66, 67, 71
76, 90
Vss
4, 11, 20, 27, 54, 61
70, 77
38, 39, 42, 43, 83, 84
64
Supply
----
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating
Conditions for range.
No Connect: These pins can be left floating or connected to GND to minimize thermal
impedance.
V
Q
DD
NC
----
38, 39, 42, 43
DNU
NF
Do Not Use: These signals may with be unconnected or wired to GND to
minimize thermal impedance.
No Function: These pins are internally connected to the die and will have the
capacitance of an input pin. It is allowable to leave these pins unconnected or
driven by signals. Pins 83 and 84 are reserved for address expansion.
----
83, 84
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
3
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
First Address Second Address Third Address Fourth Address
(external)
X...X00
X...X01
X...X10
X...X11
(internal)
X...X01
X...X00
X...X11
X...X10
(internal)
X...X10
X...X11
X...X00
X...X01
(internal)
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
First Address Second Address Third Address Fourth Address
(external)
X...X00
X...X01
X...X10
X...X11
(internal)
X...X01
X...X10
X...X11
X...X00
(internal)
X...X10
X...X11
X...X00
X...X01
(internal)
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS*
FUNCTION
R/W\
BWa\
BWb\
BWc\
BWd\
READ
H
X
X
X
X
H
H
H
H
Write Abort/NOP
L
L
L
L
H
L
H
H
L
H
H
H
L
Write Byte a (DQa, DQPa)2
Write Byte b (DQb, DQPb)2
Write Byte c (DQc, DQPc)2
H
H
H
Write Byte d (DQd, DQPd)2
L
L
H
L
H
L
H
L
L
L
Write all bytes
* NOTE: Using R/W\ and byte write(s), any one or more bytes may be written.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
4
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
17
17
15
17
SA0, SA1, SA
ADDRESS
REGISTER
SA1'
SA0'
SA1
SA0
D1
D0
Q1
Q0
MODE
K
BURST
LOGIC
ADV/LD\
K
CE
CLK
CKE\
17
WRITE ADDRESS
REGISTER
17
O
U
D
T
A
P
T
U
A
T
S
E
N
S
E
ADV/LD\
BWa\
BWb\
BWc\
BWd\
R/W\
128K X 9 X 4
WRITE REGISTRY AND
DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
WRITE
DRIVERS
B
U
F
F
E
R
S
MEMORY
ARRAY
A
M
P
S
N
G
E
INPUT
REGISTER
E
OE\
CE\
CE2
CE2\
READ
LOGIC
NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed
information.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
5
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
STATE DIAGRAM FOR ZBL SRAM
DS
BURST
DS
DS
DESELECT
WRITE
READ
WRITE
BEGIN
READ
READ
BEGIN
WRITE
READ
BURST
BURST
WRITE
BURST
READ
BURST
WRITE
BURST
BURST
KEY:
COMMAND
DS
READ
ACTION
DESELECT
New READ
New WRITE
WRITE
BURST READ,
BURST
BURST WRITE or
CONTINUE DESELECT
NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE\ HIGH only
blocks the clock (CLK) input and does not change the state of the device.
2. States change on the rising edge of the clock (CLK).
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
6
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
(5-10)
TRUTH TABLE
ADDRESS
USED
None
OPERATION
CE\ CE2\ CE2 ZZ ADV/LD\ R/W\ BWx OE\ CKE\ CLK
DQ NOTES
High-Z
DESELECT CYCLE
DESELECT CYCLE
DESELECT CYCLE
CONTINUE DESELECT CYCLE
READ CYCLE
(Begin Burst)
READ CYCLE
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
H
X
X
X
X
H
X
X
X
X
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
None
None
None
High-Z
High-Z
High-Z
X
H
1
External
Next
L
X
L
L
X
L
H
X
H
X
H
X
H
X
L
L
L
L
L
L
L
L
L
H
L
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
Q
Q
1, 11
2
External
Next
H
H
X
X
X
X
High-Z
DUMMY READ
X
L
X
L
H
L
High-Z 1, 2, 11
(Continue Burst)
WRITE CYCLE
(Begin Burst)
WRITE CYCLE
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK EDGE
(Stall)
External
Next
D
3
X
L
X
L
H
L
X
L
L
D
1, 3, 11
2, 3
None
H
H
High-Z
High-Z
1, 2, 3,
11
Next
X
X
H
X
Current
None
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
X
---
4
SNOOZE MODE
H
X
High-Z
NOTE:
1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ
or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a
DESELECT cycle is first executed.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.
A WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE\ may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. OE\ may be used when the bus turn-on and turn-off times do not meet an applications
requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK
EDGE cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa\, BWb\, BWc\,
BWd\) are HIGH. BWx = L means all byte write signals are LOW.
6. BWa\ enables WRITES to Byte “a” (DQa pins); BWb\ enables WRITES to Byte “b” (DQb pins); BWc\ enables WRITES to
Byte “c” (DQc pins); BWd\ enables WRITES to Byte “d” (DQd pins).
7. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE\ HIGH.
9. This device contains circuitry that will ensure that the outputs will be in the High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
7
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
*Stresses greater than those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operation section of this speci-
fication is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS.................-0.5V to +4.6V
Voltage on VDDQ Supply Relative to VSS.................-0.5V to VDD
VIN.................................................................. -0.5V to VDDQ +0.5V
Storage Temperature (Plastics) ..........................-55°C to +150°C
Short Circuit Output Current ........................…..................100mA
Max. Junction Temperature*.............................................+150°C
**Junction Temperature depends upon package type, cycle time, load-
ing, ambient temperture and airflow.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC < TA < +125oC;VDD, VDDQ = +3.3V +0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
2.0
V
1, 2
VIH
VDD + 0.3
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
DQ Pins
2.0
-0.3
-1.0
V
V
1, 2
1, 2
3
VIH
VIL
ILI
V
DD + 0.3
0.8
1.0
µA
0V < VIN < VDD
Output(s) Disabled,
0V < VIN < VDD
Output Leakage Current
-1.0
1.0
µA
ILO
Output High Voltage
Output Low Voltage
Supply Voltage
2.4
---
---
0.4
V
V
V
V
1, 4
1, 4
1
I
OH = -4.0mA
VOH
VOL
VDD
IOL = 8.0mA
3.135
3.135
3.465
VDD
Isolated Output Buffer Supply
1, 5
VDDQ
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL TYP
MAX UNITS NOTES
CI
CO
CA
3
4
3
3
4
pF
pF
pF
pF
6
6
6
6
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
TA = 25oC; f = 1 MHz
VDD = 3.3V
5
3.5
3.5
CCK
Clock Capacitance
NOTE:
1.
2.
All voltages referenced to VSS (GND).
Overshoot: VIH < +4.6V for t < tKHKH /2 for I < 20mA.
Undershoot: VIL < -0.7V for t < tKHKH /2 for I < 20mA.
Power-up: VIH < +3.465V and VDD < 3.135V for t < 200ms.
3.
4.
MODE pin has an internal pull-up, and input leakage = + 10µA.
The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curvers
are available upon request.
5.
6.
V
DDQ should never exceed VDD. VDD and VDDQ should be externally wired together to the same power supply.
This parameter is sampled.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
8
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(-55oC < TA < +125oC; VDD, VDDQ = +3.3V +0.165V unless otherwise noted)
MAX
DESCRIPTION
CONDITIONS
SYM
-11
-12
UNITS NOTES
Device selected; All inputs < VIL
or > VIH; Cycle time > tKC (MIN)
Power Supply
Current: Operating
IDD
275
250
mA
mA
1, 2
VDD = MAX; Outputs open
Device selected; VDD = MAX;
CKE\ > VIH;
Power Supply
Current: Idle
22
20
1, 2
IDD1
All inputs < VSS + 0.2 or > VDD -0.2;
Cycle time > tKC (MIN)
Device selected; VDD = MAX;
CMOS Standby
TTL Standby
10
25
10
25
mA
mA
2
2
ISB2
All inputs < VSS + 0.2 or > VDD -0.2;
All inputs static; CLK frequency = 0
Device selected; VDD = MAX;
ISB3
All inputs < VIL or > VIH;
All inputs static; CLK frequency = 0
Device selected; VDD = MAX;
ADV/LD\ > VIH; All inputs < VSS + 0.2
Clock Running
Snooze Mode
ISB4
65
10
60
10
mA
mA
2
2
or > VDD - 0.2; Cycle time > tKC (MIN)
ZZ > VIH
ISB2Z
THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
SYM
θJA
TYP UNITS NOTES
Thermal Resistance
(Junction to Ambient)
oC/W
46
3
3
Thermal Resistance
(Junction to Top of Case)
oC/W
2.8
θJC
NOTE:
1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
2. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device
is active (not in deselected mode).
3. This parameter is sampled.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
9
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
6, 8, 9
AC ELECTRICAL CHARACTERISTICS
(-55oC < TA < +125oC;VDD, VDDQ = +3.3V +0.165V)
-11
-12
SYM
MIN
MAX
MIN
MAX
UNITS NOTES
DESCRIPTION
CLOCK
Clock cycle time
Clock frequency
Clock HIGH time
11
12
ns
tKHKH
tKF
tKHKL
tKLKH
90
83
MHz
3.0
3.0
3.0
3.0
ns
ns
1
1
Clock LOW time
OUTPUT TIMES
Clock to output valid
8.5
9.0
ns
ns
ns
ns
ns
ns
ns
tKHQV
tKHQX
tKHQX1
tKHQZ
tGLQV
tGLQX
tGHQZ
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE\ to output valid
3.0
3.0
3.0
3.0
2
2, 3, 4, 5
2, 3, 4, 5
6
5.0
5.0
5.0
5.0
OE\ to output in Low-Z
0
0
2, 3, 4, 5
2, 3, 4, 5
OE\ to output in High-Z
SETUP TIMES
Address
5.0
5.0
2.2
2.2
2.2
2.2
2.5
2.5
2.5
2.5
ns
ns
ns
ns
7
7
7
7
tAVKH
tEVKH
tCVKH
tDVKH
Clock enable (CKE\)
Control signals
Data-in
HOLD TIMES
Address
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
7
7
7
7
tKHAX
tKHEX
tKHCX
tKHDX
Clock enable (CKE\)
Control signals
Data-in
NOTE:
1. Measured as HIGH above VIH and LOW below VIL.
2. Contact ASI for more information on these parameters.
3. This parameter is sampled.
4. This parameter is measured with the output loading shown in Figure 2.
5. Transistion is measured +200mV from steady state voltage.
6. OE\ can be considerted a “Don’t Care” during WRITEs; however, controlling OE\ can help fine-tune a system for ZBL timing.
7. This is a synchrnous device. All addresses must meet the specified setup and hold times for all rising edgges o CLK when they are being
registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of
clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD\ is LOW to remain enabled.
8. Test conditions as specified with the output loading shown in Figure 1, unless otherwise noted.
9. A WRITE cycle is defined by R/W\ LOW having been registered into the device at ADV/LD\ LOW. A READ cycle is defined by R/W\
HIGH with ADV/LD\ LOW. Both cases must meet setup and hold times.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
10
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels
Vss to 3.3V
Input slew rate
1 ns
1.5V
1.5V
Input timing reference levels
Output reference levels
Output load
See Figures 1 and 2
OUTPUT LOADS
3.3v
317Ω
Q
Z0=50Ω
Q
50Ω
5 pF
351Ω
VT=1.5V
Fig. 1 OUTPUT LOAD EQUIVALENT
Fig. 2 OUTPUT LOAD EQUIVALENT
LOAD DERATING CURVES
The ASI 128K x 36 ZBL SRAM timing is dependent upon
the capacitive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
11
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
SNOOZE MODE
becomes a logic HIGH, ISB2Z is guaranteed after the time tZZI
SNOOZE MODE is a low-current, “power-down” mode is met. Any READ or WRITE operation pending when the
in which the device is deselected and current is reduced to device enters SNOOZE MODE is not guaranteed to complete
sucessfully. Therefore, SNOOZE MODE must not be initiated
until valid pending operations are completed. Similarly, when
exiting SNOOZE MODE during tRZZ, only a DESELECTor READ
cycle should be given.
ISB2Z. The duration of SNOOZE MODE is dictated by the
length of time the ZZ pin is in a HIGH state. After the device
enters SNOOZE MODE, all inputs except ZZ become dis-
abled and all outputs go to High-Z.
The ZZ pin is an asynchronous, active HIGH input that
causes the device to enter SNOOZE MODE. When the ZZ pin
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYM
MIN
MAX UNITS NOTES
Current during SNOOZE MODE
10
mA
ns
ns
ns
ns
ZZ > VIH
ISB2Z
ZZ active to input ignored
0
0
1
1
1
1
tZZ
tRZZ
tZZI
tKHKH
tKHKH
tKHKH
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
0
tRZZI
SNOOZE MODE WAVEFORM
CLK
tZZ
tZZI
IISB2Z
tRZZ
ZZ
ISUPPLY
tRZZI
DESELECT
or READ Only
ALL INPUTS
(except ZZ)
High-Z
Outputs (Q)
Don’t Care
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
12
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
READ/WRITE TIMING
tKHKH
1
2
3
4
5
6
7
8
9
10
CLK
tKHKL
t
EVKH tKHEX
tKLKH
CLE\
t
CVKH tKHCX
CE\
ADV/LD\
R/W\
BWx\
A1
A2
A3
A4
A5
A6
A7
ADDRESS
tKHQV
tKHQX1
tAVKH tKHAX
tKHQZ
tKHQX
tGLQV
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
DQ
t
DVKH tKHDX
tGHQZ
tKHQX
tGLQX
OE\
DESELECT
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
WRITE
D(A7)
READ
Q(A6)
WRITE
D(A1)
WRITE
D(A2)
COMMAND
D(A2+1)
Q(A4 +1)
Don’t Care
Undefined
READ/WRITE TIMING PARAMETERS
-11
-12
-11
-12
SYMBOL
MIN
MAX
MIN
MAX
SYMBOL
MIN
MAX
MIN
MAX
11
12
tGHQZ
tAVKH
tEVKH
tCVKH
tDVKH
tKHAX
tKHEX
tKHCX
tGLDX
5.0
5.0
tKHKH
90
83
2.2
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
tKF
3.0
3.0
3.0
3.0
2.2
2.2
2.2
0.5
0.5
0.5
0.5
tKHKL
tKLKH
tKHQV
tKHQX
tKHQX1
tKHQZ
tGLQV
tGLQX
8.5
9.0
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
0
0
NOTE:
1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0=linear, 1=interleaved). BURST operations are optional.
3. CE\ represents three signals. When CE\ = 0, it represents CE\ = 0, CE2\ = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
13
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
NOP, STALL AND DESELECT CYCLES
1
2
3
4
5
6
7
8
9
10
CLK
CKE
CE
ADV/LD
R/W
BWx
A1
A2
A3
A4
A5
ADDRESS
tKHQZ
D(A1)
Q(A3)
Q(A2)
D(A4)
NOP
Q(A5)
DQ
tKHQX
COMMAND
DESELECT CONTINUE
DESELECT
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
READ
Q(A5)
WRITE
D(A1)
READ
Q(A2)
Don’t Care
Undefined
NOP, STALL AND DESELECT TIMING PARAMETERS
-11
-12
SYMBOL
MIN
MAX
MIN
MAX
3.0
3.0
tKHQX
5.0
5.0
tKHQZ
NOTE:
1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE\ being used to create a “pause”. A WRITE is not performed
during this cycle.
2. For this waveform, ZZ and OE\ are tied LOW.
3. CE\ represents three signals. When CE\ = 0, it represents CE\ = 0, CE2\ = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data
may be from the input data register.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
14
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
ASI Case # 1001 (Package Designator DQ)
16.00 +0.20/-0.05
14.00 + 0.10
See Detail A
1.40 + 0.05
0.10+0.10/-0.05
1.50 + 0.10
0.15 +0.03/-0.02
1.00 TYP
Detail A
0.32+0.06/-0.10
0.65 Basic
0.60 + 0.15
NOTE: All dimensions in Millimeters.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
15
SRAM
AS5SS128K36
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS5SS128K36DQ-11/IT
Package
Device Number
Speed ns Process
Type
DQ
DQ
AS5SS128K36
AS5SS128K36
-11
-12
/*
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
-40oC to +85oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.0 12/00
16
AS5SS128K36DQ-11XT 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AS5SS128K36DQ-12/IT | AUSTIN | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT | 获取价格 |
|
| AS5SS128K36DQ-12/XT | AUSTIN | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT | 获取价格 |
|
| AS5SS128K36DQ-12IT | ETC | x36 Fast Synchronous SRAM | 获取价格 |
|
| AS5SS128K36DQ-12XT | ETC | x36 Fast Synchronous SRAM | 获取价格 |
|
| AS5SS128K36DQ-15 | ETC | x36 Fast Synchronous SRAM | 获取价格 |
|
| AS5SS128K36DQ-15/883C | MICROSS | ZBT SRAM, 128KX36, 15ns, CMOS, PQFP100, TQFP-100 | 获取价格 |
|
| AS5SS128K36DQ-7.5/ET | MICROSS | Standard SRAM | 获取价格 |
|
| AS5SS128K36DQ-7.5/IT | MICROSS | Standard SRAM | 获取价格 |
|
| AS5SS128K36DQ-7.5/XT | MICROSS | Standard SRAM | 获取价格 |
|
| AS5SS128K36DQ-7.5L/ET | MICROSS | Standard SRAM | 获取价格 |
|
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