AS7C33128PFS18A-133TQC [ETC]
x18 SRAM ; X18 SRAM\n型号: | AS7C33128PFS18A-133TQC |
厂家: | ETC |
描述: | x18 SRAM
|
文件: | 总12页 (文件大小:286K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
January 2002
AS7C33128PFS16A
AS7C33128PFS18A
®
3.3V 128K × 16/18 pipeline burst synchronous SRAM
Features
• Organization: 131,072words × 16 or 18 bits
• Fast clock speeds to 200MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
• Fully synchronous register-to-register operation
• “Flow-through” mode
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• 30 mW typical standby power in power down mode
DDQ
®
• Single-cycle deselect
• Pentium® compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
1. Pentium is a registered trademark of Intel Corporation. NTD™
1
is a trademark of Alliance Semiconductor Corporation. All trade-
marks mentioned in this document are the property of their respec-
tive owners.
Logic block diagram
Pin arrangement
LBO
CLK
ADV
CLK
CS
Burst logic
17 15
128K × 16/18
Memory
ADSC
ADSP
CLR
A16
NC
NC
V
SSQ
NC
DQpa/NC
DQa
DQa
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
17
17
2
AddresQs
D
array
A[16:0]
3
CS
V
4
register
DDQ
V
DDQ
V
5
SSQ
NC
CLK
6
NC
7
16/18
16/18
DQb
DQb
8
9
GWE
BW
b
D
Q
V
DDQ
DQb
V
10
11
SSQ
SSQ
V
V
DDQ
DQb 12
DQb 13
Byte Write
registers
DQa
DQa
VSS
BWE
CLK
FT
14
15
16
17
D
Q
TQFP 14 × 20mm
DQa
NC
V
DD
2
BW
Byte Write
registers
V
ZZ
NC
a
DD
V
SS
CLK
DQa
DQa
DQb 18
DQb 19
CE0
CE1
CE2
OE
D EnableQ
register
Input
V
SSQ
V
20
21
DDQ
DDQ
Output
V
V
SSQ
registers
registers
DQa
DQa
NC
DQb 22
DQb 23
CE
CLK
CLK
CLK
DQpb/NC
NC
24
25
26
27
28
29
30
NC
D EnableQ
delay
V
DDQ
V
Power
down
SSQ
SSQ
ZZ
V
V
register
DDQ
NC
NC
NC
NC
NC
NC
CLK
OE
DATA [17:0]
DATA [15:0]
FT
Note: pins 24, 74 are NC for ×16.
Selection guide
–200
5
–183
–166
6
–133
7.5
133
4
–100
10
Units
Minimum cycle time
5.4
183
3.1
540
140
30
ns
MHz
ns
Maximum pipelined clock frequency
200
3
166
3.5
475
130
30
100
5
Maximum pipelined clock access time
Maximum operating current
570
160
30
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
1/21/02; v.1.1
Alliance Semiconductor
P. 1 of 12
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128PFS16A
AS7C33128PFS18A
®
Functional description
The AS7C33128PFS16A and AS7C33128PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
*
(TMS320C6X), and PowerPC™ -based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 5.0/5.4/6.0/7.5/10 ns with clock access times (t ) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 MHz
CD
bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst
addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes
are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium® count
sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
•
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33128PFS16A and AS7C33128PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP packaging.
™
*PowerPC is a tradenark International Business Machines Corporation.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Signals
Address and control pins
I/O pins
Test conditions
VIN = 0V
Max
5
Unit
pF
CI/O
VIN = VOUT = 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
T
L
X
L
X
L
H
T
H
H
L
X
H
F*
F*
H
Key:
X = Don’t Care, L = Low, H = High, T=True, F=False
* valid rea; n = a,b
WE, WEn = internal write signal
1/21/02; v.1.1
Alliance Semiconductor
P. 2 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
Signal descriptions
Signal
I/O
Properties
CLOCK
SYNC
Description
CLK
I
I
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
A0–A16
DQ[a,b]
I/O
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0
is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
CE0
I
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on
clock edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
I
I
SYNC
SYNC
Address strobe (processor). Asserted LOW to load a new address or to enter standby
mode.
Address strobe (controller). Asserted LOW to load a new address or to enter standby
mode.
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Burst advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and
BW[a,b] control write enable.
GWE
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]
inputs.
BWE
BW[a,b]
OE
I
I
I
I
SYNC
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and
BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the
cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in
read mode.
ASYNC
Count mode. When driven HIGH, count sequence follows Intel XOR convention.
When driven LOW, count sequence follows linear convention. This signal is
internally pulled HIGH.
STATIC default =
HIGH
LBO
Flow-through mode.When LOW, enables single register flow-through mode.
Connect to VDD if unused or for pipelined operation.
FT
I
I
STATIC
ASYNC
ZZ
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Symbol
VDD, VDDQ
VIN
Min
–0.5
–0.5
–0.5
–
Max
+4.6
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
VDD + 0.5
VDDQ + 0.5
1.8
V
VIN
V
PD
W
mA
°C
°C
DC output current
IOUT
–
50
Storage temperature (plastic)
Temperature under bias
Tstg
–65
–65
+150
Tbias
+135
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
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AS7C33128PFS16A
AS7C33128PFS18A
®
Synchronous truth table
1
CE0
H
L
CE1
X
L
CE2 ADSP ADSC ADV
WEn
X
X
X
X
X
X
X
F
O
E
Address accessed CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z2
Hi−Z
Hi−Z2
Hi−Z
Q
X
X
X
H
H
L
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
NA
NA
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
X
X
X
X
L
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
Begin read
Begin read
Begin read
Cont. read
Cont. read
Suspend read
Suspend read
Cont. read
Cont. read
Suspend read
Suspend read
Begin write
Cont. write
Cont. write
Suspend write
Suspend write
L
L
L
H
L
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
L
L
F
H
L
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
F
L
F
H
L
Next
Hi−Z
Q
H
H
L
F
Current
Current
Next
F
H
L
Hi−Z
Q
F
L
F
H
L
Next
Hi−Z
Q
H
H
X
L
F
Current
Current
External
Next
F
H
X
X
X
X
X
Hi−Z
D3
T
T
T
T
T
X
H
X
H
X
X
X
X
H
H
H
H
D
L
Next
D
H
H
Current
Current
D
D
Key: X = Don’t Care, L = Low, H = High.
1
2
3
See “Write enable truth table” on page 2 for more information.
Q in flow through mode
For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Recommended operating conditions
Parameter
Symbol
VDD
Min
3.135
0.0
Nominal
3.3
Max
3.6
0.0
3.6
0.0
2.9
0.0
Unit
Supply voltage
V
VSS
0.0
VDDQ
VSSQ
3.135
0.0
3.3
3.3V I/O supply voltage
2.5V I/O supply voltage
V
V
0.0
VDDQ
VSSQ
2.35
0.0
2.5
0.0
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P. 4 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
Recommended operating conditions
Parameter
Symbol
VIH
Min
2.0
–0.52
Nominal
Max
VDD + 0.3
0.8
Unit
–
–
–
–
–
Address and
control pins
V
VIL
Input voltages1
VIH
2.0
VDDQ + 0.3
0.8
I/O pins
V
VIL
–0.52
0
Ambient operating temperature
TA
70
°C
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 V min = –2.0V for pulse width less than 0.2 × t
IL
.
RC
TQFP thermal resistance
Description
Conditions
Symbol
Typ i c a l
Units
Thermal resistance
θ
46
°C/W
°C/W
(junction to ambient)1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
JA
Thermal resistance
θ
2.8
(junction to top of case)1
JC
1 This parameter is sampled.
DC electrical characteristics
–200
–183
–166
–133
–100
Parameter
Symbol
Test conditions
Min Max Min Max Min Max Min Max Min Max Unit
Input leakage
current1
VDD = Max, VIN = GND to
VDD
|ILI|
–
–
2
2
–
–
2
2
–
–
2
2
–
–
2
2
–
–
2
2
µA
µA
Output leakage
current
OE ≥ VIH, VDD = Max,
|ILO
|
VOUT = GND to VDD
Operating
power supply
current
CE0 = VIL, CE1 = VIH, CE2
= VIL,
f = fMax, IOUT = 0 mA
ICC
–
–
–
570
160
30
–
–
–
540
140
30
–
–
–
475
130
30
–
–
–
425
100
30
–
–
–
325 mA
90
Deselected, f = fMax, ZZ ≤
ISB
VIL
Deselected, f = 0, ZZ ≤ 0.2V
Standby power
supply current
ISB1
all VIN ≤ 0.2V or ≥ VDD
–
30
mA
0.2V
Deselected, f = f , ZZ
≥ V
DD
Max
ISB2
– 0.2V
–
30
–
30
–
30
–
30
–
30
All VIN ≤ VIL or ≥ VIH
VOL
IOL = 8 mA, VDDQ = 3.465V
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
Output voltage
V
IOH = –4 mA, VDDQ
3.135V
=
VOH
2.4
2.4
2.4
2.4
2.4
–
1 LBO pin has an internal pull-up and input leakage = 10 µa.
Note: ICC give with no output loading. ICC increases with faster cycle times and greater output loading.
1/21/02; v.1.1
Alliance Semiconductor
P. 5 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
DC electrical characteristics for 2.5V I/O operation
–200
–183
–166
–133
–100
Parameter
Symbol
Test conditions
Min Max Min Max Min Max Min Max Min Max Unit
Output leakage
current
OE ≥ VIH, VDD = Max,
|ILO
|
–1
–
1
–1
1
–1
1
–1
1
–1
1
µA
V
VOUT = GND to VDD
VOL
IOL = 2 mA, VDDQ = 2.65V
0.7
–
–
0.7
–
–
0.7
–
–
0.7
–
–
0.7
–
Output voltage
VOH
IOH = –2 mA, VDDQ = 2.35V 1.7
1.7
1.7
1.7
1.7
1/21/02; v.1.1
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P. 6 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
Timing characteristics over operating range
–200
–183
–166
–133
–100
Parameter
Clock frequency
Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes*
fMax
tCYC
–
5
9
200
–
–
183
–
–
6
166
–
–
133
–
–
100 MHz
Cycle time (pipelined mode)
5.4
10
7.5
12
10
12
–
–
ns
ns
Cycle time (flow-through mode)
tCYCF
–
–
10
–
–
Clock access time (pipelined
mode)
tCD
–
–
3.0
8.5
–
–
3.1
9
–
–
3.5
9
–
–
4.0
10
–
–
5.0
12
ns
ns
Clock access time (flow-through
mode)
tCDF
Output enable LOW to data valid
Clock HIGH to output Low Z
tOE
–
0
3.0
–
–
0
3.1
–
–
0
3.5
–
–
0
4.0
–
–
0
5.0
–
ns
ns
tLZC
2,3,4
2
Data output invalid from clock
HIGH
tOH
1.5
0
–
–
1.5
0
–
–
1.5
0
–
–
1.5
0
–
–
1.5
0
–
–
ns
ns
Output enable LOW to output
Low Z
tLZOE
2,3,4
Output enable HIGH to output
High Z
tHZOE
tHZC
–
–
0
3.0
3.0
–
–
–
0
3.1
3.1
–
–
–
0
3.5
3.5
–
–
–
0
4.0
4.0
–
–
–
0
4.5
5.0
–
ns
ns
ns
2,3,4
2,3,4
Clock HIGH to output High Z
Output enable HIGH to invalid
output
tOHOE
Clock HIGH pulse width
tCH
tCL
2.2
2.2
1.4
1.4
1.4
1.4
0.5
0.5
0.5
0.5
1.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.4
2.4
1.4
1.4
1.4
1.4
0.5
0.5
0.5
0.5
1.4
1.4
1.4
0.5
0.5
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.5
3.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
Clock LOW pulse width
Address setup to clock HIGH
Data setup to clock HIGH
Write setup to clock HIGH
Chip select setup to clock HIGH
Address hold from clock HIGH
Data hold from clock HIGH
Write hold from clock HIGH
tAS
6
tDS
6
tWS
tCSS
tAH
tDH
tWH
6,7
6,8
6
6
6,7
6,8
6
Chip select hold from clock HIGH tCSH
ADV setup to clock HIGH
ADSP setup to clock HIGH
ADSC setup to clock HIGH
ADV hold from clock HIGH
ADSP hold fromclock HIGH
tADVS
tADSPS 1.4
tADSCS 1.4
tADVH 0.5
tADSPH 0.5
tADSCH 0.5
6
6
6
6
ADSC hold from clock HIGH
6
*“Notes” column refers to “notes” on page 11.
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P. 7 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
Timing waveform of read cycle
t
t
CYC
CL
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
ADSC
t
ADSCS
t
ADSCH
t
AS
LOAD NEW ADDRESS
A3
t
AH
A1
A2
Address
t
WS
t
WH
GWE, BWE
t
CSS
t
CSH
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
CD
t
HZOE
t
OH
ADV INSERTS WAIT STATES
t
HZC
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
D
OUT
(pipelined mode)
t
OE
t
LZOE
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)
D
OUT
(flow-through mode)
t
HZC
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
BW[a:b] is don’t care.
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
1/21/02; v.1.1
Alliance Semiconductor
P. 8 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
Timing waveform of write cycle
t
t
CYC
t
CH
CL
CLK
t
ADSPS
t
ADSPH
ADSP
t
ADSCS
t
ADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
t
AS
t
AH
A1
A2
Address
t
WS
t
WH
BWE
BWa,b
t
CSS
t
CSH
CE0, CE2
CE1
t
ADV SUSPENDS BURST
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Data In
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
1/21/02; v.1.1
Alliance Semiconductor
P. 9 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
Timing waveform of read/write cycle
t
t
CYC
t
CH
CL
CLK
t
ADSPS
t
ADSPH
ADSP
t
AS
t
AH
A2
A3
A1
Address
t
WS
t
WH
GWE
CE0, CE2
CE1
t
ADVS
t
ADVH
ADV
OE
t
DS
t
DH
D(A2)
D
IN
t
t
t
t
LZOE
HZOE
OH
LZC
t
t
OE
CD
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
D
OUT
(pipeline mode)
t
CDF
Q(A3Ý11)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
D
OUT
(flow-through mode)
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
1/21/02; v.1.1
Alliance Semiconductor
P. 10 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O
317
Ω
Z = 50
Ω
50
Ω
0
D
V = 1.5V
OUT
+3.0V
D
L
OUT
90%
10%
90%
10%
5 pF*
GND
for 3.3V I/O;
30 pF*
351
Ω
= V
/2
DDQ
*including scope
and jig capacitance
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
is less than t
; and t
HZC
is less than t at any given temperature and voltage.
LZC
HZOE
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
LZOE
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
Chip select refers to CE0
,
BWE
,
BW[a:d].
CE2
,
CE1
,
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Min
0.05
1.35
0.22
0.09
13.90 14.10
19.90 20.10
0.65 nominal
15.90 16.10
21.90 22.10
Max
0.15
1.45
0.38
0.20
Hd
D
A1
A2
b
c
D
b
e
E
e
Hd
He
L
L1
α
He
E
0.45
1.00 nominal
0° 7°
0.75
Dimensions in millimeters
α
c
L1
A1 A2
L
1/21/02; v.1.1
Alliance Semiconductor
P. 11 of 12
AS7C33128PFS16A
AS7C33128PFS18A
®
Ordering information
–200 MHz
–183 MHz
AS7C33128PFS16A-200TQC
AS7C33128PFS16A-200TQI
AS7C33128PFS18A-200TQC
AS7C33128PFS18A-200TQI
AS7C33128PFS16A-183TQC
AS7C33128PFS16A-183TQI
AS7C33128PFS18A-183TQC
AS7C33128PFS18A-183TQI
–166 MHz
–133 MHz
–100 MHz
AS7C33128PFS16A-166TQC
AS7C33128PFS16A-133TQC
AS7C33128PFS16A-133TQI
AS7C33128PFS18A-133TQC
AS7C33128PFS18A-133TQI
AS7C33128PFS16A-100TQC
AS7C33128PFS16A-166TQI
AS7C33128PFS18A-166TQC
AS7C33128PFS18A-166TQI
AS7C33128PFS16A-100TQI
AS7C33128PFS18A-100TQC
AS7C33128PFS18A-100TQI
Part numbering guide
AS7C
33
128
PF
S
16/18
A
–XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 128=128K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: S=Single cycle deselect
6.Organization: 16=x16; 18=x18
7.Production version: A=first production version
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
1/21/02; v.1.1
Alliance Semiconductor
P. 12 of 12
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