AT29LV040A-20JI [ETC]
x8 Flash EEPROM ; X8闪存EEPROM\n
| 型号： | AT29LV040A-20JI |
| 厂家： | 
ETC |
| 描述： | x8 Flash EEPROM
|
| 文件： | 总13页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage, Range 3V to 3.6V Supply
• 3-Volt Only Read and Write Operation
• Software Protected Programming
• Fast Read Access Time - 200 ns
• Low Power Dissipation
– 15 mA Active Current
– 40 µA CMOS Standby Current
• Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Sectors (256 bytes/sector)
4-Megabit
(512K x 8)
3-volt Only
256-Byte Sector
Flash Memory
– Internal Address and Data Latches for 256 Bytes
• Two 16K Bytes Boot Blocks with Lockout
• Fast Sector Program Cycle Time - 20 ms Max.
• Internal Program Control and Timer
• DATA Polling for End of Program Detection
• Typical Endurance > 10,000 Cycles
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
The AT29LV040A is a 3-volt only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times to 200 ns, and a low 54 mW power dissipation. When
the device is deselected, the CMOS standby current is less than 40=µA. The device
AT29LV040A
PLCC Top View
Pin Configurations
Pin Name
A0 - A18
CE
Function
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A2 10
A1 11
A0 12
I/O0 13
OE
WE
I/O0 - I/O7
NC
TSOP Top View
Type 1
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
6
7
8
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
Rev. 0334E–03/01
1
endurance is such that any sector can typically be written
to in excess of 10,000 times. The programming algorithm is
compatible with other devices in Atmel’s 3-volt only Flash
memories.
During a reprogram cycle, the address locations and 256
bytes of data are captured at microprocessor speed and
internally latched, freeing the address and data bus for
other operations. Following the initiation of a program
cycle, the device will automatically erase the sector and
then program the latched data using an internal control
timer. The end of a program cycle can be detected by
DATA polling of I/O7. Once the end of a program cycle has
been detected, a new access for a read or program can
begin.
To allow for simple in-system reprogrammability, the
AT29LV040A does not require high input voltages for pro-
gramming. Three-volt-only commands determine the oper-
ation of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29LV040A is performed on a sector basis; 256 bytes of
data are loaded into the device and then simultaneously
programmed.
Block Diagram
Device Operation
READ: The AT29LV040A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
the software data protection feature, however the software
feature will guard against inadvertent program cycles dur-
ing power transitions.
Any attempt to write to the device without the 3-byte com-
mand sequence will start the internal write timers. No data
will be written to the device; however, for the duration of
tWC, a read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION PROGRAMMING: The
AT29LV040A has 2048 individual sectors, each 256 bytes.
Using the software data protection feature, byte loads are
used to enter the 256 bytes of a sector to be programmed.
The AT29LV040A can only be programmed or repro-
grammed using the software data protection feature. The
device is programmed on a sector basis. If a byte of data
within the sector is to be changed, data for the entire 256-
byte sector must be loaded into the device. The
AT29LV040A automatically does a sector erase prior to
loading the data into the sector. An erase command is not
required.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE.
The 256 bytes of data must be loaded into each sector. Any
byte that is not loaded during the programming of its sector
will be erased to read FFH. Once the bytes of a sector are
loaded into the device, they are simultaneously pro-
grammed during the internal programming period. After the
first data byte has been loaded into the device, successive
bytes are entered in the same manner. Each new byte to
be programmed must have its high to low transition on WE
(or CE) within 150 µs of the low to high transition of WE (or
CE) of the preceding byte. If a high to low transition is not
detected within 150 µs of the last low to high transition, the
load period will end and the internal programming period
Software data protection protects the device from inadvert-
ent programming. A series of three program commands to
specific addresses with specific data must be presented to
the device before programming may occur. The same three
program commands must begin each program operation.
All software program commands must obey the sector pro-
gram timing specifications. Power transitions will not reset
AT29LV040A
2
AT29LV040A
will start. A8 to A18 specify the sector address. The sector
address must be valid during each high to low transition of
WE (or CE). A0 to A7 specify the byte address within the
sector. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has
been initiated, and for the duration of tWC, a read operation
will effectively be a polling operation.
end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased by using a 6-byte software code. Please see
Software Chip Erase application note for details.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29LV040A
in the following ways: (a) VCC sense—if VCC is below 1.8V
(typical), the program function is inhibited; (b) VCC power on
delay—once VCC has reached the VCC sense level, the
device will automatically time out 10 ms (typical) before
programming; (c) Program inhibit—holding any one of OE
low, CE high or WE high inhibits program cycles; and
(d) Noise filter—pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The
AT29LV040A has two designated memory blocks that have
a programming lockout feature. This feature prevents pro-
gramming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 16K
bytes; the programming lockout feature can be set inde-
pendently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.
INPUT LEVELS: While operating with a 3.3V 10% power
supply, the address inputs and control inputs (OE, CE and
WE) may be driven from 0 to 5.5V without adversely affect-
ing the operation of the device. The I/O lines can only be
driven from 0 to 3.6V.
These two 16K memory sections are referred to as boot
blocks. Secure code which will bring up a system can be
contained in a boot block. The AT29LV040A blocks are
located in the first 16K bytes of memory and the last 16K
bytes of memory. The boot block programming lockout fea-
ture can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the
programming lockout feature has been activated, the data
in that block can no longer be erased or programmed; data
in other memory locations can still be changed through the
regular programming methods. To activate the lockout fea-
ture, a series of seven program commands to specific
addresses with specific data must be performed. Please
see Boot Block Lockout Feature Enable Algorithm.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e.
using the device code), and have the system software use
the appropriate sector size for program operations. In this
manner, the user can have a common board design for
256K to 4-megabit densities and, with each density’s sector
size in a memory map, have the system software apply the
appropriate sector size.
If the boot block lockout feature has been activated on
either block, the chip erase function will be disabled.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine whether programming of
either boot block section is locked out. See Software Prod-
uct Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002H will show if programming the lower
address boot block is locked out while reading location
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT29LV040A features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
FFFF2H will do so for the upper boot block. If the data is
FE, the corresponding block can be programmed; if the
data is FF, the program lockout feature has been activated
and the corresponding block cannot be programmed. The
software product identification exit mode should be used to
return to standard operation.
TOGGLE BIT: In addition to DATA polling the
AT29LV040A provides another method for determining the
3
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on A9 (including NC Pins)
with Respect to Ground...................................-0.6V to +13.5V
AT29LV040A
4
AT29LV040A
DC and AC Operating Range
AT29LV040A-20
0°C - 70°C
AT29LV040A-25
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
-40°C - 85°C
3.3V 0.3V
-40°C - 85°C
3.3V 0.3V
V
CC Power Supply(1)
Note:
1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an opera-
tional mode is started.
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High Z
VIH
X
X
VIL
VIH
X
X
High Z
A1 - A18 = VIL, A9 = VH(3), A0 = VIL
A1 - A18 = VIL, A9 = VH(3), A0 = VIH
A0 = VI
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1F, Device Code: C4.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
1
Units
µA
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
1
Com.
Ind.
40
50
1
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
ISB2
ICC
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
f = 5 MHz; IOUT = 0 mA; VCC = 3.6V
15
0.6
VIL
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
V
IOL = 1.6 mA; VCC = 3.0V
.45
V
IOH = -100 µA; VCC = 3.0V
V
5
AC Read Characteristics
AT29LV040A-20
AT29LV040A-25
Symbol
Parameter
Min
Max
Min
Max
250
250
120
60
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
200
200
100
50
(1)
tCE
ns
(2)
tOE
0
0
0
0
ns
(3)(4)
tDF
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. These parameters are characterized and not 100% tested.
AT29LV040A
6
AT29LV040A
AC Byte Load Characteristics
Symbol
Parameter
Min
10
Max
Units
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
tAH
tCS
tCH
tWP
tDS
100
0
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
0
200
100
10
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
tWPH
200
AC Byte Load Waveforms(1)(2)
WE Controlled
CE Controlled
Notes: 1. The 3-byte address and data commands shown on the next page must be applied prior to byte loads.
2. A complete sector (256 bytes) should be loaded using these waveforms shown in these byte load waveform diagrams.
7
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
20
tAS
10
100
100
10
tAH
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
200
ns
tBLC
tWPH
150
µs
200
ns
Software Protected Program Waveform
Notes: 1. OE must be high when WE and CE are both low.
2. A8 through A18 must specify the sector address during each high to low transition of WE (or CE) after the software code has
been entered.
3. All words that are not loaded within the sector being programmed will be indeterminate.
Programming Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
LOAD DATA A0
TO
2. Data Protect state will be re-activated at end of program
ADDRESS 5555
WRITES ENABLED
ENTER DATA
cycle.
3. 256 bytes of data MUST BE loaded.
LOAD DATA
TO
SECTOR (256 BYTES)(3) PROTECT STATE(2)
AT29LV040A
8
AT29LV040A
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggling Bit Waveforms(1)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used by the address should not vary.
9
Software Product Identification Entry(1)
5. Manufacturer Code is 1F. The Device Code is C4.
LOAD DATA AA
TO
ADDRESS 5555
Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA 55
TO
LOAD DATA AA
TO
ADDRESS 2AAA
ADDRESS 5555
LOAD DATA 90
TO
LOAD DATA 55
TO
ADDRESS 5555
ADDRESS 2AAA
LOAD DATA 80
TO
PAUSE 20 mS
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA F0
TO
ADDRESS 5555
LOAD DATA 00
TO
ADDRESS 00000H(2)
LOAD DATA FF
TO
ADDRESS FFFFFH(3)
PAUSE 20 mS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 20 mS
PAUSE 20 mS
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
AT29LV040A
10
AT29LV040A
Ordering Information
I
Active
15
CC (mA)
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
200
0.04
0.05
0.04
0.05
AT29LV040A-20TC
AT29LV040A-20JC
32T
32J
Commercial
(0° to 70°C)
15
15
15
AT29LV040A-20TI
AT29LV040A-20JI
32T
32J
Industrial
(-40° to 85°C)
250
AT29LV040A-25TC
AT29LV040A-25JC
32T
32J
Commercial
(0° to 70°C)
AT29LV040A-25TI
AT29LV040A-25JI
32T
32J
Industrial
(-40° to 85°C)
Package Type
32J
32T
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32-Lead, Thin Small Outline Package (TSOP)
11
AT29LV040A
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32T, 32-Lead, Plastic Thin Small Outline Package
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BD
.025(.635) X 30˚ - 45˚
.045(1.14) X 45˚ PIN NO. 1
.012(.305)
.008(.203)
IDENTIFY
INDEX
MARK
.530(13.5)
.490(12.4)
.553(14.0)
.547(13.9)
.595(15.1)
18.5(.728)
18.3(.720)
20.2(.795)
19.8(.780)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.585(14.9)
.030(.762)
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
0.50(.020)
BSC
0.25(.010)
0.15(.006)
AT CONTACT
POINTS
7.50(.295)
REF
8.20(.323)
7.80(.307)
1.20(.047) MAX
.022(.559) X 45˚ MAX (3X)
0.15(.006)
0.05(.002)
.453(11.5)
.447(11.4)
0
0.20(.008)
0.10(.004)
REF
5
.495(12.6)
.485(12.3)
0.70(.028)
0.50(.020)
12
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© Atmel Corporation 2001.
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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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