AT40K20LV-2AGC_技术文档

Features

• Ultra High Performance

– System Speeds to 100 MHz

– Array Multipliers > 50 MHz

– 10ns Flexible SRAM

– Internal 3-State Capability in each Cell

• FreeRAM^™

– Flexible, Single/Dual Port, Sync/Async 10 ns SRAM

– 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells

• 84 - 384 PCI Compliant I/Os

– 3V/5V Capability

– Programmable Output Drive

– Fast, Flexible Array Access Facilitates Pin-Locking

– Pin Compatible with XC4000, XC5200 FPGAs

• 8 Global Clocks

AT40K FPGAs

with FreeRAM™

– Fast, Low Skew Clock Distribution

– Programmable Rising/Falling Edge Transitions

– Distributed Clock Shut-Down Capability for Low Power Management

– Global Reset/Asynchronous Reset Options

– 4 Additional Dedicated PCI Clocks

AT40K05

AT40K10

AT40K20

AT40K40

• Cache Logic^®Dynamic Full/Partial Reconfigurability In-System

– Unlimited Reprogrammability via Serial or Parallel Modes

– Enables Adaptive Designs

– Enables Fast Vector Multiplier Updates

– QuickChange^™Tools for Fast, Easy Design Changes

• Pin-Compatible Package Options

– Plastic Leaded Chip Carriers (PLCC)

– Thin, Plastic Quad Flat Packs (VQFP, TQFP, PQFP)

– Ball Grid Arrays (BGA)

– Pin Grid Arrays (PGAs)

• Industry-Standard Design Tools

– Seamless Integration (Libraries, Interface, Full Back-Annotation) with

Concept, Everest, Exemplar, Mentor, OrCAD, Synario, Synopsys,

Verilog, Veribest, Viewlogic, Synplicity

– Timing Driven Placement & Routing

– Automatic/Interactive Multi-Chip Partitioning

– Fast, Efficient Synthesis

– Over 50 Automatic Component Generators Create 1000’s

of Reusable, Fully Deterministic Logic and RAM Functions

• Intellectual Property Cores

AT40K

– Fir Filters, UARTs, PCI, FFT and other System Level Functions

• Easy Migration to Atmel Gate Arrays for High Volume Production

Device

AT40K05

5K - 10K

16 x 16

256

AT40K10

10K - 20K

24 x 24

576

AT40K20

20K - 30K

32 x 32

1,024

AT40K40

40K - 50K

48 x 48

2,304

Usable Gates

RowsXColumns

Cells

Registers

RAM Bits

I/O (max)

256

576

1,024

2,304

2,048

128

4,608

8,192

18,432

384

192

256

Rev. 0896B–01/99

1

Description

The AT40K is a family of fully PCI-compliant, SRAM-based

FPGAs with distributed 10ns programmable synchro-

nous/asynchronous, dual port/single port SRAM, 8 global

clocks, Cache Logic ability (partially or fully reconfigurable

without loss of data), automatic component generators, and

range in size from 5,000 to 50,000 usable gates. I/O counts

range from 128 to 384 in industry standard packages rang-

ing from 84-pin PLCC to 475-pin BGA, and support 3.3V

and 5V designs.

without loss of data, on-the-fly) for building adaptive logic

and systems. As new logic functions are required, they can

be loaded into the logic cache without losing the data

already there or disrupting the operation of the rest of the

chip; replacing or complementing the active logic. The

AT40K can act as a reconfigurable coprocessor.

Automatic Component Generators

The AT40K is the only FPGA family capable of implement-

ing user-defined, automatically generated, macros in multi-

ple designs; speed and functionality are unaffected by the

macro orientation or density of the target device. This

enables the fastest, most predictable and efficient FPGA

design approach and minimizes design risk by reusing

already proven functions. The Automatic Component Gen-

erators work seamlessly with industry standard schematic

and synthesis tools to create the fastest, most efficient

designs available.

The AT40K is designed to quickly implement high perfor-

mance, large gate count designs through the use of synthe-

sis and schematic-based tools used on a PC, Sun and HP

platform. Atmel’s design tools provide seamless integration

with industry standard tools from Cadence (Concept/Ver-

ilog), Everest, Exemplar, Mentor, OrCAD, Synario, Veri-

best, and Viewlogic.

The AT40K can be used as a Coprocessor for high speed

(DSP/Processor-based) designs by implementing a variety

of compute-intensive, arithmetic functions. These include

adaptive finite impulse response (FIR) filters, fast Fourier

transforms (FFT), convolvers, interpolators and discrete-

cosine transforms (DCT) that are required for video com-

pression and decompression, encryption, convolution and

other multimedia applications.

The patent-pending AT40K Series architecture employs a

symmetrical grid of small yet powerful cells connected to a

flexible busing network. Independently controlled clocks

and resets govern every column of cells. The array is sur-

rounded by programmable I/O.

Devices range in size from 5,000 to 50,000 usable gates in

the initial family, and 256 to 2,304 registers. Pin locations

are consistent throughout the AT40K Series for easy

design migration in the same package footprint. AT40K

Series FPGAs utilize a reliable 0.6 micron single-poly, tri-

ple-metal CMOS process and are 100% factory-tested.

Atmel’s PC- and workstation-based Integrated Develop-

ment System is used to create AT40K Series designs. Mul-

tiple design entry methods are supported.

Fast, Flexible and Efficient SRAM

The AT40K FPGA offers a patented distributed 10ns

SRAM capability where the RAM can be used without los-

ing logic resources. Multiple independent, synchronous or

asynchronous, dual port or single port RAM functions

(FIFO, scratch pad, etc.) can be created using Atmel’s

macro generator tool.

The Atmel architecture was developed to provide the high-

est levels of performance, functional density and design

flexibility in an FPGA. The cells in the Atmel array are

small, efficient and can implement any pair of Boolean

functions of (the same) three inputs or any single Boolean

function of four inputs. The cell’s small size leads to arrays

with large numbers of cells, greatly multiplying the function-

ality in each cell. A simple, high-speed busing network pro-

vides fast, efficient communication over medium and long

distances

Fast, Efficient Array & Vector Multipliers

The AT40K’s patented 8-sided core cell with direct horizon-

tal, vertical and diagonal cell-to-cell connections imple-

ments ultra fast array multipliers without using any busing

resources. The AT40K’s Cache Logic capability enables a

large number of design coefficients and variables to be

implemented in a very small amount of silicon, enabling

vast improvement in system speed at much lower cost than

conventional FPGAs.

Cache Logic Design

The AT40K is the only FPGA family capable of implement-

ing Cache Logic (Dynamic full/partial logic reconfiguration,

AT40K

2

AT40K

The Symmetrical Array

At the heart of the Atmel architecture is a symmetrical array

of identical cells (Figure 1). The array is continuous from

one edge to the other, except for bus repeaters spaced

every four cells (Figure 2). At the intersection of each

repeater row and column is a 32 x 4 RAM block accessible

by adjacent buses. The Ram can be configured as either a

single-ported or dual-ported RAM, with either synchronous

or asynchronous operation.

Figure 1. Symmetrical Array Surrounded by I/O (AT40K20)

= I/O Pad

= AT40K Cell

= Repeater Row

= Repeater Column

3

Figure 2. Floorplan (representative portion)

RV

RH

= Vertical Repeater

= Horizontal Repeater

= Cell

RAM

RV

RAM

RV

RAM

RH

RAM

RH

RAM

RH

RAM

The Busing Network

Figure 3 depicts one of five identical busing planes. Each

plane has 3 bus resources: a local-bus resource (the mid-

dle bus) and 2 express-bus resources. Bus resources are

connected via repeaters. Each repeater has connections to

two adjacent local-bus segments and two express-bus seg-

ments. Each local-bus segment spans four cells and con-

nects to consecutive repeaters. Each express-bus segment

spans eight cells and “leapfrogs” or bypasses a repeater.

Repeaters regenerate signals and can connect any bus to

any other bus (all pathways are legal) on the same plane.

Although not shown, a local bus can bypass a repeater via

a programmable pass gate allowing long on-chip three

state buses to be created. Local/Local turns are imple-

mented through pass gates in the cell-bus interface (see

following page). Express/Express turns are implemented

through separate pass gates distributed throughout the

array.

AT40K

4

AT40K

Figure 3. Busing Plane (one of five)

= AT40K Cell

= Local/Local or Express/Express Turn Point

= Row Repeater

= Column Repeater

5

Cell Connections

Figure 4(a) depicts direct connections between a cell and

its eight nearest neighbors. Figure 4(b) shows the connec-

tions between a cell five horizontal local buses (one per

busing plane) and five vertical local buses (one per busing

plane).

Figure 4. Cell Connections

CEL

WXYZL

CEL

W

X

Y

Z

CEL

L

CEL

(a) Cell to Cell Connections

(b) Cell to Bus Connections

AT40K

6

AT40K

The Cell

Figure 5 depicts the AT40K cell. Configuration bits for sep-

arate muxes and pass gates are independent. All permuta-

tions of programmable muxes and pass gates are legal. Vn

is connected to the vertical local bus in plane n. Hn is con-

nected to the horizontal local bus in plane n. A local/local

turn in plane n is achieved by turning on the two pass gates

connected to Vn and Hn. Up to five simultaneous local/local

turns are possible.

Figure 5. The Cell

"1"

N

E

S

Y

W

"1" NW NE SE SW

"1"

X

W

Z

X

W

Y

FB

8X1 LUT

OUT

8X1 LUT

OUT

"1"

"0" "1"

V1

H1

V2

H2

V3

H3

V4

H4

V5

H5

1

0

Z

L

"1" OE OE

H

V

D

Q

CLOCK

RESET/SET

Y

X

NW NE SE SW

N

E

S

W

X

Y

= Diagonal Direct Connect or Bus

= Orthogonal Direct Connect or Bus

W = Bus Connection

= Bus Connection

FB = Internal Feedback

Z

The core cell can be configured in several “modes”. The

core cell flexibility makes the AT40K architecture well

suited to most digital design application areas

(see Figure 6).

7

Figure 6. Some Single Cell Modes

A

B

C

D

Q (Registered)

and/or

Q

Synthesis Mode

D Q

SUM

or

A

B

C

D Q

SUM (Registered)

and/or

Arithmetic Mode

CARRY

PRODUCT (Registered)

or

PRODUCT

D Q

A

B

C

D

DSP/Multiplier Mode

and/or

CARRY

D Q

Q

CARRY IN

Counter Mode

and/or

CARRY

A

B

C

Q

Tri-State / Mux Mode

EN

AT40K

8

AT40K

RAM

32 x 4 Dual-Ported RAM blocks are dispersed throughout

the array as shown in Figure 7. A four-bit Input Data Bus

connects to four horizontal local buses distributed over four

sector rows (plane 1). A four-bit Output Data Bus connects

to four horizontal local buses distributed over four sector

rows (plane 2). A five-bit Input-Address Bus connects to

five vertical express buses in same column. A five-bit Out-

put-Address Bus connects to five vertical express buses in

same column. WAddr (Write Address) and RAddr (Read

Address) alternate positions in horizontally aligned RAM

blocks. For the left-most RAM blocks, RAddr is on the left

and WAddr is on the right. For the right-most RAM blocks,

WAddr is on the left and RAddr is tied off. For single-ported

RAM, WAddr is the READ/WRITE address port and Din is

the (bi-directional) data port. Right-most RAM blocks can

be used only for single-ported memories. /WE & /OE con-

nect to the vertical express buses in the same column.

WAddr, RAddr, /WE and /OE connect to express buses

that are full length at array edge.

Figure 7. RAM Connections (One Ram Block)

CL

CL Di

WAdd

Dou

RAdd

32X4

W

O

9

Reading and writing the 32 x 4 Dual-Port RAM are inde-

pendent of each other. Reading the 32 x 4 Dual-Port RAM

is completely asynchronous. Latches are transparent;

when Load is logic 1, data flows through; when Load is

logic 0, data is latched. Each bit in the 32 x 4 Dual-Port

RAM is also a transparent latch. The front-end latch and

the memory latch together form an edge-triggered flip flop.

When a Bit = 7 Nibble is (Write) addressed and LOAD is

Logic 1 and WE is logic 0, DATA flows through the bit.

When a nibble is not (Write) addressed or LOAD is logic 0

or WE is logic 1, DATA is latched in the nibble. The two

CLOCK muxes are controlled together; they both select

CLOCK or they both select “1”. CLOCK is obtained from

the clock for the sector-column immediately to the left and

immediately above the RAM block. Writing any value to the

RAM Clear Byte during configuration clears the RAM (see

Bit Map Spec).

Figure 8. RAM Logic

CLOCK

"1

Load

5

Read

READ ADDR

Load

Latch

5

WRITE ADDR

WE

32 x 4

Dual-Port

RAM

Write

"1

OE

Load

Latch

Write Enable

Data

Load

Latch

4

DATA IN

Data

DATA OUT

Clear

RAM-Clear

AT40K

10

Clocking and Set/Reset

Each of 8 dedicated Global Clock buses is connected to a

dual-use Global Clock pad (GCK1 - GCK8). An internal sig-

nal can be placed on a Global Clock bus by routing that sig-

nal to a Global Clock pad. Each column of the array has a

Column Clock selected from one of the 8 Global Clock

buses. The extreme-left Column Clock mux has two addi-

tional inputs from dual-use pins FCK1 & FCK2 to provide

fast clocking to left-side I/O. The extreme-right Column

Clock mux has two additional inputs from dual-use pins

FCK3 & FCK4 to provide fast clocking to right-side I/O.

Each sector column of 4 cells can be clocked from a (Plane

4) express bus or from the Column Clock. Clocking to the 4

cells can be disabled. The Plane 4 express bus used for

clocking is half length at the array edge. The clock provided

to each sector column of 4 cells can be either inverted or

not inverted. The register in each cell is triggered on a ris-

ing clock edge. On power up, constant “0” is provided to

each registers clock pins.

A dedicated Global Set/Reset bus can be driven by any

USER I/O pad, except those used for clocking, Global or

Fast. An internal signal can be placed on the Global

Set/Reset bus by routing that signal to the pad pro-

grammed as the Global Set/Reset input. Global Set/Reset

is distributed to each column of the array. Each sector col-

umn of 4 cells can be Set/Reset by a (Plane 5) express bus

or by the Global Set/Reset. The Plane 5 express bus used

for Set/Reset is half length at array edge. The Set/Reset

provided to each sector column of 4 cells can be either

inverted or not inverted. The function of the Set/Reset input

of a register (either Set or Reset) is determined by a config-

uration bit in each cell. The Set/Reset input of a register is

Active Low (logic 0). Setting or resetting of a register is

asynchronous. On power up, a logic 1 (a high) is provided

by each register, i.e., all registers are set at power up.

AT40K

12

AT40K

Figure 10. Clocking (for one column of cells)

FCK (2 Per Edge Column of Cells)

GCK1 - GCK8

}

"1"

Global Clock Line (Buried)

Express Bus

(Plane 4; Half length at edge)

"1"

Repeater

13

Figure 11. Set/Reset (for one column of cells)

Each Cell has a programmable Set or Reset

Repeater

"1"

Global Set/Reset line (Buried)

Express Bus

(Plane 5; Half length at edge)

"1"

Any User I/O can drive Global Set/Reset line

AT40K

14

AT40K

Figure 12. West I/O (Mirrored for East I /O)

CEL

"0

"1

"0

"1

PULL-

PA

PULL-DOWN

(a) Primary

"0

"1

CEL

"0

"1

PULL-

PA

PULL-DOWN

CEL

(a) Secondary

15

Figure 13. South I/O (Mirrored for North I/O)

CEL

DELA

TRI-

SCHMIT

TTL/CMO

DRIV

VC

GN

PA

(a) Primary

CEL

DELA

TRI-

SCHMIT

DRIV

TTL/CMO

VC

GN

PA

(a) Secondary

AT40K

16

AT40K

Figure 14. North/West Corner, (similar for NE/SE/SW corners)

PA

VC

GN

VC

GN

TTL/CMO

SCHMIT

DELA

TTL/CMO

SCHMIT

DELA

DRIV

TRI-

"0

"1

"0

"1

PULL-

PA

CEL

PULL-DOWN

CEL

17

Some of the bus resource on ATK40K is used as a dual-

function resource. Table 1 shows which buses are used in

a dual-function mode and which bus plane is used. The

ATK40K software tools are designed to accommodate

dual-function buses in an efficient manner.

Table 1. Dual-Function Buses

Function

Type

Plane(s)

Direction

Comments

Cell Output Enable

Local

5

Horizontal and

Vertical

RAM Output Enable

RAM Write Enable

RAM Address

Express

2

1

Vertical

Bus full length at array edge

Bus in first column to left of RAM block

Bus full length at array edge

Bus in first column to left of RAM block

1-5

Buses full length at array edge

Buses in second column to left of RAM block

RAM Data In

RAM Data Out

Clocking

Local

1

2

4

5

Horizontal

Vertical

Express

Bus half length at array edge

Set/Reset

Vertical

AT40K

18

AT40K

Absolute Maximum Ratings - 5V Commercial/Industrial*

Symbol

V_CC

V_I

Parameter

Conditions

Min

-0.5

Max

7.0

Units

Supply Voltage

With respect to GND

With respect ot GND

V

DC Input Voltage⁽¹⁾

-0.5

7.0

V_O

DC Output Voltaage

Storage Temperature

Junction Temperature

Lead Temperature (Soldering, 10 sec.)

-0.5

7.0

T_STG

T_J

-65°C

+150°C

+250°C

2000

T_L

ESD

R_ZAP= 1.5K, C_ZAP= 100 pF

V

Note:

1. Minimum voltage of -0.5V DC which may undershoot to -2.0V for pulses of less than 20 ns.

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the oper-

ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

DC and AC Operating Range - 5V Operation

AT40K05-2

AT40K10-2

AT40K20-2

AT40K40-2

AT40K05-2

AT40K10-2

AT40K20-2

AT40K40-2

AT40K10-2

AT40K20-2

AT40K40-2

Commercial

0°C - 70°C

5V ± 5%

Industrial

-40°C - 85°C

5V ± 10%

Military

-55°C - 125°C

5V ± 10%

Operating Temperature (Case)

_CCPower Supply

V

High (V_IHT

Low (V_ILT

High (V_IHC

Low (V_ILC

)

2.0V - V_CC

Input Voltage Level (TTL)

)

0V - 0.8V

)

70% - 100% V_CC

0 - 30% V_CC

70% - 100% V_CC

0 - 30% V_CC

70% - 100% V_CC

0 - 30% V_CC

Input Voltage Level (CMOS)

)

19

DC Characteristics - 5V Operation - Commercial/Industrial/Military

Symbol

Parameter

Conditions

CMOS

TTL

Min

70% V_CC

2.0

Typ

Max

Units

V

V_IH

High-Level Input Voltage

CMOS

TTL

-0.3

30% V_CC

0.8

V_IL

Low-Level Input Voltage

High-Level Output Voltage

-0.3

I_OH= 6mA

V_CC= V_CCmin

4.0

V

I_OH= 14mA

V_CC= V_CCmin

V_OH

I_OH= 20mA

Comm. = 4.75V

Ind./Military = 4.5V

4.0

V

I

_OL= -6mA

Comm. = 4.75V

Ind./Military = 4.5V

0.4

I

_OL= -14mA

V_OL

Low-Level Output Voltage

Comm. = 4.75V

Ind./Military = 4.5V

I

_OL= -20mA

Comm. = 4.75V

Ind./Military = 4.5V

V

_IN= V_CCmax

With pulldown, V_IN= V_CC

_IN= V_SS

10

µA

mA

pF

I_IH

High-Level Input Current

125

-10

250

-250

250

500

V

I_IL

Low-Level Input Current

With pullup, V_IN= V_SS

Without pulldown, V_IN= V_CC

With pulldown, V_IN= V_CC

Without pullup, V_IN= V_SSmax

With pullup, V_IN= V_SSmax

Standby, unprogrammed

All pins

-500

-125

10

I_OZH

High-Level Tristate Output leakage current

Low-Level Tristate Output leakage current

125

-10

500

I_OZL

-500

-250

0.6

-125

1

I_CC

Standby Current Consumption

Input Capacitance

C_IN

10

AT40K

20

AT40K

AC Timing Characteristics - 5V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 4.75V, temperature = 70°C

Minimum times based on best case: V_CC= 5.25V, temperature = 0°C

Maximum delays are the average of t_PDLHand t_PDHL

.

Cell Function

Core

Parameter

Path

-2

Units

Notes

2 input gate

3 input gate

4 input gate

fast carry

DFF

t

_PD(max)

x/y -> x/y

x/y/z -> x/y

x/y/w -> x/y

x/y/w/z -> x/y

y -> y

1.8

2.1

2.2

1.4

1.7

1.8

1.5

2.2

2.3

1.7

1.8

ns

1 unit load

x -> y

y -> x

t_PD(max)

x -> x

t

_PD(max)

w -> y

w -> x

t_PD(max)

z -> y

t

_PD(max)

z -> x

q -> x/y

x/y -> clk

R -> x/y

S -> x/y

q -> w

DFF

t_setup(min)

DFF

t

_hold(min)

_PD(max)

DFF

2.2

1.8

1.5

1.4

1.8

1 unit load

DFF

t_PD(max)

DFF

t

_PD(max)

incremental --> L

Local output enable

x/y -> L

oe -> L

1 unit load

t_PZX(max)

_PXZ(max)

t

21

AC Timing Characteristics - 5V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 4.75V, temperature = 70°C

Minimum times based on best case: V_CC= 5.25V, temperature = 0°C

Max delays are the average of t_PDLHand t_PDHL

.

All input IO characteristics measured from a V_IHof 50% of V_DDat the pad (CMOS threshold) to the internal V_IHof 50%

of V_C.

All output IO characteristics are measured as the average of t_PDLHand t_PDHLto the pad V_IHof 50% of V_CC

.

Cell Function

Repeaters

Repeater

Parameter

Path

-2

Units

Notes

t

_PD(max)

L->E

E->E

L->L

1.3

0.8

ns

1 unit load

t_PD(max)

t

_PD(max)

E->L

E->IO

L->IO

t_PD(max)

All input IO characteristics measured from a V_IHof 50% at the pad (CMOS threshold) to the internal V_IHof 50% of V_CC

All output IO characteristics are measured as the average of t_PDLHand t_PDHLto the pad V_IHof 50% of V_CC

.

Cell Function

IO

Parameter

Path

-2

Units

Notes

Input

t_PD(max)

pad -> x/y

x/y/E/L -> pad

oe -> pad

1.2

3.6

7.3

10.8

5.9

4.8

3.9

6.2

1.3

4.8

1.9

3.7

1.6

ns

no extra delay

1 extra delay

2 extra delays

3 extra delays

50pf load

Input

t

_PD(max)

Input

t_PD(max)

Input

t

_PD(max)

Output, slow

Output, medium

Output, fast

Output, slow

Output, low

Output, medium

Output, fast

t

t_PD(max)

50pf load

t

_PD(max)

50pf load

t_PZX(max)

50pf load

t_PXZ(max)

oe -> pad

50pf load

t

_PZX(max)

_PXZ(max)

oe -> pad

50pf load

oe -> pad

50pf load

t_PZX(max)

_PXZ(max)

oe -> pad

50pf load

t

oe -> pad

50pf load

AT40K

22

AT40K

AC Timing Characteristics - 5V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 4.75V, temperature = 70°C

Minimum times based on best case: V_CC= 5.25V, temperature = 0°C

Max delays are the average of t_PDLHand t_PDHL

.

Clocks and Reset Input buffers are measured from a V_IHof 1.5V at the input pad to the internal V_IHof 50% of V_CC

Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.

.

Cell Function

Global Clocks and Set/Reset

_PD(max)

Parameter

Path

Device

-2

Units

Notes

GCLK Input buffer

FCLK Input buffer

Clock column driver

Clock sector driver

GSRN Input buffer

Global clock to output

t

pad -> clock

AT40K05

1.1

1.2

1.4

ns

rising edge clock

AT40K10

AT40K20

AT40K40

t_PD(max)

pad -> clock

AT40K05

AT40K10

AT40K20

AT40K40

0.7

0.8

ns

t_PD(max)

clock -> colclk

AT40K05

AT40K10

AT40K20

AT40K40

0.8

0.9

1.0

1.1

ns

t_PD(max)

colclk -> secclk

AT40K05

AT40K10

AT40K20

AT40K40

0.5

ns

pad -> GSRN

colclk -> secclk

AT40K05

AT40K10

AT40K20

AT40K40

3.0

3.7

4.3

5.6

ns

t_PD(max)

clock pad -> out

AT40K05

AT40K10

AT40K20

AT40K40

8.3

8.4

8.6

8.8

ns

rising edge clock

fully loaded clock tree

rising edge DFF

20mA output buffer

50 pf pin load

Output, fast

t_PD(max)

clock pad -> out

AT40K05

AT40K10

AT40K20

AT40K40

7.9

8.0

8.1

8.3

ns

rising edge clock

fully loaded clock tree

rising edge DFF

20mA output buffer

50 pf pin load

23

AC Timing Characteristics - 5V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 4.75V, temperature = 70°C

Minimum times based on best case: V_CC= 5.25V, temperature = 0°C

Max delays are the average of t_PDLHand t_PDHL

.

Cell Function

Async RAM

Write

Parameter

Path

-2

Units

Notes

t

_WECYC(min)

_WEL(min)

_WEH(min)

_setup(min)

_hold(min)

cycle time

8.0

3.0

2.0

0.0

2.0

0.0

4.6

3.1

1.6

2.0

ns

Write

we

pulse width low

pulse width high

Write

we

Write

wr addr setup-> we

wr addr hold -> we

din setup -> we

din hold -> we

oe hold -> we

din -> dout

Write

_setup(min)

_hold(min)

Write

t_hold(min)

Write/Read

Read

t

_PD(max)

rd addr = wr addr

rd addr -> dout

oe -> dout

Read

t_PZX(max)

Read

t

_PXZ(max)

oe -> dout

Sync RAM

Write

t

_CYC(min)

_CLKL(min)

_CLKH(min)

cycle time

8.0

3.0

2.0

0.0

2.0

0.0

2.0

0.0

4.6

3.5

3.1

1.6

2.0

ns

Write

clk

pulse width low

pulse width high

Write

clk

Write

t_setup(min)

we setup-> clk

we hold -> clk

wr addr setup-> clk

wr addr hold -> clk

wr data setup-> clk

wr data hold -> clk

din -> dout

Write

t

_hold(min)

Write

_setup(min)

Write

t_hold(min)

Write

t

_setup(min)

_hold(min)

Write

Write/Read

Read

t_PD(max)

rd addr = wr addr

t

_PD(max)

clk -> dout

rd addr -> dout

oe -> dout

Read

t_PZX(max)

_PXZ(max)

Read

t

oe -> dout

AT40K

24

AT40K

Absolute Maximum Ratings - 3.3V Commercial/Industrial*

Symbol

V_CC

V_I

Parameter

Conditions

Min

-0.5

Max

7.0

Units

Supply Voltage

With respect to GND

With respect ot GND

V

DC Input Voltage⁽¹⁾

-0.5

7.0

V_O

DC Output Voltaage

Storage Temperature

Junction Temperature

Lead Temperature (Soldering, 10 sec.)

-0.5

7.0

T_STG

T_J

-65°C

+150°C

+250°C

2000

T_L

ESD

R_ZAP= 1.5K, C_ZAP= 100 pF

V

Note:

1. Minimum voltage of -0.5V DC which may undershoot to -2.0V for pulses of less than 20 ns.

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the oper-

ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

DC and AC Operating Range - 3.3V Operation

AT40K05LV-4/3/2

AT40K10LV-4/3/2

AT40K20LV-4/3/2

AT40K40LV-4/3/2

Commercial

AT40K05LV-4/3/2

AT40K10LV-4/3/2

AT40K20LV-4/3/2

AT40K40LV-4/3/2

Industrial

Operating Temperature (Case)

V_CCPower Supply

0°C - 70°C

3.3V ± 0.3V

-40°C - 85°C

3.3V ± 0.3V

High (V_IHC

Low (V_ILC

)

70% - 100% V_CC

0 - 30% V_CC

70% - 100% V_CC

0 - 30% V_CC

Input Voltage Level (CMOS)

)

25

DC Characteristics - 3.3V Operation - Commercial/Industrial

Symbol

Parameter

Conditions

CMOS

TTL

Min

70% V_CC

2.0

Typ

Max

Units

V

V_IH

High-Level Input Voltage

CMOS

TTL

-0.3

30% V_CC

0.8

V_IL

Low-Level Input Voltage

-0.3

I_OH= 4 mA

V_CC= V_CCmin

2.1

V

I_OH= 12 mA

V_CC= 3.0V

V_OH

High-Level Output Voltage

I_OH= 16 mA

V_CC= 3.0V

I_OL= -4 mA

V_CC= 3.0V

0.4

I_OL= -12 mA

V_CC= 3.0V

V_OL

Low-Level Output Voltage

I_OL= -16 mA

V_CC= 3.0V

V

_IN= V_CCmax

10

µA

I_IH

High-Level Input Current

With pulldown, V_IN= V_CC

_IN= V_SS

75

-10

150

-150

150

300

V

I_IL

Low-Level Input Current

With pullup, V_IN= V_SS

Without pulldown, V_IN= V_CCmax

With pulldown, V_IN= V_CCmax

Without pullup, V_IN= V_SS

With pullup, V_IN= V_SS

Standby, unprogrammed

All pins

-300

-75

10

I_OZH

High-Level Tristate Output leakage current

Low-Level Tristate Output leakage current

75

-10

300

µA

mA

pF

I_OZL

-300

-150

0.6

-75

1

I_CC

Standby Current Consumption

Input Capacitance

C_IN

10

Note:

1. Parameter based on characterization and simulation; it is not tested in production.

AT40K

26

AT40K

AC Timing Characteristics - 3.3V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 3.00V, temperature = 70°C

Minimum times based on best case: V_CC= 3.60V, temperature = 0°C

Max delays are the average of t_PDLHand t_PDHL

.

Cell Function

Core

Parameter

Path

-3

Units

Notes

2 input gate

3 input gate

4 input gate

fast carry

DFF

t

_PD(max)

x/y -> x/y

x/y/z -> x/y

x/y/w -> x/y

x/y/w/z -> x/y

y -> y

2.9

2.8

3.4

2.3

2.9

3.0

2.3

3.4

2.4

2.8

ns

1 unit load

x -> y

y -> x

t_PD(max)

x -> x

t

_PD(max)

w -> y

w -> x

t_PD(max)

z -> y

t

_PD(max)

z -> x

q -> x/y

x/y -> clk

R -> x/y

S -> x/y

q -> w

DFF

t_setup(min)

DFF

t

_hold(min)

_PD(max)

DFF

3.2

3.0

2.7

2.4

2.8

2.4

1 unit load

DFF

t_PD(max)

DFF

t

_PD(max)

incremental --> L

Local output enable

x/y -> L

oe -> L

1 unit load

t_PZX(max)

_PXZ(max)

t

27

AC Timing Characteristics - 3.3V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 3.0V, temperature = 70°C

Minimum times based on best case: V_CC= 3.6V, temperature = 0°C

Max delays are the average of t_PDLHand t_PDHL

All input IO characteristics measured from a V_IHof 50% of V_DDat the pad (CMOS threshold) to the internal V_IHof 50% of

V_DD. All output IO characteristics are measured as the average of t_PDLHand t_PDHLto the pad V_IHof 50% of V_DD

.

Cell Function

Repeaters

Repeater

Parameter

Path

-3

Units

Notes

t

_PD(max)

L -> E

E -> E

L -> L

E -> L

E -> IO

L -> IO

2.2

1.4

ns

1 unit load

t_PD(max)

All input IO characteristics measured from a V_IHof 50% of V_DDat the pad (CMOS threshold) to the internal V_IHof 50% of

V_DD. All output IO characteristics are measured as the average of t_PDLHand t_PDHLto the pad V_IHof 50% of V_DD

.

Cell Function

IO

Parameter

Path

-3

Units

Notes

Input

t

_PD(max)

pad -> x/y

x/y/E/L -> pad

oe -> pad

1.9

5.8

11.5

17.4

9.1

7.6

6.2

9.5

2.1

7.4

2.7

5.9

2.4

ns

no extra delay

1 extra delay

2 extra delays

3 extra delays

50pf load

Input

t

Input

t_PD(max)

Input

t

_PD(max)

Output, slow

Output, medium

Output, fast

Output, slow

Output, medium

Output, fast

t

t_PD(max)

50pf load

t_PD(max)

50pf load

t_PZX(max)

50pf load

t_PXZ(max)

oe -> pad

50pf load

t

_PZX(max)

_PXZ(max)

oe -> pad

50pf load

t

oe -> pad

50pf load

t_PZX(max)

_PXZ(max)

oe -> pad

50pf load

t

oe -> pad

50pf load

AT40K

28

AT40K

AC Timing Characteristics - 3.3V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 3.0V, temperature = 70°C

Minimum times based on best case: V_CC= 3.6V, temperature = 0°C

Max delays are the average of t_PDLHand t_PDHL

.

Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC.

Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.

Cell Function

Parameter

Path

Device

-3

Units

Notes

Global Clocks and Set/Reset

GCK Input buffer

t

_PD(max)

pad -> clock

AT40K05

AT40K10

AT40K20

AT40K40

1.3

1.5

1.6

1.9

ns

rising edge clock

FCK Input buffer

t_PD(max)

pad -> clock

AT40K05

AT40K10

AT40K20

AT40K40

0.7

0.8

0.9

ns

rising edge clock

Clock column driver

Clock sector driver

GSRN Input buffer

Global clock to output

t_PD(max)

clock -> colclk

AT40K05

AT40K10

AT40K20

AT40K40

1.5

1.8

2.0

2.5

ns

t_PD(max)

colclk -> secclk

AT40K05

AT40K10

AT40K20

AT40K40

1.0

ns

pad -> GSRN

colclk -> secclk

AT40K05

AT40K10

AT40K20

AT40K40

4.5

5.4

6.3

8.2

ns

t

_PD(max)

clock pad -> out

AT40K05

AT40K10

AT40K20

AT40K40

13.0

13.4

13.8

14.5

ns

rising edge clock

fully loaded clock tree

rising edge DFF

20mA output buffer

50 pf pin load

Fast clock to output

t_PD(max)

clock pad -> out

AT40K05

AT40K10

AT40K20

AT40K40

12.4

12.7

13.0

13.5

ns

rising edge clock

fully loaded clock tree

rising edge DFF

20mA output buffer

50 pf pin load

29

AC Timing Characteristics - 3.3V Operation

Delays are based on fixed loads and are described in the notes.

Maximum times based on worst case: V_CC= 3.0V, temperature = 70°C

Minimum times based on best case: V_CC= 3.6V, temperature = 0°C

Cell Function

Async RAM

Write

Parameter

Path

-4

-3

Units

Notes

t

_WECYC(min)

_WEL(min)

cycle time

14.0

6.0

5.3

0.0

6.0

0.0

12.1

9.7

4.2

3.5

12.0

5.0

5.3

0.0

5.0

0.0

8.7

6.3

2.9

3.5

ns

Write

we

pulse width low

pulse width high

Write

_WEH(min)

we

Write

t_setup(min)

wr addr setup-> we

wr addr hold -> we

din setup -> we

din hold -> we

oe hold -> we

din -> dout

Write

t

_hold(min)

Write

_setup(min)

Write

t_hold(min)

Write

t

_hold(min)

_PD(max)

Write/Read

Read

rd addr = wr addr

t_PD(max)

rd addr -> dout

oe -> dout

Read

t

_PZX(max)

_PXZ(max)

Read

oe -> dout

Sync RAM

Write

t

_CYC(min)

_CLKL(min)

_CLKH(min)

cycle time

12.0

6.0

3.2

0.0

6.0

0.0

3.0

0.0

12.1

9.9

9.7

4.01

3.5

12.0

5.0

3.2

0.0

5.0

0.0

3.9

0.0

8.7

5.8

6.3

2.9

3.5

ns

Write

clk

pulse width low

pulse width high

Write

clk

Write

t_setup(min)

we setup-> clk

we hold -> clk

wr addr setup-> clk

wr addr hold -> clk

wr data setup-> clk

wr data hold -> clk

din -> dout

Write

t

_hold(min)

Write

_setup(min)

Write

t_hold(min)

Write

t

_setup(min)

_hold(min)

Write

Write/Read

Read

t_PD(max)

rd addr = wr addr

t

_PD(max)

clk -> dout

rd addr -> dout

oe -> dout

Read

t_PZX(max)

_PXZ(max)

Read

t

oe -> dout

Notes: 1. CMOS buffer delays are measured from a V_IHof 1/2 V_CCat the pad to the internal V_IHat A. The input buffer load is constant.

2. Buffer delay is to a pad voltage of 1.5V with one output switching.

3. Parameter based on characterization and simulation; not tested in production.

4. Exact power calculation is available in Atmel FPGA Designer Software.

AT40K

30

AT40K

Part/Package Availability

AT40K05

AT40K10

AT40K20

AT40K40

PC 84

X

RQ100

VQ 100

TQ 144

PQ 160

PQ 208

PQ 240

PQ 304

BG 225

BG 352

BG 432

PG 475

X

USER I/O Counts - (Including Dual-Function Pins)

AT40K05

AT40K10

AT40K20

AT40K40

PC 84

62

RQ 100

VQ 100

TQ 144

PQ 160

PQ 208

PQ 240

PQ 304

BG 225

BG 352

BG 432

PG 475

78

114

128

114

130

161

192

114

130

161

193

256

192

256

114

161

193

256

192

289

352

384

Devices in same packages are pin-for-pin replaceable.

31

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

Left Side (Top to Bottom)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

GND

12

13

4

5

1

2

1

2

1

2

4

GND⁽¹⁾

D4

1

2

304

303

GND⁽¹⁾

D23

GND⁽¹⁾

D29

I/O1,

GCK1

(A16)

I/O1,

GCK1

(A16)

I/O1,

GCK1

(A16)

I/O1,

GCK1

(A16)

I/O2

(A17)

I/O2

(A17)

I/O2

(A17)

I/O2

(A17)

14

6

3

5

B1

3

302

C25

C30

I/O3

I/O4

I/O3

I/O4

I/O3

I/O4

I/O3

I/O4

4

5

4

5

6

7

C2

E5

4

5

301

300

D24

E23

E28

E29

I/O5

(A18)

I/O5

(A18)

I/O5

(A18)

I/O5

(A18)

15

16

7

8

4

5

6

7

6

7

8

9

D3

C1

6

7

299

298

C26

E24

D30

D31

I/O6

(A19)

I/O6

(A19)

I/O6

(A19)

I/O6

(A19)

GND

I/O7

GND⁽¹⁾

F28

I/O8

F29

I/O9

D25

F23

E30

I/O10

I/O11

I/O12

VCC

GND

E31

I/O7

I/O8

VCC

GND

297

296

F24

G28

E25

G29

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

I/O13

I/O14

I/O15

I/O16

I/O17

I/O18

F30

F31

H28

H29

G30

H30

I/O7

I/O8

I/O7

I/O8

I/O9

I/O10

I/O11

I/O12

8

9

10

11

12

13

D2

G6

E4

D1

8

9

295

294

293

292

D26

G24

F25

F26

I/O9

10

11

I/O10

GND

GND⁽¹⁾

I/O19

I/O20

I/O21

I/O22

I/O23

I/O24

GND

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

GND

E3

E2

12

13

291

290

289

288

287

H23

H24

J28

J29

G25

H31

G26

J30

GND

8

9

10

11

12

13

14

15

16

17

GND*

F5

14

15

16

17

GND⁽¹⁾

I/O9,

FCK1

I/O13,

FCK1

I/O17,

FCK1

I/O25,

FCK1

286

285

284

J23

J24

H25

K28

K29

K30

I/O10

I/O14

I/O18

I/O26

10

11

E1

I/O11

(A20)

I/O15

(A20)

I/O19

(A20)

I/O27

(A20)

17

18

9

6

7

F4

I/O12

(A21)

I/O16

(A21)

I/O20

(A21)

I/O28

(A21)

10

12

14

18

F3

18

19

283

282

K23

K31

VCC

VCC*

VCC⁽¹⁾

I/O17

I/O21

I/O29

F2

20

280

K24

L29

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

AT40K

32

AT40K

AT40K05

128 I/O

AT40K10

192 I/O

I/O18

AT40K20

256 I/O

I/O22

AT40K40

384 I/O

I/O30

Left Side (Top to Bottom)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

L30

F1

21

279

J25

GND

GND*

M30

I/O31

I/O32

M28

128 I/O

192 I/O

256 I/O

384 I/O

I/O33

I/O34

I/O35

I/O36

GND

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

J26

BG432

M29

L23

M31

I/O23

I/O24

GND

278

277

L24

N31

K25

N28

22

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

N29

VCC

I/O37

I/O38

I/O39

I/O40

I/O41

I/O42

GND

N30

I/O25

I/O26

I/O27

I/O28

276

275

274

273

L25

L26

P30

P28

I/O19

I/O20

19

20

G4

G3

23

24

M23

M24

P29

R31

GND⁽¹⁾

R30

I/O13

I/O14

I/O21

I/O22

I/O29

I/O30

I/O43

I/O44

I/O45

I/O46

13

14

15

16

21

22

G2

G1

25

26

272

271

M25

M26

11

8

R28

I/O15

(A22)

I/O23

(A22)

I/O31

(A22)

I/O47

(A22)

19

20

12

13

9

15

16

17

18

23

24

G5

H3

27

28

270

269

N24

N25

R29

T31

I/O16

(A23)

I/O24

(A23)

I/O32

(A23)

I/O48

(A23)

10

GND

VCC

I/O17

I/O18

GND

VCC

GND

VCC

GND

VCC

21

22

23

24

14

15

16

17

11

12

13

14

17

18

19

20

19

20

21

22

25

26

27

28

GND⁽¹⁾

VCC⁽¹⁾

H4

29

30

31

32

268

267

266

265

GND⁽¹⁾

VCC⁽¹⁾

N26

GND⁽¹⁾

VCC⁽¹⁾

T30

I/O25

I/O26

I/O33

I/O34

I/O49

I/O50

I/O51

I/O52

I/O53

I/O54

GND

I/O55

I/O56

I/O57

I/O58

I/O59

I/O60

VCC

H5

P25

T29

I/O19

I/O20

I/O27

I/O28

I/O35

I/O36

18

15

21

22

23

24

29

30

J2

J1

33

34

264

263

P23

P24

U31

U30

GND⁽¹⁾

U28

I/O29

I/O30

I/O37

I/O38

I/O39

I/O40

31

32

J3

J4

35

36

262

261

260

259

R26

R25

R24

R23

U29

V30

V29

V28

W31

VCC⁽¹⁾

GND⁽¹⁾

W30

W29

VCC⁽¹⁾

GND⁽¹⁾

T26

GND

I/O41

I/O42

GND

I/O61

I/O62

37

258

257

T25

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

33

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

I/O63

Left Side (Top to Bottom)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

W28

Y31

I/O64

I/O65

T24

U25

Y30

I/O66

Y29

GND

GND⁽¹⁾

Y28

I/O31

I/O32

I/O43

I/O44

I/O67

J5

38

39

256

255

T23

V26

I/O68

K1

AA30

VCC

192 I/O

I/O33

I/O34

I/O35

VCC

256 I/O

I/O45

I/O46

I/O47

VCC

384 I/O

I/O69

I/O70

I/O71

VCC⁽¹⁾

BG225

K2

40

PQ240

41

253

PQ304

252

VCC⁽¹⁾

BG352

U24

VCC⁽¹⁾

BG432

AA29

128 I/O

I/O21

I/O22

I/O23

PC84

25

RQ100

19

VQ100

16

TQ144

23

PQ160

25

PQ208

33

26

20

17

24

26

34

K3

42

251

V25

AB31

25

27

35

J6

43

250

V24

AB30

I/O24,

FCK2

I/O36,

FCK2

I/O48,

FCK2

I/O72,

FCK2

26

27

28

29

36

37

L1

44

45

249

U23

AB29

GND

I/O49

I/O50

I/O51

I/O52

GND

I/O73

I/O74

I/O75

I/O76

I/O77

I/O78

GND*

248

247

246

245

244

GND⁽¹⁾

Y26

GND⁽¹⁾

AB28

AC30

AC29

AC28

W25

W24

V23

I/O37

I/O38

L2

46

47

K4

GND

GND⁽¹⁾

VCC⁽¹⁾

I/O79

I/O80

I/O81

I/O82

I/O83

I/O84

GND

VCC

AD31

AD30

AD29

AD28

AE30

AE29

GND⁽¹⁾

VCC⁽¹⁾

AF31

AE28

AF30

AF29

AG31

AF28

GND⁽¹⁾

AG30

AG29

AH31

AG28

I/O39

I/O40

I/O41

I/O42

I/O53

I/O54

I/O55

I/O56

GND

VCC

38

39

40

41

L3

M1

K5

M2

48

49

50

51

243

242

241

240

AA26

Y25

I/O25

I/O26

30

31

Y24

AA25

GND⁽¹⁾

VCC⁽¹⁾

AB25

AA24

I/O57

I/O58

I/O85

I/O86

I/O87

I/O88

I/O89

I/O90

GND

I/O91

I/O92

I/O93

I/O94

239

238

I/O27

I/O28

I/O43

I/O44

I/O59

I/O60

27

21

22

18

19

28

29

32

33

42

43

L4

52

53

237

236

Y23

N1

AC26

AD26

AC25

AA23

AB24

I/O29

I/O30

I/O45

I/O46

I/O61

I/O62

30

31

34

35

44

45

M3

N2

54

55

235

234

I/O31

(/OTS)

I/O47

(/OTS)

I/O63

(/OTS)

I/O95

(/OTS)

28

23

20

32

36

46

K6

56

233

AD25

AH30

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

AT40K

34

AT40K

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

Left Side (Top to Bottom)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

I/O32,

GCK2

I/O48,

GCK2

I/O64,

GCK2

I/O96,

GCK2

29

24

21

33

37

47

P1

57

232

AC24

AJ30

M1

GND

M0

M1

GND

M0

M1

GND

M0

M1

GND

M0

30

31

32

25

26

27

22

23

24

34

35

36

38

39

40

48

49

50

N3

GND⁽¹⁾

P2

58

59

60

231

230

229

AB23

GND⁽¹⁾

AD24

AH29

GND⁽¹⁾

AH28

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

Bottom Side (Left to Right)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

VCC

M2

VCC

M2

VCC

M2

VCC

M2

33

34

28

29

25

26

37

38

41

42

55

56

VCC*

M4

61

62

228

227

VCC⁽¹⁾

AC23

VCC⁽¹⁾

AJ28

I/O33,

GCK3

I/O49,

GCK3

I/O65,

GCK3

I/O97,

GCK3

35

36

30

31

27

28

39

40

43

44

57

58

R2

P3

63

64

226

225

AE24

AD23

AK29

AH27

I/O34

(HDC)

I/O50

(HDC)

I/O66

(HDC)

I/O98

(HDC)

I/O35

I/O36

I/O37

I/O51

I/O52

I/O53

I/O67

I/O68

I/O69

I/O99

I/O100

I/O101

41

42

43

45

46

47

59

60

61

L5

N4

R3

65

66

67

224

223

222

AC22

AF24

AD22

AK28

AJ27

AL28

32

33

29

30

I/O38

(LDC)

I/O54

(LDC)

I/O70

(LDC)

I/O102

(LDC)

37

44

48

62

P4

68

221

AE23

AH26

GND

I/O103

I/O104

I/O105

I/O106

I/O107

I/O108

VCC

GND⁽¹⁾

AK27

AJ26

AC21

AD21

AE22

AF23

VCC⁽¹⁾

GND⁽¹⁾

AD20

AE21

AF21

AC19

AL27

AH25

AK26

AL26

VCC⁽¹⁾

GND⁽¹⁾

AH24

AJ25

I/O71

I/O72

VCC

220

219

GND

I/O73

I/O74

I/O75

I/O76

GND

I/O39

I/O40

I/O55

I/O56

I/O57

I/O58

I/O109

I/O110

I/O111

I/O112

I/O113

I/O114

49

50

63

64

65

66

K7

M5

R4

N5

69

70

71

72

218

217

216

215

AK25

AJ24

AH23

AK24

VCC⁽¹⁾

GND⁽¹⁾

GND

I/O115

I/O116

I/O117

I/O118

I/O119

I/O120

GND

I/O59

I/O60

I/O77

I/O78

I/O79

I/O80

GND

P5

L6

73

74

214

213

212

211

210

AD19

AE20

AF20

AL24

AH22

AJ23

AC18

GND⁽¹⁾

AK23

GND⁽¹⁾

GND

45

51

67

GND⁽¹⁾

75

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

35

AT40K05

128 I/O

I/O41

AT40K10

192 I/O

I/O61

AT40K20

256 I/O

I/O81

I/O82

I/O83

I/O84

VCC

AT40K40

384 I/O

I/O121

I/O122

I/O123

I/O124

VCC

Bottom Side (Left to Right)

PC84

RQ100

VQ100

TQ144

46

PQ160

52

PQ208

68

BG225

R5

PQ240

76

PQ304

209

BG352

AD18

AE19

AC17

AD17

VCC⁽¹⁾

AE18

AF18

BG432

AJ22

I/O42

I/O62

47

53

69

M6

77

208

AK22

AL22

AJ21

I/O43

I/O63

38

39

34

35

31

32

48

54

70

N6

78

207

I/O44

I/O64

49

55

71

P6

79

206

VCC

VCC⁽¹⁾

R6

80

204

VCC⁽¹⁾

AH20

AK21

GND⁽¹⁾

AJ20

I/O65

I/O85

I/O86

I/O125

I/O126

GND

72

73

81

203

I/O66

M7

82

202

I/O127

I/O128

I/O129

I/O130

I/O131

I/O132

GND

AH19

AK20

AJ19

AC16

AD16

AE17

AE16

GND⁽¹⁾

VCC⁽¹⁾

AF16

AC15

AD15

AE15

AF15

AD14

I/O87

I/O88

GND

201

200

AL20

AH18

GND⁽¹⁾

VCC⁽¹⁾

AK19

AJ18

83

VCC

I/O89

I/O90

I/O91

I/O92

I/O93

I/O94

I/O133

I/O134

I/O135

I/O136

I/O137

I/O138

GND

199

198

197

196

195

194

I/O67

I/O68

I/O69

I/O70

N7

P7

R7

L7

84

85

86

87

AL19

AK18

AH17

AJ17

I/O45

I/O46

36

37

33

34

50

51

56

57

74

75

GND⁽¹⁾

I/O139

I/O140

I/O141

I/O142

AK17

AL17

I/O47

(D15)

I/O71

(D15)

I/O95

(D15)

I/O143

(D15)

40

41

38

39

35

36

52

53

58

59

76

77

N8

P8

88

89

193

192

AE14

AF14

AJ16

AK16

I/O48

(INIT)

I/O72

(INIT)

I/O96

(INIT)

I/O144

(INIT)

VCC

GND

VCC

GND

VCC

GND

VCC

GND

42

43

40

41

37

38

54

55

60

61

78

79

VCC⁽¹⁾

GND⁽¹⁾

90

91

191

190

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

I/O49

(D14)

I/O73

(D14)

I/O97

(D14)

I/O145

(D14)

44

45

42

43

39

40

56

57

62

63

80

81

L8

92

93

189

188

AE13

AC13

AL16

AH15

I/O50

(D13)

I/O74

(D13)

I/O98

(D13)

I/O146

(D13)

P9

I/O147

I/O148

I/O149

I/O150

GND

AL15

AJ15

GND⁽¹⁾

AK15

AJ14

AH14

AK14

AL13

I/O51

I/O52

I/O75

I/O76

I/O77

I/O78

I/O99

I/O100

I/O101

I/O102

I/O103

I/O151

I/O152

I/O153

I/O154

I/O155

44

45

41

42

58

59

64

65

82

83

84

85

R9

N9

M9

L9

94

95

96

97

187

186

185

184

183

AD13

AF12

AE12

AD12

AC12

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

AT40K

36

AT40K

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

I/O104

AT40K40

384 I/O

I/O156

VCC

Bottom Side (Left to Right)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

AF11

BG432

AK13

VCC⁽¹⁾

GND⁽¹⁾

AJ13

182

VCC⁽¹⁾

GND⁽¹⁾

AE11

AD11

AE10

AC11

GND

98

I/O105

I/O106

I/O157

I/O158

I/O159

I/O160

I/O161

I/O162

GND

181

180

AH13

AL12

AK12

AJ12

AK11

GND⁽¹⁾

AH12

AJ11

I/O79

I/O80

VCC

I/O107

I/O108

VCC

I/O163

I/O164

VCC

R10

P10

99

179

178

177

AF9

AD10

VCC⁽¹⁾

100

101

VCC⁽¹⁾

I/O53

(D12)

I/O81

(D12)

I/O109

(D12)

I/O165

(D12)

46

47

46

47

43

44

60

61

66

67

86

87

N10

K9

102

103

175

174

AE9

AD9

AL10

AK10

I/O54

(D11)

I/O82

(D11)

I/O110

(D11)

I/O166

(D11)

I/O55

I/O56

GND

I/O83

I/O84

GND

I/O111

I/O112

GND

I/O167

I/O168

GND

62

63

64

68

69

70

88

89

90

R11

P11

104

105

106

173

172

171

170

169

168

167

AC10

AF7

AJ10

AK9

GND⁽¹⁾

AE8

GND⁽¹⁾

AL8

I/O113

I/O114

I/O115

I/O116

I/O169

I/O170

I/O171

I/O172

I/O173

I/O174

AD8

AH10

AJ9

I/O85

I/O86

M10

N11

107

108

AC9

AF6

AK8

GND

GND⁽¹⁾

VCC⁽¹⁾

I/O175

I/O176

I/O177

I/O178

I/O179

I/O180

GND

AJ8

AH9

I/O87

I/O88

I/O89

I/O90

I/O117

I/O118

I/O119

I/O120

GND

91

92

93

94

R12

L10

P12

M11

109

110

111

112

166

165

164

163

AE7

AD7

AK7

AL6

I/O57

I/O58

71

72

AE6

AJ7

AE5

AH8

GND⁽¹⁾

VCC⁽¹⁾

AD6

GND⁽¹⁾

VCC⁽¹⁾

AK6

VCC

I/O121

I/O122

I/O181

I/O182

162

161

AC7

AL5

I/O59

(D10)

I/O91

(D10)

I/O123

(D10)

I/O183

(D10)

48

49

48

49

45

46

65

66

73

74

95

96

R13

N12

113

114

160

159

AF4

AH7

I/O60

(D9)

I/O92

(D9)

I/O124

(D9)

I/O184

(D9)

AF3

AE4

AJ6

AK5

I/O185

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

37

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

I/O186

GND

Bottom Side (Left to Right)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

AL4

AC6

GND⁽¹⁾

AH6

I/O187

I/O188

I/O189

I/O190

AJ5

I/O61

I/O62

I/O93

I/O94

I/O125

I/O126

67

68

75

76

97

98

P13

K10

115

116

158

157

AD5

AE3

AK4

AH5

I/O63

(D8)

I/O95

(D8)

I/O127

(D8)

I/O191

(D8)

50

51

50

51

47

48

69

70

77

78

99

R14

N13

117

118

156

155

AD4

AC5

AK3

AJ4

I/O64,

GCK4

I/O96,

GCK4

I/O128,

GCK4

I/O192

,GCK4

100

GND

52

53

52

53

49

50

71

72

79

80

101

103

GND⁽¹⁾

P14

119

120

154

153

GND⁽¹⁾

AD3

GND⁽¹⁾

AH4

/CON

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

Right Side (Bottom to Top)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

VCC

54

55

54

55

51

52

73

74

81

82

106

108

VCC⁽¹⁾

M12

121

122

152

151

VCC⁽¹⁾

AC4

VCC⁽¹⁾

AH3

/RESET

I/O65

(D7)

I/O97

(D7)

I/O129

(D7)

I/O193

(D7)

56

57

56

57

53

54

75

76

83

84

109

110

P15

N14

123

124

150

149

AD2

AC3

AJ2

I/O66,

GCK5

I/O98,

GCK5

I/O130,

GCK5

I/O194,

GCK5

AG4

I/O67

I/O68

I/O99

I/O131

I/O132

I/O195

I/O196

I/O197

I/O198

GND

77

78

85

86

111

112

L11

125

126

148

147

AB4

AD1

AB3

AC2

AG3

AH2

I/O100

M13

AH1

AF4

GND⁽¹⁾

AF3

I/O101

I/O102

I/O133

I/O134

I/O199

I/O200

I/O201

I/O202

I/O203

I/O204

VCC

N15

M14

127

128

146

145

AA4

AA3

AG2

AG1

AE4

I/O135

I/O136

VCC

144

143

AB2

AC1

AE3

AF2

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

GND

I/O69

(D6)

I/O103

(D6)

I/O137

(D6)

I/O205

(D6)

58

59

55

56

79

80

87

113

J10

129

142

Y3

AF1

I/O70

I/O71

I/O72

I/O104

I/O105

I/O106

I/O138

I/O139

I/O140

I/O206

I/O207

I/O208

I/O209

I/O210

88

89

90

114

115

116

L12

M15

L13

130

131

132

141

140

139

AA2

AA1

W4

AD4

AD3

AE2

AD2

AC4

VCC⁽¹⁾

GND⁽¹⁾

GND

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

AT40K

38

AT40K

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

I/O211

I/O212

I/O213

I/O214

I/O215

I/O216

GND

Right Side (Bottom to Top)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

I/O107

I/O108

I/O141

I/O142

I/O143

I/O144

GND

117

118

L14

K11

133

134

138

137

136

135

134

133

132

W3

Y2

AC3

AD1

AC2

Y1

V4

AB4

GND

81

91

119

GND⁽¹⁾

L15

135

136

137

GND⁽¹⁾

V3

GND⁽¹⁾

AB3

I/O109

I/O110

I/O145

I/O146

I/O217

I/O218

K12

W2

AB2

I/O73,

FCK3

I/O111,

FCK3

I/O147,

FCK3

I/O219,

FCK3

82

83

92

93

120

121

K13

138

131

U4

AB1

I/O74

I/O112

VCC

I/O148

VCC

I/O220

VCC

K14

139

140

130

129

U3

AA3

VCC⁽¹⁾

I/O75

(D5)

I/O113

(D5)

I/O149

(D5)

I/O221

(D5)

59

60

61

57

58

84

85

94

95

122

123

K15

J12

141

142

127

126

V2

V1

AA2

Y2

I/O76

(CS0)

I/O114

(CS0)

I/O150

(CS0)

I/O222

(CS0)

GND

GND⁽¹⁾

Y4

I/O223

I/O224

I/O225

I/O226

T4

T3

Y3

Y1

W1

I/O151

I/O152

GND

I/O227

I/O228

GND

125

124

U2

T2

W4

W3

143

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

W2

VCC

I/O229

I/O230

I/O231

I/O232

I/O233

I/O234

GND

V2

I/O153

I/O154

I/O155

I/O156

123

122

121

120

T1

R4

R3

R2

V4

V3

I/O115

I/O116

124

125

J13

J14

144

145

U1

U2

GND⁽¹⁾

U4

I/O77

I/O78

I/O117

I/O118

I/O157

I/O158

I/O235

I/O236

I/O237

I/O238

I/O239(D4)

I/O240

VCC

62

63

59

60

86

87

96

97

126

127

J15

J11

146

147

119

118

R1

P3

U3

I/O79(D4)

I/O80

I/O119(D4)

I/O120

VCC

I/O159(D4)

I/O160

VCC

61

62

63

64

65

66

67

61

62

63

64

88

89

90

91

98

99

128

129

130

131

H13

H14

148

149

150

151

117

116

115

114

P2

T1

P1

T2

VCC

100

101

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

GND

I/O81

(D3)

I/O121

(D3)

I/O161

(D3)

I/O241

(D3)

65

66

68

69

65

66

92

93

102

103

132

133

H12

H11

152

153

113

112

N2

N4

T3

I/O82

(/CHECK)

I/O122

(/CHECK)

I/O162

(/CHECK)

I/O242

(/CHECK)

R1

I/O243

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

39

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

I/O244

I/O245

I/O246

GND

Right Side (Bottom to Top)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

I/O83

I/O84

I/O123

I/O124

I/O163

I/O164

70

67

94

95

104

105

134

135

G14

G15

154

155

111

110

N3

M1

R2

R4

GND⁽¹⁾

R3

I/O125

I/O126

I/O165

I/O166

I/O167

I/O168

I/O247

I/O248

I/O249

I/O250

I/O251

I/O252

VCC

136

137

G13

G12

156

157

109

108

107

106

M2

M3

M4

L1

P2

P3

P4

N1

N2

VCC⁽¹⁾

GND⁽¹⁾

L2

VCC⁽¹⁾

GND⁽¹⁾

N3

GND

I/O169

I/O170

GND

158

I/O253

I/O254

I/O255

I/O256

105

104

L3

N4

K2

M1

L4

M2

I/O257

I/O258

GND

M3

M4

GND⁽¹⁾

I/O85

(D2)

I/O127

(D2)

I/O171

(D2)

I/O259

(D2)

67

68

71

72

68

69

96

97

106

107

138

139

G11

F15

159

160

103

102

J1

L2

L3

I/O86

I/O128

I/O172

I/O260

K3

VCC

VCC⁽¹⁾

F14

161

162

101

99

VCC⁽¹⁾

J2

VCC⁽¹⁾

K1

I/O87

I/O129

I/O173

I/O261

98

99

108

109

140

141

I/O88,

FCK4

I/O130,

FCK4

I/O174,

FCK4

I/O262,

FCK4

F13

163

98

J3

K2

I/O131

I/O132

GND

I/O175

I/O176

GND

I/O263

I/O264

GND

G10

E15

164

165

166

97

96

95

94

93

92

91

K4

G1

K3

K4

GND

100

110

142

GND⁽¹⁾

H2

GND⁽¹⁾

J2

I/O177

I/O178

I/O179

I/O180

I/O265

I/O266

I/O267

I/O268

I/O269

I/O270

H3

J3

I/O133

I/O134

E14

F12

167

168

J4

F1

H1

GND

GND⁽¹⁾

I/O135

I/O136

I/O137

I/O181

I/O182

I/O183

I/O271

I/O272

I/O273

143

144

145

E13

D15

F11

169

170

171

90

89

88

G2

G3

F2

H2

H3

H4

I/O89

111

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

AT40K

40

AT40K

AT40K05

128 I/O

I/O90

AT40K10

192 I/O

I/O138

AT40K20

256 I/O

I/O184

AT40K40

384 I/O

I/O274

I/O275

I/O276

Right Side (Bottom to Top)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

G2

112

146

D14

172

87

E2

G3

F1

GND

VCC

GND

VCC

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

I/O91

(D1)

I/O139

(D1)

I/O185

(D1)

I/O277

(D1)

69

70

73

74

70

71

101

102

113

114

147

148

E12

C15

173

174

86

85

F3

G4

I/O92

I/O140

I/O186

I/O278

I/O279

I/O280

I/O281

I/O282

GND

G4

D1

C1

F2

F3

E1

F4

E2

GND⁽¹⁾

E3

I/O187

I/O188

I/O189

I/O190

I/O283

I/O284

I/O285

I/O286

84

83

82

81

D2

F4

E3

C2

D1

I/O93

I/O94

I/O141

I/O142

103

104

115

116

149

150

D13

C14

175

176

E4

D2

I/O95

(D0)

I/O143

(D0)

I/O191

(D0)

I/O287

(D0)

71

72

75

76

72

73

105

106

117

118

151

152

F10

B15

177

178

80

79

D3

E4

C2

D3

I/O96,

GCK6

I/O144,

GCK6

I/O192,

GCK6

I/O288,

GCK6

(/CSOUT)

CCLK

VCC

CCLK

VCC

CCLK

VCC

CCLK

VCC

73

74

77

78

74

75

107

108

119

120

153

154

C13

179

180

78

77

C3

D4

VCC⁽¹⁾

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

Top Side (Right to Left)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

GND

76

77

80

81

77

78

110

111

122

123

160

161

GND⁽¹⁾

A14

182

183

75

74

GND⁽¹⁾

B3

GND⁽¹⁾

B3

I/O97

(A0)

I/O145

(A0)

I/O193

(A0)

I/O289

(A0)

I/O98,

GCK7

(A1)

I/O146,

GCK7

(A1)

I/O194,

GCK7

(A1)

I/O290,

GCK7

(A1)

78

82

79

112

124

162

B13

184

73

C4

D5

I/O99

I/O147

I/O148

I/O195

I/O196

I/O291

I/O292

I/O293

I/O294

GND

113

114

125

126

163

164

E11

C12

185

186

72

71

D5

A3

B4

C5

I/O100

A4

D6

GND⁽¹⁾

B5

I/O295

I/O296

C5

B4

C6

I/O101

(/CS1,A2)

I/O149

(/CS1,A2)

I/O197

(/CS1,A2)

I/O297

(/CS1,A2)

79

80

83

84

80

81

115

116

127

128

165

166

A13

B12

187

188

70

69

D6

C6

A5

D7

I/O102

(A3)

I/O150

(A3)

I/O198

(A3)

I/O298

(A3)

I/O199

I/O200

VCC

I/O299

I/O300

VCC

68

67

B5

A4

B6

A6

VCC⁽¹⁾

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

41

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

GND

AT40K40

384 I/O

GND

Top Side (Right to Left)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

GND⁽¹⁾

C7

BG432

GND⁽¹⁾

D8

I/O151

I/O152

I/O153

I/O154

I/O201

I/O202

I/O203

I/O204

I/O301

I/O302

I/O303

I/O304

I/O305

I/O306

75

79

76

109

121

159

F9

189

190

191

192

66

65

64

63

D11

A12

C11

B6

C7

I/O103

I/O104

117

129

130

167

168

A6

B7

75⁽²⁾

79⁽²⁾

76⁽²⁾

109⁽²⁾

D8

D9

C8

B8

A8

VCC⁽¹⁾

GND⁽¹⁾

GND

I/O307

I/O308

I/O309

I/O310

I/O311

I/O312

GND

I/O155

I/O156

I/O205

I/O206

I/O207

I/O208

GND

169

170

B11

E10

193

194

195

62

61

60

59

58

57

56

55

54

52

51

50

B7

A7

D10

C9

D9

B9

C9

C10

GND

I/O157

I/O158

I/O159

I/O160

VCC

118

119

120

131

132

133

171

172

173

GND⁽¹⁾

A11

196

197

198

199

200

201

GND⁽¹⁾

B8

GND⁽¹⁾

B10

v

I/O105

I/O106

I/O209

I/O210

I/O211

I/O212

VCC

I/O313

I/O314

I/O315

I/O316

VCC

D10

C10

B9

A10

C10

C11

B10

D12

VCC*

VCC⁽¹⁾

A9

VCC⁽¹⁾

B11

I/O213

I/O214

I/O317

I/O318

D11

C12

GND

GND⁽¹⁾

I/O319

I/O320

I/O321

I/O322

I/O323

I/O324

GND

D13

B12

C11

B10

C13

A12

I/O215

I/O216

GND

49

48

B11

D14

A11

B13

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

VCC

I/O107

(A4)

I/O161

(A4)

I/O217

(A4)

I/O325

(A4)

81

82

85

86

82

83

121

122

134

135

174

175

A10

D9

202

203

47

46

D12

C12

C14

A13

I/O108

(A5)

I/O162

(A5)

I/O218

(A5)

I/O326

(A5)

I/O163

I/O164

I/O165

I/O166

I/O219

I/O220

I/O221

I/O222

I/O327

I/O328

I/O329

I/O330

176

177

178

179

C9

B9

A9

E9

205

206

207

208

45

44

43

42

B12

A12

C13

B13

B14

D15

C15

B15

136

137

138

I/O109

I/O110

87

88

84

85

123

124

Notes: 1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

2. This applies to the AT40K05 only.

AT40K

42

AT40K

AT40K05

128 I/O

AT40K10

192 I/O

AT40K20

256 I/O

AT40K40

384 I/O

GND

Top Side (Right to Left)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

BG352

BG432

GND⁽¹⁾

I/O331

I/O332

I/O333

I/O334

A15

C16

I/O111

(A6)

I/O167

(A6)

I/O223

(A6)

I/O335

(A6)

83

84

89

90

86

87

125

126

139

140

180

181

C8

B8

209

210

41

40

A13

B14

B16

A16

I/O112

(A7)

I/O168

(A7)

I/O224

(A7)

I/O336

(A7)

GND

VCC

GND

VCC

GND

VCC

GND

VCC

1

2

91

92

88

89

127

128

141

142

182

183

GND⁽¹⁾

VCC⁽¹⁾

211

212

39

38

GND⁽¹⁾

VCC⁽¹⁾

GND⁽¹⁾

VCC⁽¹⁾

I/O113

(A8)

I/O169

(A8)

I/O225

(A8)

I/O337

(A8)

3

4

93

94

90

91

129

130

143

144

184

185

E8

B7

213

214

37

36

D14

C14

D17

A17

I/O114

(A9)

I/O170

(A9)

I/O226

(A9)

I/O338

(A9)

I/O339

I/O340

I/O341

I/O342

GND

C17

B17

GND⁽¹⁾

C18

I/O115

I/O116

I/O171

I/O172

I/O173

I/O174

I/O227

I/O228

I/O229

I/O230

I/O343

I/O344

I/O345

I/O346

95

96

92

93

131

132

145

146

186

187

188

189

A7

C7

D7

E7

215

216

217

218

35

34

33

32

A15

B15

C15

D15

D18

B18

A19

I/O117

(A10)

I/O175

(A10)

I/O231

(A10)

I/O347

(A10)

5

6

97

98

94

95

133

134

147

148

190

191

A6

B6

220

221

31

30

A16

B16

B19

C19

I/O118

(A11)

I/O176

(A11)

I/O232

(A11)

I/O348

(A11)

VCC

VCC⁽¹⁾

GND⁽¹⁾

C16

VCC⁽¹⁾

GND⁽¹⁾

D19

GND

I/O233

I/O234

I/O349

I/O350

I/O351

I/O352

I/O353

I/O354

29

28

B17

A20

D16

B20

A18

C20

B21

D20

GND

GND⁽¹⁾

I/O235

I/O236

VCC

I/O355

I/O356

VCC

27

26

25

23

22

21

20

C17

B18

C21

A22

VCC

VCC⁽¹⁾

C6

222

223

224

225

226

VCC⁽¹⁾

C18

VCC⁽¹⁾

B22

I/O177

I/O178

I/O179

I/O180

I/O237

I/O238

I/O239

I/O240

I/O357

I/O358

I/O359

I/O360

F7

D17

C22

I/O119

I/O120

135

136

149

150

192

193

A5

A20

B23

B5

B19

A24

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

43

AT40K05

128 I/O

GND

AT40K10

192 I/O

GND

AT40K20

256 I/O

GND

AT40K40

384 I/O

GND

Top Side (Right to Left)

PC84

RQ100

VQ100

TQ144

PQ160

PQ208

BG225

PQ240

PQ304

19

BG352

GND⁽¹⁾

C19

BG432

GND⁽¹⁾

D22

137

151

194

GND*

227

I/O241

I/O242

I/O243

I/O244

I/O361

I/O362

I/O363

I/O364

I/O365

I/O366

18

17

D18

C23

I/O181

I/O182

195

196

D6

C5

228

229

16

A21

B24

15

B20

C24

GND

GND⁽¹⁾

I/O367

I/O368

I/O369

I/O370

D23

B25

A26

C25

I/O121

I/O122

I/O183

I/O184

I/O245

I/O246

152

153

197

198

A4

E6

230

231

14

13

C20

B21

I/O123

(A12)

I/O185

(A12)

I/O247

(A12)

I/O371

(A12)

7

8

99

96

97

138

139

154

155

199

200

B4

D5

232

233

12

10

B22

C21

D24

B26

I/O124

(A13)

I/O186

(A13)

I/O248

(A13)

I/O372

(A13)

100

GND

VCC

GND

VCC

GND*

VCC*

D20

GND*

VCC*

A27

I/O249

I/O250

I/O373

I/O374

I/O375

I/O376

I/O377

I/O378

GND

9

8

A23

D25

C26

B27

A24

B23

A28

D26

GND*

C27

B28

I/O187

I/O188

I/O189

I/O190

I/O251

I/O252

I/O253

I/O254

I/O379

I/O380

I/O381

I/O382

A3

C4

B3

F6

234

235

236

237

7

6

5

4

D21

C22

B24

C23

I/O125

I/O126

140

141

156

157

201

202

D27

B29

I/O127

(A14)

I/O191

(A14)

I/O255

(A14)

I/O383

(A14)

9

1

98

142

158

203

A2

238

3

D22

C28

I/O128,

GCK8

(A15)

I/O192,

GCK8

(A15)

I/O256,

GCK8

(A15)

I/O384,

GCK8

(A15)

10

11

2

3

99

143

144

159

160

204

205

C3

239

240

2

1

C24

D28

VCC

100

VCC*

VCC⁽¹⁾

Note:

1. Pads labelled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-

nection to any specific package pin.

AT40K

44

AT40K

Figure 15. AT40K20 Pad Ring

VCC

CCLK

GND I/O1,GCK1

(A16)

I/O2 (A17)

I/O3 I/O4 I/O5

(A18)

I/O192,GCK6 (/CSCOUT)

I/O191 (D0)

I/O190

I/O189

I/O6 (A19)

I/O7 I/O8 VCC

GND I/O9 I/O10

I/O11

I/O188

I/O187

I/O186

I/O185 (D1)

VCC

I/O12

I/O13

GND

I/O14

I/O184

I/O15

I/O183

I/O16

I/O182

GND

I/O181

I/O17,FCK1

I/O18

I/O180

I/O179

I/O19 (A20)

I/O20 (A21)

VCC

I/O178

I/O177

GND

I/O21

I/O176

I/O22

I/O175

I/O23

I/O174,FCK4

I/O173

I/O24

GND‡

I/O25

VCC

I/O172

I/O26

I/O171 (D2)

I/O170

I/O27

I/O28

I/O169

I/O29

GND‡

I/O30

I/O168

I/O31 (A22)

I/O32 (A23)

GND

I/O167

I/O166

I/O165

VCC

I/O164

I/O33

I/O163

I/O34

I/O162 (/CHECK)

I/O161 (D3)

GND

I/O35

I/O36

I/O37

VCC

I/O160

I/O38

I/O39

I/O159 (D4)

I/O158

I/O40

GND‡

I/O41

I/O157

I/O156

I/O42

I/O155

I/O43

I/O154

I/O44

I/O153

VCC

GND

I/O45

I/O152

I/O46

I/O151

I/O47

GND‡

I/O48,FCK2

GND

I/O150 (/CS0)

I/O149 (D5)

VCC

I/O49

I/O50

I/O148

I/O51

I/O147,FCK3

I/O146

I/O52

I/O53

I/O145

I/O54

GND

I/O55

I/O144

I/O56

I/O143

GND

I/O142

VCC

I/O141

I/O57

I/O140

I/O58

I/O139

I/O59

I/O138

I/O60

I/O137 (D6)

GND

I/O61

I/O62

VCC

I/O63 (/OTS)

I/O64,GCK2

M1

I/O136

I/O135

I/O134

GND

M0

I/O133

I/O132

I/O131

I/O130,GCK5

I/O129 (D7)

/RESET

VCC

45

AT40K05 Ordering Information

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

5,000-10,000

2

AT40K05-2AJC

AT40K05-2AQC

AT40K05-2BQC

AT40K05-2CQC

AT40K05-2DQC

84J

5V Commercial

100Q

144Q

160Q

208Q

(0°C to 70°C)

5,000-10,000

2

AT40K05-2AJI

AT40K05-2AQI

AT40K05-2BQI

AT40K05-2CQI

AT40K05-2DQI

84J

5V Industrial

100Q

144Q

160Q

208Q

(-40°C to 85°C)

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

5,000-10,000

3

AT40K05LV-3AJC

AT40K05LV-3AQC

AT40K05LV-3BQC

AT40K05LV-3CQC

AT40K05LV-3DQC

84J

3.3V Commercial

100Q

144Q

160Q

208Q

(0°C to 20°C)

Package Type

84J

84-lead, Plastic J-Leaded Chip Carrier (PLCC)

100Q

100RQ

144Q

160Q

208Q

225G

240Q

304Q

352G

432G

100-lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP)

100-lead, Rectangular Plastic Plastic Gull Wing Quad Flat Package (RQPD)

144-lead, Thin (1.4 mm) Plastic Gull Wing Quad Flat Package (TQFP)

160-lead, Plastic Gull Wing Quad Flat Package (PQFP)

208-lead, Plastic Gull Wing Quad Flat Package (PQFP)

225-lead, Ball Grid Array Package (BGA)

240-lead, Plastic Gull Wing Quad Flat Package (PQFP)

304-lead, Plastic Gull Wing Quad Flat Package (PQFP)

352-ball, Ball Grid Array Package (BGA)

432-ball, Ball Grid Array Package (BGA)

AT40K

46

AT40K

AT40K10 Ordering Information

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

10,000-20,000

2

AT40K10-2AJC

AT40K10-2AQC

AT40K10-2RQC

AT40K10-2BQC

AT40K10-2CQC

AT40K10-2DQC

AT40K10-2EQC

AT40K10-2AGC

84J

5V Commercial

100Q

100RQ

144Q

160Q

208Q

240Q

225G

(0°C to 70°C)

10,000-20,000

2

AT40K10-2AJI

AT40K10-2AQI

AT40K10-2BQI

AT40K10-2CQI

AT40K10-2DQI

AT40K10-2EQI

AT40K10-2AGI

84J

5V Industrial

100Q

144Q

160Q

208Q

240Q

225G

(-40°C to 85°C)

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

10,000-20,000

3

AT40K10LV-3AJC

AT40K10LV-3AQC

AT40K10LV-3RQC

AT40K10LV-3BQC

AT40K10LV-3CQC

AT40K10LV-3DQC

AT40K10LV-3EQC

AT40K10LV-3AGC

84J

3.3V Commercial

100Q

100RQ

144Q

160Q

208Q

240Q

225G

(0°C to 20°C)

Package Type

84J

84-lead, Plastic J-Leaded Chip Carrier (PLCC)

100Q

100RQ

144Q

160Q

208Q

225G

240Q

304Q

352G

432G

100-lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP)

100-lead, Rectangular Plastic Plastic Gull Wing Quad Flat Package (RQPD)

144-lead, Thin (1.4 mm) Plastic Gull Wing Quad Flat Package (TQFP)

160-lead, Plastic Gull Wing Quad Flat Package (PQFP)

208-lead, Plastic Gull Wing Quad Flat Package (PQFP)

225-lead, Ball Grid Array Package (BGA)

240-lead, Plastic Gull Wing Quad Flat Package (PQFP)

304-lead, Plastic Gull Wing Quad Flat Package (PQFP)

352-ball, Ball Grid Array Package (BGA)

432-ball, Ball Grid Array Package (BGA)

47

AT40K20 Ordering Information

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

20,000-30,000

2

AT40K20-2AJC

AT40K20-2AQC

AT40K20-2BQC

AT40K20-2CQC

AT40K20-2DQC

AT40K20-2EQC

AT40K20-2FQC

AT40K20-2BGC

AT40K20-2AGC

84J

5V Commercial

100Q

144Q

160Q

208Q

240Q

304Q

352G

225G

(0°C to 70°C)

20,000-30,000

2

AT40K20-2AJI

AT40K20-2BQI

AT40K20-2CQI

AT40K20-2DQI

AT40K20-2EQI

AT40K20-2FQI

AT40K20-2BGI

AT40K20-2AGI

84J

5V Industrial

144Q

160Q

208Q

240Q

304Q

352G

225G

(-40°C to 85°C)

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

20,000-30,000

3

AT40K20LV-2AJC

AT40K20LV-2AQC

AT40K20LV-2BQC

AT40K20LV-2CQC

AT40K20LV-2DQC

AT40K20LV-2EQC

AT40K20LV-2FQC

AT40K20LV-2BGC

AT40K20LV-2AGC

84J

3.3V Commercial

100Q

144Q

160Q

208Q

240Q

304Q

352G

225G

(0°C to 20°C)

Package Type

84J

84-lead, Plastic J-Leaded Chip Carrier (PLCC)

100Q

144Q

160Q

208Q

225G

240Q

304Q

352G

432G

100-lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP)

144-lead, Thin (1.4 mm) Plastic Gull Wing Quad Flat Package (TQFP)

160-lead, Plastic Gull Wing Quad Flat Package (PQFP)

208-lead, Plastic Gull Wing Quad Flat Package (PQFP)

225-lead, Ball Grid Array Package (BGA)

240-lead, Plastic Gull Wing Quad Flat Package (PQFP)

304-lead, Plastic Gull Wing Quad Flat Package (PQFP)

352-ball, Ball Grid Array Package (BGA)

432-ball, Ball Grid Array Package (BGA)

AT40K

48

AT40K

AT40K40 Ordering Information

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

40,000-50,000

2

AT40K40-2BQC

AT40K40-2DQC

AT40K40-2EQC

AT40K40-2FQC

AT40K40-2BGC

AT40K40-2CGC

144Q

208Q

240Q

304Q

352G

432G

5V Commercial

(0°C to 70°C)

40,000-50,000

2

AT40K40-2BQI

AT40K40-2DQI

AT40K40-2EQI

AT40K40-2FQI

AT40K40-2BGI

AT40K40-2CGI

144Q

208Q

240Q

304Q

352G

432G

5V Industrial

(-40°C to 85°C)

Usable Gates

Speed Grade (ns)

Ordering Code

Package

Operation Range

40,000-50,000

3

AT40K40LV-3BQC

AT40K40LV-3DQC

AT40K40LV-3EQC

AT40K40LV-3FQC

AT40K40LV-3BGC

AT40K40LV-3CGC

144Q

208Q

240Q

304Q

352G

432G

3.3V Commercial

(0°C to 20°C)

Package Type

144Q

160Q

208Q

225G

240Q

304Q

352G

432G

144-lead, Thin (1.4 mm) Plastic Gull Wing Quad Flat Package (TQFP)

160-lead, Plastic Gull Wing Quad Flat Package (PQFP)

208-lead, Plastic Gull Wing Quad Flat Package (PQFP)

225-lead, Ball Grid Array Package (BGA)

240-lead, Plastic Gull Wing Quad Flat Package (PQFP)

304-lead, Plastic Gull Wing Quad Flat Package (PQFP)

352-ball, Ball Grid Array Package (BGA)

432-ball, Ball Grid Array Package (BGA)

49

Packaging Information

84J, 84-lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AF

100Q, 100-lead, Plastic Gull Wing Quad Flat

Package (VQFP)

Dimensions in Millimeters and (Inches)*

16.25(0.640)

15.75(0.620)

PIN 1 ID

0.27(0.011)

0.17(0.007)

0.56(0.022)

0.44(0.018)

1.05(0.041)

0.95(0.037)

14.10(0.555)

13.90(0.547)

0.20(0.008)

0.10(0.004)

0-7

0.15(0.006)

0.05(0.002)

0.75(0.030)

0.45(0.018)

*Controlling dimension: millimeters

144Q, 144-lead, Plastic Gull Wing Quad Flat

Package (TQFP)

160Q, 160-lead, Plastic Gull Wing Quad Flat

Package (PQFP)

Dimensions in Millimeters and (Inches)*

Dimensions in (Millimeters) and Inches

1.238(31.45)

SQ

1.218(30.95)

PIN 1 ID

.016(0.40)

.008(0.20)

.0256(0.65) BSC

1.106(28.10)

1.098(27.90)

SQ

.157(3.97)

.127(3.22)

7

0

.009(0.23)

.004(0.10)

.037(0.95)

.025(0.65)

.020(0.50)

.002(0.05)

*Controlling dimension: millimeters

AT40K

50

AT40K

Packaging Information

208Q, 208-lead, Plastic Gull Wing Quad Flat

Package (PQFP)

240Q, 240-lead, Plastic Gull Wing Quad Flat

Package (PQFP)

Dimensions in (Millimeters) and Inches

*Controlling dimension: millimeters

100RQ, 100-lead, Rectangular Plastic Gull Wing

Quad Flat Pack (RQFP)

304Q, 304-lead, Plastic Gull Wing

Quad Flat Pack (PQFP)

Dimensions in Millimeters and (Inches)*

Dimensions in (Millimeters) and Inches

1.685 (42.8)

20.10 (0.791)

1.669 (42.40)

19.90 (0.783)

PIN 1 ID

14.10 (0.555)

13.90 (0.547)

0.65 (0.026) BSC

0.27 (6.90)

0.17 (4.32)

0.50 (12.7) BSC

2.87 (0.113)

2.57 (0.101)

7

0

0.17 (0.007)

0.13 (0.005)

1.03 (0.041)

0.73 (0.029)

0.36 (0.014)

0.10 (0.004)

1.579 (40.11)

1.571 (30.90)

0.40

(0.016)

0.13 (3.30)

0.005 (0.13)

7

0

0.43 (10.92)

0.25 (6.35)

*Controlling dimension: millimeters

51

Packaging Information

352B, 352-ball Ball Grid Array (BGA)

432B, 432-ball Ball Grid Array (BGA)

Dimensions in (Millimeters) and Inches

1.38 (35.1 )

1.37 (34.9)

0.88 (.035)

.030 (0.76)

1.58 (40.1)

1.53 (39.9)

.035 (0.88)

.030 (0.76)

1.58 (40.1)

1.53 (39.9)

1.38 (35.1)

1.37 (34.9)

0.062 (1.58) MAX

(1.25)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 171819 20 21 2223 24 25 26

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 171819 20 21 2223 24 25 26 2728 29 3031

KK

JJ

HH

GG

FF

EE

DD

CC

BB

AA

Z

EE

DD

CC

BB

AA

Z

Y

X

W

V

U

Y

X

T

R

P

N

M

L

K

W

V

U

T

R

P

N

M

L

1.25 (31.85)

1.25 (31.65)

1.50 (38.20)

1.50 (38.00)

J

K

J

H

G

F

E

H

G

F

E

D

C

D

B

C

B

A

(1.27)

1.25 (31.85)

1.25 (31.65)

(1.27)

1.50 (38.20)

1.50 (38.00)

AT40K

52

AT40K

Thermal Coefficient Table

Theta J-A

0 LFPM

Theta J-A

225 LFPM

Theta J-A

500 LPFM

Package Style

PQFP

TQFP

RQFP

PLCC

BGA

Lead Count

Theta J-C

144

160

208

240

304

100

84

33

30

32

27

19

47

3

27

24

23

20

8.5

7

28

24

10

No Data

39

No Data

33

22

12

37

26

30

25

225

352

432

No Data

BGA

53

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Europe

Atmel U.K., Ltd.

Atmel Rousset

Zone Industrielle

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

13106 Rousset Cedex, France

TEL (33) 4 42 53 60 00

FAX (33) 4 42 53 60 01

TEL (44) 1276-686677

FAX (44) 1276-686697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road

Tsimshatsui East

Kowloon, Hong Kong

TEL (852) 27219778

FAX (852) 27221369

Japan

Atmel Japan K.K.

Tonetsu Shinkawa Bldg., 9F

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

®

™

Marks bearing and/or

are registered trademarks and trademarks of Atmel Corporation.

Printed on recycled paper.

0896B–01/99/xM

Terms and product names in this document may be trademarks of others.


型号：	AT40K20LV-2AGC
厂家：	ETC
描述：	Field Programmable Gate Array (FPGA) 现场可编程门阵列（FPGA）的\n 现场可编程门阵列栅
文件：	总54页 (文件大小：935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT40K20LV-2AGC [ETC]

相关型号：

AT40K20LV-2AJC

AT40K20LV-2AJI

AT40K20LV-2AQC

AT40K20LV-2BGC

AT40K20LV-2BGI

AT40K20LV-2BQC

AT40K20LV-2BQI

AT40K20LV-2CQC

AT40K20LV-2DQC

AT40K20LV-2DQI

AT40K20LV-2EQC

AT40K20LV-2EQI