AT49BV080-12TC [ETC]
x8 Flash EEPROM ; X8闪存EEPROM\n![AT49BV080-12TC](http://pdffile.icpdf.com/pdf1/p00009/img/icpdf/AT49B_41177_icpdf.jpg)
型号: | AT49BV080-12TC |
厂家: | ![]() |
描述: | x8 Flash EEPROM
|
文件: | 总16页 (文件大小:174K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
Features
• Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
• Fast Read Access Time - 120 ns
• Internal Program Control and Timer
• 16K Bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte-By-Byte Programming - 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
8-Megabit
(1M x 8)
• Small Packaging
– 8 x 14 mm CBGA
Single 2.7-volt
Battery-Voltage™
Flash Memory
Description
The AT49BV/LV080(T) are 3-volt-only in-system Flash Memory devices. Their 8
megabits of memory are organized as 1,024,576 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to
120 ns with power dissipation of just 90 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA.
(continued)
AT49BV080
AT49BV080T
AT49LV080
AT49LV080T
Pin Configurations
TSOP Top View
Pin Name
A0 - A19
CE
Function
Type 1
Addresses
A19
A18
A17
A16
A15
A14
A13
A12
CE
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
2
NC
Chip Enable
Output Enable
Write Enable
Reset
3
WE
4
OE
5
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
GND
GND
I/O3
I/O2
I/O1
I/O0
A0
OE
6
7
WE
8
9
RESET
RDY/BUSY
I/O0 - I/O7
VCC
NC
10
11
12
13
14
15
16
17
18
19
20
RESET
A11
A10
A9
Ready/Busy Output
Data Inputs/Outputs
A8
A7
A6
A1
A5
A2
SOIC
A4
A3
NC
RESET
A11
A10
A9
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
2
3
A12
A13
A14
A15
A16
A17
A18
A19
NC
CBGA
Top View
4
5
A8
6
1
2
3
4
5
6
7
A7
7
A6
8
A5
9
A4
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A
B
C
D
E
F
NC
NC
A5 A8 A11 NC A12 A15 A17
A4 A7 A10 VCC A13 NC A18
A6 A9 RST CE A14 A16 A19
A3 I/O1 NC VCC I/O4 I/O7 NC
A2 A0 I/O3 GND I/O6 OE NC
A1 I/O0 I/O2 GND I/O5 RY/BY WE
A3
NC
A2
NC
A1
WE
A0
OE
I/O0
I/O1
I/O2
I/O3
GND
GND
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
Rev. 0812B–10/98
1
The device contains a user-enabled “boot block” protection
feature. Two versions of the feature are available: the
AT49BV/LV080 locates the boot block at lowest order
addresses (“bottom boot”); the AT49BVLV080T locates it at
highest order addresses (“top boot”).
on a byte-by-byte basis. The typical byte programming time
is a fast 30 µs. The end of a program cycle can be option-
ally detected by the DATA polling feature. Once the end of
a byte program cycle has been detected, a new access for
a read or program can begin. The typical number of pro-
gram and erase cycles is in excess of 10,000 cycles.
To allow for simple in-system reprogrammability, the
AT49BV/LV080(T) does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV080 is performed by eras-
ing the entire 8 megabits of memory and then programming
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
AT49BV/LV080
AT49BV/LV080T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
8
8
OE
WE
CE
DATA LATCH
DATA LATCH
OE, CE, AND WE
LOGIC
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
Y DECODER
X DECODER
Y-GATING
Y-GATING
FFFFFH
FFFFFH
ADDRESS
INPUTS
MAIN MEMORY
(1008K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
04000H
03FFFH
FC000H
FBFFFH
OPTIONAL BOOT
MAIN MEMORY
(1008K BYTES)
BLOCK (16K BYTES)
00000H
00000H
Device Operation
READ: The AT49BV/LV080(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
AT49BV/LV080(T)
2
AT49BV/LV080(T)
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the
AT49BV/LV080 boot block is 00000H to 03FFFH while the
address range of the AT49BV/LV080T boot block is
FC000H to FFFFFH.
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling, the
AT49BV/LV080 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out for the AT49BV/LV080, and a read from address
location FC002H will show if programming the boot block is
locked out for the AT49BV/LV080T. If the data on I/O0 is
low, the boot block can be programmed; if the data on I/O0
is high, the program lockout feature has been activated and
the block cannot be programmed. The software product
identification exit code should be used to return to standard
operation.
RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR - tying of several devices to the same
RDY/BUSY line.
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program
or erase operation, the operation may not be successfully
completed, and the operation will have to be repeated after
a high level is applied to the RESET pin. When a high level
is reasserted on the RESET pin, the device returns to the
read or standby mode, depending upon the state of the
control inputs. By applying a 12V + 0.5V input signal to the
RESET pin the boot block array can be reprogrammed
even if the boot block lockout feature has been enabled
(see Boot Block Programming Lockout Override section).
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 + 0.5 volts. By doing this,
protected boot block data can be altered through a chip
erase, or byte programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV/LV080(T) in the following ways: (a) VCC sense–if
VCC is below 1.8V (typical), the program function is inhib-
ited; (b) Program inhibit—holding any one of OE low, CE
high or WE high inhibits program cycles; and (c) Noise fil-
ter—pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV/LV080(T) features DATA
polling to indicate the end of a program cycle. During a pro-
3
Command Definition (in Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
5555
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
Chip Erase
2AAA
2AAA
55
55
5555
5555
80
5555
Addr
AA
DIN
2AAA
2AAA
55
5555
5555
10
Byte
Program
4
6
3
3
1
5555
5555
5555
5555
XXXX
AA
AA
AA
AA
F0
A0
Boot Block
Lockout(1)
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
90
F0
5555
AA
55
40
Product ID
Entry
Product ID
Exit(2)
Product ID
Exit(2)
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV080 and FC000H to FFFFFH for the
AT49BV/LV080T.
2. Either one of the Product ID Exit Commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
AT49BV/LV080(T)
4
AT49BV/LV080(T)
DC and AC Operating Range
AT49BV/LV080(T)-12
0°C - 70°C
AT49BV/LV080(T)-15
AT49BV/LV080(T)-20
0°C - 70°C
Com.
0°C - 70°C
-40°C - 85°C
Operating
Temperature (Case)
Ind.
-40°C - 85°C
-40°C - 85°C
VCC Power Supply
2.7V - 3.6V / 3.0V - 3.6V
2.7V - 3.6V / 3.0V - 3.6V
2.7V - 3.6V / 3.0V - 3.6V
Operating Modes
Mode
CE
OE
VIL
VIH
X(1)
X
WE
RESET
VIH
Ai
Ai
Ai
X
I/O
RDY/BUSY
VOH
Read
VIL
VIL
VIH
X
VIH
VIL
X
DOUT
DIN
Program(2)
VIH
VOL
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
RESET
VIH
High Z
VOH
VOH
VOH
VOH
VIH
X
VIH
X
VIL
VIH
X
VIH
X
X
VIH
High Z
High Z
X
X
VIL
X
Product Identification
A1 - A19 = VIL, A9 = VH,(3) A0 = VIL
A1 - A19 = VIL, A9 = VH,(3) A0 = VIH
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A19 = VIL
Notes: 1. X can be VIH or VIL.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: 23H (AT49BV/LV080), 27H (AT49BV/LV080T).
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
1
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC
ILO
VI/O = 0V to VCC
1
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
50
1
ISB2
(1)
ICC
f = 5 MHz; IOUT = 0 mA, VCC = 3.6V
25
0.6
VIL
VIH
VOL
VOH
Input High Voltage
2.0
2.4
V
Output Low Voltage
IOL = 1.6 mA, VCC = 3.0V
0.45
V
Output High Voltage
IOH = -100 µA, VCC = 3.0V
V
Note:
1. ICC in the erase mode is 50 mA.
5
AC Read Characteristics
AT49BV/LV080(T)
-15
-12
-20
Symbol
Parameter
Min
Max
120
120
50
Min
Max
150
150
70
Min
Max
200
200
100
50
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
ns
(2)
tOE
0
0
0
0
0
0
ns
(3)(4)
tDF
30
40
ns
Output Hold from OE, CE or Address, whichever
occurred first
tOH
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AT49BV/LV080(T)
6
AT49BV/LV080(T)
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
7
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
50
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
1. OE must be high only when WE and CE are both low.
AT49BV/LV080(T)
8
AT49BV/LV080(T)
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used by the address should not vary.
9
Software Product Identification Entry(1) Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA 55
TO
LOAD DATA AA
TO
OR
LOAD DATA F0
TO
ADDRESS 2AAA
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
LOAD DATA 55
TO
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ADDRESS 5555
ADDRESS 2AAA
LOAD DATA F0
TO
PAUSE 1 second(2)
ADDRESS 5555
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
EXIT PRODUCT
IDENTIFICATION
MODE(4)
2. Boot block lockout feature enabled.
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A19 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1FH. The Device Code is 23H
(AT49BV/LV080), 27H (AT49BV/LV080T).
AT49BV/LV080(T)
10
AT49BV/LV080(T)
AT49BV080(T) Ordering Information
I
Active
25
CC (mA)
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
120
150
200
120
150
200
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49BV080-12CC
AT49BV080-12RC
AT48BV080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
25
25
25
25
25
25
25
25
25
25
AT49BV080-12CI
AT49BV080-12RI
AT49BV080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080-15CC
AT49BV080-15RC
AT49BV080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080-15CI
AT49BV080-15RI
AT49BV080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080-20CC
AT49BV080-20RC
AT49BV080-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080-20CI
AT49BV080-20RI
AT49BV080-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080T-12CC
AT49BV080T-12RC
AT48BV080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080T-12CI
AT49BV080T-12RI
AT49BV080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080T-15CC
AT49BV080T-15RC
AT49BV080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080T-15CI
AT49BV080T-15RI
AT49BV080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49BV080T-20CC
AT49BV080T-20RC
AT49BV080T-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49BV080T-20CI
AT49BV080T-20RI
AT49BV080T-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
42C2
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40 Lead, Thin Small Outline Package (TSOP)
44R
40T
11
AT49LV080(T) Ordering Information
I
Active
25
CC (mA)
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
120
150
200
120
150
200
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49LV080-12CC
AT49LV080-12RC
AT48LV080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
25
25
25
25
25
25
25
25
25
25
AT49LV080-12CI
AT49LV080-12RI
AT49LV080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080-15CC
AT49LV080-15RC
AT49LV080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080-15CI
AT49LV080-15RI
AT49LV080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080-20CC
AT49LV080-20RC
AT49LV080-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080-20CI
AT49LV080-20RI
AT49LV080-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080T-12CC
AT49LV080T-12RC
AT48LV080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080T-12CI
AT49LV080T-12RI
AT49LV080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080T-15CC
AT49LV080T-15RC
AT49LV080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080T-15CI
AT49LV080T-15RI
AT49LV080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49LV080T-20CC
AT49LV080T-20RC
AT49LV080T-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49LV080T-20CI
AT49LV080T-20RI
AT49LV080T-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
42C2
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40 Lead, Thin Small Outline Package (TSOP)
44R
40T
AT49BV/LV080(T)
12
AT49BV/LV080(T)
Packaging Information
42C2, 42-Ball, Plastic Chip-Size Ball Grid Array
Package (CBGA)
44R, 44-Lead, 0.525” Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Millimeters and (Inches)*
Dimensions in Inches and (Millimeters)
8.2 (0.323)
7.8 (0.307)
14.2 (0.559)
13.8 (0.543)
0.30 (0.012)
1.40 (0.055) MAX
1.12 (0.044)
0.86 (0.034)
4.6 (0.181)
4.3 (0.169)
6.0 (0.236)
7
6
5
4
3
2
1
A
B
C
D
E
F
5.0 (0.197)
0.46 (0.018)
DIA BALL TYP
1.00 (0,039) BSC
NON-ACCUMULATIVE
*Controlling dimension: millimeters
*Controlling dimension; millimeters
40T, 40-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
*Controlling dimension: millimeters
13
AT49BV/LV080(T)
14
AT49BV/LV080(T)
15
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel U.K., Ltd.
Atmel Rousset
Zone Industrielle
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
13106 Rousset Cedex, France
TEL (33) 4 42 53 60 00
FAX (33) 4 42 53 60 01
TEL (44) 1276-686677
FAX (44) 1276-686697
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road
Tsimshatsui East
Kowloon, Hong Kong
TEL (852) 27219778
FAX (852) 27221369
Japan
Atmel Japan K.K.
Tonetsu Shinkawa Bldg., 9F
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1998.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0812B–10/98/xM
相关型号:
©2020 ICPDF网 联系我们和版权申明