AT49BV160T-11TI [ETC]
x8/x16 Flash EEPROM ; X8 / X16闪存EEPROM
| 型号： | AT49BV160T-11TI |
| 厂家： | 
ETC |
| 描述： | x8/x16 Flash EEPROM
|
| 文件： | 总24页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)
• Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
• Fast Word Program Time – 20 µs
• Fast Sector Erase Time – 200 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Byte/Word by Suspending Programming of Any Other
Byte/Word
• Low-power Operation
16-megabit
(1M x 16/2M x 8)
3-volt Only
– 25 mA Active
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program/Erase Operations
• RESET Input for Device Initialization
Flash Memory
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
AT49BV160
AT49BV160T
AT49BV161
AT49BV161T
AT49LV160
AT49LV160T
AT49LV161
AT49LV161T
Description
The AT49BV/LV16X(T) is a 3.0-volt 16-megabit Flash memory organized as
1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 39 sectors for erase operations. The device is offered in 48-lead TSOP and
48-ball CBGA packages. The device has CE and OE control signals to avoid any bus
contention. This device can be read or reprogrammed using a single 2.65V power
supply, making it ideally suited for in-system programming.
Pin Configurations
Pin Name
A0 - A19
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
RDY/BUSY
READY/BUSY Output
Write Protection and Power Supply for
Accelerated Program/Erase Operations
VPP
I/O0 - I/O14
I/O15 (A-1)
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
NC
Selects Byte or Word Mode
No Connect
Rev. 1427H–06/01
VCCQ
Output Power Supply
CBGA Top View (Ball Down)
TSOP Top View
Type 1
8
1
2
3
4
5
6
7
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
3
A
B
C
D
E
F
4
A13
A14
A15
A16
A11
A10
A8
WE
VPP
RST
A19
A17
A6
A7
A5
A4
A2
5
6
7
A18
A8
8
NC
9
AT49BV/LV160(T)
A12
A9
A3
A1
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
RESET
VPP
NC
I/O14
I/O5
I/O6
I/O13
I/O11
I/O12
I/O4
I/O2
I/O3
I/O8
I/O9
CE
A0
A19
A18
A17
A7
VCCQ I/O15
I/O0
I/O1
GND
OE
GND
I/O7
VCC I/O10
A6
A5
A4
A3
GND
CE
A2
A1
A0
TSOP Top View
CBGA Top View
Type 1
1
2
3
4
5
6
A15
A14
A13
A12
A11
A10
A9
1
48
A16
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE
GND
I/O15/A-1
I/O7
A
B
C
D
E
F
3
A3
A4
A7 RDY/BUSY WE
A9
A13
A12
A14
A15
A16
4
5
6
I/O14
I/O6
A17
A6
NC RESET A8
7
A8
8
I/O13
I/O5
A2
A18
NC
VPP
A19
I/O5
A10
A11
I/O7
A19
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O12
I/O4
AT49BV/LV161(T)
WE
A1
A5
RESET
VPP
NC
VCC
I/O11
I/O3
A0
I/O0
I/O8
I/O9
I/O1
I/O2
RDY/BUSY
A18
A17
A7
I/O10
I/O2
CE
OE
VSS
I/O10 I/O12 I/O14 BYTE
I/O9
G
H
I/O1
I/O11 VCC I/O13 I/O15
/A-1
A6
I/O8
A5
I/O0
A4
OE
I/O3
I/O4
I/O6
VSS
A3
GND
CE
A2
A1
A0
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any sector. (See “Sector
Lockdown” section.)
The VPP pin provides data protection and faster program-
ming. When the VPP input is below 0.8V, the program and
erase functions are inhibited. When VPP is at 1.65V or
above, normal program and erase operations can be per-
formed. With VPP at 5.0V or 12.0V, the program and erase
operations are accelerated.
To increase the flexibility of the device, it contains an Erase
Suspend and Program Suspend feature. This feature will
put the Erase or Program on hold for any amount of time
and let the user read data from or program data to any of
the remaining sectors within the memory. The end of a pro-
gram or an erase cycle is detected by the Ready/Busy pin,
Data Polling or by the toggle bit.
A six-byte command (Enter Single Pulse Program Mode)
sequence to remove the requirement of entering the three-
byte program sequence is offered to further improve pro-
gramming time. After entering the six-byte code, only single
pulses on the write control lines are required for writing into
the device. This mode (Single Pulse Byte/Word Program)
AT49BV/LV160(T)/161(T)
2
AT49BV/LV160(T)/161(T)
is exited by powering down the device, or by pulsing the
RESET pin low for a minimum of 50 ns and then bringing it
back to VCC. Erase, Erase Suspend/Resume, and Program
Suspend/Resume commands will not work while in this
mode; if entered they will result in data being programmed
into the device. It is not recommended that the six-byte
code reside in the software of the final product but only
exist in external programming code.
AT49BV/LV161(T) configuration, the BYTE pin controls
whether the device data I/O pins operate in the byte or
word configuration. If the BYTE pin is set at logic “1”, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated, and the I/O15 pin is used as an input for the
LSB (A-1) address function.
When using the AT49BV/LV160(T) pinout configuration,
the device always operates in the word mode. In the
Block Diagram
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
INPUT
A0 - A19
BUFFER
STATUS
CE
REGISTER
WE
COMMAND
REGISTER
OE
RESET
BYTE
ADDRESS
LATCH
DATA
RDY/BUSY
VPP
COMPARATOR
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
Y-DECODER
X-DECODER
Y-GATING
VCC
GND
MAIN
MEMORY
Device Operation
READ: The AT49BV/LV16X(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins are asserted on the outputs. The outputs are
put in the high-impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
sequences are entered into the device. The command
sequences are shown in the “Command Definition in Hex”
table on page 10 (I/O8 - I/O15 are don’t care inputs for the
command codes). The command sequences are written by
applying a low pulse on the WE or CE input with CE or WE
low (respectively) and OE high. The address is latched on
the falling edge of CE or WE, whichever occurs last. The
data is latched by the first rising edge of CE or WE. Stan-
dard microprocessor write timings are used. The address
locations used in the command sequences are not affected
by entering the command sequences.
COMMAND SEQUENCES: When the device is first pow-
ered on, it will be reset to the read or standby mode,
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
3
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high-impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the read or standby mode, depending upon the
state of the control inputs.
VPP PIN: The circuitry of the AT49BV/LV16X(T) is
designed so that the device can be programmed or erased
from the VCC power supply or from the VPP input pin. When
VPP is greater than 1.65V and less than or equal to the VCC
pin, the device selects the VCC supply for programming and
erase operations. When the VPP pin is greater than the
VCC supply, the device will select the VPP input as the
power supply for programming and erase operations. The
device will allow for some variations between the VPP input
and the VCC power supply in its selection of VCC or VPP for
program or erase operations. If the VPP pin is within 0.3V
of VCC for 2.65V < VCC < 3.6V, then the program or erase
operations will use VCC and disregard the VPP input signal.
When the VPP signal is used for program and erase opera-
tions, the VPP must be in the 5V 0.5V or 12V 0.5V range
to ensure proper operation. The Vpp pin cannot be left
floating.
ERASURE: Before a byte/word can be reprogrammed, it
must be erased. The erased state of memory bits is a logi-
cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time
by using the six-byte chip erase software code. After the
chip erase has been initiated, the device will internally time
the erase operation so that no external clocks are required.
PROGRAM/ERASE STATUS: The device provides sev-
eral bits to determine the status of a program or erase
operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit
Table” on page 9 and the following four sections describe
the function of these bits. To provide greater flexibility for
system designers, the AT49BV/LV16X(T) contains a pro-
grammable configuration register. The configuration
register allows the user to specify the status bit operation.
The configuration register can be set to one of two different
values, “00” or “01”. If the configuration register is set to
“00”, the part will automatically return to the read mode
after a successful program or erase operation. If the config-
uration register is set to a “01”, a Product ID Exit command
must be given after a successful program or erase opera-
tion before the part will return to the read mode. It is
important to note that whether the configuration register is
set to a “00” or to a “01”, any unsuccessful program or
erase operation requires using the Product ID Exit com-
mand to return the device to read mode. The default value
(after power-up) for the configuration register is “00”. Using
the four-bus cycle Set Configuration Register command as
shown in the “Command Definition in Hex” table on
page 10, the value of the configuration register can be
changed. Voltages applied to the RESET pin will not alter
the value of the configuration register. The value of the
configuration register will affect the operation of the I/O7
status bit as described below.
The maximum time to erase the chip is tEC
.
If the sector lockdown has been enabled, the chip erase
will not erase the data in the sector that has been locked
out; it will erase only the unprotected sectors. After the chip
erase, the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into 39 sectors (SA0 - SA38) that can
be individually erased. The Sector Erase command is a six-
bus cycle operation. The sector address is latched on the
falling WE edge of the sixth cycle while the 30H data input
command is latched on the rising edge of WE. The sector
erase starts after the rising edge of WE of the sixth cycle.
The erase operation is internally controlled; it will automati-
cally time to completion. The maximum time to erase a
sector is tSEC. When the sector programming lockdown fea-
ture is not enabled, the sector will erase (from the same
Sector Erase command). An attempt to erase a sector that
has been protected will result in the operation terminating
in 2 µs.
BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or on a word-by-word basis. Programming is accomplished
via the internal device command register and is a four-bus
cycle operation. The device will automatically generate the
required internal program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The Data Polling feature or the
Toggle Bit feature may be used to indicate the end of a pro-
gram cycle. If the erase/program status bit is a “1”, the
device was not able to verify that the erase or program
operation was performed successfully.
DATA POLLING: The AT49BV/LV16X(T) features Data
Polling to indicate the end of a program cycle. If the status
configuration register is set to a “00”, during a program
cycle an attempted read of the last byte/word loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. During a chip
or sector erase operation, an attempt to read the device will
give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. Data
AT49BV/LV160(T)/161(T)
4
AT49BV/LV160(T)/161(T)
Polling may begin at any time during the program cycle.
Please see “Status Bit Table” on page 9 for more details.
tion successfully, the VPP status bit will output a “0”. Please
see “Status Bit Table” on page 9 for more details.
If the status bit configuration register is set to a “01”, the
I/O7 status bit will be low while the device is actively pro-
gramming or erasing data. I/O7 will go high when the
device has completed a program or erase operation. Once
I/O7 has gone high, status information on the other pins
can be checked.
SECTOR LOCKDOWN: Each sector has a programming
lockdown feature. This feature prevents programming of
data in the designated sectors once the feature has been
enabled. These sectors can contain secure code that is
used to bring up the system. Enabling the lockdown feature
will allow the boot code to stay in the device while data in
the rest of the device is updated. This feature does not
have to be activated; any sector’s usage as a write-
protected region is optional to the user.
The Data Polling status bit must be used in conjunction
with the erase/program and VPP status bit as shown in the
algorithm in Figures 1 and 2 on page 7.
At power-up or reset, all sectors are unlocked. To activate
the lockdown for a specific sector, the six-bus cycle Sector
Lockdown command must be issued. Once a sector has
been locked down, the contents of the sector is read-only
and cannot be erased or programmed.
TOGGLE BIT: In addition to Data Polling, the
AT49BV/LV16X(T) provides another method for determin-
ing the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the memory will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop
toggling and valid data will be read. Examining the toggle
bit may begin at any time during a program cycle. Please
see “Status Bit Table” on page 9 for more details.
SECTOR LOCKDOWN DETECTION: A software method
is available to determine if programming of a sector is
locked down. When the device is in the software product
identification mode (see “Software Product Identification
Entry/Exit” sections on page 20), a read from address loca-
tion 00002H within a sector will show if programming the
sector is locked down. If the data on I/O0 is low, the sector
can be programmed; if the data on I/O0 is high, the pro-
gram lockdown feature has been enabled and the sector
cannot be programmed. The software product identification
exit code should be used to return to standard operation.
The toggle bit status bit should be used in conjunction with
the erase/program and VPP status bit as shown in the algo-
rithm in Figures 3 and 4 on page 8.
ERASE/PROGRAM STATUS BIT: The device offers a sta-
tus bit on I/O5, which indicates whether the program or
erase operation has exceeded a specified internal pulse
count limit. If the status bit is a “1”, the device is unable to
verify that an erase or a byte/word program operation has
been successfully performed. The device may also output
a “1” on I/O5 if the system tries to program a “1” to a loca-
tion that was previously programmed to a “0”. Only an
erase operation can change a “0” back to a “1”. If a pro-
gram (Sector Erase) command is issued to a protected
sector, the protected sector will not be programmed
(erased). The device will go to a status read mode and the
I/O5 status bit will be set high, indicating the program
(erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system
must write the Product ID Exit command to return to the
read mode. The erase/program status bit is a “0” while the
erase or program operation is still in progress. Please see
“Status Bit Table” on page 9 for more details.
SECTOR LOCKDOWN OVERRIDE: The only way to
unlock a sector that is locked down is through reset or
power-up cycles. After power-up or reset, the content of a
sector that is locked down can be erased and
reprogrammed.
ERASE SUSPEND/ERASE RESUME: The Erase Sus-
pend command allows the system to interrupt a sector
erase or chip erase operation and then program or read
data from a different sector within the memory. After the
Erase Suspend command is given, the device requires a
maximum time of 15 µs to suspend the erase operation.
After the erase operation has been suspended, the system
can then read data or program data to any other sector
within the device. An address is not required during the
Erase Suspend command. During a sector erase suspend,
another sector cannot be erased. To resume the sector
erase operation, the system must write the Erase Resume
command. The Erase Resume command is a one-bus
cycle command. The device also supports an erase sus-
pend during a complete chip erase. While the chip erase is
suspended, the user can read from any sector within the
memory that is protected. The command sequence for a
chip erase suspend and a sector erase suspend are the
same.
VPP STATUS BIT: The AT49BV/LV16X(T) provides a sta-
tus bit on I/O3, which provides information regarding the
voltage level of the VPP pin. During a program or erase
operation, if the voltage on the VPP pin is not high enough
to perform the desired operation successfully, the I/O3 sta-
tus bit will be a “1”. Once the VPP status bit has been set to
a “1”, the system must write the Product ID Exit command
to return to the read mode. On the other hand, if the voltage
level is high enough to perform a program or erase opera-
5
PROGRAM SUSPEND/PROGRAM RESUME: The Pro-
gram Suspend command allows the system to interrupt a
programming operation and then read data from a different
byte/word within the memory. After the Program Suspend
command is given, the device requires a maximum of 15 µs
to suspend the programming operation. After the program-
ming operation has been suspended, the system can then
read data from any other byte/word within the device. An
address is not required during the program suspend opera-
tion. To resume the programming operation, the system
must write the Program Resume command. The program
suspend and resume are one-bus cycle commands. The
command sequence for the erase suspend and program
suspend are the same, and the command sequence for the
erase resume and program resume are the same.
80H. If data bit D1 is zero, block B is locked. If data bit D1 is
one, block B can be reprogrammed. Please see the “Pro-
tection Register Addressing Table” on page 11 for the
address locations in the protection register. To read the
protection register, the Product ID Entry command is given
followed by a normal read operation from an address within
the protection register. After determining whether block B is
protected or not, or reading the protection register, the
Product ID Exit command must be given prior to performing
any other operation.
RDY/BUSY: An open-drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open-drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line. Please see “Status Bit Table” on page 9
for more details.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external
programmer to identify the correct programming algorithm
for the Atmel product.
HARDWARE DATA PROTECTION: The Hardware Data
Protection feature protects against inadvertent programs to
the AT49BV/LV16X(T) in the following ways: (a) VCC
sense: if VCC is below 1.8V (typical), the program function
is inhibited. (b) VCC power-on delay: once VCC has reached
the VCC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle. (e) Program inhibit: VPP is less than VILPP. (f) VPP
power-on delay: once VPP has reached 1.65V, program and
erase operations can occur after 100 ns.
For details, see “Operating Modes” on page 14 (for hard-
ware operation) or “Software Product Identification
Entry/Exit” on page 20. The manufacturer and device
codes are the same for both modes.
128-BIT
PROTECTION
REGISTER:
The
AT49BV/LV16X(T) contains a 128-bit register that can be
used for security purposes in system design. The protec-
tion register is divided into two 64-bit blocks. The two
blocks are designated as block A and block B. The data in
block A is non-changeable and is programmed at the fac-
tory with a unique number. The data in block B is
programmed by the user and can be locked out such that
data in the block cannot be reprogrammed. To program
block B in the protection register, the four-bus cycle Pro-
gram Protection Register command must be used as
shown in the “Command Definition in Hex” table on
page 10. To lock out block B, the four-bus cycle Lock Pro-
tection Register command must be used as shown in the
“Command Definition in Hex” table on page 10. Data bit D1
must be zero during the fourth bus cycle. All other data bits
during the fourth bus cycle are don’t cares. To determine
whether block B is locked out, the Product ID Entry com-
mand is given followed by a read operation from address
INPUT LEVELS: While operating with a 2.65V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
OUTPUT LEVELS: For the AT49BV/LV160(T), output high
levels (VOH) are equal to VCCQ - 0.2V (not VCC). For 2.65V -
3.6V output levels, VCCQ must be tied to VCC. For 1.8V -
2.2V output levels, VCCQ must be regulated to 2.0V 10%,
while VCC must be regulated to 2.65V - 3.0V (for minimum
power).
AT49BV/LV160(T)/161(T)
6
AT49BV/LV160(T)/161(T)
Figure 1. Data Polling Algorithm
Figure 2. Data Polling Algorithm
(Configuration Register = 00)
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Addr = VA
NO
I/O7 = 1?
YES
I/O7 = Data?
NO
YES
NO
I/O3, I/O5 = 1?
NO
I/O3, I/O5 = 1?
YES
YES
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Program/Erase
Operation Not
Successful, Write
Product ID
Read I/O7 - I/O0
Addr = VA
Exit Command
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
YES
I/O7 = Data?
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful,
Device in
Exit Command
Read Mode
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
7
Figure 3. Toggle Bit Algorithm
Figure 4. Toggle Bit Algorithm
(Configuration Register = 00)
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
NO
NO
Toggle Bit =
Toggle?
Toggle Bit =
Toggle?
YES
YES
NO
NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Twice
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
Toggle Bit =
Toggle?
NO
NO
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful
Exit Command
Exit Command
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
AT49BV/LV160(T)/161(T)
8
AT49BV/LV160(T)/161(T)
Status Bit Table
Status Bit
I/O7
00
I/O7
01
0
I/O6
I/O5(1)
I/O3(2)
I/O2
00/01
1
RDY/BUSY
Configuration Register:
Programming
00/01
00/01
00/01
00/01
I/O7
0
TOGGLE
TOGGLE
0
0
0
0
0
0
Erasing
0
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
DATA
0
1
0
DATA
0
0
DATA
0
TOGGLE
DATA
1
1
0
Erase Suspended & Read
Non-erasing Sector
DATA
I/O7
DATA
Erase Suspended &
Program Non-erasing Sector
TOGGLE
TOGGLE
Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.
9
Command Definition in Hex(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
555
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
6
4
Chip Erase
AAA(2)
AAA
55
55
55
555
555
555
80
80
A0
555
555
AA
AA
DIN
AAA
AAA
55
55
555
SA(3)(4)
10
30
Sector Erase
Byte/Word Program
555
AA
555
AA
AAA
Addr
Enter Single Pulse
Program Mode
6
555
AA
AAA
55
555
80
555
AA
AAA
AAA
55
55
555
A0
60
Single Pulse
Byte/Word Program
1
6
1
Addr
555
DIN
AA
B0
Sector Lockdown
AAA
55
555
80
555
AA
SA(3)(4)
Erase/Program
Suspend
XXX
Erase/Program
Resume
1
XXX
30
Product ID Entry
Product ID Exit(5)
Product ID Exit(5)
3
3
1
555
555
AA
AA
F0
AAA
AAA
55
55
555
555
90
F0
XXX
Program Protection
Register
4
4
4
4
555
555
555
555
AA
AA
AA
AA
AAA
AAA
AAA
AAA
55
55
55
55
555
555
555
555
C0
C0
90
Addr
080
80
DIN
X0
Lock Protection
Register - Block B
Status of Block B
Protection
(6)
DOUT
Set Configuration
Register
D0
XXX
00/01(7)
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’t Care.
The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’t Care
in the word mode. Address A19 through A11 and A-1 are Don’t Care in the byte mode.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 12 and
13 for details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and VPP
with Respect to Ground...................................-0.6V to +13.0V
AT49BV/LV160(T)/161(T)
10
AT49BV/LV160(T)/161(T)
Protection Register Addressing Table
Word
Use
Factory
Factory
Factory
Factory
User
Block
A7
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
1
0
1
2
3
4
5
6
7
A
A
A
A
B
B
B
B
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
User
1
0
0
0
0
1
1
0
User
1
0
0
0
0
1
1
1
User
1
0
0
0
1
0
0
0
Note:
1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
11
AT49BV/LV 160/161 – Sector Address Table
x8
x16
Sector
SA0
Size (Bytes/Words)
8K/4K
Address Range (A19 - A-1)
000000 - 001FFF
002000 - 003FFF
004000 - 005FFF
006000 - 007FFF
008000 - 009FFF
00A000 - 00BFFF
00C000 - 00DFFF
00E000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0FFFFF
100000 - 10FFFF
110000 - 11FFFF
120000 - 12FFFF
130000 - 13FFFF
140000 - 14FFFF
150000 - 15FFFF
160000 - 16FFFF
170000 - 17FFFF
180000 - 18FFFF
190000 - 19FFFF
1A0000 - 1AFFFF
1B0000 - 1BFFFF
1C0000 - 1CFFFF
1D0000 - 1DFFFF
1E0000 - 1EFFFF
1F0000 - 1FFFFF
Address Range (A19 - A0)
00000 - 00FFF
01000 - 01FFF
02000 - 02FFF
03000 - 03FFF
04000 - 04FFF
05000 - 05FFF
06000 - 06FFF
07000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - FFFFF
SA1
8K/4K
SA2
8K/4K
SA3
8K/4K
SA4
8K/4K
SA5
8K/4K
SA6
8K/4K
SA7
8K/4K
SA8
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
AT49BV/LV160(T)/161(T)
12
AT49BV/LV160(T)/161(T)
AT49BV/LV 160T/161T – Sector Address Table
x8
x16
Sector
SA0
Size (Bytes/Words)
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
8K/4K
Address Range (A19 - A-1)
Address Range (A19 - A0)
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - F8FFF
F9000 - F9FFF
FA000 - FAFFF
FB000 - FBFFF
FC000 - FCFFF
FD000 - FDFFF
FE000 - FEFFF
FF000 - FFFFF
000000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0FFFFF
100000 - 10FFFF
110000 - 11FFFF
120000 - 12FFFF
130000 - 13FFFF
140000 - 14FFFF
150000 - 15FFFF
160000 - 16FFFF
170000 - 17FFFF
180000 - 18FFFF
190000 - 19FFFF
1A0000 - 1AFFFF
1B0000 - 1BFFFF
1C0000 - 1CFFFF
1D0000 - 1DFFFF
1E0000 - 1EFFFF
1F0000 - 1F1FFF
1F2000 - 1F3FFF
1F4000 - 1F5FFF
1F6000 - 1F7FFF
1F8000 - 1F9FFF
1FA000 - 1FBFFF
1FC000 - 1FDFFF
1FE000 - 1FFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
13
DC and AC Operating Range
AT49BV/LV16X(T)-70
-40°C - 85°C
AT49BV/LV16X(T)-90
-40°C - 85°C
AT49BV/LV16X(T)-11
-40°C - 85°C
Operating Temperature (Case)
CC Power Supply
Ind.
V
2.65V to 3.3V/3.0V to 3.6V
2.65V to 3.3V/3.0V to 3.6V
2.65V to 3.3V/3.0V to 3.6V
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
WE
VIH
VIL
X
RESET
VIH
VPP
X
Ai
Ai
Ai
X
I/O
Read
VIL
VIH
X(1)
X
DOUT
DIN
(6)
Program/Erase(2)
Standby/Program Inhibit
VIH
VIHPP
X
VIH
High-Z
VIH
X
VIH
X
Program Inhibit
X
VIL
X
VIH
X
(7)
X
X
VIH
VILPP
X
Output Disable
Reset
X
VIH
X
X
VIH
High-Z
High-Z
X
X
VIL
X
X
Product Identification
A1 - A19 = VIL, A9 = VH(3), A0 = VIL
A1 - A19 = VIL, A9 = VH(3), A0 = VIH
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A19 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms on page 19.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV/LV16X; 00C0H (x16)-AT49BV/LV16X;
C2H (x8)-AT49BV/LV16XT; 00C2H (x16)-AT49BV/LV16XT.
5. See details under “Software Product Identification Entry/Exit” on page 20.
6. VIHPP (min) = 1.65V; VIHPP (max) = 3.6V. For faster erase/program operations, VPP can be set to 5.0V 0.5V or 12V 0.5V.
7. VILPP (max) = 0.8V.
AT49BV/LV160(T)/161(T)
14
AT49BV/LV160(T)/161(T)
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
10
1
Units
µA
µA
µA
mA
µA
mA
mA
µA
µA
mA
mA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Standby Current TTL
VCC Active Read Current
VCC Programming Current (VPP = VCC
VI/O = 0V to VCC
ISB1
ISB2
ISB3
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
CE = 2.0V to VCC, VCC = 2.85V
f = 5 MHz; IOUT = 0 mA, 3.3V≤ VCC
10
30
30
-10
50
30
25
30
40
0.6
(1)(2)
ICC
ICC1
)
VPP = 0V, VCC = 3.0V
IPP1
VPP Input Load Current
V
PP = VCC = 3.0V
ICC2
IPP2
ICC3
IPP3
VIL
VCC Programming Current (VPP = 5.0V 0.5V)
VPP Programming Current (VPP = 5.0V 0.5V)
VCC Programming Current (VPP = 12.0V 0.5V)
VPP Programming Current (VPP = 12.0V 0.5V)
Input Low Voltage
VIH
Input High Voltage
2.0
V
VOL1
VOL2
Output Low Voltage
IOL = 2.1 mA
IOL = 1.0 mA
IOH = -400 µA
0.45
0.20
V
Output Low Voltage
V
V
CCQ < 2.6V
VCCQ - 0.2 [AT49BV/LV160(T)]
2.4 [AT49BV/LV160(T)]
V
V
V
VOH1
Output High Voltage
Output High Voltage
I
I
OH = -400 µA
OH = -400 µA
VCCQ ≥ 2.6V
2.4 [AT49BV/LV161(T)]
IOH = -100 µA
VCCQ < 2.6V
VCCQ - 0.1 [AT49BV/LV160(T)]
2.5 [AT49BV/LV160(T)]
V
V
V
VOH2
I
I
OH = -100 µA
OH = -100 µA
VCCQ ≥ 2.6V
2.5 [AT49BV/LV161(T)]
Notes: 1. In the erase mode, ICC is 50 mA.
2. For 3.3V < VCC < 3.6V, ICC (max) = 35 mA
15
.
AC Read Characteristics
AT49BV/LV16X(T)-70
AT49BV/LV16X(T)-90
AT49BV/LV16X(T)-11
Symbol
tRC
Parameter
Min
Max
70
Min
Max
90
Min
Max
110
110
110
45
Units
ns
Read Cycle Time
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
70
90
ns
(1)
tCE
70
90
ns
(2)
tOE
0
0
35
0
0
40
0
0
ns
(3)(4)
tDF
25
25
30
ns
Output Hold from OE, CE or Address, whichever
occurred first
tOH
tRO
0
0
0
ns
ns
RESET to Output Delay
600
600
600
AC Read Waveforms(1)(2)(3)(4)
tRC
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
16
1. This parameter is characterized and is not 100% tested
AT49BV/LV160(T)/161(T)
AT49BV/LV160(T)/161(T)
.
AC Byte/Word Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Setup Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
ns
0
ns
50
40
10
40
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
17
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
20
Max
200
100
Units
µs
tBP
Byte/Word Programming Time (VIHPP < VPP < 4.5V)
Byte/Word Programming Time (VPP > 4.5V)
Address Setup Time
tBPVPP
tAS
10
µs
0
50
40
10
50
40
90
0
ns
tAH
Address Hold Time
ns
tDS
Data Setup Time
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
ns
tWPH
tWC
Write Pulse Width High
ns
Write Cycle Time
ns
tSR/W
tRP
Latency between Read and Write Operations
Reset Pulse Width
ns
500
200
ns
tRH
Reset High Time before Read
Chip Erase Cycle Time (VPP < 4.5V)
Chip Erase Cycle Time (VPP > 4.5V)
Sector Erase Cycle Time (VPP < 4.5V)
Sector Erase Cycle Time (VPP > 4.5V)
Erase or Program Suspend Time
ns
tEC
10
5
seconds
seconds
ms
tECVPP
tSEC
tSECVPP
tEPS
200
100
400
150
15
ms
µs
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
WP
BP
WPH
WE
t
t
t
DH
AS
AH
555
t
AAA
555
ADDRESS
555
A0 -A19
DATA
WC
t
DS
INPUT
DATA
AA
55
A0
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
A0-A19
DATA
t
t
t
DH
AS
AH
555
t
AAA
555
555
AAA
Note
2
WC
t
t
EC
DS
AA
WORD
55
WORD
80
WORD
AA
WORD
55
WORD
Note 3
0
1
2
3
4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
AT49BV/LV160(T)/161(T)
18
AT49BV/LV160(T)/161(T)
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 16.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 16.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
19
Software Product Identification Entry(1) Sector Lockdown Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 555
ADDRESS 555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS AAA
ADDRESS AAA
LOAD DATA 80
TO
LOAD DATA 90
TO
ADDRESS 555
ADDRESS 555
LOAD DATA AA
TO
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
ADDRESS 555
LOAD DATA 55
TO
Software Product Identification Exit(1)(6)
ADDRESS AAA
OR
LOAD DATA AA
LOAD DATA F0
TO
TO
ADDRESS 555
ANY ADDRESS
LOAD DATA 60
TO
SECTOR ADDRESS
EXIT PRODUCT
IDENTIFICATION
LOAD DATA 55
TO
(4)
MODE
ADDRESS AAA
(2)
PAUSE 200 µs
LOAD DATA F0
TO
ADDRESS 555
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), A-1, and A11 - A19
(Don’t Care).
EXIT PRODUCT
IDENTIFICATION
2. Sector Lockdown feature enabled.
(4)
MODE
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), A-1, and A11 - A19
(Don’t Care).
2. A1 - A19 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH
.
Additional Device Code is read for address 0003H
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH(x8); 001FH(x16)
Device Code: C0H (x8) - AT49BV/LV16X;
00C0H (x16) - AT49BV/LV16X;
C2H (x8) - AT49BV/LV16XT;
00C2H (x16) - AT49BV/LV16XT.
Additional Device Code: 08H (x8) - AT49BV/LV16X(T)
0008H (x16) - AT49BV/LV16X(T)
6. Either one of the Product ID Exit commands can be used.
AT49BV/LV160(T)/161(T)
20
AT49BV/LV160(T)/161(T)
AT49BV160(T)/161(T) Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
25
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
AT49BV160-70CI
AT49BV160-70TI
45C1
48T
Industrial
(-40° to 85°C)
90
25
25
25
25
25
25
25
25
25
25
25
AT49BV160-90CI
AT49BV160-90TI
45C1
48T
Industrial
(-40° to 85°C)
110
70
AT49BV160-11CI
AT49BV160-11TI
45C1
48T
Industrial
(-40° to 85°C)
AT49BV160T-70CI
AT49BV160T-70TI
45C1
48T
Industrial
(-40° to 85°C)
90
AT49BV160T-90CI
AT49BV160T-90TI
45C1
48T
Industrial
(-40° to 85°C)
110
70
AT49BV160T-11CI
AT49BV160T-11TI
45C1
48T
Industrial
(-40° to 85°C)
AT49BV161-70CI
AT49BV161-70TI
48C5
48T
Industrial
(-40° to 85°C)
90
AT49BV161-90CI
AT49BV161-90TI
48C5
48T
Industrial
(-40° to 85°C)
110
70
AT49BV161-11CI
AT49BV161-11TI
48C5
48T
Industrial
(-40° to 85°C)
AT49BV161T-70CI
AT49BV161T-70TI
48C5
48T
Industrial
(-40° to 85°C)
90
AT49BV161T-90CI
AT49BV161T-90TI
48C5
48T
Industrial
(-40° to 85°C)
110
AT49BV161T-11CI
AT49BV161T-11TI
48C5
48T
Industrial
(0° to 70°C)
Package Type
48C5
45C1
48T
48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
45-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
48-lead, Plastic Thin Small Outline Package (TSOP)
21
AT49LV160(T)/161(T) Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
25
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
AT49LV160-70CI
AT49LV160-70TI
45C1
48T
Industrial
(-40° to 85°C)
90
25
25
25
25
25
25
25
25
25
25
25
AT49LV160-90CI
AT49LV160-90TI
45C1
48T
Industrial
(-40° to 85°C)
110
70
AT49LV160-11CI
AT49LV160-11TI
45C1
48T
Industrial
(-40° to 85°C)
AT49LV160T-70CI
AT49LV160T-70TI
45C1
48T
Industrial
(-40° to 85°C)
90
AT49LV160T-90CI
AT49LV160T-90TI
45C1
48T
Industrial
(-40° to 85°C)
110
70
AT49LV160T-11CI
AT49LV160T-11TI
45C1
48T
Industrial
(-40° to 85°C)
AT49LV161-70CI
AT49LV161-70TI
48C5
48T
Industrial
(-40° to 85°C)
90
AT49LV161-90CI
AT49LV161-90TI
48C5
48T
Industrial
(-40° to 85°C)
110
70
AT49LV161-11CI
AT49LV161-11TI
48C5
48T
Industrial
(-40° to 85°C)
AT49LV161T-70CI
AT49LV161T-70TI
48C5
48T
Industrial
(-40° to 85°C)
90
AT49LV161T-90CI
AT49LV161T-90TI
48C5
48T
Industrial
(-40° to 85°C)
110
AT49LV161T-11CI
AT49LV161T-11TI
48C5
48T
Industrial
(0° to 70°C)
Package Type
48C5
45C1
48T
48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
45-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
48-lead, Plastic Thin Small Outline Package (TSOP)
AT49BV/LV160(T)/161(T)
22
Packaging Information
48C5, 48-ball, Plastic Chip-size Ball Grid Array
Package (CBGA)
45C1, 45-ball, Plastic Chip-size Ball Grid Array
Package (CBGA)
Dimensions in Millimeters and (Inches)*
Dimensions in Millimeter and (Inches)*
6.1 (0.240)
5.9 (0.232)
6.6 (0.260)
6.4 (0.252)
7.6 (0.299)
7.4 (0.291)
8.1 (0.319)
7.9 (0.311)
0.30 (0.012)
1.20 (0.047)
0.30 (0.012)
1.20 (0.047)
1.00 (0.039)
5.25 (0.206)
1.00 (0.039)
8
7
6
5
4
3
2
1
4.0 (0.157)
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
3.75 (0.147)
5.6 (0.220)
G
H
0.30 (0.014)
DIA BALL TYP
0.75 (0.029) BSC
NON-ACCUMULATIVE
0.80 (0.031) BSC
0.40 (0.016)
NON-ACCUMULATIVE
DIA BALL TYP
*Controlling dimension: millimeters
*Controlling dimension: millimeters
48T, 48-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 DD
*Controlling dimension: millimeters
AT49BV/LV160(T)/161(T)
23
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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