AT49F512-50PI [ETC]
x8 Flash EEPROM ; X8闪存EEPROM\n
| 型号： | AT49F512-50PI |
| 厂家： | 
ETC |
| 描述： | x8 Flash EEPROM
|
| 文件： | 总12页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time - 50 ns
• Internal Program Control and Timer
• 8K Bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte-by-Byte Programming - 10 µs/Byte
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 30 mA Active Current
– 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
512K (64K x 8)
5-volt Only
Flash Memory
Description
The AT49F512 is a 5-volt-only in-system programmable and erasable Flash Memory.
Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 50
ns with a power dissipation of just 165 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA.
AT49F512
To allow for simple in-system reprogrammability, the AT49F512 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the
entire 512K of memory and then programming on a byte by byte basis. The typical
byte programming time is a fast 10 µs. The end of a program cycle can be optionally
(continued)
Pin Configurations
DIP Top View
Pin Name
A0 - A15
CE
Function
NC
NC
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A6
OE
A5
26 A9
A4
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
512K (64K x 8)
5-volt Only
CMOS Flash
Memory
A3
WE
A2 10
A1 11
I/O0 - I/O7
NC
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
PLCC Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
5
6
7
8
A2 10
A1 11
A0 12
I/O0 13
9
10
11
12
13
14
15
16
Rev. 1027D–04/99
A6
A1
A5
A2
A4
A3
detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
FFFFH
2000H
1FFFH
0000H
Device Operation
READ: The AT49F512 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
ERASURE: Before a byte can be reprogrammed, the 64K
bytes memory array (or 56K bytes if the boot block featured
is used) must be erased. The erased state of the memory
bits is a logical “1”. The entire device can be erased at one
time by using a 6-byte software code. The chip erase code
consists of 6-byte load commands to specific address loca-
tions with a specific data pattern (please refer to the Chip
Erase Cycle Waveforms).
After the chip erase has been initiated, the device will inter-
nally time the erase operation so that no external clocks
are required. The maximum time needed to erase the
whole chip is tEC. If the boot block lockout feature has been
enabled, the data in the boot sector will not be erased.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
AT49F512
2
AT49F512
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49F512
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F512 in
the following ways: (a) VCC sense: if VCC is below 3.8V (typ-
ical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Noise filter: Pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: The AT49F512 features DATA polling to
indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
4
Addr
5555
5555
Chip Erase
Byte Program
2AAA
2AAA
55
55
5555
5555
80
A0
5555
Addr
AA
DIN
2AAA
2AAA
55
5555
5555
10
AA
Boot Block
Lockout(1)
6
3
3
1
5555
5555
5555
XXXX
AA
AA
AA
F0
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
90
F0
5555
AA
55
40
Product ID
Entry
Product ID
Exit(2)
Product ID
Exit(2)
Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
3
DC and AC Operating Range
AT49F512-50
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT49F512-70
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT49F512-90
0°C - 70°C
-40°C - 85°C
5V ± 10%
Com.
Operating
Temperature (Case)
Ind.
V
CC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High Z
VIH
X
X
VIL
VIH
X
X
High Z
(3)
(3)
A1 - A15 = VIL, A9 = VH, A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
A1 - A15 = VIL, A9 = VH, A0 = VIH
A0 = VIL, A1 - A15 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A15 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 03H
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
10
Com.
Ind.
100
300
3
ISB1
ISB2
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
Com.
Ind.
30
(1)
ICC
f = 5 MHz; IOUT = 0 mA
40
VIL
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
Note:
1. In the erase mode, ICC is 90 mA.
AT49F512
4
AT49F512
AC Read Characteristics
AT49F512-50
AT49F512-70
AT49F512-90
Symbol
Parameter
Min
Max
50
Min
Max
70
Min
Max
90
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
50
70
90
ns
(2)
tOE
30
35
0
0
40
ns
(3)(4)
tDF
0
0
25
0
0
25
25
ns
Output Hold from OE, CE or
Address, whichever occurred first
tOH
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE, after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T= 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Word Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
50
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
90
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
AT49F512
6
AT49F512
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
50
tAS
0
ns
tAH
50
50
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
90
90
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
WP
BP
WPH
WE
t
t
t
AS
AH
DH
5555
5555
2AAA
ADDRESS
A0-A15
DATA
t
DS
INPUT
DATA
55
A0
AA
Chip Erase Cycle Waveforms
OE
CE
t
t
WP
WPH
WE
t
t
t
AS
DH
AH
5555
5555
5555
5555
2AAA
2AAA
A0-A15
DATA
t
t
EC
DS
55
BYTE 1
80
BYTE 2
55
BYTE 4
10
BYTE 5
AA
BYTE 0
AA
BYTE 3
Note:
OE must be high only when WE and CE are both low.
7
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
10
ns
OE to Output Delay (2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
t
OEH
OE
tDH
tWR
tOE
HIGH Z
An
I/O7
A0-A15
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s)
2. Begining and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49F512
8
AT49F512
Software Product Identification Entry(1) Boot Block
Lockout Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identifcation Exit(1)
LOAD DATA 55
TO
LOAD DATA AA
TO
LOAD DATA F0
TO
OR
ADDRESS 2AAA
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
LOAD DATA 55
TO
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ADDRESS 5555
ADDRESS 2AAA
LOAD DATA F0
TO
PAUSE 1 second(2)
ADDRESS 5555
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
EXIT PRODUCT
IDENTIFICATION
MODE(4)
2. Boot block lockout feature enabled.
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH
.
3. The device does not remain in identification mode if pow-
ered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 03H
9
Ordering Information(1)
tACC
(ns)
ICC (mA)
Ordering Code
Package
Operation Range
Active
Standby
50
70
90
30
0.1
0.3
0.1
0.3
0.1
0.3
AT49F512-50JC
AT49F512-50PC
AT49F512-50TC
AT49F512-50VC
32J
Commercial
32P6
32T
32V
(0° to 70°C)
40
30
40
30
40
AT49F512-50JI
AT49F512-50PI
AT49F512-50TI
AT49F512-50VI
32J
Industrial
32P6
32T
32V
(-40° to 85°C)
AT49F512-70JC
AT49F512-70PC
AT49F512-70TC
AT49F512-70VC
32J
Commercial
32P6
32T
32V
(0° to 70°C)
AT49F512-70JI
AT49F512-70PI
AT49F512-70TI
AT49F512-70VI
32J
Industrial
32P6
32T
32V
(-40° to 85°C)
AT49F512-90JC
AT49F512-90PC
AT49F512-90TC
AT49F512-90VC
32J
Commercial
32P6
32T
32V
(0° to 70°C)
AT49F512-90JI
AT49F512-90PI
AT49F512-90TI
AT49F512-90VI
32J
Industrial
32P6
32T
32V
(-40° to 85°C)
Note:
1. The AT49F512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.
Package Type
32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32-lead, Thin Small Outline Package (TSOP) (8 x 20 mm)
32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
32J
32P6
32T
32V
AT49F512
10
AT49F512
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
32P6, 32-lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
1.67(42.4)
1.64(41.7)
.025(.635) X 30˚ - 45˚
PIN
1
.045(1.14) X 45˚ PIN NO. 1
.012(.305)
IDENTIFY
.008(.203)
.530(13.5)
.490(12.4)
.566(14.4)
.530(13.5)
.553(14.0)
.547(13.9)
.595(15.1)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.585(14.9)
.090(2.29)
MAX
1.500(38.10) REF
.030(.762)
.050(1.27) TYP
.220(5.59)
MAX
.005(.127)
MIN
.300(7.62) REF
.430(10.9)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.390(9.90)
AT CONTACT
POINTS
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.022(.559) X 45˚ MAX (3X)
.630(16.0)
.590(15.0)
.453(11.5)
.447(11.4)
0
15
REF
.495(12.6)
.485(12.3)
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
32T, 32-lead, Plastic Thin Small Outline Package
(TSOP)
32V, 32-lead, Plastic Thin Small Outline Package
(VSOP)
Dimensions in Millimeters and (Inches)*
Dimensions in Millimeters and (Inches)*
INDEX
MARK
INDEX
MARK
18.5(.728)
18.3(.720)
20.2(.795)
19.8(.780)
12.5(.492)
12.3(.484)
14.2(.559)
13.8(.543)
0.50(.020)
BSC
0.50(.020)
BSC
0.25(.010)
0.15(.006)
0.25(.010)
0.15(.006)
7.50(.295)
REF
7.50(.295)
REF
8.20(.323)
7.80(.307)
8.10(.319)
7.90(.311)
1.20(.047) MAX
1.20(.047) MAX
0.15(.006)
0.05(.002)
0.15(.006)
0.05(.002)
0
0
0.20(.008)
0.10(.004)
REF
5
0.20(.008)
0.10(.004)
REF
5
0.70(.028)
0.50(.020)
0.70(.028)
0.50(.020)
*Controlling dimensions: millimeters
*Controlling dimensions: millimeters
11
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
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