AT93C46-10SA-2.7C 概述
Microwire Serial EEPROM
Microwire串行EEPROM\n
AT93C46-10SA-2.7C 数据手册
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PDF下载Features
• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• 3-wire Serial Interface
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
3-wire Serial
Automotive
EEPROMs
Description
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 64/128/256 words of 16 bits
each, when the ORG pin is connected to VCC and 128/256/512 words of 8 bits each
when it is tied to ground. The device is optimized for use in many automotive applica-
tions where low power and low voltage operations are essential. The AT93C46/56/66
is available in space-saving 8-lead PDIP and 8-lead JEDEC SOIC packages.
AT93C46
AT93C56
AT93C66
Pin Configurations
8-lead PDIP
Pin Name
Function
CS
Chip Select
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
ORG
GND
DI
DO
DO
GND
VCC
ORG
DC
Power Supply
Internal Organization
Don’t Connect
8-lead SOIC
CS
1
8
7
6
5
VCC
SK
DI
2
3
4
DC
ORG
GND
DO
Rev. 3264A–SEEPR–01/02
Description (Continued)
The AT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely self-
timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought
“high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY
status of the part.
The AT93C46/56/66 is available in 4.5V to 5.5V and 2.7V to 5.5V versions.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
Notes: 1. When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organiza-
tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the x 16 organization is selected.
2. For the AT93C46, if x 16 organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends using
the AT93C46A device. For more details, see the AT93C46A datasheet.
2
AT93C46/56/66
3264A–SEEPR–01/02
AT93C46/56/66
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TA = -40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted).
Symbol
VCC1
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
VCC2
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
6.0
17
2.0
mA
mA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
VCC = 2.7V
10.0
30
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
1.0
IOL
Output Leakage
1.0
(1)
VIL1
Input Low Voltage
Input High Voltage
-0.6
VCC x 0.7
VCC x 0.3
2.7V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
V
(1)
VIH1
V
CC + 1
I
I
OL = 2.1 mA
OH = -0.4 mA
0.4
V
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.4
IOL = 0.15 mA
OH = -100 µA
0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
1.8V ≤ VCC ≤ 2.7V
I
VCC - 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
3
3264A–SEEPR–01/02
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
2
1
fSK
MHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
tPD1
tPD0
tSV
Output Delay to ‘1’
Output Delay to ‘0’
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDF
10
ms
ms
tWP
Write Cycle Time
2.7V ≤ VCC ≤ 5.5V
3
Endurance(1)
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT93C46/56/66
3264A–SEEPR–01/02
AT93C46/56/66
Instruction Set for the AT93C46
Address
Data
Op
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
READ
1
10
00
A6 - A0
A5 - A0
Reads data stored in memory, at
specified address.
EWEN
1
11XXXXX
11XXXX
Write enable must precede all
programming modes.
ERASE
WRITE
ERAL
1
1
1
11
01
00
A6 - A0
A6 - A0
A5 - A0
A5 - A0
Erase memory location An - A0.
Writes memory location An - A0.
D7 - D0
D7 - D0
D15 - D0
10XXXXX
10XXXX
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
WRAL
1
00
01XXXXX
01XXXX
D15 - D0
Writes all memory locations. Valid
only at VCC = 4.5V to 5.5V.
EWDS
1
00
00XXXXX
00XXXX
Disables all programming instructions.
Note:
The X’s in the address field represent don’t care values and must be clocked.
5
3264A–SEEPR–01/02
Functional
Description
The AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory Address
location.
READ (READ): The Read (READ) instruction contains the Address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic
“1” indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle, tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the READY/BUSY status of the part if CS is brought high after being kept low for
a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C46/56/66
3264A–SEEPR–01/02
AT93C46/56/66
Timing Diagrams
Synchronous Data Timing
Note:
1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C46 (1K)
AT93C56 (2K)
x 16
AT93C66 (4K)
I/O
AN
DN
x 8
A6
x 16
A5
x 8
x 8
A8
x 16
A7
(1)
(2)
A8
D7
A7
D15
D7
D15
D7
D15
Notes: 1. A8 is a DON’T CARE value, but the extra clock is required.
2. A7 is a DON’T CARE value, but the extra clock is required.
READ Timing
7
3264A–SEEPR–01/02
EWEN Timing
EWDS Timing
WRITE Timing
tCS
CS
SK
DI
...
1
0
0
1
1
tCS
CS
SK
DI
...
0
0
0
1
0
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
8
AT93C46/56/66
3264A–SEEPR–01/02
AT93C46/56/66
ERASE Timing
tCS
CS
SK
DI
STANDBY
CHECK
STATUS
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
3264A–SEEPR–01/02
AT93C46 Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
2000
800
30.0
10.0
2000
1000
AT93C46-10PA-5.0C
AT93C46-10SA-5.0C
8P3
8S1
Automotive
(-40°C to 125°C)
AT93C46-10PA-2.7C
AT93C46-10SA-2.7C
8P3
8S1
Automotive
(-40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
-5.0
-2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
10
AT93C46/56/66
3264A–SEEPR–01/02
AT93C46/56/66
AT93C56 Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
2000
800
30.0
10.0
2000
1000
AT93C56-10PA-5.0C
AT93C56-10SA-5.0C
8P3
8S1
Automotive
(-40°C to 125°C)
AT93C56-10PA-2.7C
AT93C56-10SA-2.7C
8P3
8S1
Automotive
(-40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
-5.0
-2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
11
3264A–SEEPR–01/02
AT93C66 Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
2000
800
30.0
10.0
2000
1000
AT93C66-10PA-5.0C
AT93C66-10SA-5.0C
8P3
8S1
Automotive
(-40°C to 125°C)
AT93C66-10PA-2.7C
AT93C66-10SA-2.7C
8P3
8S1
Automotive
(-40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
-5.0
-2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
12
AT93C46/56/66
3264A–SEEPR–01/02
AT93C46/56/66
Packaging Information
8P3 – PDIP
D
PIN
1
E1
A
B1
SEATING PLANE
A1
L
B
e
B2
(4 PLACES)
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
MAX
NOM
NOTE
SYMBOL
eC
A
–
–
4.318
eB
A1
D
0.381
9.144
7.620
6.096
0.406
1.397
0.762
3.175
0.203
–
–
–
–
–
–
–
–
–
–
–
–
–
9.652 Note 2
8.255
E
E1
B
6.604 Note 2
0.508
B1
B2
L
1.651
Notes:
1. This package conforms to JEDEC reference MS-001 BA.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
1.143
3.429
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
09/28/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
8P3
B
R
13
3264A–SEEPR–01/02
8S2 – JEDEC SOIC
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
14
AT93C46/56/66
3264A–SEEPR–01/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Atmel Corporate
Atmel Heilbronn
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 436-4270
FAX 1(408) 436-4314
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Europe
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TEL (41) 26-426-5555
FAX (41) 26-426-5500
Atmel Corporate
Atmel Colorado Springs
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Colorado Springs, CO 80906
TEL 1(719) 576-3300
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TEL 1(408) 436-4270
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Japan
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TEL 1(719) 576-3300
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
FAX 1(719) 540-1759
Atmel Smart Card ICs
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Maxwell Building
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TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
3264A–SEEPR–01/02
0M
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