ATT3030-125T84I [ETC]
Field-Programmable Gate Arrays; 现场可编程门阵列型号: | ATT3030-125T84I |
厂家: | ETC |
描述: | Field-Programmable Gate Arrays |
文件: | 总80页 (文件大小:499K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
Description
■ High performance:
The CMOS ATT3000 Series Field-Programmable
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
Gate Array (FPGA) family provides a group of high-
density, digital integrated circuits. Their regular,
extendable, flexible, user-programmable array
architecture is composed of a configuration program
store plus three types of configurable elements: a
perimeter of I/O blocks, a core array of logic blocks,
and resources for interconnection. The general struc-
ture of an FPGA is shown in Figure 1.
■ User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system
logic changes
■ Flexible array architecture:
— Compatible arrays ranging from 1500 to
6000 gate logic complexity
— Extensive register, combinatorial, and I/O
capabilities
The ORCA Foundry for ATT3000 Development Sys-
tem provides automatic place and route of netlists.
Logic and timing simulation are available as design
verification alternatives. The design editor is used for
interactive design optimization and to compile the
data pattern that represents the configuration pro-
gram.
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator amplifier
The FPGA’s user-logic functions and interconnec-
tions are determined by the configuration program
data stored in internal static memory cells. The pro-
gram can be loaded in any of several modes to
accommodate various system requirements. The
program data resides externally in an EEPROM,
EPROM, or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of pro-
gram data at powerup. A serial configuration PROM
can provide a very simple serial configuration pro-
gram storage.
■ Standard product availability:
— Low-power 0.55 µm CMOS, static memory
technology
— Pin-for-pin compatible with Xilinx* XC3000*
and XC3100* families
— Cost-effective for volume production
— 100% factory pretested
— Selectable configuration modes
■ ORCA™ Foundry for ATT3000 Development
System support
*
Xilinx, XC3000, and XC3100 are registered trademarks of
Xilinx, Inc.
■ All FPGAs processed on a QML-certified line
■ Extensive packaging options
Table 1. ATT3000 Series FPGAs
Max
Logic
Gates
Configurable
Logic
Typical Gate
Range
User I/Os
Max
Flip-
Flops
Horizontal Configuration
FPGA
Array
Long Lines
Data Bits
Blocks
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
1,500
2,000
3,000
4,500
6,000
1,000—1,500
1,500—2,000
2,000—3,000
3,500—4,500
5,000—6,000
64
8 x 8
64
80
96
120
144
256
360
480
688
928
16
20
24
32
40
14,779
22,176
30,784
46,064
64,160
100
144
224
320
10 x 10
12 x 12
16 x 14
20 x 16
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Table of Contents
Contents
Page
Contents
Page
Features ..................................................................... 1
Description ................................................................. 1
Architecture ................................................................ 3
Configuration Memory................................................ 4
I/O Block ..................................................................... 5
Summary of I/O Options ......................................... 6
Configurable Logic Block ............................................ 7
Programmable Interconnect ....................................... 9
General-Purpose Interconnect ............................. 10
Direct Interconnect ............................................... 11
Long Lines ............................................................ 13
Internal Buses ...................................................... 14
Crystal Oscillator .................................................. 16
Configuration ............................................................ 17
Initialization Phase ............................................... 17
Configuration Data ............................................... 19
Configuration Modes ................................................ 22
Master Mode ........................................................ 22
Peripheral Mode ................................................... 24
Slave Mode .......................................................... 25
Daisy Chain .......................................................... 26
Special Configuration Functions .............................. 27
Input Thresholds ................................................... 27
Readback ............................................................. 27
Reprogram ........................................................... 28
DONE Pull-Up ...................................................... 28
DONE Timing ....................................................... 28
RESET Timing ...................................................... 28
Crystal Oscillator Division .................................... 28
Performance .............................................................29
Device Performance .............................................29
Logic Block Performance ......................................30
Interconnect Performance .....................................30
Power ........................................................................32
Power Distribution .................................................32
Power Dissipation .................................................33
Pin Information .........................................................34
Pin Assignments .......................................................39
Package Thermal Characteristics .............................50
Package Coplanarity .................................................51
Package Parasitics ...................................................51
Absolute Maximum Ratings ......................................53
Electrical Characteristics ..........................................54
Outline Diagrams ......................................................68
Terms and Definitions ...........................................68
44-Pin PLCC .........................................................68
68-Pin PLCC .........................................................69
84-Pin PLCC .........................................................70
100-Pin QFP .........................................................71
100-Pin TQFP .......................................................72
132-Pin PPGA ......................................................73
144-Pin TQFP .......................................................74
160-Pin QFP .........................................................75
175-Pin PPGA ......................................................76
208-Pin SQFP .......................................................77
Ordering Information .................................................78
2
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
implemented with metal segments joined by program-
controlled pass transistors. These functions of the
FPGA are established by a configuration program
which is loaded into an internal, distributed array of
configuration memory cells. The configuration program
is loaded into the FPGA at powerup and may be
reloaded on command. The FPGA includes logic and
control signals to implement automatic or passive
configuration. Program data may be either bit serial or
byte parallel. The ORCA Foundry for ATT3000 Devel-
opment System generates the configuration program
bit stream used to configure the FPGA. The memory
loading process is independent of the user logic func-
tions.
Architecture
The perimeter of configurable I/O blocks (IOBs) pro-
vides a programmable interface between the internal
logic array and the device package pins. The array of
configurable logic blocks (CLBs) performs user-
specified logic functions. The interconnect resources
are programmed to form networks, carrying logic
signals among blocks, analogous to printed-circuit
board traces connecting MSI/SSI packages.
The blocks’ logic functions are implemented by
programmed look-up tables. Functional options are
implemented by program-controlled multiplexers.
Interconnecting networks between blocks are
Figure 1. Field-Programmable Gate Array Structure
Lucent Technologies Inc.
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
The memory cell outputs Q and Q use full ground and
VCC levels and provide continuous, direct control. The
additional capacitive load and the absence of address
decoding and sense amplifiers provide high stability to
the cell. Due to their structure, the configuration mem-
ory cells are not affected by extreme power supply
excursions or very high levels of alpha particle radia-
tion. Soft errors have not been observed in reliability
testing.
Configuration Memory
The static memory cell used for the configuration mem-
ory in the FPGA has been designed specifically for
high reliability and noise immunity. Integrity of the
FPGA configuration memory based on this design is
ensured even under various adverse conditions. Com-
pared with other programming alternatives, static mem-
ory is believed to provide the best combination of high
density, high performance, high reliability, and compre-
hensive testability.
Two methods of loading configuration data use serial
data, while three use byte-wide data. The internal con-
figuration logic utilizes framing information, embedded
in the program data by the ORCA Foundry Develop-
ment System, to direct memory cell loading. The serial
data framing and length count preamble provide pro-
gramming compatibility for mixes of various Lucent pro-
grammable gate arrays in a synchronous, serial, daisy-
chain fashion.
As shown in Figure 2, the basic memory cell consists of
two CMOS inverters plus a pass transistor used for
writing and reading cell data. The cell is only written to
during configuration and only read from during read-
back. During normal operation, the cell provides contin-
uous control and the pass transistor is off and does not
affect cell stability. This is quite different from the opera-
tion of conventional memory devices, in which the cells
are frequently read and rewritten.
Q
CONFIGURATION
CONTROL
Q
READ OR
WRITE
DATA
5-3101(F)
Figure 2. Static Configuration Memory Cell
4
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
package pin to internal logic levels. The global input-
buffer threshold of the IOB can be programmed to be
compatible with either TTL or CMOS levels. The buff-
ered input signal drives the data input of a storage
element which may be configured as a positive-edge
triggered D flip-flop or a low-level transparent latch. The
sense of the clock can be inverted (negative edge/high
transparent) as long as all IOBs on the same clock net
use the same clock sense. Clock/load signals (IOB pins
.ik and .ok) can be selected from either of two die edge
metal lines. I/O storage elements are reset during con-
figuration or by the active-low chip RESET input. Both
direct input (from IOB pin .i) and registered input (from
IOB pin .q) signals are available for interconnect.
I/O Block
Each user-configurable I/O block (IOB), shown in
Figure 3, provides an interface between the external
package pin of the device and the internal user logic.
Each IOB includes both registered and direct input
paths and a programmable 3-state output buffer which
may be driven by a registered or direct output signal.
Configuration options allow each IOB an inversion, a
controlled slew rate, and a high-impedance pull-up.
Each input circuit also provides input clamping diodes
to provide electrostatic protection and circuits to inhibit
latch-up produced by input currents.
The input buffer portion of each IOB provides threshold
detection to translate external signals applied to the
PROGRAM-CONTROLLED MEMORY CELLS
VCC
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
.t
3-STATE
OUTPUT ENABLE
.o
OUTPUT
BUFFER
D
Q
OUT
FLIP-
FLOP
I/O PAD
R
.i
DIRECT IN
.q
REGISTERED IN
Q
D
TTL OR
FLIP-
FLOP
OR
CMOS
INPUT
THRESHOLD
LATCH
R
(GLOBAL RESET)
CK1
.ok
.lk
CK2
PROGRAM-
CONTROLLED
MULTIPLEXER
= PROGRAMMABLE INTERCONNECTION POINT OR PIP
5-3102(F)
Figure 3. Input/Output Block
Lucent Technologies Inc.
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
The program-controlled memory cells in Figure 3
control the following options:
I/O Block (continued)
For reliable operation, inputs should have transition
times of less than 100 ns and should not be left float-
ing. Floating CMOS input-pin circuits might be at
threshold and produce oscillations. This can produce
additional power dissipation and system noise. A
typical hysteresis of about 300 mV reduces sensitivity
to input noise. Each user IOB includes a programmable
high-impedance pull-up resistor which is selected by
the program to provide a constant high for otherwise
undriven package pins. Normal CMOS handling
precautions should be observed.
■ Logical inversion of the output is controlled by one
configuration program bit per IOB.
■ Logical 3-state control of each IOB output buffer is
determined by the states of configuration program
bits which turn the buffer on or off or select the output
buffer 3-state control interconnection (IOB pin .t).
When this IOB output control signal is high, a logic 1,
the buffer is disabled and the package pin is high
impedance. When this IOB output control signal is
low, a logic 0, the buffer is enabled and the package
pin is active. Inversion of the buffer 3-state control
logic sense (output enable) is controlled by an addi-
tional configuration program bit.
Flip-flop loop delays for the IOB and logic block flip-
flops are approximately 3 ns. This short delay provides
good performance under asynchronous clock and data
conditions. Short loop delays minimize the probability
of a metastable condition which can result from asser-
tion of the clock during data transitions. Because of the
short loop delay characteristic in the FPGA, the IOB
flip-flops can be used to synchronize external signals
applied to the device. When synchronized in the IOB,
the signals can be used internally without further con-
sideration of their clock relative timing, except as it
applies to the internal logic and routing path delays.
■ Direct or registered output is selectable for each IOB.
The register uses a positive-edge, clocked flip-flop.
The clock source may be supplied (IOB pin .ok) by
either of two metal lines available along each die
edge. Each of these lines is driven by an invertible
buffer.
■ Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce
capacitive load peak currents of noncritical outputs
and minimize system noise.
Output buffers of the IOBs provide CMOS-compatible
4 mA source-or-sink drive for high fan-out CMOS or
TTL compatible signal levels. The network driving IOB
pin .o becomes the registered or direct data source for
the output buffer. The 3-state control signal (IOB pin .t)
can control output activity. An open-drain type output
may be obtained by using the same signal for driving
the output and 3-state signal nets so that the buffer out-
put is enabled only for a LOW.
■ A high-impedance pull-up resistor may be used to
prevent unused inputs from floating.
Summary of I/O Options
■ Inputs
—Direct
—Flip-flop/latch
—CMOS/TTL threshold (chip inputs)
—Pull-up resistor/open circuit
Configuration program bits for each IOB control
features such as optional output register, logical signal
inversion, and 3-state and slew rate control of the out-
put.
■ Outputs
—Direct/registered
—Inverted/not
—3-state/on/off
—Full speed/slew limited
—3-state/output enable (inverse)
6
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
when enabled and high, is dominant over clocked
inputs. All flip-flops are reset by the active-low chip
Configurable Logic Block
input, RESET, or during the configuration process.
The array of configurable logic blocks (CLBs) provides
the functional elements from which the user’s logic is
constructed. The logic blocks are arranged in a matrix
within the perimeter of IOBs. The ATT3020 has 64 such
blocks arranged in eight rows and eight columns. The
ORCA Foundry Development System is used to com-
pile the configuration data for loading into the internal
configuration memory to define the operation and inter-
connection of each block. User definition of CLBs and
their interconnecting networks may be done by auto-
matic translation from a schematic capture logic dia-
gram or optionally by installing library or user macros.
The flip-flops share the enable clock (.ec) which, when
low, recirculates the flip-flops’ present states and inhib-
its response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control
inputs and select their sources. The user may also
select the clock net input (.k), as well as its active
sense within each logic block. This programmable
inversion eliminates the need to route both phases of a
clock signal throughout the device. Flexible routing
allows use of common or individual CLB clocking.
The combinatorial logic portion of the logic block uses
a 32 x 1 look-up table to implement Boolean functions.
Variables selected from the five logic inputs and the
two internal block flip-flops are used as table address
inputs. The combinatorial propagation delay through
the network is independent of the logic function gener-
ated and is spike-free for single-input variable changes.
This technique can generate two independent logic
functions of up to four variables each as shown in Fig-
ure 5A, or a single function of five variables as shown in
Figure 5B, or some functions of seven variables as
shown in Figure 5C.
Each CLB has a combinatorial logic section, two flip-
flops, and an internal control section; see Figure 4
below. There are five logic inputs (.a, .b, .c, .d, and .e);
a common clock input (.k); an asynchronous direct
reset input (.rd); and an enable clock (.ec). All may be
driven from the interconnect resources adjacent to the
blocks. Each CLB also has two outputs (.x and .y)
which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied
from the function F or G outputs of the combinatorial
logic, or the block input, data-in (.di). Both flip-flops in
each CLB share the asynchronous reset (.rd) which,
.di
DATA IN
0
D
Q
MUX
F
1
DIN
G
QX
F
RD
QX
.x
.a
.b
F
LOGIC
VARIABLES
.c
.d
.e
COMBINATORIAL
FUNCTION
CLB OUTPUTS
G
G
.y
QX
F
DIN
QY
0
G
D
Q
MUX
1
.ec
ENABLE
CLOCK
RD
“1” (ENABLE)
.k
CLOCK
DIRECT
RESET
.rd
“0” (INHIBIT)
(GLOBAL RESET)
5-3103(F)
Figure 4. Configurable Logic Block
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Figure 6 shows a modulo 8 binary counter with parallel
enable. It uses one CLB of each type. The partial func-
tions of six or seven variables are implemented by
using the input variable (.e) to dynamically select
between two functions of four different variables. For
the two functions of four variables each, the indepen-
dent results (F and G) may be used as data inputs to
either flip-flop or logic block output. For the single func-
tion of five variables and merged functions of six or
seven variables, the F and G outputs are identical.
Symmetry of the F and G functions and the flip-flops
allows the interchange of CLB outputs to optimize
routing efficiencies of the networks interconnecting
the logic and IOBs.
Configurable Logic Block (continued)
A
B
QX
ANY FUNCTION
OF UP TO 4
VARIABLES
QY
F
C
D
E
A
B
QX
ANY FUNCTION
OF UP TO 4
VARIABLES
QY
G
C
D
E
5A
CLOCK
ENABLE
TERMINAL
COUNT
PARALLEL
ENABLE
A
B
DUAL FUNCTION OF
4 VARIABLES
CLOCK
F
QX
ANY FUNCTION
OF 5
VARIABLES
QY
C
D
E
G
Q0
D
Q
D0
5B
A
B
QX
ANY FUNCTION
OF UP TO 4
VARIABLES
QY
C
D
F
D
Q
Q1
M
U
X
D1
G
A
B
QX
FUNCTION OF 5 VARIABLES
ANY FUNCTION
OF UP TO 4
VARIABLES
QY
C
D
5C
E
5-3104(F)
5A. Combinatorial Logic Option 1 generates two functions of four
variables each. One variable, A, must be common to both func-
tions. The second and third variables can be any choice among
B, C, Qx, and Qy. The fourth variable can be either D or E.
Q2
D
Q
D2
5B. Combinatorial Logic Option 2 generates any function of five
variables: A, D, E, and two choices among B, C, Qx, Qy.
5C. Combinatorial Logic Option 3 allows variable E to select
between two functions of four variables: both have common
inputs, A and D, and any choice among B, C, Qx, and Qy for
the remaining two variables. Option 3 can then implement
some functions of six or seven variables.
FUNCTION OF 6 VARIABLES
Figure 5. Combinatorial Logic Diagram
5-3105(F)
Figure 6. C8BCP Macro
8
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect
Programmable interconnection resources in the FPGA
provide routing paths to connect inputs and outputs of
the IOBs and logic blocks into logical networks. Inter-
connections between blocks are composed from a two-
layer grid of metal segments. Specially designed pass
transistors, each controlled by a configuration bit, form
programmable interconnect points (PIPs) and switching
matrices used to implement the necessary connections
between selected metal segments and block pins.
Figure 7 is an example of a routed net. The ORCA
Foundry Development System provides automatic rout-
ing of these interconnections. Interactive routing is also
available for design optimization. The inputs of the logic
or IOBs are multiplexers which can be programmed to
select an input network from the adjacent interconnect
segments. Since the switch connections to block inputs
are unidirectional (as are block outputs), they are
usable only for block input connection and not routing.
Figure 8 illustrates routing access to logic block input
variables, control inputs, and block outputs.
Three types of metal resources are provided to accom-
modate various network interconnect requirements:
■ General-purpose interconnect
■ Direct connection
Figure 8. CLB Input and Output Routing
■ Long lines (multiplexed buses and wide-AND gates)
Figure 7. Example of Routing Resources
Lucent Technologies Inc.
9
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect (continued)
General-Purpose Interconnect
General-purpose interconnect, as shown in Figure 9,
consists of a grid of five horizontal and five vertical
metal segments located between the rows and col-
umns of logic and IOBs. Each segment is the height or
width of a logic block. Switching matrices join the ends
of these segments and allow programmed interconnec-
tions between the metal grid segments of adjoining
rows and columns. The switches of an unprogrammed
device are all nonconducting. The connections through
the switch matrix may be established by automatic or
interactive routing by selecting the desired pairs of
matrix pins to be connected or disconnected. The
legitimate switching matrix combinations for each pin
are indicated in Figure 10.
Figure 9. FPGA General-Purpose Interconnect
Special buffers within the general interconnect areas
provide periodic signal isolation and restoration for
improved performance of lengthy nets. The intercon-
nect buffers are available to propagate signals in either
direction on a given general interconnect segment.
These bidirectional (bidi) buffers are found adjacent to
the switching matrices, above and to the right. The
other PIPs adjacent to the matrices are accessed to or
from long lines. The development system automatically
defines the buffer direction based on the location of the
interconnection network source. The delay calculator in
the ORCA Foundry Development System automatically
calculates and displays the block, interconnect, and
buffer delays for any paths selected. Generation of the
simulation netlist with a worst-case delay model is also
provided by the development system.
1
2
3
4
5
6
7
8
9
10
15
11
12
13
14
Some of the interconnect PIPs are directional, as
indicated below:
16
17
18
19
20
Figure 10. Switch Matrix Interconnection Options
■ ND is a nondirectional interconnection.
■ D:H->V is a PIP which drives from a horizontal to a
vertical line.
■ D:V->H is a PIP which drives from a vertical to a
horizontal line.
■ D:C->T is a T-PIP which drives from a cross of a
T to the tail.
■ D:CW is a corner PIP which drives in the clockwise
direction.
■ P0 indicates the PIP is nonconducting; P1 is on.
10
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect (continued)
Direct Interconnect
Direct interconnect (shown in Figure 11) provides the
most efficient implementation of networks between
adjacent logic or IOBs. Signals routed from block to
block using the direct interconnect exhibit minimum
interconnect propagation and use no general intercon-
nect resources. For each CLB, the .x output may be
connected directly to the .b input of the CLB immedi-
ately to its right and to the .c input of the CLB to its left.
The .y output can use direct interconnect to drive the .d
input of the block immediately above, and the .a input
of the block below. Direct interconnect should be used
to maximize the speed of high-performance portions of
logic. Where logic blocks are adjacent to IOBs, direct
connect is provided alternately to the IOB inputs (.i)
and outputs (.o) on all four edges of the die. The right
edge provides additional direct connects from CLB out-
puts to adjacent IOBs. Direct interconnections of IOBs
with CLBs are shown in Figure 12.
Figure 11. Direct Interconnect
Lucent Technologies Inc.
11
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect (continued)
Figure 12. ATT3020 Die Edge I/O Blocks with Direct Access to Adjacent CLB
12
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
lines are located adjacent to the outer sets of switching
matrices. Two vertical long lines in each column are
connectable half-length lines, except on the ATT3020,
where only the outer long lines serve that function.
Programmable Interconnect (continued)
Long Lines
The long lines bypass the switch matrices and are
intended primarily for signals which must travel a long
Long lines can be driven by a logic block or IOB output
on a column-by-column basis. This capability provides
distance, or must have minimum skew among multiple
destinations. Long lines, shown in Figure 13, run
vertically and horizontally the height or width of the
interconnect area. Each interconnection column has
three vertical long lines, and each interconnection row
has two horizontal long lines. Additionally, two long
a common low-skew control or clock line within each
column of logic blocks. Interconnections of these long
lines are shown in Figure 14. Isolation buffers are pro-
vided at each input to a long line and are enabled auto-
matically by the development system when a
connection is made.
3-
-
Figure 13. Horizontal and Vertical Long Lines in the FPGA
Lucent Technologies Inc.
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Internal Buses
Programmable Interconnect (continued)
A buffer in the upper left corner of the FPGA chip drives
a global net which is available to all .k inputs of logic
blocks. Using the global buffer for a clock signal pro-
vides a skew-free, high fan-out, synchronized clock for
use at any or all of the I/O and logic blocks. Configura-
tion bits for the .k input to each logic block can select
this global line, or another routing resource, as the
clock source for its flip-flops. This net may also be pro-
grammed to drive the die edge clock lines for IOB use.
An enhanced speed, CMOS threshold, offers direct
access to this buffer and is available at the
A pair of 3-state buffers is located adjacent to each
CLB. These buffers allow logic to drive the horizontal
long lines. Logical operation of the 3-state buffer
controls allows them to implement wide multiplexing
functions. Any 3-state buffer input can be selected as
drive for the horizontal long line bus by applying a low
logic level on its 3-state control line (see Figure 15A).
The user is required to avoid contention that can result
from multiple drivers with opposing logic levels. Control
of the 3-state input by the same signal that drives the
buffer input creates an open-drain wired-AND function.
A logical high on both buffer inputs creates a high
impedance which represents no contention. A logical
low enables the buffer to drive the long line low (see
Figure 15B). Pull-up resistors are available at each end
of the long line to provide a high output when all con-
nected buffers are nonconducting. This forms fast, wide
gating functions. When data drives the inputs and sep-
arate signals drive the 3-state control lines, these buff-
ers form multiplexers (3-state buses). In this case, care
must be used to prevent contention through multiple
active buffers of conflicting levels on a common line.
Figure 16 shows 3-state buffers, long lines, and pull-up
resistors.
second pad from the top of the left die edge.
A buffer in the lower right corner of the array drives a
horizontal long line that can drive programmed connec-
tions to a vertical long line in each interconnection
column. This alternate buffer also has low skew and
high fan-out. The network formed by this alternate buf-
fer’s long lines can be selected to drive the .k inputs of
the logic blocks. CMOS threshold, high-speed access
to this buffer is available from the third pad from the
bottom of the right die edge.
3-STATE
Figure 14. Programmable Interconnection of Long Lines
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Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect (continued)
VCC
VCC
Z = DA • DB • DC • ... • DN
(LOW)
DN
5-3106(F)
DA
DB
DC
Figure 15A. 3-State Buffers Implement a Wired-AND Function
Z = DA • A + DB • B + DC • C + ... + DN • N
DA
A
DB
B
DC
C
DN
N
WEAK KEEPER CIRCUIT
5-3107(F)
Figure 15B. 3-State Buffers Implement a Multiplexer
3 VERTICAL LONG LINES
PER COLUMN
BIDIRECTIONAL
INTERCONNECT
BUFFERS
GLOBAL NET
GG
GH
P48
HORIZONTAL LONG LINE
PULL-UP RESISTOR
HORIZONTAL LONG LINE
OSCILLATOR
AMPLIFIER OUTPUT
P47
DIRECT INPUT OF P47
TO AUXILIARY BUFFER
BCL
KIN
CRYSTAL OSCILLATOR
BUFFER
HG
HH
3-STATE INPUT
O
S
C
3-STATE CONTROL
3-STATE BUFFER
P46
.l .lk
.q.ok
.o
O
P
ALTERNATE BUFFER
G
M
P40
P41
P42
P43
RST
OSCILLATOR
AMPLIFIER INPUT
5-3108(F)
Figure 16. Lower-Right Corner of ATT3020
Lucent Technologies Inc.
15
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
to minimize loading of the crystal. The inversion of the
amplifier, together with the R-C networks and an AT cut
series resonant crystal, produces the 360° phase shift
of the Pierce oscillator. A series resistor, R2, may be
included to add to the amplifier output impedance when
needed for phase shift control or crystal resistance
matching, or to limit the amplifier input swing to control
clipping at large amplitudes. Excess feedback voltage
may be corrected by the ratio of C2/C1. The amplifier is
designed to be used from 1 MHz to one-half the speci-
fied CLB toggle frequency. Use at frequencies below
1 MHz may require individual characterization with
respect to a series resistance. Crystal oscillators above
20 MHz generally require a crystal which operates in a
third overtone mode, where the fundamental frequency
must be suppressed by an inductor across C2. When
the oscillator inverter is not used, these IOBs and their
package pins are available for general user I/O.
Programmable Interconnect (continued)
Crystal Oscillator
Figure 16 shows the location of an internal high-speed
inverting amplifier which may be used to implement an
on-chip crystal oscillator. It is associated with the auxil-
iary buffer in the lower right corner of the die. When the
oscillator is configured and connected as a signal
source, two special user IOBs are also configured to
connect the oscillator amplifier with external crystal
oscillator components as shown in Figure 17. A divide-
by-two option is available to ensure symmetry. The
oscillator circuit becomes active before configuration is
complete in order to allow the oscillator to stabilize.
Actual internal connection is delayed until completion
of configuration. In Figure 17, the feedback resistor,
R1, between output and input biases the amplifier at
threshold. The value should be as large as is practical
INTERNAL
EXTERNAL
D
Q
XTAL1 (OUT)
XTAL2
(IN)
ALTERNATE
CLOCK BUFFER
R1
R2
C1
Y1
C2
L
THIRD
OVERTONE
ONLY
5-3109(F)
Suggested component values:
R1—0.5 MWto 1 MW
R2—0 kWto 1 kW(may be required for low frequency, phase shift, and/or compensation level for Crystal Q)
C1, C2—10 pF to 40 pF
Y1—1 MHz to 20 MHz AT cut series resonant
100-Pin
44-Pin
PLCC
68-Pin
PLCC
84-Pin
PLCC
132-Pin
PPGA
144-Pin
TQFP
160-Pin
QFP
175-Pin
PPGA
208-Pin
SQFP
Pin
QFP
TQFP
XTAL1 (OUT)
XTAL2 (IN)
30
26
47
43
57
53
82
76
79
73
P13
M13
75
69
82
76
T14
P15
110
100
Figure 17. Crystal Oscillator Inverter
16
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
In master configuration mode, the FPGA becomes the
source of configuration clock (CCLK). Beginning con-
figuration of devices using peripheral or slave modes
must be delayed long enough for their initialization to
be completed. An FPGA with mode lines selecting a
master configuration mode extends its initialization
Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when
power is applied. When VCC reaches the voltage where
portions of the FPGA begin to operate (2.5 V to 3 V),
the programmable I/O output buffers are disabled and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time, the power-
down mode is inhibited. The initialization state time-out
(about 11 ms to 33 ms) is determined by a 14-bit
counter driven by a self-generated, internal timer. This
nominal 1 MHz timer is subject to variations with pro-
cess, temperature, and power supply over the range of
0.5 MHz to 1.5 MHz. As shown in Table 2, five configu-
ration mode choices are available, as determined by
the input levels of three mode pins: M0, M1, and M2.
state using four times the delay (43 ms to 130 ms) to
ensure that all daisy-chained slave devices it may be
driving will be ready, even if the master is very fast and
the slave(s), very slow (see Figure 18). At the end of
initialization, the FPGA enters the clear state where it
clears configuration memory. The active-low, open-
drain initialization signal INIT indicates when the initial-
ization and clear states are complete. The FPGA tests
for the absence of an external active-low RESET before
it makes a final sample of the mode lines and enters
the configuration state. An external wired-AND of one
or more INIT pins can be used to control configuration
by the assertion of the active-low RESET of a master
mode device or to signal a processor that the FPGAs
are not yet initialized.
Table 2. Configuration Modes
If a configuration has begun, a reassertion of RESET for
a minimum of three internal timer cycles will be recog-
nized and the FPGA will initiate an abort, returning to
the clear state to clear the partially loaded configura-
tion memory words. The FPGA will then resample
RESET and the mode lines before reentering the con-
figuration state.
M0 M1 M2
Clock
Mode
Data
0
0
0
0
0
1
Active
Active
Master
Master
Bit Serial
Byte Wide
(Address = 0000
up)
0
0
1
1
0
1
—
Reserved
Master
—
Active
Byte Wide
(Address = FFFF
down)
A reprogram is initiated when a configured FPGA
senses a high-to-low transition on the DONE/PROG
package pin. The FPGA returns to the clear state
where configuration memory is cleared and mode lines
resampled, as for an aborted configuration. The com-
plete configuration program is cleared and loaded dur-
ing each configuration program cycle.
1
1
1
1
0
0
1
1
0
1
0
1
—
Active
—
Reserved
Peripheral
Reserved
Slave
—
Byte Wide
—
Passive
Bit Serial
Lucent Technologies Inc.
17
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Configuration (continued)
USER I/O PINS WITH HIGH-IMPEDANCE PULL-UP
POWERDOWN
NO HDC, LDC
OR PULL-UP
INIT = LOW
HDC = HIGH
LDC = LOW
PWRDWN
INACTIVE
INITIALIZATION
POWER-ON
TIME DELAY
PWRDWN
ACTIVE
ACTIVE RESET
NO
CLEAR
CONFIGURATION
MEMORY
TEST
MODE PINS
CONFIGURATION
PROGRAM MODE
OPERATIONAL
MODE
RESET
ACTIVE
START-UP
ACTIVE RESET
OPERATES ON
USER LOGIC
YES
LOW ON DONE/PROG AND RESET
5-3110(F)
Figure 18. State Diagram of Configuration Process for Powerup and Reprogram
Length count control allows a system of multiple
become active. A similar timing selection is program-
mable for the DONE/PROG output signal. DONE/PROG
may also be programmed to be an open drain or
include a pull-up resistor to accommodate wired-
ANDing. The high during configuration (HDC) and low
during configuration (LDC) are two user I/O pins which
are driven active when an FPGA is in initialization,
clear, or configure states. These signals and DONE/
PROG provide for control of external logic signals such
as reset, bus enable, or PROM enable during
configuration.
FPGAs in assorted sizes to begin operation in a syn-
chronized fashion. The configuration program gener-
ated by the ORCA Foundry Development System
begins with a preamble of 111111110010 (binary), fol-
lowed by a 24-bit length count representing the total
number of configuration clocks needed to complete
loading of the configuration program(s). The data fram-
ing is shown in Figure 19. All FPGAs connected in
series read and shift preamble and length count in (on
positive) and out (on negative) CCLK edges. An FPGA
which has received the preamble and length count then
presents a HIGH data out until it has intercepted the
appropriate number of data frames. When the configu-
ration program memory of an FPGA is full and the
length count does not compare, the FPGA shifts any
additional data through, as it did for preamble and
length count.
For parallel master configuration modes, these signals
provide PROM enable control and allow the data pins
to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At powerup, all inputs
have TTL thresholds and can change to CMOS thresh-
olds at the completion of configuration, if the user has
selected CMOS thresholds. The threshold of PWRDWN
and the direct clock inputs are fixed at a CMOS level.
When the FPGA configuration memory is full and the
length count compares, the FPGA will execute a syn-
chronous start-up sequence and become operational
(see Figure 20 on page 20). Two CCLK cycles after the
completion of loading configuration data, the user
I/O pins are enabled as configured. As selected in
ORCA Foundry, the internal user-logic reset is released
either one clock cycle before or after the I/O pins
If the crystal oscillator is used, it will begin operation
before configuration is complete to allow time for
stabilization before it is connected to the internal
circuitry.
18
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Configuration (continued)
Configuration Data
Configuration data to define the function and interconnection within an FPGA are loaded from an external storage
at powerup and on a reprogram signal. Several methods of automatic and controlled loading of the required data
are available. Logic levels applied to mode selection pins at the start of configuration time determine the method to
be used (see Table 2). The data may be either bit-serial or byte-parallel, depending on the configuration mode.
Various Lucent programmable gate arrays have different sizes and numbers of data frames. For the ATT3020, con-
figuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the
header (see Figure 20).
11111111
0010
– DUMMY BITS*
– PREAMBLE CODE
HEADER
< 24-BIT LENGTH COUNT >
1111
– CONFIGURATION PROGRAM LENGTH
– DUMMY BITS (4 BITS MINIMUM)
0 < DATA FRAME # 001 > 111
0 < DATA FRAME # 002 > 111
0 < DATA FRAME # 003 > 111
FOR ATT3020
PROGRAM DATA
197 CONFIGURATION DATA FRAMES
.
.
.
.
.
.
.
.
.
.
.
.
(EACH FRAME CONSISTS OF:
A START BIT (0)
A 71-BIT DATA FIELD
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
)
THREE STOP BITS
0 < DATA FRAME # 196 > 111
0 < DATA FRAME # 197 > 111
1111
POSTAMBLE CODE (4 BITS MINIMUM)
* The FPGA devices require four dummy bits minimum.
Figure 19. Internal Configuration Data Structure
Lucent Technologies Inc.
19
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Configuration (continued)
Table 3. ATT3000 Device Configuration Data
Device
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
Gates
CLBs
1500
2000
3000
4500
6000
64
100
144
224
320
(row x column)
(8 x 8)
(10 x 10)
(12 x 12)
(16 x 14)
(20 x 16)
IOBs
64
256
75
80
360
92
96
120
688
140
144
928
172
Flip-flops
480
108
Bits-per-frame
(with 1 start/3 stop)
Frames
197
241
285
329
373
Program Data =
Bits * Frames + 4
(excludes header)
14779
22176
30784
46064
64160
PROM Size (bits) =
Program Data
14819
22216
30824
46104
64200
+ 40-bit Headers
Note: The length count produced by the bit stream generation program = [(40-bit preamble + sum of program data + 1 per daisy-chain device)
rounded up to a multiple of 8] – (2 £ K £ 4), where K is a function of DONE and RESET timing selected. An additional 8 is added if the
roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
POSTAMBLE
DATA FRAME
LAST FRAME
12
24
4
75
3
3
STOP
4
STOP
3
PREAMBLE LENGTH COUNT
DATA
LENGTH COUNT*
WEAK PULL-UP
START
HIGH
START
I/O ACTIVE
DONE
DOUT LEAD DEVICE
1/2 CLOCK CYCLE
PROG
DELAY FROM DATA INPUT
INTERNAL RESET
5-3111(F)
* The configuration data consists of a composite 40-bit preamble/length count, followed by one or more concatenated FPGA programs,
separated by 4-bit postambles. An additional final postamble bit is added for each slave device, and the result rounded up to byte boundary.
The length count is two less than the number of resulting bits. Timing of the assertion of DONE and termination of the internal RESET may
each be programmed to occur one cycle before or after the I/O outputs become active.
Figure 20. FPGA Configuration and Start-Up
20
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
into one word of the internal configuration memory
array. The configuration loading process is complete
Configuration (continued)
when the current length count equals the loaded length
count and the required configuration program data
frames have been written. Internal user flip-flops are
held reset during configuration.
The specific data format for each device is produced by
the bit stream generation program, and one or more of
these files can then be combined and appended to a
length count preamble and be transformed into a
PROM format file by the PROM generation program of
the ORCA Foundry Development System. The tie
option of the bit stream generation program defines
output levels of unused blocks of a design and con-
nects these to unused routing resources. This prevents
indeterminate levels which might produce parasitic
supply currents. This tie option can be omitted for quick
breadboard iterations where a few additional mA of ICC
are acceptable.
Two user-programmable pins are defined in the uncon-
figured FPGA: high during configuration (HDC) and low
during configuration (LDC), and DONE/PROG may be
used as external control signals during configuration. In
master mode configurations, it is convenient to use LDC
as an active-low EPROM chip enable. After the last
configuration data bit is loaded and the length count
compares, the user I/O pins become active. Options in
the bit stream generation program allow timing choices
of one clock earlier or later for the timing of the end of
the internal logic reset and the assertion of the DONE
signal. The open-drain DONE/PROG output can be
AND-tied with multiple FPGAs and used as an active-
high READY, an active-low PROM enable, or a RESET
to other portions of the system. The state diagram of
Figure 18 illustrates the configuration process.
The configuration bit stream begins with high preamble
bits, a 4-bit preamble code, and a 24-bit length count.
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count the total number of con-
figuration clock cycles applied to the device. As each
configuration data frame is supplied to the FPGA, it is
internally assembled into a data word. As each data
word is completely assembled, it is loaded in parallel
Lucent Technologies Inc.
21
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
required. The FPGA HEX starting address is 0000 and
increments for master low mode, and it is FFFF and
decrements for master high mode. These two modes
provide address compatibility with microprocessors
which begin execution from opposite ends of memory.
Configuration Modes
Master Mode
In master mode, the FPGA automatically loads configu-
ration data from an external memory device. There are
three master modes which use the internal timing
source to supply the configuration clock (CCLK) to time
the incoming data. Serial master mode uses serial con-
figuration data supplied to data-in (DIN) from a syn-
chronous serial source such as the serial configuration
PROM shown in Figure 21. Parallel master low and
master high modes automatically use parallel data sup-
plied to the D[7:0] pins in response to the 16-bit
For master high or low, data bytes are read in parallel
by each read clock (RCLK) and internally serialized by
the configuration clock. As each data byte is read, the
least significant bit of the next byte, D0, becomes the
next bit in the internal serial configuration word. One
master mode FPGA can be used to interface the
configuration program-store, and pass additional
concatenated configuration data to additional FPGAs in
a serial daisy-chain fashion. CCLK is provided for the
slaved devices, and their serialized data is supplied
from DOUT to DIN, DOUT to DIN, etc.
address generated by the FPGA. Figure 22 shows an
example of the parallel master mode connections
+5 V
DURING CONFIGURATION
THE 5 kWM2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
M0 M1 PWRDWN
BUT IT ALLOWS M2 TO
BE USER I/O.
DOUT
M2
*
*
HDC
LDC
GENERAL-
OPTIONAL
PURPOSE
USER I/O
PINS
IDENTICAL SLAVE
FPGAs CONFIGURED
THE SAME
OTHER
I/O PINS
ATT3000
SERIES
FPGA
ATT1700A
RESET
SYSTEM RESET
CASCADED
ATT1700A
MEMORY
DIN
DATA
CLK
DATA
CLK
CCLK
D/P
CE
CEO
CE
INIT
OE/RESET
OE/RESET
(HIGH RESETS THE ADDRESS POINTER)
5-3112(C)
Note: The serial configuration PROM supports automatic loading of configuration programs up to 36/64/128 Kbits. Multiple devices can be
cascaded to support additional FPGAs. An early DONE inhibits the data output one CCLK cycle before the FPGA I/O becomes active.
Figure 21. Master Serial Mode
22
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Configuration Modes (continued)
+5 V
USER CONTROL OF HIGHER
ORDER FROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS
M0 M1
PWRDWN
5 kW
DOUT
M2
*
*
CCLK
HDC
LDC
A15
A14
A13
A12
A11
A10
A9
GENERAL-
PURPOSE
USER I/O
PNS
RCLK
INIT
EPROM
(2K x 8
OR LARGER)
OTHER
I/O PINS
A10
A9
SYSTEM
RESET
RESET
FPGA
A8
A8
D7
A7
A7
A6
D7
D6
A6
D6
D5
D4
D3
A5
A4
A3
A5
A4
A3
D5
D4
D3
D2
D1
D0
A2
A1
A2
A1
A0
OE
CE
D2
D1
D0
A0
+5 V
D/P
5 kW
8
DATA BUS
5-3113(F)
Figure 22. Master Parallel Mode
Lucent Technologies Inc.
23
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Configuration Modes (continued)
Peripheral Mode
Peripheral mode provides a simplified interface through which the device may be loaded byte-wide, as a processor
peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the com-
mon assertion of the active-low write strobe (WS), and two active-low and one active-high chip selects (CS0, CS1,
CS2). If all of these signals are not available, the unused inputs should be driven to their respective active levels.
The FPGA will accept 1 byte of configuration data on the D[7:0] inputs for each selected processor write cycle.
Each byte of data is loaded into a buffer register. The FPGA generates a CCLK from the internal timing generator
and serializes the parallel input data for internal framing or for succeeding slaves on data out (DOUT). An output
HIGH on READY/BUSY pin indicates the completion of loading for each byte when the input register is ready for a
new byte. As with master modes, peripheral mode may also be used as a lead device for a daisy-chain of slave
devices.
+5 V
CONTROL ADDRESS
SIGNALS BUS
DATA
BUS
5 kW
8
M0
M1
PWRDWN
CCLK
D[7:0]
D[7:0]
*
*
DOUT
ADDRESS
DECODE
LOGIC
CS0
M2
HDC
LDC
GENERAL-
PURPOSE
USER I/O
+5 V
CS1
CS2
WS
OTHER
I/O PINS
RDY/BUSY
INIT
REPROGRAM
OC
D/P
RESET
5-3114(F)
Figure 23. Peripheral Mode
24
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Configuration Modes (continued)
Slave Mode
Slave mode provides a simple interface for loading the FPGA configuration as shown in Figure 24. Serial data is
supplied in conjunction with a synchronizing input clock. Most slave mode applications are in daisy-chain configu-
rations in which the data input is supplied by the previous FPGA’s data out, while the clock is supplied by a lead
device in master or peripheral mode. Data may also be supplied by a processor or other special circuits.
+5 V
M0 M1
PWRDWN
MICROCOMPUTER
5 kW
M2
CCLK
DIN
STRB
D0
*
*
DOUT
HDC
LDC
D1
D2
FPGA
GENERAL-
PURPOSE
USER I/O
+5 V
I/O PORT
D3
D4
D5
OTHER
I/O PINS
D/P
INIT
D6
D7
RESET
RESET
SYSTEM
RESET
5-3115(F)
Figure 24. Slave Mode
Lucent Technologies Inc.
25
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
program and the current length count has not reached
the full value. Additional data is passed through the
lead device and appears on the data out (DOUT) pin in
serial form. The lead device also generates the CCLK
to synchronize the serial output data and data in of
downstream FPGAs. Data is read in on DIN of slave
devices by the positive edge of CCLK and shifted out
the DOUT on the negative edge of CCLK. A parallel
master mode device uses its internal timing generator
to produce an internal CCLK of eight times its EPROM
address rate, while a peripheral mode device produces
a burst of eight CCLKs for each chip select and write-
strobe cycle. The internal timing generator continues to
operate for general timing and synchronization of
inputs in all modes.
Configuration Modes (continued)
Daisy Chain
The ORCA Foundry for ATT3000 Development System
is used to create a composite configuration bit stream
for selected FPGAs including a preamble, a length
count for the total bit stream, multiple concatenated
data programs, a postamble, plus an additional fill bit
per device in the serial chain. After loading and passing
on the preamble and length count to a possible daisy
chain, a lead device will load its configuration data
frames while providing a high DOUT to possible down-
stream devices as shown in Figure 25. Loading contin-
ues while the lead device has received its configuration
+5 V
+5 V
+5 V
+5 V
M0 M1
M0 M1
M0 M1
PWRDWN
PWRDWN
PWRDWN
5 kW
5 kW
5 kW
CCLK
DIN
CCLK
DIN
CCLK
DOUT
M2
DOUT
M2
DOUT
M2
HDC
LDC
RCLK
FPGA
FPGA
SLAVE #n
A15
A14
A13
A12
A15
A14
A13
A12
A11
A10
A9
GENERAL-
PURPOSE
USER I/O
PINS
SLAVE #1
HDC
LDC
HDC
LDC
GENERAL-
PURPOSE
USER I/O
GENERAL-
PURPOSE
USER I/O
EPROM
OTHER
OTHER
I/O PINS
I/O PINS
OTHER
I/O PINS
A11
A10
A9
D/P
RESET
D/P
INIT
INIT
RESET
FPGA
MASTER
A8
A8
D7
D6
D5
D4
D3
A7
A7
D7
A6
A6
D6
D5
D4
D3
A5
A5
A4
A4
A3
A3
D2
D1
D0
A2
A1
A2
A1
A0
OE
CE
D2
D1
D0
A0
D/P
+5 V
RESET
INIT
8
5 kWEACH
OPEN COLLECTOR
REPROGRAM
SYSTEM
RESET
5-3116(F)
Figure 25. Master Mode with Daisy-Chained Slave Mode Devices
26
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Readback
Special Configuration Functions
The configuration data includes control over several
special functions in addition to the normal user logic
functions and interconnects:
The contents of an FPGA may be read back if it has
been programmed with a bit stream in which the read-
back option has been enabled. Readback may be used
for verification of configuration and as a method for
determining the state of internal logic nodes. There are
three options in generating the configuration bit stream:
■ Input thresholds
■ Readback enable
■ DONE pull-up resistor
■ DONE timing
■ Never will inhibit the readback capability.
■ One-time will inhibit readback after one readback
has been executed to verify the configuration.
■ RESET timing
■ On-command will allow unrestricted use of read-
back.
■ Oscillator frequency divided by two
Each of these functions is controlled by configuration
data bits which are selected as part of the normal
development system bit stream generation process.
Readback is accomplished without the use of any of
the user I/O pins; only M0, M1, and CCLK are used.
The initiation of readback is produced by a low-to-high
transition of the M0/RTRIG (read trigger) pin. Once the
readback command has been given, the input CCLK is
driven by external logic to read back each data bit in a
format similar to loading. After two dummy bits, the first
Input Thresholds
Prior to the completion of configuration, all FPGA input
thresholds are TTL compatible. Upon completion of
configuration, the input thresholds become either TTL
or CMOS compatible as programmed. The use of the
TTL threshold option requires some additional supply
current for threshold shifting. The exception is the
threshold of the PWRDWN input and direct clocks which
always have a CMOS input. Prior to the completion of
configuration, the user I/O pins each have a high-
impedance pull-up. The configuration program can be
used to enable the IOB pull-up resistors in the opera-
tional mode to act either as an input load or to avoid a
floating input on an otherwise unused pin.
data frame is shifted out on the M1/RDATA (read data)
pin. The logic polarity of the readback data is always
inverted, such that a zero in configuration becomes a
one in readback and vice versa. Each readback frame
has one start bit and one stop bit per frame (configura-
tion writes at least 3 stop bits per frame). All data
frames must be read back to complete the process and
return the mode select and CCLK pins to their normal
functions.
The readback data includes the current state of each
internal logic block storage element, and the state of
the input (.i and .ri) connection pins on each IOB. The
data is imbedded into unused configuration bit posi-
tions during readback. This state information is used by
the FPGA development system in-circuit verifier to pro-
vide visibility into the internal operation of the logic
while the system is operating. To read back a uniform
time sample of all storage elements, it may be neces-
sary to inhibit the system clock.
Lucent Technologies Inc.
27
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
DONE Timing
Special Configuration Functions
(continued)
The timing of the DONE status signal can be controlled
by a selection in the bit stream generation program to
occur a CCLK cycle before, or after, the timing of out-
puts being activated (see Figure 20). This facilitates
control of external functions, such as a PROM enable
or holding a system in a wait-state.
Reprogram
The FPGA configuration memory can be rewritten
while the device is operating in the user’s system. To
initiate a reprogramming cycle, the dual-function pack-
age pin DONE/PROG must be given a high-to-low tran-
sition. To reduce sensitivity to noise, the input signal is
filtered for two cycles of the FPGA’s internal timing gen-
erator. When reprogram begins, the user-programma-
ble I/O output buffers are disabled and high-impedance
pull-ups are provided for the package pins. The device
returns to the clear state and clears the configuration
memory before it prompts INITIALIZED. Since this
clear operation uses chip-individual internal timing, the
master might complete the clear operation and then
start configuration before the slave has completed the
clear operation. To avoid this, wire-AND the slave INIT
pins and use them to force a RESET on the master (see
Figure 25). Reprogram control is often implemented by
using an external open-collector driver which pulls
DONE/PROG low. Once it recognizes a stable request,
the FPGA will hold a low until the new configuration has
been completed. Even if the reprogram request is
externally held low beyond the configuration period, the
FPGA will begin operation upon completion of configu-
ration.
RESET Timing
As with DONE timing, the timing of the release of the
internal RESET can be controlled by a selection in the
bit stream generation program to occur a CCLK cycle
before, or after, the timing of outputs being enabled
(see Figure 20). This reset maintains all user-program-
mable flip-flops and latches in a zero state during con-
figuration.
Crystal Oscillator Division
A selection in the bit stream generation program allows
the user to incorporate a dedicated divide-by-two flip-
flop in the crystal oscillator function. This provides
higher assurance of a symmetrical timing signal.
Although the frequency stability of crystal oscillators is
high, the symmetry of the waveform can be affected by
bias or feedback drive.
DONE Pull-Up
DONE/PROG is an open-drain I/O pin that indicates the
FPGA is in the operational state. An optional internal
pull-up resistor can be enabled by the user of the devel-
opment system when the bit stream generation pro-
gram is executed. The DONE/PROG pins of multiple
FPGAs in a daisy chain may be connected together to
indicate that all are DONE or to direct them all to repro-
gram.
28
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
of internal worst-case timing are included in the
performance data to allow the user to make the best
use of the capabilities of the device. The ORCA
Foundry Development System timing calculator or
Performance
Device Performance
The high performance of the FPGA is due in part to the
manufacturing process, which is similar to that used for
high-speed CMOS static memories. Performance can
be measured in terms of minimum propagation times
for logic elements. The parameter which traditionally
describes the overall performance of a gate array is the
toggle frequency of a flip-flop. The configuration for
determining the toggle performance of the FPGA is
shown in Figure 26. The flip-flop output Q is fed back
through the combinatorial logic as Q to form the toggle
flip-flop.
ORCA Foundry-generated simulation models should
be used to calculate worst-case paths by using actual
impedance and loading information.
Figure 27 shows a variety of elements which are
involved in determining system performance. Table 20
gives the parameter values for the different speed
grades. Actual measurement of internal timing is not
practical, and often only the sum of component
timing is relevant as in the case of input to output. The
relationship between input and output timing is arbi-
trary, and only the total determines performance.
Timing components of internal functions may be deter-
mined by the measurement of differences at the pins of
the package. A synchronous logic function which
involves a clock to block-output and a block-input to
clock setup is capable of higher-speed operation than a
logic configuration of two synchronous blocks with an
extra combinatorial block level between them. System
clock rates to 60% of the toggle frequency are practical
for logic in which an extra combinatorial level is located
between synchronized blocks. This allows implementa-
tion of functions of up to 25 variables. The use of the
wired-AND is also available for wide, high-speed
functions.
D Q
CLOCK
5-3117(F)
Figure 26. Toggle Flip-Flop
FPGA performance is determined by the timing of
critical paths, including both the fixed timing for the
logic and storage elements in that path, and the timing
associated with the routing of the network. Examples
CLOCK TO
OUTPUT
COMBINATORIAL
SETUP
OP
T
TILO
TICK
TCKO
CLB
CLB
CLB
IOB
LOGIC
LOGIC
PAD
(K)
(K)
CLOCK
PAD
IOB
TCKO
TPID
TOKOP
5-3118(F)
Figure 27. Examples of Primary Block Speed Factors
Lucent Technologies Inc.
29
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
segment used for long lines exhibits low resistance
from end to end, but relatively high capacitance.
Signals driven through a programmable switch will
have the additional impedance of the switch added to
their normal drive impedance.
Performance (continued)
Logic Block Performance
Logic block performance is expressed as the propaga-
tion time from the interconnect point at the input of the
combinatorial logic to the output of the block in the
interconnect area. Combinatorial performance is inde-
pendent of the specific logic function because of the
table look-up based implementation. Timing is different
when the combinatorial logic is used in conjunction with
the storage element. For the combinatorial logic func-
tion driving the data input of the storage element, the
critical timing is data setup relative to the clock edge
provided to the flip-flop element. The delay from the
clock source to the output of the logic block is critical in
the timing of signals produced by storage elements.
Loading of a logic block output is limited only by the
resulting propagation delay of the larger interconnect
network. Speed performance of the logic block is a
function of supply voltage and temperature (see
Figures 28 and 29).
General-purpose interconnect performance depends
on the number of switches and segments used, the
presence of the bidirectional repowering buffers, and
the overall loading on the signal path at all points along
the path. In calculating the worst-case timing for a
general interconnect path, the timing calculator portion
of the ORCA Foundry Development System accounts
for all of these elements.
As an approximation, interconnect timing is propor-
tional to the summation of totals of local metal seg-
ments beyond each programmable switch. In effect, the
time is a sum of R-C time each approximated by an R
times the total C it drives. The R of the switch and the C
of the interconnect are functions of the particular
device performance grade.
For a string of three local interconnects, the approxi-
mate time at the first segment after the first switch
resistance would be three units—an additional two
units after the next switch plus an additional unit after
the last switch in the chain. The interconnect R-C chain
terminates at each repowering buffer. The capacitance
of the actual block inputs is not significant; the capaci-
tance is in the interconnect metal and switches.
Figure 30 illustrates this.
Interconnect Performance
Interconnect performance depends on the routing
resource used to implement the signal path. As dis-
cussed earlier, direct interconnect from block to block
provides a fast path for a signal. The single metal
30
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Performance (continued)
1.2
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.1
1.0
0.9
0.6
0.5
4.0
4.5
5.0
5.5
6.0
–55 –40
0
30
70 85
125
VCC
TEMPERATURE (°C)
5-3120(F)
5-3119(F)
Figure 28. Change in Speed Performance
Figure 29. Speed Performance of a CMOS Device
SWITCH MATRIX
R3
R2
REPOWERING
BUFFER
C1
C2
C3
C4
CLB
R1
TIMING: INCREMENTAL
R1(C1 + C2 + C3)
T1 = 3RC
+ R2(C2 + C3)
T2 = 3RC + 2RC
= 5RC
+ R3 + C3
6RC + BUFFER
IF R1 = R2 = R3 = R AND C1 = C2 = C3 = C,
THEN CUMULATIVE TIMING
T3 = 3RC + 2RC + RC
= 6RC
= 3RC
5-3121(F)
Figure 30. Interconnection Timing Example
Lucent Technologies Inc.
31
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Output buffers which drive the specified 4 mA loads
under worst-case conditions may drive 25 to 30 times
this amount under best-case process conditions. Noise
can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in
the same direction. It may also be beneficial to locate
heavily loaded output buffers near the ground pads.
The IOB output buffers have a slew-limited mode which
should be used where output rise and fall times are not
speed critical.
Power
Power Distribution
Power for the FPGA is distributed through a grid to
achieve high noise immunity and isolation between
logic and I/O. Inside the FPGA, a dedicated VCC and
ground ring surrounding the logic array provides power
to the I/O drivers (see Figure 31 below). An indepen-
dent matrix of VCC and ground lines supplies the inte-
rior logic of the device. This power distribution grid
provides a stable supply and ground for all internal
logic, provided that the external package power pins
are all connected and appropriately decoupled. Typi-
cally, a 0.1 µF capacitor connected near the VCC and
ground pins of the package will provide adequate
decoupling.
Slew-limited outputs maintain their dc drive capability
but generate less external reflections and internal
noise. More than 32 fast outputs should not be switch-
ing in the same direction simultaneously.
GND
GROUND AND
VCC RING FOR
I/O DRIVERS
VCC
VCC
LOGIC POWER GRID
GND
5-3122(F)
Figure 31. FPGA Power Distribution
32
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Because the control storage of the FPGA is CMOS
static memory, its cells require a very low standby cur-
rent for data retention. In some systems, this low data
retention current characteristic can be used as a
method of preserving configurations in the event of a
primary power loss. The FPGA has built-in powerdown
logic which, when activated, will disable normal opera-
tion of the device and retain only the configuration data.
All internal operation is suspended and output buffers
are placed in their high-impedance state with no pull-
ups. Powerdown data retention is possible with a sim-
ple battery backup circuit, because the power require-
ment is extremely low. For retention at 2.4 V, the
Power (continued)
Power Dissipation
The FPGA exhibits the low power consumption charac-
teristic of CMOS ICs. The configuration option of TTL
chip input threshold requires power for the threshold
reference. The power required by the static memory
cells that hold the configuration data is very low and
may be maintained in a powerdown mode.
Typically, most of the power dissipation is produced by
external capacitive loads on the output buffers. This
load and frequency dependent power is 25 µW/pF/MHz
per output. Another component of I/O power is the dc
loading on each output pin by devices driven by the
FPGA.
required current is typically on the order of 50 nA.
To force the FPGA into the powerdown state, the user
must pull the PWRDWN pin low and continue to supply
a retention voltage to the VCC pins of the package.
When normal power is restored, VCC is elevated to its
normal operating voltage and PWRDWN is returned to a
high. The FPGA resumes operation with the same
internal sequence that occurs at the conclusion of
configuration. Internal I/O and logic block storage ele-
ments will be reset, the outputs will become enabled,
and the DONE/PROG pin will be released. No configu-
ration programming is involved.
Internal power dissipation is a function of the number
and size of the nodes, and the frequency at which they
change. In an FPGA, the fraction of nodes changing on
a given clock is typically low (10% to 20%). For
example, in a large binary counter, the average clock
cycle produces changes equal to one CLB output at
the clock frequency. Typical global clock buffer power is
between 1.7 mW/MHz for the ATT3020 and 3.5 mW/
MHz for the ATT3090. The internal capacitive load is
more a function of interconnect than fan-out. With a
typical load of three general interconnect segments,
each configurable logic block output requires about
0.22 mW/MHz of its output frequency:
When the power supply is removed from a CMOS
device, it is possible to supply some power from an
input signal. The conventional electrostatic input pro-
tection is implemented with diodes to the supply and
ground. A positive voltage applied to an I/O will cause
the positive protection diode to conduct and drive the
power pin. This condition can produce invalid power
conditions and should be avoided. A large series resis-
tor might be used to limit the current or a bipolar buffer
may be used to isolate the input signal.
Total Power = VCC + ICCO + External
(dc + Capacitive) + Internal
(CLB + IOB + Long Line + Pull-up)
Lucent Technologies Inc.
33
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Information
Table 4. Permanently Dedicated Pins
Symbol
Name/Description
VCC
Two to eight (depending on package type) connections to the nominal +5 V supply voltage. All
must be connected.
GND
Two to eight (depending on package type) connections to ground. All must be connected.
PWRDWN
A low on this CMOS compatible input stops all internal activity to minimize VCC power, and puts
all output buffers in a high-impedance state; configuration is retained. When the PWRDWN pin
returns high, the device returns to operation with the same sequence of buffer enable and
DONE/PROG as at the completion of configuration. All internal storage elements are reset. If
not used, PWRDWN must be tied to VCC.
RESET
This is an active-low input which has three functions:
■ Prior to the start of configuration, a low input will delay the start of the configuration process.
An internal circuit senses the application of power and begins a minimal time-out cycle. When
the time-out and RESET are complete, the levels of the M lines are sampled and configuration
begins.
■ If RESET is asserted during a configuration, the FPGA is reinitialized and will restart the con-
figuration at the termination of RESET.
■ If RESET is asserted after configuration is complete, it will provide an asynchronous reset of all
IOB and CLB storage elements of the FPGA.
CCLK
Configuration Clock. During configuration, this is an output of an FPGA in master mode or
peripheral mode. FPGAs in slave mode use it as a clock input. During a readback operation, it is
a clock input for the configuration data being filtered out.
DONE/
PROG
DONE Output. Configurable as open drain with or without an internal pull-up resistor. At the
completion of configuration, the circuitry of the FPGA becomes active in a synchronous order,
and DONE may be programmed to occur one cycle before or after that occurs. Once configura-
tion is done, a high-to-low transition of this pin will cause an initialization of the FPGA and start a
reconfiguration.
M0/RTRIG
M1/RDATA
Mode 0. This input, M1, and M2 are sampled before the start of configuration to establish the
configuration mode to be used. After configuration is complete, a low-to-high transition acts as a
read trigger to initiate a readback of configuration and storage-element data clocked by CCLK.
Mode 1. This input, M0, and M2 are sampled before the start of configuration to establish the
configuration mode to be used. After configuration is complete, this pin is the active-low output of
the readback data.
34
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Information (continued)
Table 5. I/O Pins with Special Functions
Symbol
Name/Description
M2
HDC
LDC
Mode 2. This input has a passive pull-up during configuration. Together with M0 and M1, it is
sampled before the start of configuration to establish the configuration mode to be used. After
configuration, this pin becomes a user-programmable I/O pin.
High During Configuration. HDC is held at a high level by the FPGA until after configuration. It
is available as a control output indicating that configuration is not yet completed. After
configuration, this pin is a user I/O pin.
Low During Configuration. This active-low signal is held at a low level by the FPGA until after
configuration. It is available as a control output indicating that configuration is not yet completed.
It is particularly useful in master mode as a low enable for an EPROM. After configuration, this
pin is a user I/O pin. If used as a low EPROM enable, it must be programmed as a high after
configuration.
INIT
This is an active-low, open-drain output which is held low during the power stabilization and
internal clearing of the configuration memory. It can be used to indicate status to a configuring
microprocessor or, as a wired-AND of several slave mode devices, a hold-off signal for a master
mode device. After configuration, this pin becomes a user-programmable I/O pin.
BCLKIN
XTL1
This is a direct CMOS level input to the alternate clock buffer (auxiliary buffer) in the lower right
corner.
This user I/O pin can be used to operate as the output of an amplifier driving an external crystal
and bias circuitry.
XTL2
This user I/O pin can be used as the input of an amplifier connected to an external crystal and
bias circuitry. The I/O block is left unconfigured. The oscillator configuration is activated by
routing a net from the oscillator buffer symbol output and by the ORCA Foundry bit stream
generation program.
CS0, CS1,
CS2, WS
These four inputs represent a set of signals, three active-low and one active-high, which are
used in the peripheral mode to control configuration data entry. The assertion of all four
generates a write to the internal data buffer. The removal of any assertion clocks in the D[7:0]
data present. In the master parallel mode,WS and CS2 are the A0 and A1 outputs. After
configuration, the pins are user-programmable I/O pins.
Lucent Technologies Inc.
35
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Information (continued)
Table 5. I/O Pins with Special Functions (continued)
Symbol
Name/Description
During master parallel mode configuration, RCLK represents a read of an external dynamic
RCLK
memory device (normally not used).
RDY/BUSY
During peripheral parallel mode configuration, this pin indicates when the chip is ready for
another byte of data to be written to it. After configuration is complete, this pin becomes a user-
programmed I/O pin.
D[7:0]
A[15:0]
DIN
This set of eight pins represents the parallel configuration byte for the parallel master and
peripheral modes. After configuration is complete, they are user-programmed I/O pins.
This set of 16 pins presents an address output for a configuration EPROM during master parallel
mode. After configuration is complete, they are user-programmed I/O pins.
This user I/O pin is used as serial data input during slave or master serial configuration. This pin
is data zero input in master or peripheral configuration mode.
DOUT
This user I/O pin is used during configuration to output serial configuration data for daisy-
chained slaves’ data in.
TCLKIN
I/O
This is a direct CMOS level input to the global clock buffer.
Input/Output (Unrestricted). May be programmed by the user to be input and/or output pin
following configuration. Some of these pins present a high-impedance pull-up (see next page) or
perform other functions before configuration is complete (see above).
36
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Information (continued)
Table 6A. ATT3000 Family Configuration (44, 68, and 84 PLCC; 100 QFP; and 100 TQFP)
Configuration Mode (M2:M1:M0)
44
PLCC*
68
PLCC
84
PLCC
100
QFP
100
TQFP
User
Operation
†
Slave
(1:1:1)
Master-Serial Peripheral Master-High Master-Low
(0:0:0)
(1:0:1)
(1:1:0)
(1:0:0)
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
7
10
18
25
26
27
28
30
34
35
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
1
12
22
31
32
33
34
36
42
43
53
54
55
56
57
58
60
61
62
64
65
66
67
70
71
72
73
74
75
76
77
78
81
82
83
84
1
29
41
52
54
56
57
59
65
66
76
78
80
81
82
83
87
88
89
91
92
93
94
98
99
100
1
26
38
49
51
53
54
56
62
63
73
75
77
78
79
80
84
85
86
88
89
90
91
95
96
97
98
99
2
12
16
17
18
19
20
22
23
26
27
28
—
30
—
—
—
—
34
—
—
—
—
—
38
39
40
—
—
—
—
—
—
—
—
1
VCC
RDATA
M1 (High)
M0 (High)
M2 (High)
M1 (Low)
M0 (Low)
M2 (Low)
M1 (Low)
M0 (Low)
M2 (High)
HDC (High)
LDC (Low)
M1 (High)
M0 (High)
M2 (High)
HDC (High)
LDC (Low)
M1 (Low)
M0 (Low)
M2 (Low)
HDC (High)
LDC (Low)
RTRIG
I/O
HDC (High) HDC (High)
LDC (Low) LDC (Low)
I/O
I/O
‡
INIT
‡
INIT
‡
INIT
‡
INIT
‡
INIT
I/O
GND
GND
GND
GND
GND
GND
XTL2–I/O
RESET
PROG
RESET
DONE
RESET
DONE
RESET
DONE
D7
RESET
DONE
D7
RESET
DONE
D7
I/O
XTL1–I/O
I/O
D6
D5
D6
D5
D6
D5
I/O
CS0
—
—
I/O
D4
VCC
D3
D4
D4
I/O
VCC
VCC
VCC
D3
VCC
D3
VCC
I/O
CS1
—
—
I/O
D2
D1
D2
D2
I/O
D1
RCLK
D1
RCLK
I/O
RDY/BUSY
D0
I/O
DIN
DIN
D0
DOUT
CCLK
A0
D0
DOUT
CCLK
A0
I/O
DOUT
CCLK
DOUT
CCLK
DOUT
CCLK
WS
I/O
2
CCLK
I/O
5
CS2
A1
A1
6
3
I/O
A2
A2
8
5
I/O
A3
A3
9
6
I/O
A15
A4
A15
A4
12
13
14
15
16
17
18
19
20
23
24
25
26
9
I/O
10
11
12
13
14
15
16
17
20
21
22
23
I/O
A14
A5
A14
A5
I/O
I/O
GND
GND
GND
GND
A13
A6
GND
A13
A6
GND
I/O
—
—
—
—
—
—
—
—
2
2
3
3
I/O
A12
A7
A12
A7
4
4
I/O
5
5
I/O
A11
A8
A11
A8
6
8
I/O
7
9
I/O
A10
A9
A10
A9
8
10
11
I/O
9
I/O
Represents a 50 kWto 100 kWpull-up.
*
†
‡
Peripheral mode and master parallel mode are not supported in the 44-pin PLCC package; see Table 7.
Pin assignments for the ATT3064/ATT3090 differ from those shown; see page 42.
INIT is an open-drain output during configuration.
Lucent Technologies Inc.
37
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Information (continued)
Table 6B. ATT3000 Family Configuration (132 PPGA, 144 TQFP, 160 QFP, 175 PPGA, 208 SQFP)
Configuration Mode (M2:M1:M0)
132
PPGA
144
TQFP
160
QFP
175
PPGA
208
SQFP
User
Operation
Slave
(1:1:1)
Master-Serial Peripheral Master-High Master-Low
(0:0:0)
(1:0:1)
(1:1:0)
(1:0:0)
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
VCC
PWRDWN
A1
C8
1
159
20
B2
D9
3
19
26
VCC
RDATA
M1 (High)
M0 (High)
M2 (High)
M1 (Low)
M0 (Low)
M2 (Low)
M1 (Low)
M0 (Low)
M2 (High)
HDC (High)
LDC (Low)
INIT*
M1 (High)
M0 (High)
M2 (High)
HDC (High)
LDC (Low)
INIT*
M1 (Low)
M0 (Low)
M2 (Low)
HDC (High)
LDC (Low)
INIT*
B13
A14
C13
B14
D14
G14
H12
M13
P14
N13
M12
P13
N11
M9
N9
36
40
B14
B15
C15
E14
D16
H15
J14
P15
R15
R14
N13
T14
P12
T11
R10
R9
48
38
42
50
RTRIG
I/O
40
44
56
HDC (High) HDC (High)
41
45
57
I/O
LDC (Low)
INIT*
LDC (Low)
INIT*
45
49
61
I/O
53
59
77
I/O
GND
GND
GND
GND
GND
55
19
25
GND
XTL2–I/O
RESET
PROG
69
76
100
102
107
109
110
115
122
123
128
130
132
133
138
145
146
151
152
153
161
162
165
166
172
173
178
179
182
184
185
192
193
199
200
203
204
RESET
DONE
RESET
DONE
RESET
DONE
D7
RESET
DONE
D7
RESET
DONE
D7
71
78
73
80
74
81
I/O
XTL1–I/O
I/O
75
82
D6
D5
D6
D5
D6
D5
78
86
84
92
I/O
CS0
—
—
85
93
I/O
D4
VCC
D3
D4
D4
N8
88
98
I/O
VCC
VCC
VCC
D3
VCC
D3
M8
N7
90
100
102
103
108
114
115
119
120
121
124
125
128
129
132
133
136
137
139
141
142
147
148
151
152
155
156
N9
VCC
I/O
92
P8
CS1
—
—
P6
93
R8
I/O
D2
D1
D2
D2
M6
M5
N4
96
R7
I/O
D1
RCLK
D1
RCLK
102
103
106
107
108
111
112
115
116
119
120
123
124
126
128
129
133
134
137
138
141
142
R5
I/O
RDY/BUSY
D0
P5
I/O
DIN
DIN
D0
DOUT
CCLK
A0
D0
DOUT
CCLK
A0
N2
R3
I/O
DOUT
CCLK
DOUT
CCLK
DOUT
CCLK
WS
M3
P1
N4
I/O
R2
CCLK
I/O
M2
N1
P2
CS2
A1
A1
M3
P1
I/O
A2
A2
L2
I/O
A3
A3
L1
N1
I/O
A15
A4
A15
A4
K1
M1
L2
I/O
J2
I/O
A14
A5
A14
A5
H1
K2
I/O
H2
K1
I/O
GND
GND
GND
GND
A13
A6
GND
A13
A6
H3
J3
GND
I/O
G2
G1
F2
H2
H1
I/O
A12
A7
A12
A7
F2
I/O
E1
E1
I/O
A11
A8
A11
A8
D1
D1
I/O
D2
C1
I/O
A10
A9
A10
A9
B1
E3
I/O
C2
C2
I/O
Represents a 50 kWto 100 kWpull-up.
INIT is an open-drain output during configuration.
*
38
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments
Table 7. ATT3030 44-Pin PLCC Pinout
Pin No.
Function
Pin No.
Function
1
2
GND
I/O
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
I/O
3
I/O
I/O
4
I/O
XTL2–I/O
RESET
5
I/O
6
I/O
DONE–PROG
PWRDWN
TCLKIN–I/O
I/O
7
I/O
8
XTL1–BCLKIN–I/O
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
M1–RDATA
M0–RTRIG
M2–I/O
HDC–I/O
LDC–I/O
I/O
DIN–I/O
DOUT–I/O
CCLK
I/O
I/O
I/O
INIT–I/O
I/O
Notes:
Peripheral mode and master parallel mode are not supported in the M44 package.
Parallel address and data pins are not assigned.
Lucent Technologies Inc.
39
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 8. ATT3020, ATT3030, and ATT3042; 68-Pin PLCC and 84-Pin PLCC Pinout*
Pin Numbers
Pin Numbers
Function
Function
68 PLCC 84 PLCC
68 PLCC 84 PLCC
PWRDWN
TCLKIN–I/O
I/O†
10
11
—
12
13
—
14
15
16
17
18
19
—
20
21
22
—
23
24
25
26
27
28
29
30
31
—
32
33
—
34
35
36
37
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
38
39
40
41
—
—
42
43
44
45
46
47
48
—
49
50
51
—
52
53
54
55
—
—
56
57
58
59
60
61
62
63
64
—
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
I/O
I/O
I/O
I/O
I/O
I/O†
I/O†
I/O
I/O
I/O
I/O
I/O
XTL2–I/O
RESET
I/O
I/O
DONE–PROG
D7–I/O
XTL1–BCLKIN–I/O
D6–I/O
I/O
VCC
I/O
I/O
I/O
I/O
D5–I/O
CS0–I/O
D4–I/O
I/O
I/O
I/O
I/O
I/O
VCC
M1–RDATA
M0–RTRIG
M2–I/O
HDC–I/O
I/O
D3–I/O
CS1–I/O
D2–I/O
I/O
I/O†
LDC–I/O
D1–I/O
RDY/BUSY–RCLK–I/O
D0–DIN–I/O
DOUT–I/O
CCLK
I/O
I/O†
I/O
I/O
I/O†
A0–WS–I/O
A1–CS2–I/O
A2–I/O
A3–I/O
I/O†
INIT–I/O
GND
I/O
I/O
* Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are
default slew-limited.
† Indicates unconnected package pins for the ATT3020.
40
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 8. ATT3020, ATT3030, and ATT3042; 68-Pin PLCC and 84-Pin PLCC Pinout* (continued)
Pin Numbers
Pin Numbers
Function
Function
68 PLCC 84 PLCC
68 PLCC 84 PLCC
—
65
66
67
68
1
80
81
82
83
84
1
I/O†
4
5
4
5
A12–I/O
A7–I/O
I/O†
A15–I/O
A4–I/O
A14–I/O
A5–I/O
GND
—
—
6
6
7
I/O†
8
A11–I/O
A8–I/O
A10–I/O
A9–I/O
7
9
2
2
A13–I/O
A6–I/O
8
10
11
3
3
9
* Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are
default slew-limited.
† Indicates unconnected package pins for the ATT3020.
Note: Table 8 describes the pin assignments for three different chips in two different packages. The function column lists 84 of the 118 pads on
the ATT3042 and 84 of the 98 pads on the ATT3030. Ten pads [indicated with a dagger (†)] do not exist on the ATT3020, which has
74 pads; therefore, the corresponding pins on the 84-pin packages have no connections to an ATT3020.
Lucent Technologies Inc.
41
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 9. ATT3064 and ATT3090 84-Pin PLCC Pinout
84
PLCC
84
PLCC
84
PLCC
Function
Function
Function
PWRDWN
TCLKIN–I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
I/O
INIT–I/O*
VCC*
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
D2–I/O*
I/O
D1–I/O
I/O
GND
RDY/BUSY–RCLK–I/O
D0–DIN–I/O
DOUT–I/O
CCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A0–WS–I/O
A1–CS2–I/O
A2–I/O
I/O
I/O
GND*
VCC
I/O
I/O
A3–I/O
I/O
I/O
I/O*
I/O
I/O
I/O*
I/O
XTL2–I/O
RESET
DONE–PROG
D7–I/O
XTL1–BCLKIN–I/O
D6–I/O
I/O
A15–I/O
A4–I/O
I/O
I/O
A14–I/O
A5–I/O
I/O
I/O
GND
I/O
2
VCC*
M1–RDATA
M0–RTRIG
M2–I/O
HDC–I/O
I/O
3
A13–I/O*
A6–I/O*
A12–I/O*
A7–I/O*
I/O
D5–I/O
CS0 –I/O
D4–I/O
I/O
4
5
6
7
LDC–I/O
I/O
VCC
8
A11–I/O
A8–I/O
GND*
D3–I/O*
CS1–I/O*
9
I/O
10
11
A10–I/O
A9–I/O
I/O
*
Different pin definition than ATT3020/ATT3030/ATT3042 PC84 package.
Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-limited.
42
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 10. ATT3020, ATT3030, and ATT3042 100-Pin QFP Pinout
100
QFP
100
QFP
100
QFP
Function
Function
Function
16
17
18
19
20
21
22
23
24
25
26
27*
28*
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
GND
A13–I/O
A6–I/O
A12–I/O
A7–I/O
I/O*
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77*
78
79
80
81
82
83
I/O*
I/O*
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
I/O*
I/O*
M1–RDATA
GND*
M0–RTRIG
VCC*
I/O
D5–I/O
CS0–I/O
D4–I/O
I/O
I/O*
M2–I/O
HDC–I/O
I/O
A11–I/O
A8–I/O
A10–I/O
A9–I/O
VCC
VCC
D3–I/O
CS1–I/O
D2–I/O
I/O
LDC–I/O
I/O*
I/O*
GND
PWRDWN
TCLKIN–I/O
I/O**
I/O*
I/O
I/O*
I/O
I/O*
I/O
D1–I/O
RCLK–RDY/BUSY–I/O
D0–DIN–I/O
DOUT–I/O
CCLK
INIT–I/O
GND
I/O*
I/O
I/O
I/O
2
I/O
I/O
3
VCC*
I/O
I/O
4
GND*
I/O
I/O
5
A0–WS–I/O
A1–CS2–I/O
I/O**
I/O
I/O
6
I/O
I/O
7
I/O
I/O*
8
A2–I/O
A3–I/O
I/O*
VCC
I/O*
9
I/O
XTL2–I/O
GND
10
11
12
13
14
15
—
—
I/O
I/O*
RESET
VCC*
I/O
A15–I/O
A4–I/O
A14–I/O
A5–I/O
—
I/O
I/O
DONE–PROG
D7–I/O
XTL1–BCLKIN–I/O
D6–I/O
I/O
I/O
I/O
—
* Only 100 of the 118 pads on the ATT3042 are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on
the ATT3030, which has 98 pads; therefore, the corresponding pins have no connections. Twenty-six pads, indicated by single or double
asterisks, do not exist on the ATT3020, which has 74 pads; therefore, the corresponding pins have no connections.
Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs
are default slew-limited.
Lucent Technologies Inc.
43
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 11. ATT3030, ATT3042, and ATT3064 100-Pin TQFP Pinout
100
TQFP
100
TQFP
100
TQFP
Function
Function
Function
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
GND
A13–I/O
A6–I/O
A12–I/O
A7–I/O
I/O
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
I/O
I/O
I/O
M1–RDATA
I/O
GND
D5–I/O
CS0–I/O
D4–I/O
I/O
M0–RTRIG
VCC
I/O
M2–I/O
A11–I/O
A8–I/O
A10–I/O
A9–I/O
VCC
HDC–I/O
VCC
I/O
D3–I/O
CS1–I/O
D2–I/O
I/O
LDC–I/O
I/O
I/O
GND
PWRDWN
TCLKIN–I/O
I/O*
I/O
I/O
I/O
I/O
I/O
D1–I/O
RCLK–RDY/BUSY–I/O
D0–DIN–I/O
DOUT–I/O
CCLK
INIT–I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
2
A0–WS–I/O
A1–CS2–I/O
I/O*
I/O
I/O
I/O
3
I/O
4
I/O
I/O
5
A2–I/O
A3–I/O
I/O
VCC
I/O
6
I/O
XTL2–I/O
GND
7
I/O
8
I/O
RESET
I/O
9
A15–I/O
A4–I/O
A14–I/O
A5–I/O
—
I/O
VCC
10
11
12
—
—
I/O
DONE–PROG
D7–I/O
XTL1–BCLKIN–I/O
D6–I/O
I/O
I/O
I/O
—
* Indicates unconnected package pins for the ATT3030.
Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs
are default slew-limited.
44
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 12. ATT3042 and ATT3064 132-Pin PPGA Pinout
132
PPGA
132
PPGA
132
PPGA
Function
Function
Function
C4
A1
C3
B2
B3
A2
B4
C5
A3
A4
B5
C6
A5
B6
A6
B7
C7
C8
A7
B8
A8
A9
B9
C9
A10
B10
A11
C10
B11
A12
B12
A13
C12
B13
C11
A14
D12
C13
B14
C14
E12
D13
D14
E13
GND
PWRDWN
TCLKIN–I/O
I/O
F12
E14
F13
F14
G13
G14
G12
H12
H14
H13
J14
J13
K14
J12
K13
L14
L13
K12
M14
N14
M13
L12
P14
M11
N13
M12
P13
N12
P12
N11
M10
P11
N10
P10
M9
I/O
I/O
I/O
I/O
N6
P5
M6
N5
P4
P3
M5
N4
P2
N3
N2
M3
P1
M4
L3
M2
N1
M1
K3
L2
L1
K2
J3
I/O*
I/O*
D2–I/O
I/O
I/O
I/O
I/O
I/O*
I/O
I/O
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O
I/O
I/O*
I/O
I/O*
I/O
I/O
INIT–I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O
D1–I/O
RCLK–RDY/BUSY–I/O
I/O
I/O
D0–DIN–I/O
DOUT–I/O
CCLK
VCC
GND
A0–WS–I/O
A1–CS2–I/O
I/O
I/O
I/O
I/O
I/O
A2–I/O
A3–I/O
I/O
XTL2–I/O
GND
RESET
VCC
I/O
K1
J2
J1
A15–I/O
A4–I/O
I/O*
A14–I/O
A5–I/O
GND
DONE–PROG
D7–I/O
XTL1–BCLKIN–I/O
I/O
H1
H2
H3
G3
G2
G1
F1
F2
E1
F3
E2
D1
D2
E3
C1
B1
C2
D3
I/O
D6–I/O
I/O
I/O*
I/O
VCC
A13–I/O
A6–I/O
I/O*
A12–I/O
A7–I/O
I/O
M1–RDATA
GND
M0–RTRIG
VCC
M2–I/O
HDC–I/O
I/O
I/O
I/O
LDC–I/O
I/O*
I/O
D5–I/O
CS0–I/O
I/O*
I/O*
D4–I/O
I/O
VCC
GND
D3–I/O
CS1–I/O
N9
P9
P8
N8
P7
M8
M7
N7
I/O
A11–I/O
A8–I/O
I/O
I/O
A10–I/O
A9–I/O
VCC
P6
* Indicates unconnected package pins for the ATT3030.
Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs
are default slew-limited.
Lucent Technologies Inc.
45
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 13. ATT3042 and ATT3064 144-Pin TQFP Pinout
144
TQFP
144
TQFP
144
TQFP
144
TQFP
Function
Function
Function
Function
1
2
3
4
5
6
7
8
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GND
M0–RTRIG
VCC
M2–I/O
HDC–I/O
I/O
I/O
I/O
LDC—I/O
I/O*
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
DONE—PROG
D7–I/O
XTL1–BCLKIN–I/O
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VCC
GND
A0–WS–I/O
A1–CS2–I/O
I/O
PWRDWN
TCLKIN—I/O
I/O*
I/O
I/O
I/O
D6–I/O
I/O
I/O*
I/O
I/O
I/O*
D5–I/O
CS0 –I/O
I/O*
I/O*
D4–I/O
I/O
I/O*
I/O
I/O
I/O*
I/O
I/O
I/O
I/O
I/O
I/O*
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
A2–I/O
A3–I/O
I/O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O
I/O
I/O
I/O
I/O*
A15–I/O
A4–I/O
I/O*
I/O*
I/O
I/O
INIT–I/O
VCC
GND
I/O
A14–I/O
A5–I/O
—
GND
VCC
A13–I/O
A6–I/O
I/O*
—
I/O*
A12–I/O
A7–I/O
I/O
I/O
VCC
GND
D3—I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O*
I/O
I/O
I/O
I/O
CS1—I/O
I/O*
I/O*
D2—I/O
I/O
I/O
I/O*
I/O
I/O*
I/O
I/O
I/O
I/O*
I/O
98
99
100
101
102
103
104
105
106
107
108
I/O
A11–I/O
A8–I/O
I/O
I/O
D1—I/O
RCLK—BUSY/RDY—I/O
I/O
I/O*
I/O*
I/O
I/O*
I/O
I/O
I/O
A10–I/O
A9–I/O
VCC
XTL2—I/O
GND
RESET
VCC
D0—DIN—I/O
DOUT–I/O
CCLK
M1–RDATA
GND
* Indicates unconnected package pins for the ATT3042.
Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs
are default slew-limited.
46
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 14. ATT3064 and ATT3090 160-Pin QFP Pinout
160
QFP
160
QFP
160
QFP
160
QFP
Function
Function
Function
Function
1
2
3
4
5
6
7
8
I/O*
I/O*
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
M0–RTRIG
VCC
M2–I/O
HDC–I/O
I/O
I/O
I/O
LDC–I/O
I/O*
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
D7–I/O
XTL1–BCLKIN–I/O
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
CCLK
VCC
GND
I/O*
I/O
I/O
D6–I/O
A0–WS–I/O
A1–CS2–I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2–I/O
A3–I/O
I/O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D5–I/O
CS0 – I/O
A15–I/O
A4–I/O
I/O
I/O*
I/O*
I/O
I/O
D4–I/O
I/O
VCC
GND
I/O
A14–I/O
A5–I/O
I/O*
GND
VCC
A13–I/O
A6–I/O
I/O*
98
99
INIT–I/O
VCC
GND
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
D3–I/O
CS1–I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O*
I/O*
I/O
I/O
A12–I/O
A7–I/O
I/O
D2–I/O
I/O
I/O
I/O
I/O
I/O
A11–I/O
A8–I/O
I/O
I/O
D1–I/O
RCLK–RDY/BUSY–I/O
I/O
I/O
I/O*
A10–I/O
A9–I/O
VCC
GND
PWRDWN
TCLKIN–I/O
XTL2–I/O
GND
RESET
VCC
I/O
I/O
I/O*
D0–DIN–I/O
DOUT–I/O
I/O*
I/O*
M1–RDATA
DONE– PROG
* Indicates unconnected package pins for the ATT3064.
Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs
are default slew-limited.
Lucent Technologies Inc.
47
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 15. ATT3000 Family 175-Pin PPGA Pinout
175
PPGA
175
PPGA
175
PPGA
175
PPGA
Function
Function
Function
Function
B2
D4
B3
C4
B4
A4
D5
C5
B5
A5
C6
D6
B6
A6
B7
C7
D7
A7
A8
B8
C8
D8
D9
C9
B9
D13
I/O
M1–RDATA
GND
M0–RTRIG
VCC
M2–I/O
HDC–I/O
I/O
I/O
I/O
LDC–I/O
I/O
R14
N13
T14
P13
R13
T13
N12
P12
R12
T12
P11
N11
R11
T11
R10
P10
N10
T10
T9
R9
P9
N9
N8
P8
R8
T8
T7
N7
P7
R7
T6
R6
N6
P6
T5
R5
P5
N5
T4
R4
P4
—
DONE–PROG
R3
N4
R2
P3
N3
P2
M3
R1
N2
P1
N1
L3
D0–DIN–I/O
DOUT–I/O
CCLK
VCC
PWRDWN
TCLKIN–I/O B14
D7–I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C14
B15
D14
C15
E14
B16
D15
C16
D16
F14
E15
E16
F15
F16
G14
G15
G16
H16
H15
H14
J14
XTL1–BCLKIN–I/O
I/O
I/O
I/O
I/O
D6–I/O
I/O
I/O
I/O
I/O
I/O
D5–I/O
CS0–I/O
GND
A0–WS–I/O
A1–CS2–I/O
I/O
I/O
A2–I/O
A3–I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M2
M1
L2
I/O
A15–I/O
A4–I/O
I/O
I/O
I/O
I/O
I/O
L1
K3
K2
K1
J1
J2
J3
I/O
A14–I/O
A5–I/O
I/O
I/O
GND
D4–I/O
I/O
VCC
GND
D3–I/O
CS1–I/O
INIT–I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H3
H2
H1
G1
G2
G3
F1
F2
E1
E2
F3
D1
C1
D2
B1
E3
C2
D3
C3
—
VCC
J15
J16
A13–I/O
A6–I/O
I/O
A9
K16
K15
K14
L16
L15
M16
M15
L14
N16
P16
N15
R16
M14
P15
N14
R15
P14
I/O
I/O
I/O
I/O
A10
D10
C10
B10
A11
B11
D11
C11
A12
B12
C12
D12
A13
B13
C13
A14
I/O
I/O
I/O
D2–I/O
A12–I/O
A7–I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1–I/O
I/O
A11–I/O
A8–I/O
I/O
I/O
RDY/BUSY–RCLK–I/O
I/O
I/O
I/O
I/O
—
A10–I/O
A9–I/O
VCC
GND
—
XTL2–I/O
GND
RESET
VCC
Note:Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-limited. Pins A2, A3, A15, A16, T1, T2, T3, T15, and T16 are not connected. Pin A1 does not exist.
48
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Pin Assignments (continued)
Table 16. ATT3000 Family 208-Pin SQFP Pinout
208
208
208
208
SQFP
Function
SQFP
Function
—
SQFP
Function
SQFP
Function
—
1
2
3
4
5
6
7
8
—
GND
PWRDWN
TCLKIN–I/O
I/O
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
—
VCC
DONE–PROG
—
D7–I/O
XTL1–BCLKIN–I/O
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
—
—
—
VCC
M2–I/O
HDC–I/O
I/O
I/O
I/O
LDC –I/O
I/O
GND
A0–WS–I/O
A1–CS2–I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
D6–I/O
I/O
I/O
I/O
—
I/O
I/O
D5–I/O
I/O
9
A2–I/O
A3–I/O
I/O
I/O
—
—
—
A15–I/O
A4–I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
—
—
—
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
CS0–I/O
I/O
—
—
I/O
I/O
I/O
I/O
D4–I/O
I/O
VCC
GND
A14–I/O
A5–I/O
I/O
INIT–I/O
VCC
GND
I/O
I/O
GND
VCC
A13–I/O
A6–I/O
I/O
D3–I/O
CS1–I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D2–I/O
I/O
I/O
I/O
—
I/O
I/O
D1–I/O
I/O
—
—
I/O
I/O
A12–I/O
A7–I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
RDY/BUSY–RCLK–I/O
I/O
I/O
I/O
A11–I/O
A8–I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D0–DIN–I/O
DOUT–I/O
CCLK
VCC
A10–I/O
A9–I/O
VCC
—
M1–RDATA
GND
M0–RTRIG
—
XTL2–I/O
GND
RESET
—
—
—
—
—
—
—
Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs
are default slew-limited.
Lucent Technologies Inc.
49
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Package Thermal Characteristics
TJ – TA
-------------------
QC
QJA =
When silicon die junction temperature is below the rec-
ommended junction temperature of 125 °C, the
where:
temperature-activated failure mechanisms are mini-
mized. There are four major factors that affect the ther-
mal resistance value: silicon device size/paddle size,
board-mounting configuration (board density, multilayer
nature of board), package type and size, and system
airflow over the package. The values in the table below
reflect the capability of the various package types to
dissipate heat at given airflow rates. The numbers rep-
resent the delta °C/W between the ambient tempera-
ture and the device junction temperature.
TJ = peak temperature on the active surface of the IC
TA = ambient air temperature
QC = IC power
The tests are repeated at several velocities from 0 fpm
(feet per minute) to 1000 fpm.
The definition of the junction to case thermal resistance
QJC is:
To test package thermal characteristics, a single pack-
age containing a 0.269 in. sq. test IC of each configura-
tion is mounted at the center of a printed-circuit board
(PCB) measuring 8 in. x 13 in. x 0.062 in. The assem-
bled PCB is mounted vertically in the center of the rect-
angular test section of a wind tunnel. The walls of the
wind tunnel simulate adjacent boards in the electronic
rack and can be adjusted to study the effects of PCB
spacing. Forced air at room temperature is supplied by
a pair of push-pull blowers which can be regulated to
supply the desired air velocities. The air velocity is
measured with a hot-wire anemometer at the center of
the channel, 3 in. upstream from the package.
TJ – TC
QC
Q JC =
-------------------
where:
TC = temperature measured to the thermocouple at
the top dead center of the package
The actual QJC measurement performed at Lucent,
QJ – TDC, uses a different package mounting arrange-
ment than the one defined for QJC in MIL-STD-883D
and SEMI standards. Please contact Lucent for a dia-
gram.
The maximum power dissipation for a package is cal-
culated from the maximum junction temperature, maxi-
mum operating temperature, and the junction to
ambient characteristic QJA. The maximum power dissi-
pation for commercial grade ICs is calculated as fol-
lows: max power (watts) = (125 °C – 70 °C) x (1/QJA),
where 125 °C is the maximum junction temperature.
Table 17 lists the ATT3000 plastic package thermal
characteristics.
A typical test consists of regulating the wind tunnel
blowers to obtain the desired air velocity and applying
power to the test IC. The power to the IC is adjusted
until the maximum junction temperature (as measured
by its diodes) reaches 115 °C to 120 °C. The thermal
resistance QJA (°C/W) is computed by using the power
supplied to the IC, junction temperature, ambient tem-
perature, and air velocity:
50
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Package Thermal Characteristics (continued)
Table 17. ATT3000 Plastic Package Thermal Characteristics
QJA (°C/W)
Package
QJC
(°C/W)
Max Power
(70 °C—0 fpm)
0 fpm
49
200 fpm
43
400 fpm
40
44-Pin PLCC
68-Pin PLCC
84-Pin PLCC
100-Pin QFP
100-Pin TQFP
132-Pin PPGA
144-Pin TQFP
160-Pin QFP
175-Pin PPGA
208-Pin SQFP
—
11
9
1.12 W
1.28 W
1.38 W
0.68 W
0.90 W
2.50 W
1.06 W
1.38 W
2.39 W
1.49 W
43
38
35
40
35
32
81
67
64
11
6
61
49
46
22
18
16
—
4
52
39
36
40
36
32
8
23
20
17
—
8
37
33
29
capacitances in pF are listed: CM, the mutual capaci-
tance of the lead to the nearest neighbor lead; and C1
and C2, the total capacitance of the lead to all other
leads (all other leads are assumed to be grounded).
These parameters are important in determining capaci-
tive crosstalk and the capacitive loading effect of the
lead.
Package Coplanarity
The coplanarity of Lucent Technologies postmolded
packages is 4 mils. The coplanarity of the SQFP and
TQFP packages is 3.15 mils.
Package Parasitics
The parasitic values in Table 18 are for the circuit
model of bond wire and package lead parasitics. If the
mutual capacitance value is not used in the designer’s
model, then the value listed as mutual capacitance
should be added to each of the C1 and C2 capacitors.
The PGAs contain power and ground planes that will
make the inductance value for power and ground leads
the minimum value listed. The PGAs also have a signif-
icant range of parasitic values. This is due to the large
variation in internal trace lengths and is also due to two
signal metal layers that are separated from the ground
plane by different distances. The upper signal layer is
more inductive but less capacitive than the closer,
lower signal layer.
The electrical performance of an IC package, such as
signal quality and noise sensitivity, is directly affected
by the package parasitics. Table 18 lists eight parasitics
associated with the ATT3000 packages. These parasit-
ics represent the contributions of all components of a
package, which include the bond wires, all internal
package routing, and the external leads.
Four inductances in nH are listed: LW and LL, the self-
inductance of the lead; and LMW and LML, the mutual
inductance to the nearest neighbor lead. These
parameters are important in determining ground
bounce noise and inductive crosstalk noise. Three
Lucent Technologies Inc.
51
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Package Parasitics (continued)
Table 18. Package Parasitics
Package Type
LW
MW
RW
C1
C2
CM
LL
ML
44-Pin PLCC
68-Pin PLCC
84-Pin PLCC
100-Pin QFP
100-Pin TQFP
132-Pin PPGA
144-Pin TQFP
160-Pin QFP
175-Pin PPGA
208-Pin SQFP
3
3
3
3
3
3
3
4
3
4
1
1
140
140
140
160
150
150
140
180
150
200
0.5
0.5
1
0.5
0.5
1
0.3
0.4
0.5
0.5
0.4
0.25
0.6
1
5—6
6—9
2—2.5
3—4
1
7—11
7—9
3—6
1
1
1
4—5
1
0.5
1
0.5
1
4—6
2—3
1
4—10
4—6
0.5—1
2—2.5
6—8
1
1
1
1.5
1
1.5
1
1.5
1
10—13
5—11
7—10
0.3
1
1—1.5
4—6
2
1
1
* Leads designated as ground (power) can be connected to the ground plane, reducing the trace inductance to the minimum value listed.
CIRCUIT
BOARD PAD
C2
LW
RW
LL
PAD N
C1
LMW
LW
LML
LL
CM
PAD N + 1
RW
C1
C2
5-3862(C)
Figure 32. Package Parasitics
52
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Symbol
Min
Max
Unit
Supply Voltage Relative to GND
Input Voltage Relative to GND
Voltage Applied to 3-state Output
Storage Temperature (ambient)
VCC
VIN
–0.5
–0.5
–0.5
–65
—
7.0
0.5
V
V
VTS
Tstg
TSOL
0.5
V
150
260
°C
°C
Maximum Soldering Temperature
(10 seconds at 1/16 in.)
Junction Temperature
TJ
—
125
°C
Lucent Technologies Inc.
53
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics
Table 19. dc Electrical Characteristics Over Operating Conditions
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
-50, -70, -100, and -125
-3, -4, and -5
Parameter/Conditions
High-level Input Voltage
Symbol
Unit
Min
Max
Min
Max
CMOS Level
TTL Level
70%
2.0
100%
VCC
70%
2.0
100%
VCC
V
V
VIHC
VIHT
Low-level Input Voltage
CMOS Level
TTL Level
0
0
20%
0.8
0
0
20%
0.8
VILC
VILT
V
V
Output Voltage
High
(IOH = –4 mA)
(IOH = –8 mA)
Low
3.86
—
—
—
—
3.86
—
—
V
V
VOH
VOH
(IOL = 4 mA)
(IOL = 8 mA)
—
—
0.40
—
—
—
—
0.40
V
V
VOL
VOL
Input Signal Transition Time
Powerdown Supply Current
ATT3020
ATT3030
ATT3042
—
250
—
250
TIN
ICCPD
ns
—
—
—
—
—
50
80
120
170
250
—
—
—
—
—
50
80
120
170
250
µA
µA
µA
µA
µA
ATT3064
ATT3090
Quiescent FPGA Supply Current
(in addition to ICCPD)
CMOS Inputs
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
TTL Inputs
Leakage Current
Input Capacitance*
All Packages Except 175-PGA:
All Pins Except XTL1/XTL2
XTL1 and XTL2
ICCO
—
—
—
—
—
—
—
–10
10
500
500
500
500
500
20
mA
µA
µA
µA
µA
µA
mA
µA
—
—
—
—
—
500
500
500
500
500
10
—
–10
10
10
IIL
CIN
—
—
10
15
—
—
10
15
pF
pF
175-PGA Package:
All Pins Except XTL1/XTL2
XTL1 and XTL2
—
—
15
20
—
—
15
20
pF
pF
Pad Pull-up* (when selected)
(at VIN = 0 V)
Horizontal Long-line Pull-up (when
selected) at Logic LOW
IRIN
IRLL
0.02
0.2
0.17
2.5
0.02
0.2
0.17
2.8
mA
mA
* Sample tested.
Note: With no output current loads, no active input or long-line pull-up resistors, all package pins at VCC or GND, and the FPGA configured
with a bit stream generation program tie option.
54
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
Table 20. CLB Switching Characteristics (-50, -70, -100, and -125)
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
-50
-70
-100
-125
Description
Combinatorial Delay
Symbol
TILO
Unit
Min Max Min Max Min Max Min Max
1
—
14.0
—
9.0
—
7.0
—
5.5
ns
Sequential Delay
Clock K to Outputs x or y
Clock K to Outputs x or y when Q
Returned Through Function
Generators F or G to Drives x or y
8
—
TCKO
TQLO
—
—
12.0
23.0
—
—
6.0
13.0
—
—
5.0
10.0
—
—
4.5
8.0
ns
ns
Setup Time
Logic Variables
Data In
Enable Clock
Reset Direct Active
2
4
6
TICK
12.0
8.0
10.0
1.0
—
—
—
—
8.0
5.0
7.0
1.0
—
—
—
—
7.0
4.0
5.0
1.0
—
—
—
—
5.5
3.0
4.5
1.0
—
—
—
—
ns
ns
ns
ns
TDICK
TECCK
TRDCK
—
Hold Time
Logic Variables
Data In
Enable Clock
3
5
7
TCKI
TCKDI
TCKEC
1.0
6.0
0
—
—
—
0
4.0
0
—
—
—
0
2.0
0
—
—
—
0
1.5
0
—
—
—
ns
ns
ns
Clock
High Time*
Low Time*
Flip-Flop Toggle Rate*
11
12
—
TCH
TCL
FCLK
9.0
9.0
50
—
—
—
5.0
5.0
70
—
—
—
4.0
4.0
100
—
—
—
3.0
3.0
125
—
—
—
ns
ns
MHz
Reset Direct (rd)
rd Width
Delay from rd to Outputs x, y
13
9
TRPW
TRIO
12.0
—
—
12.0
8.0
—
—
8.0
7.0
—
—
7.0
6.0
—
—
6.0
ns
ns
Master Reset (MR)
MR Width
Delay from MR to Outputs x, y
—
—
TMRW
TMRQ
30
—
—
27
25
—
—
23
21
—
—
19
20
—
—
17
ns
ns
* These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.
Note: The CLB K to Q output delay (TCKO—#8) of any CLB, plus the shortest possible interconnect delay, is always longer than the data in
hold time requirement (TCKDI—#5) of any CLB on the same die.
Lucent Technologies Inc.
55
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
Table 21. CLB Switching Characteristics (-3, -4, and -5)
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
-5
-4
-3
Description
Combinatorial Delay
Symbol
Unit
Min
Max
Min
Max
Min
Max
1
TILO
—
4.1
—
3.3
—
2.7
ns
Sequential Delay
Clock K to Outputs x or y
Clock K to Outputs x or y when Q Returned
Through Function Generators F or G to
Drives x or y
8
—
TCKO
TQLO
—
—
3.1
6.3
—
—
2.5
5.2
—
—
2.1
4.3
ns
ns
Setup Time
Logic Variables
Data In
Enable Clock
Reset Direct Active
2
4
6
TICK
3.1
2.0
3.8
1.0
—
—
—
—
2.5
1.6
3.2
1.0
—
—
—
—
2.1
1.4
2.7
1.0
—
—
—
—
ns
ns
ns
ns
TDICK
TECCK
TRDCK
—
Hold Time
Logic Variables
Data In
Enable Clock
3
5
7
TCKI
TCKDI
TCKEC
0
1.2
1.0
—
—
—
0
1.0
0.8
—
—
—
0
0.9
0.7
—
—
—
ns
ns
ns
Clock
High Time*
Low Time*
Flip-Flop Toggle Rate*
11
12
—
TCH
TCL
FCLK
2.4
2.4
190
—
—
—
2.0
2.0
230
—
—
—
1.6
1.6
270
—
—
—
ns
ns
MHz
Reset Direct (rd)
rd Width
Delay from rd to Outputs x, y
13
9
TRPW
TRIO
3.8
—
—
4.4
3.2
—
—
3.7
2.7
—
—
3.1
ns
ns
Master Reset (MR)
MR Width
Delay from MR to Outputs x, y
—
—
TMRW
TMRQ
18.0
—
—
17.0
15.0
—
—
14.0
13.0
—
—
12.0
ns
ns
* These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.
Note: The CLB K to Q output delay (TCKO—#8) of any CLB, plus the shortest possible interconnect delay, is always longer than the data in
hold time requirement (TCKDI—#5) of any CLB on the same die.
56
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
CLB OUTPUT (X,Y)
(COMBINATORIAL)
TILO
1
CLB INPUT
(A, B, C, D, E)
TICK
TCKI
3
2
CLB CLOCK
TCL
4
TCH
11
TCKDI
12
TDICK
5
CLB INPUT
(DIRECT IN)
TECCK
TCKEC
7
6
CLB INPUT
(ENABLE CLOCK)
TCKO
8
CLB OUTPUT
(FLIP-FLOP)
CLB INPUT
(RESET DIRECT)
TRPW
13
9 TRIO
CLB OUTPUT
(FLIP-FLOP)
5-3124(F)
Figure 33. CLB Switching Characteristics
Lucent Technologies Inc.
57
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
Table 22. IOB Switching Characteristics (-50, -70, -100, and -125)
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
-50
-70
-100
-125
Description
Input Delays
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Pad to Direct In
Pad to Registered In
Clock to Registered In
3
—
4
TPID
TPTG
TIKRI
—
—
—
9.0
34.0
11.0
—
—
—
6.0
21.0
5.5
—
—
—
4.0
17.0
4.0
—
—
—
3.0
16.0
3.0
ns
ns
ns
Setup Time (Input):
Clock Setup Time
1
TPICK
30.0
—
20.0
—
17.0
—
16.0
—
ns
Output Delays
Clock to Pad
Fast
Slew-rate Limited
Output to Pad
Fast
Slew-rate Limited
3-state to Pad Hi-Z
Fast
Slew-rate Limited
3-state to Pad Valid
Fast
7
7
TOKPO
TOKPO
—
—
18.0
43.0
—
—
13.0
33.0
—
—
10.0
27.0
—
—
9.0
24.0
ns
ns
10
10
TOPF
TOPS
—
—
15.0
40.0
—
—
9.0
29.0
—
—
6.0
23.0
—
—
5.0
20.0
ns
ns
9
9
TTSHZ
TTSHZ
—
—
10.0
37.0
—
—
8.0
28.0
—
—
8.0
25.0
—
—
7.0
24.0
ns
ns
8
8
TTSON
TTSON
—
—
20.0
45.0
—
—
14.0
34.0
—
—
12.0
29.0
—
—
11.0
27.0
ns
ns
Slew-rate Limited
Setup and Hold Times (out-
put)
Clock Setup Time
Clock Hold Time
5
6
TOCK
TOKO
15.0
0
—
—
10.0
0
—
—
9.0
0
—
—
8.0
0
—
—
ns
ns
Clock
High Time*
Low Time*
Max. Flip-Flop Toggle*
11
12
—
TCH
TCL
FCLK
9.0
9.0
—
—
—
50
5.0
5.0
—
—
—
70
4.0
4.0
—
—
—
100
3.0
3.0
—
—
—
125
ns
ns
MHz
Master Reset Delays
RESET to:
Registered In
13
15
15
TRRI
TRPO
TRPO
—
—
—
35
50
68
—
—
—
25
35
53
—
—
—
24
33
45
—
—
—
23
29
42
ns
ns
ns
Output Pad (fast)
Output Pad (slew-
rate limited)
* These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.
Notes:
Timing is measured at pin threshold with 50 pF external capacitive loads (including test fixture).
Typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pF of additional load.
Typical slew-rate limited output rise/fall times are approximately 4 times longer.
A maximum total external capacitive load for simultaneous fast mode switching in the same direction is 200 pF per power/ground pin pair. For
slew-rate limited outputs, this total is 4 times larger. Exceeding this maximum capacitive load can result in ground bounce of >1.5 V amplitude
and <5 ns duration, which may cause problems when the FPGA drives clocks and other asynchronous signals.
Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or
alternatively configured as a driven output or driven from an external source.
Input pad setup time is specified with respect to the internal clock (ik).
To calculate system setup time, subtract clock delay (pad to ik) from the input pad setup time value. Input pad hold time with respect to the inter-
nal clock (ik) is negative. This means that pad levels changed immediately before the internal clock edge (ik) will not be recognized.
58
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
Table 23. IOB Switching Characteristics (-3, -4, and -5)
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
-5
-4
-3
Description
Input Delays
Symbol
Unit
Min
Max
Min
Max
Min
Max
Pad to Direct In
Pad to Registered In
Clock to Registered In
3
—
4
TPID
TPTG
TIKRI
—
—
—
2.8
16.0
2.8
—
—
—
2.5
15.0
2.5
—
—
—
2.2
13.0
2.2
ns
ns
ns
Setup Time (Input):
Clock Setup Time
1
TPICK
15.0
—
14.0
—
12.0
—
ns
Output Delays
Clock to Pad
Fast
Slew-rate Limited
Output to Pad
Fast
Slew-rate Limited
3-state to Pad Hi-Z
Fast
Slew-rate Limited
3-state to Pad Valid
Fast
7
7
TOKPO
TOKPO
—
—
5.5
14.0
—
—
5.0
12.0
—
—
4.4
10.0
ns
ns
10
10
TOPF
TOPS
—
—
4.1
13.0
—
—
3.7
11.0
—
—
3.3
9.0
ns
ns
9
9
TTSHZ
TTSHZ
—
—
6.9
21.0
—
—
6.2
19.0
—
—
5.5
17.0
ns
ns
8
8
TTSON
TTSON
—
—
12.0
20.0
—
—
10.0
17.0
—
—
9.0
15.0
ns
ns
Slew-rate Limited
Setup and Hold Times
(output)
Clock Setup Time
Clock Hold Time
5
6
TOCK
TOKO
6.2
0
—
—
5.6
0
—
—
5.0
0
—
—
ns
ns
Clock
High Time*
Low Time*
Max. Flip-Flop Toggle*
11
12
—
TCH
TCL
FCLK
2.4
2.4
190
—
—
—
2.0
2.0
230
—
—
—
1.6
1.6
270
—
—
—
ns
ns
MHz
Master Reset Delays
RESET to:
Registered In
13
15
15
TRRI
TRPO
TRPO
—
—
—
18
24
32
—
—
—
15
20
27
—
—
—
13
17
23
ns
ns
ns
Output Pad (fast)
Output Pad (slew-
rate limited)
* These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.
Notes:
Timing is measured at pin threshold with 50 pF external capacitive loads (including test fixture).
Typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pF of additional load.
Typical slew-rate limited output rise/fall times are approximately 4 times longer.
A maximum total external capacitive load for simultaneous fast mode switching in the same direction is 200 pF per power/ground pin pair. For
slew-rate limited outputs, this total is 4 times larger. Exceeding this maximum capacitive load can result in ground bounce of >1.5 V amplitude
and <5 ns duration, which may cause problems when the FPGA drives clocks and other asynchronous signals.
Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or
alternatively configured as a driven output or driven from an external source.
Input pad setup time is specified with respect to the internal clock (ik).
To calculate system setup time, subtract clock delay (pad to ik) from the input pad setup time value. Input pad hold time with respect to the
internal clock (ik) is negative. This means that pad levels changed immediately before the internal clock edge (ik) will not be recognized.
Lucent Technologies Inc.
59
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
I/O BLOCK (I)
3
TPID
I/O PAD INPUT
1
2
TIKPI
TPICK
I/O CLOCK
(IK/OK)
12
11
TCL
TCH
I/O BLOCK (RI)
RESET
4 TIKRI
TRRI
13
TOCK
TOKO
5
6
TRPO
15
I/O BLOCK (O)
TOP
10
I/O PAD OUTPUT
(DIRECT)
TOKPO
7
I/O PAD OUTPUT
(REGISTERED)
I/O PAD TS
TTSHZ
9
TTSON
8
I/O PAD OUTPUT
5-3126(F)
Figure 34. IOB Switching Characteristics
60
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
Table 24. Buffer (Internal) Switching Characteristics
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
-50
-70 -100 -125
-5
-4
-3
Description
Symbol
Unit
Max Max Max Max Max Max Max
Global and Alternate Clock Distribution*:
Either Normal IOB Input Pad to
Clock Buffer Input or
Fast (CMOS only) Input Pad to
Clock Buffer Input
TPID
10.0 8.0
7.5
6.0
7.0
5.7
6.8
5.4
6.5
5.1
5.6
4.3
ns
ns
TPIDC
8.0
6.5
TBUF Driving a Horizontal Long Line (LL)*:
I to LL While T Is Low (buffer active)
T¯ to LL Active and Valid with
Single Pull-up Resistor
TIO
TON
8.0
5.0
4.7
4.5
4.1
5.6
3.7
5.0
3.1
4.2
ns
ns
12.0 11.0 10.0 9.0
T¯ to LL Active and Valid with
Pair of Pull-up Resistors
T• to LL High with Single Pull-up
Resistor
T• to LL High with Pair of Pull-up
Resistors
TON
TPUS
TPUF
14.0 12.0 11.0 10.0
7.1
6.5
5.7
ns
ns
ns
42.0 24.0 22.0 17.0 15.6 13.5 11.4
22.0 17.0 15.0 12.0 12.0 10.5
8.8
1.0
Bidirectional Buffer Delay
TBIDI
6.0 2.0 1.8 1.7 1.4 1.2
ns
* Timing is based on the ATT3042; for other devices, see timing calculator in ORCA Foundry.
Lucent Technologies Inc.
61
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
4 TMRW
RESET
2
TMR
3 TRM
M0/M1/M2
VALID
TPGW
5
DONE/PROG
TPGI
6
INIT
(OUTPUT)
CLEAR STATE
CONFIGURE
USER STATE
PWRDWN
See *
VCC (VALID)
VCCPD
5-3124(F)
* At powerup, VCC must rise from 2 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding
RESET low until VCC has reached 4 V. A very long VCC rise time of >100 ms or a nonmonotonically rising VCC may require a >1 µs high level
on RESET, followed by a >6 µs low level on RESET and DONE/PROG after VCC has reached 4 V.
Figure 35. General FPGA Switching Characteristics
Testing of the switching characteristics is modeled after testing specified by MIL-M-38510/605. Devices are 100%
functionally tested. Actual worst-case timing is provided by the timing calculator or simulation.
Table 25. General FPGA Switching Characteristics
Signal
RESET *
Description
Symbol
Min
Max
Unit
M0, M1, and M2 Setup Time
M0, M1, and M2 Hold Time
RESET Width (LOW) Required for Abort
TMR (2)
TRM (3)
TMRW (4)
1
4.5
6
—
—
—
µs
µs
µs
DONE/PROG
Width Low Required for Reconfiguration
INIT Response After DONE/PROG is Pulled Low
TPGW (5)
TPGI (6)
6
—
—
7
µs
µs
†
VCC
Powerdown VCC (commercial/industrial)
VCCPD
2.3
—
V
*
RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration.
† PWRDWN transitions must occur while VCC > 4 V.
62
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
CCLK
(OUTPUT)
2 TCKDS
1 TDSCK
SERIAL DIN
SERIAL DOUT
(OUTPUT)
5-3127(F).a
Figure 36. Master Serial Mode Switching Characteristics
Table 26. Master Serial Mode Switching Characteristics
Signal
Description
Symbol
Min
Max
Unit
CCLK
Data-in Setup
Data-in Hold
1
2
TDSCK
TCKDS
60
0
—
—
ns
ns
Notes:
At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require
a >1 µs high level on RESET, followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V.
Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high.
Master serial mode timing is based on slave mode testing.
Lucent Technologies Inc.
63
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
A[15:0]
ADDRESS FOR BYTE N
ADDRESS FOR BYTE N + 1
1 TRAC
D[7:0]
BYTE N
2 TDRC
TRCD
3
RCLK
(OUTPUT)
7 CCLKs
CCLK
CCLK
(OUTPUT)
DOUT
(OUTPUT)
D6
D7
BYTE N – 1
5-3128(F)
Note: The EPROM requirements in this timing diagram are extremely relaxed; EPROM access time can be longer than 4000 ns. EPROM data
output has no hold time requirements.
Figure 37. Master Parallel Mode Switching Characteristics
Table 27. Master Parallel Mode Switching Characteristics
Signal
RCLK
Description
Symbol
Min
Max
Unit
To Address Valid
To Data Setup
To Data Hold
RCLK High
1
2
3
—
—
TRAC
0
60
0
600
4.0
200
—
—
—
—
ns
ns
ns
ns
µs
TDRC
TRCD
TRCH
TRCL
RCLK Low
Notes:
At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET
low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >1 µs high level on
RESET, followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V.
Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high.
64
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
CS1/CS0
CS2
TCA
1
WS
TDC
TRBWT
5
2
3 TCD
VALID
D[7:0]
CCLK
GROUP OF
8 CCLKs
TWTRB
4
TBUSY
6
RDY/BUSY
DOUT
5-3129(F)
Note: The requirements in this timing diagram are extremely relaxed; data need not be held beyond the rising edge of WS. BUSY will go active
within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immediately after the end of BUSY.
Figure 38. Peripheral Mode Switching Characteristics
Table 28. Peripheral Mode Switching Characteristics
Signal
Description
Symbol
Min
Max
Unit
Write Signal
Effective Write Time Required
(Assertion of CS0, CS1, CS2, WS)
1
TCA
100
—
ns
D[7:0]
DIN Setup Time Required
DIN Hold TIme Required
2
3
TDC
TCD
60
0
—
—
ns
ns
RDY/BUSY
RDY/BUSY Delay after End of WS
Earliest Next WS after End of BUSY
BUSY Low Time Generated
4
5
6
TWTRB
TRBWT
TBUSY
—
0
2.5
60
—
9
ns
ns
CCLK
Periods
Notes:
At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET
low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >1 µs high level on
RESET, followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V.
Configuration must be delayed until the INIT of all FPGAs is high.
Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the phase of the
internal timing generator for CCLK.
CCLK and DOUT timing is tested in slave mode.
TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a
byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the
second-level buffer has started shifting out data.
Lucent Technologies Inc.
65
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
DIN
BIT N
BIT N + 1
TDCC
TCCD
2
1
TCCL
5
CCLK
TCCH
TCCO
3
4
DOUT
(OUTPUT)
BIT N
BIT N – 1
5-3130(F)
Figure 39. Slave Mode Switching Characteristics
Table 29. Slave Mode Switching Characteristics
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
Signal
CCLK
Description
To DOUT
DIN Setup
DIN Hold
HIGH Time
LOW Time
Frequency
Symbol
Min
Max
Unit
3
1
2
4
5
TCCO
—
60
0
0.05
0.05
—
100
—
—
—
5.0
10.0
ns
ns
ns
µs
µs
TDCC
TCCD
TCCH
TCCL
FCC
—
MHz
Notes:
The maximum limit of CCLK LOW time is caused by dynamic circuitry inside the FPGA device.
Configuration must be delayed until the INIT of all FPGAs is high.
At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET
low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC, may require a >1 µs high level on
RESET, followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V.
66
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Electrical Characteristics (continued)
DONE/PROG
(OUTPUT)
TRTH
1
RTRIG (M0)
CCLK (1)
2 TRTCC
TCCL
4
TCCL
4
TCCRD
3
RDATA
(OUTPUT)
VALID
5-3131(F)
Figure 40. Program Readback Switching Characteristics
Table 30. Program Readback Switching Characteristics
Commercial: VCC = 5.0 V ± 5%; 0 °C £ TA £ 70 °C; Industrial: VCC = 5.0 ± 10%, –40 °C £ TA £ +85 °C.
Signal
Description
RTRIG HIGH
Symbol
Min
Max
Unit
RTRIG
CCLK
1
TRTH
250
—
ns
RTRIG Setup
RDATA Delay
HIGH Time
LOW Time
2
3
5
4
TRTCC
TCCRD
TCCH
200
—
0.5
0.5
—
100
—
ns
ns
µs
µs
TCCL
5.0
Notes:
During readback, CCLK frequency may not exceed 1 MHz.
RTRIG (M0 positive transition) must not be done until after one clock following active I/O pins.
Readback should not be initiated until after configuration is complete.
Lucent Technologies Inc.
67
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams
Terms and Definitions
Basic Size (BSC):
Design Size:
The basic size of a dimension is the size from which the limits for that dimension are derived
by the application of the allowance and the tolerance.
The design size of a dimension is the actual size of the design, including an allowance for fit
and tolerance.
Typical (TYP):
When specified after a dimension, indicates the repeated design size if a tolerance is speci-
fied or repeated basic size if a tolerance is not specified.
Reference (REF):
The reference dimension is an untoleranced dimension used for informational purposes only.
It is a repeated dimension or one that can be derived from other values in the drawing.
Minimum (MIN) or
Maximum (MAX):
Indicates the minimum or maximum allowable size of a dimension.
44-Pin PLCC
Dimensions are in millimeters.
17.65 MAX
16.66 MAX
PIN #1 IDENTIFIER
ZONE
6
1
40
7
39
16.66
MAX
17.65
MAX
17
29
18
28
4.57
MAX
SEATING PLANE
0.10
0.51 MIN
TYP
1.27 TYP
0.53
5-2506r7(C)
MAX
68
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
68-Pin PLCC
Dimensions are in millimeters.
25.27 MAX
24.33 MAX
PIN #1 IDENTIFIER ZONE
9
1
61
10
60
24.33
MAX
25.27
MAX
26
44
27
43
5.08
MAX
SEATING PLANE
0.10
1.27 TYP
0.53 MAX
0.51 MIN,
TYP
5-2139r13(C)
Lucent Technologies Inc.
69
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
84-Pin PLCC
Dimensions are in millimeters.
30.35 MAX
29.16 MAX
PIN #1 IDENTIFIER ZONE
11
1
75
12
74
29.16
MAX
30.35
MAX
32
54
33
53
5.08 MAX
SEATING PLANE
0.10
0.51 MIN
TYP
0.53 MAX
5-2347r13(C)
1.27 TYP
70
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
100-Pin QFP
Dimensions are in millimeters.
17.20 ± 0.20
14.00 ± 0.20
PIN #1 IDENTIFIER
ZONE
1.60 REF
100
81
1
0.25
80
GAGE PLANE
SEATING PLANE
0.73/1.03
DETAIL A
20.00
± 0.20
23.20
± 0.20
0.13/0.23
0.22/0.38
51
M
30
0.12
DETAIL B
31
50
DETAIL A
DETAIL B
2.80 ± 0.25
3.30
MAX
SEATING PLANE
0.10
0.65 TYP
0.25 MAX
5-2131r9(C)
Lucent Technologies Inc.
71
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
100-Pin TQFP
Dimensions are in millimeters.
16.00 ± 0.20
14.00 ± 0.20
PIN #1 IDENTIFIER ZONE
100
76
1.00 REF
1
75
0.25
GAGE PLANE
SEATING PLANE
0.45/0.75
14.00
± 0.20
DETAIL A
16.00
± 0.20
0.106/0.200
25
51
0.19/0.27
0.08
M
26
50
DETAIL B
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 TYP
5-2146r14(C)
72
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
132-Pin PPGA
Dimensions are in millimeters.
37.08 ± 0.38
TYPICAL THERMAL VIA
PACKAGE ID
37.08
± 0.38
PIN A1 INDEX MARK
2.16 ± 0.23
1.19 ± 0.20
1.78 ± 0.20
TYP 4 PLACES
5.21 ± 0.20
0.46 ± 0.05
13 SPACES @ 2.54 = 33.02
PIN A1 CORNER
1
2
3
4
5
6
7
13 SPACES @
2.54 = 33.02
8
9
10
11
12
13
14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
5-2115(C)
Lucent Technologies Inc.
73
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
144-Pin TQFP
Dimensions are in millimeters.
22.00 ± 0.20
20.00 ± 0.20
PIN #1 IDENTIFIER ZONE
144
109
1.00 REF
0.25
1
108
GAGE PLANE
SEATING PLANE
0.45/0.75
DETAIL A
20.00
± 0.20
22.00
± 0.20
0.106/0.200
0.19/0.27
36
73
0.08
M
37
72
DETAIL B
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 TYP
5-3815r5(C)
74
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
160-Pin QFP
Dimensions are in millimeters.
31.20 ± 0.20
28.00 ± 0.20
PIN #1 IDENTIFIER ZONE
121
1.60 REF
120
1
0.25
GAGE PLANE
SEATING PLANE
0.73/1.03
28.00
± 0.20
DETAIL A
31.20
± 0.20
0.13/0.23
81
40
0.22/0.38
M
0.12
41
80
DETAIL B
DETAIL A
DETAIL B
3.42 ± 0.25
4.07
MAX
SEATING PLANE
0.10
0.65 TYP
0.25 MIN
5-2132r12(C)
Lucent Technologies Inc.
75
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
175-Pin PPGA
Dimensions are in inches.
42.16 ± 0.40
TYPICAL THERMAL VIA
PACKAGE ID
42.16
± 0.40
PIN A1 INDICATOR INDEX MARK
2.16 ± 0.23
1.19 ± 0.20
1.78 ± 0.20 TYP
4 PLACES
5.21 ± 0.20
0.46 ± 0.05
PIN A1 CORNER
15 SPACES @ 2.54 = 38.10
1
2
3
4
5
6
7
8
9
15 SPACES @
2.54 = 38.10
10
11
12
13
14
15
16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R S
5-2116(C)
76
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Outline Diagrams (continued)
208-Pin SQFP
Dimensions are in millimeters.
30.60 ± 0.20
28.00 ± 0.20
PIN #1 IDENTIFIER ZONE
208
157
1.30 REF
1
156
0.25
GAGE PLANE
SEATING PLANE
28.00
± 0.20
0.50/0.75
30.60
DETAIL A
± 0.20
0.090/0.200
105
52
0.17/0.27
53
104
M
0.10
DETAIL A
DETAIL B
3.40 ± 0.20
DETAIL B
4.10 MAX
SEATING PLANE
0.10
0.50 TYP
0.25 MIN
5-2196(C)R12
Lucent Technologies Inc.
77
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Example: ATT3020, 100 MHz, 68-Lead PLCC,
Industrial Temperature
Ordering Information
The ATT3000 Series includes standard and high-
performance FPGAs. The part nomenclature uses two
different suffixes for speed designation. The lower-
speed ATT3000 Series devices use a flip-flop toggle
rate (-50, -70, -100, -125), which corresponds to
XC3000 Series nomenclature. The ATT3000 Series
High-Performance FPGAs use a suffix which is an
approximation of the look-up table delay (-5, -4, and
-3), which corresponds to XC3100 nomenclature.
ATT3020-100 M 68
I
DEVICE
TYPE
TEMPERATURE
RANGE
TOGGLE
RATE
NUMBER OF
PINS
PACKAGE
TYPE
Table 31. FPGA Temperature Options
For packaging options, burn-in diagrams, and/or pack-
age assembly information, call 1-800-EASY-FPG(A) or
1-800-327-9374.
Symbol
Description
Temperature
(Blank)
I
Commercial
Industrial
0 °C to 70 °C
–40 °C to +85 °C
Table 32. FPGA Package Options
Symbol
Description
H
J
Plastic Pin Grid Array
Quad Flat Pack
M
S
T
Plastic Leaded Chip Carrier
Shrink Quad Flat Pack
Thin Quad Flat Pack
78
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Ordering Information (continued)
Table 33. ATT3000 Series Package Matrix
100-Pin
44-Pin
PLCC
68-Pin
PLCC
84-Pin
PLCC
132-Pin 144-Pin 160-Pin 175-Pin 208-Pin
PPGA
TQFP
QFP
PPGA
SQFP
Device
Speed
QFP
TQFP
M44
—
—
—
—
—
—
CI
CI
CI
CI
C
M68
CI
CI
CI
CI
C
M84
CI
CI
CI
CI
C
J100
CI
CI
CI
CI
C
T100
—
—
—
—
—
—
CI
CI
CI
CI
C
H132
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
T144
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
J160
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
H175
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
S208
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
-70
-100
-125
-5
-4
-3
-70
-100
-125
-5
-4
-3
-70
-100
-125
-5
-4
-3
-70
-100
-125
-5
-4
-3
ATT3020
C
C
C
CI
CI
CI
CI
C
CI
CI
CI
CI
C
CI
CI
CI
CI
C
ATT3030
ATT3042
ATT3064
ATT3090
C
C
C
C
C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
CI
CI
CI
CI
C
CI
CI
CI
CI
C
C
C
C
C
C
CI
CI
CI
CI
C
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
CI
CI
CI
CI
C
CI
CI
CI
CI
C
C
C
C
C
C
-70
-100
-125
-5
-4
-3
CI
CI
CI
CI
C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CI
CI
CI
CI
C
C
C
C
C
Key: C = commercial, I = industrial.
Lucent Technologies Inc.
79
For FPGA technical applications support, please call 1-800-327-9374. Outside the U.S.A., please call 1-610-712-4331.
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro/fpga
U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 1-610-712-4106 (In CANADA: 1-800-553-2448, FAX 1-610-712-4106), e-mail docmaster@micro.lucent.com
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
JAPAN: Microelectronics Group, Lucent Technologies Semiconductor Marketing Ltd., 2-7-18, Higashi-Gotanda, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1770, FAX (81) 3 5421 1785
For data requests in Europe:
MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148
For technical inquiries in Europe:
CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK),
FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. ORCA is a trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.
Copyright © 1997 Lucent Technologies Inc.
All Rights Reserved
Printed in U.S.A.
February 1997
DS97-048FPGA (Replaces DS94-177FPGA)
相关型号:
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