AV2638 [ETC]
音频D/A转换。hangbiao gbf; 音频D / A转换.hangbiao GBF
| 型号： | AV2638 |
| 厂家： | 
ETC |
| 描述： | 音频D/A转换。hangbiao gbf |
| 文件： | 总16页 (文件大小：766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AVSTechnology
AV2636
24-bit 192kHz Stereo Audio DAC
DESCRIPTION
FEATURES
The AV2636 is a high performance, low power
stereo audio digital to analog converter (DAC). It
is designed for high performance audio
applications such as CD player, DVD player,
home theater systems, digital TVs and set top
boxes. Based on the state of the art multi-bit
∆−Σ modulator, it also includes the digital
interpolation filters, digital volume control, digital
de-emphasis and analog low pass filters. It has
no linearity drift due to time and temperature. It
also has high tolerance to clock jitter.
•
•
•
•
•
•
•
•
•
•
SNR: 102 dB
THD+N: -90 dB
Input Sample rate: 8kHz – 192kHz
Input data resolution: 16/18/20/24 bits
Digital De-Emphasis for 32k/44.1k/48kHz
Digital Volume Control
Mute Control
Single Power Supply 2.2V – 3.6V
Low Clock Jitter Sensitivity
Small 14-pin SOIC Package
The device has a serial audio interface that
accepts 16/18/20/24 digital data in I2S, Right-
justified or DSP mode. It can work at auto-detect
mode or programmable mode with a two-wire
serial command interface. Audio sample rates
from 8kHz to 192kHz are supported.
APPLICATIONS
•
•
•
•
DVD/CD Player
Home Theatre Systems
Digital TV and Set-Top Boxes
Electronic Music Instrument
CHIP BLOCK DIAGRAM
LOW PASS
SC
AOUTL
AOUTR
DAC
DAC
FILTER
SERIAL
AUDIO
INTERPOLATION
DIGITAL
MULTI-LEVEL
∆−Σ
MODULATOR
SF
SD
INTERFACE
FILTERS
LOW PASS
FILTER
CONTROL INTERFACE
VDD
VCM
GND
FMTC
FMTD
MUTE
MODE
MCK
AVS Technology, Inc.
1-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
PIN CONFIGURATION
SF
SD
MCK
1
2
3
4
5
6
7
14
13
12
11
10
9
FMTD
FMTC
MODE
MUTE
AOUTL
VDD
SC
AV2636
NC
VCM
AOUTR
GND
8
PIN DESCRIPTION
Pin Name
SF
Pin
1
Type
Description
Digital Input
Digital Input
Sample rate frame clock input.
SD
2
Audio data input. It can be 16/18/20/24 bit in 2’s complement
format.
SC
(NC)
VCM
3
4
5
Digital Input
-
Serial audio data bit clock input.
No Connection
Analog Output Common mode voltage output. Connect to 10uF cap in parallel with
0.1uF cap.
AOUTR
GND
6
7
8
9
Analog Output Right channel analog audio signal output.
Supply
Supply
Ground supply. Need a solid ground plane.
Power supply. Need a clean power supply.
VDD
AOUTL
MUTE
Analog Output Left channel analog audio signal output.
10 Digital Input
Mute control with internal pull down.
High = Mute on.
Low = Mute off.
MODE
FMTC
11 Digital Input
Chip operation mode selection with internal pull down.
High = Programmable mode.
Low = Auto-detect mode.
12 Digital Input
13 Digital I/O
Dual functional pin. Its function is controlled by the MODE pin.
Internal pull up.
When MODE = High, FMTC = Serial clock in control interface.
When MODE = Low, FMTC = De-Emphasis: On (high) / Off (low).
Dual functional pin. Its function is controlled by the MODE pin.
Internal pull up. Needs an external 4.7kΩ to VDD.
When MODE = High, FMTD = Serial data in control interface.
When MODE = Low, FMTD = Data input format select:
High = 16-24 bit I2S or 16 bit DSP ‘early’
Low = 16 bit right justified or 16 bit DSP ‘late’
External master clock input. The clock frequency depends on the
audio sample rate.
FMTD
MCK
14 Digital Input
AVS Technology, Inc.
2-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
ORDERING INFORMATION
PRODUCT
AV2636
PACKAGE
14 pin SOIC
TEMPERATURE RANGE
-25˚C — +85˚C
ELECTROSTATIC DISCHARGE SENSITIVITY
The device of integrated circuits is manufactured on CMOS process. It can be damaged by ESD. AVS
Technology recommends that the device be handled with appropriate ESD precautions. Improper
handling and installation procedures can cause damage to the device.
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are the limiting values of the stress. Operation beyond these limits may cause
permanent damage to the device. Normal operation is not guaranteed at these limits.
Symbol
VDD
Vi
Characteristics
Power supply voltage (Measured to GND)
Digital input voltage range
Min
Max
Units
V
-0.3
+3.6
GND – 0.3 VDD + 0.3
V
Ai
Digital input forced current
-100
-25
-65
-65
+100
+125
+150
+150
+240
+220
mA
˚C
TA
Ambient operating temperature range
Storage temperature range
Tstg
Tj
˚C
Junction temperature (Plastic package)
Lead soldering temperature (10 sec., ¼” from pin)
Vapor phase soldering (1 minute)
˚C
Tsol
Tvsol
˚C
˚C
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
GND
MCK
TA
Characteristics
Min
Typical
Max
Units
Power supply voltage
2.2
3.3
0
3.6
V
V
Ground
Master clock frequency
Ambient operating temperature range
75
85
MHz
˚C
-25
AVS Technology, Inc.
3-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
ELECTRICAL CHARACTERISTICS
(Test conditions: VDD = 3.3V, GND = 0V, TA = +25˚C, fs = 48kHz, MCK = 256fs unless otherwise stated.
The measurement bandwidth is from 20Hz to 20kHz.)
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
DC Electrical Characteristics
Supply current (VDD = 3.3V)
Supply current (VDD = 2.5V)
Digital I/O Levels (TTL Level)
Digital input high level
IDD
IDD
10
7
mA
mA
VIH
VIL
2.0
V
V
V
V
Digital input low level
0.8
Digital output high level (IOH = 2mA)
Digital output low level (IOL = 2mA)
Analog Characteristics
Reference voltage
VOH
VOL
VDD–0.2
GND+0.2
VCM
AOUT
RL
VDD/2
V
Vrms
kΩ
Full scale analog output level
Minimum resistive load
VDD/3.3
10
Maximum capacitive load
Output DC level
CL
100
pF
VDD/2
V
DAC Analog Output Performance (Test load RL = 10kΩ, CL = 10pF)
VDD = 3.3V SNR
102
-90
98
dB
dB
dB
dB
dB
dB
dB
dB
dB
THD+N (1kHz, 0dBFs input)
Dynamic Range (1kHz, -60dBFs input)
VDD = 2.5V SNR
100
-90
96
THD+N (1kHz, 0dBFs input)
Dynamic Range (1kHz, -60dBFs input)
Channel separation (1kHz)
-95
0.1
Interchannel gain mismatch
Program gain range
-∞
+6
Notes:
1. SNR is measured as the ratio of output level with 1kHz full scale signal, to output level with all zero
signal into the digital input. The measurement is over 20Hz to 20kHz bandwidth with a ‘A-weight’ filter.
2. THD is measured at the output with 1kHz full scale signal into the digital input. The measurement is
over 20Hz to 20kHz bandwidth.
3. Dynamic Range is the ratio of maximum output over minimum output. It is normally measured by
THD+N at the output with an input signal that is 60dB below full scale. The 60dB is then added back
to the THD+N value for the final result.
4. Channel separation is also known as channel cross talk. It is measured by sending a 1kHz full scale
signal into one channel and measuring the output value at the other channel.
5. All measurements are done with a 20kHz low pass filter. Fail to use the filter will result in reduced
performance reading.
6. The VCM pin should be decoupled with a 10uF capacitor in parallel with a 0.1uF capacitor. Smaller
value may result in reduced performance.
AVS Technology, Inc.
4-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
OPERATING MODE
The AV2636 can operate at two modes. They are auto-detect mode and programmable mode. The
‘MODE’ pin status (High/Low) determines which mode the device will be operated. If MODE = Low (pull to
GND or not connected using internal pull down), the device will be operated at auto-detect mode. If
MODE = High (pull to VDD), the device will be operated at programmable mode. The basic functions of
the two modes are described as follows:
•
Auto-detect mode: The relation between sample rate and master clock frequency is auto detected.
De-emphasis and serial interface mode are determined by FMTC and FMTD pins.
Programmable mode: The device operation will be set by on chip control registers that can be
accessed through a two-wire command interface.
•
AUDIO DATA SAMPLE RATE AND MASTER CLOCK FREQUENCY
The AV2636 supports various audio data sample rate (fs) from 8kHz to 192kHz. The typical audio sample
rates are 32kHz, 44.1kH, 48kHz, 96kHz and 192kHz. The master clock (MCK) can be of 64fs to 384fs
depending on the operation mode. MCK is an input clock that operates the internal digital filters. Other on
chip clocks are also derived from MCK.
The on-chip master clock detection circuit automatically determines the relationship of master clock
frequency and audio sample rate. The counting error is set to be ±8 master clock cycles. If the error is
larger than the threshold, the DAC output will be shut down and auto muted.
The master clock has to be synchronized with the serial audio data frame signal ‘SF’. SF is also called left
and right data frame signal. The phase difference and clock jitters can be tolerated.
Sample
Rate (fs)
32 kHz
Master Clock Frequency MCK (MHz)
64fs
N/A
96fs
N/A
128fs
N/A
192fs
N/A
256fs
8.192
384fs
12.288
16.9344
18.432
33.8688
36.864
73.728*
44.1 kHz
48 kHz
N/A
N/A
N/A
N/A
11.2896
12.288
22.5792
24.576
49.152*
N/A
N/A
N/A
N/A
88.2 kHz
96 kHz
N/A
N/A
11.1896
12.288
24.576
16.9344
18.432
36.864
N/A
N/A
192 kHz
12.288
18.432
Note:
* Only available at programmable mode.
AVS Technology, Inc.
www.avstech.com
5-16
August 18, 2004
AV2636
Product Datasheet
DIGITAL AUDIO DATA INTERFACE
The serial audio data is send to the device through a three-wire interface. The interface consists of three
input pins that are serial clock (SC), serial data (SD) and sync-frame (SF). The sync-frame is also a
left/right channel indicator. Three interface formats are supported.
•
•
•
I2S mode
Right justified mode
DSP mode
All formats send MSB first. The audio data is in 2’s complement format. The mode selection can be either
in auto-detect mode or programmable mode.
The three-wire digital audio data interface timing specification is shown at the following diagram.
SF
tSC
tSFH
tSFS
SC
SD
tSCH
tSCL
tDCS
tDCH
The timing characteristics are shown at the following table.
Symbol
tSC
tSCH
tSCL
Description
Min
50
20
20
10
10
10
10
Max
Units
ns
SC clock cycle time
SC pulse width high
SC pulse width low
ns
ns
tDCS
tDCH
tSFH
SD data setup time relative to SC rising edge
SD data hold time relative to SC rising edge
SF hold time relative to SC rising edge
SF setup time relative to SC rising edge
ns
ns
ns
tSFS
ns
I2S MODE
In I2S mode, the serial interface accepts input data at SD pin and frame input at SF pin. The serial
data is time multiplexed with the frame signal SF indicating left and right channel data. SF is low
during left channel data and high during right channel data. The SF is also a timing signal for the
start of each word of left and right channel.
The MSB of the audio data SD is sampled on the second rising edge of SC following SF transition.
Word lengths of 16/18/20/24 bits are supported.
AVS Technology, Inc.
6-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
1/fs
Left Channel
Right Channel
SF
SC
SD
1 SC
1 SC
n-1 n-2
1
0
n-1 n-2
1
0
MSB
LSB
MSB
LSB
RIGHT JUSTIFIED MODE
In right justified mode, the serial interface accepts input data at SD pin and frame input at SF pin.
The serial data is time multiplexed with the frame signal SF indicating left and right channel data.
SF is high during left channel data and low during right channel data. The SF is also a timing
signal for the end of each word of left and right channel.
The MSB is received first and LSB is aligned with the transition of frame signal SF. Data is
sampled at the rising edge of SC. Word lengths of 16/18/20/24 bits are supported.
1/fs
Left Channel
Right Channel
SF
SC
SD
n-1 n-2
MSB
1
0
n-1 n-2
MSB
1
0
LSB
LSB
DSP MODE
In DSP mode, the serial interface accepts input data at SD pin and frame input at SF pin. Audio
data SD is time multiplexed with left channel first followed by right channel data. Frame sync SF
appears every 1/fs time. Minimum SF pulse high is 1 SC cycle and maximum SF pulse high is 8
SC cycles. Both DSP ‘early’ mode and ‘late’ mode are supported.
The MSB is received first. Data is sampled at the rising edge of SC. Word lengths of 16/18/20/24
bits are supported.
AVS Technology, Inc.
7-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
DSP ‘early’ mode:
1/fs
SF
Max 8 SC cycles
Left Channel
SC
SD
1 SC
Right Channel
n-1 n-2
MSB
1
0
n-1 n-2
1
0
No Valid Data
LSB MSB
LSB
DSP ‘late’ mode:
SF
1/fs
Max 8 SC cycles
Left Channel
SC
SD
Right Channel
n-1 n-2
MSB
1
0
n-1 n-2
1
0
LSB
No Valid Data
LSB MSB
AVS Technology, Inc.
8-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
SERIAL CONTROL INTERFACE
The AV2636 supports a 2-wire I2C compatible serial control interface. When MODE pin is externally
pulled high, the FMTC and FMTD pins function as SCL and SDA. Where SCL is serial clock input and
SDA is serial data input and output. The internal control registers can be programmed through the
interface.
The chip ID for the AV2636 is a 7-bit hexadecimal number “32hex”. The protocol for write operation
consists of sending 3 bytes of data to the AV2636 at SDA pin. Following each byte is the acknowledge bit
generated by the AV2636. The first byte is the 7-bit chip ID followed by the read/write bit (read is logic
high and write is logic low). The second byte is control register address. The third byte is control register
data. The following diagram shows a “write” sequence and timing of control register address 00H and
data 30H.
START CA6
CA0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP
0
1
1
0
0
1
1
SDA
SCL
Chip ID:
CA[6:0] = 0110010
Register Address: A[7:0] = 00H
Data:
D[7:0] = 30H
Timing specifications
tBF
SDA
tDH_STA
tDH_DA tDS_DA
tDS_STA
tHIGH
tDS_STO
SCL
tLOW
STOP
START
tf
START
STOP
tr
Symbol
Descriptions
Min
Max
Units
fSC
SCL clock frequency
100
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
tDS_STA
tDH_STA
tDS_STO
tLOW
tHIGH
tr
START condition SDA setup time
START condition SDA hold time
STOP condition SDA setup time
SCL low pulse time
4.7
4.0
4.0
4.7
4.0
SCL high pulse time
SCL and SDA rise time
SCL and SDA fall time
Data setup time
1.0
0.3
tf
tDS_DA
tDH_DA
tBF
250
0
Data hold time
Bus free time
4.7
AVS Technology, Inc.
9-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
PROGRAMMABLE CONTROL REGISTER ASSIGNMENT
There are 4 programmable control registers in AV2636. Their function and address assignment are
described in the following tables. All the contents of the programmable control registers can be read back
through the serial control interface.
Address
Register
Default Value
Function Description
(7-bit hex)
(hex)
7F
0
1
2
3
CREG0[7:0]
CREG1[7:0]
CREG2[7:0]
CREG3[7:0]
Volume control for both left and right channel
Device control
Serial audio interface mode control
Clock and sample rate settings
00
00
00
Volume Control Register (CREG0[7:0])
Address
CREG0[7:0]
Bit4 Bit3
VOLUME[7:0]
7’h00
Bit7
Bit6
Bit5
Bit2
Bit1
Bit0
Default Value
0
1
1
1
1
1
1
1
Device Control Register (CREG1[7:0])
Address
CREG1[7:0]
7’h01
Bit7
StdBy
0
Bit6
DeEmp
0
Bit5
Bit4
Bit3
Reserved
0
Bit2
Bit1
Bit0
Mute
0
Default Value
0
0
0
0
StdBy: Stand-By Control
0: disable Stand-By (default)
1: enable Stand-By for power saving
(Notes: Mute should be enabled when StdBy is enabled.)
DeEmp: De-emphasis control
0: by-pass de-emphasis filter (default)
1: enable de-emphasis filter
Mute: Software mute control
0: do not mute the left and right channel DACs (default)
1: mute the left and right channel DACs simultaneously
Serial Audio Interface Control Register (CREG2[7:0])
Address
7’h02
CREG2[7:0]
Bit7
Bit6
Bit5
SFJ
0
Bit4
SCJ
0
Bit3
Bit2
Bit1
Bit0
Reserved
SAIM[1:0]
Format[1:0]
Default Value
0
0
0
0
0
0
SFJ: Sync Frame Adjustment
0: do not delay SF signal by 1 SC clock cycle (default)
1: delay SF signal by 1 SC clock cycle
SCJ: Serial Clock Adjustment
0: do not invert SC clock (default)
1: invert SC clock
AVS Technology, Inc.
www.avstech.com
10-16
August 18, 2004
AV2636
Product Datasheet
SAIM[1:0]: Serial Audio Interface Mode Control
00: I2S mode
01: DSP ‘early’ mode
10: right justified mode
11: DSP ‘late’ mode
Format[1:0]: Serial Audio Interface Data Resolution
00: 24-bit resolution (default)
01: 20-bit resolution
10: 18-bit resolution
11: 16-bit resolution
Master Clock and Sample Rate Setting Register (CREG3[7:0])
Address
7’h03
CREG3[7:0]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reserved
CKSET[3:0]
Default Value
0
0
0
0
0
0
0
0
CKSET[3:0]: The internal operation of AV2636 is affected by the relations between MCK
frequency and input audio sample rate. The correct setting of these 4-bit based on the relations
ensures the correct operation of the device. The following table shows the values of the 4-bit.
CKSET[3:0] For Various Clock and Sample Rate
Sample Rate (kHz)
MCK (MHz)
8.192/11.2896/12.288
12.288/16.934/18.432
11.2896/12.288
16.9344/18.432
22.5792/24.576
33.8688/36.864
12.288
CKSET[3:0]
1X Speed 32/44.1/48
256fs
384fs
128fs
192fs
256fs
384fs
64fs
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
32/44.1/48
2X Speed 88.2/96
88.2/96
88.2/96
88.2/96
4X Speed 192
192
192
192
192
192
18.432
96fs
24.576
128fs
192fs
256fs
384fs
36.864
49.152
73.728
AVS Technology, Inc.
www.avstech.com
11-16
August 18, 2004
AV2636
Product Datasheet
DIGITAL FILTER CHARACTERISTICS
The digital interpolation filters have small passband ripples and large stopband attenuations. There are
three types of filters that are implemented for different sample mode (1X/2X/4X) and MCK relations. The
selection of the filters depends on the operation mode of the device, auto-detect mode or programmable
mode.
Programmable mode: filter selection is shown in the following table. 20kHz audio passband is assumed.
Sample Mode
Parameter
Condition
F < 0.45fs
Min
60
Max
Unit
dB
dB
dB
dB
dB
dB
Normal (1X)
Passband Ripple
±0.03
Stopband Attenuation
Passband Ripple
F > 0.55fs
Double (2X)
Quad (4X)
F < 0.225fs
F > 0.775fs
F < 0.1125fs
F > 0.8875fs
±0.03
±0.03
Stopband Attenuation
Passband Ripple
60
Stopband Attenuation
53
Auto-detect mode: filter type is automatically selected based on the detected sample mode and MCK
relations.
The following plots show the digital filter response and closer look of the passband ripple for normal
speed mode (1X), double speed mode (2X) and quad speed (4X).
AVS Technology, Inc.
12-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
AVS Technology, Inc.
13-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
DIGITAL DE-EMPHASIS CHARACTERISTIC
The device has a build in digital de-emphasis filter that can be utilized or bypassed in either auto-detect
mode or programmable mode. The characteristic of the filter for 44.1kHz sample frequency is shown as
follows:
Gain (dB)
T1=50µs
0 dB
T1=15µs
-10 dB
F1=3.18kHz
F2=10.61kHz
Frequency
The filter response scales with sample frequency fs and is only applied to 1X sample speed mode.
AVS Technology, Inc.
14-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
RECOMMENDED APPLICATION CONNECTIONS
2.3V – 3.6V
+
10uF
C2
0.1uF
C1
8
VDD
1
2
3
Audio
Data
SF
SD
SC
10uF
10uF
Processor
6
AOUTR
External
Low Pass
Filters for
AV2636
9
5
10
11
12
13
L/R Channel
MUTE
MODE
FMTC
FMTD
AOUTL
Hardware
& Software
Control
VCM
0.1uF
C3
+
10uF
C4
GND
7
Notes:
1. Power supply VDD should be a clean analog power that separated from system digital power.
2. C1 and C3 should be placed as close to the AV2636 as possible.
3. Use low ESR capacitors for better performance.
RECOMMENDED EXTERNAL LOW PASS FILTER
1.0nF
2.2kΩ
10kΩ
+Vs
-Vs
51Ω
Vi
+
Vo
680pF
−
47kΩ
10kΩ
10kΩ
AVS Technology, Inc.
15-16
August 18, 2004
www.avstech.com
AV2636
Product Datasheet
PACKAGE INFORMATION
e
B
14
8
7
14 PIN SOIC 3.9 mm BODY WIDE
E
H
1
D
h x 45˚
A
A1
C
α
SEATING PLANE
L
Symbols
Dimensions (mm)
Dimensions (inches)
Min
1.35
0.10
0.33
0.19
8.55
3.80
Max
1.75
0.25
0.51
0.25
8.75
4.00
Min
Max
A
A1
B
C
D
E
e
0.0532
0.0040
0.0130
0.0075
0.3367
0.1497
0.0688
0.0098
0.0200
0.0098
0.3444
0.1574
1.27 BSC
0.05 BSC
H
h
5.8
0.25
0.40
0˚
6.2
0.5
1.27
8˚
0.2284
0.0099
0.0160
0˚
0.2440
0.0196
0.0500
8˚
L
α
Note:
The package meets JEDEC.95, MS-012. Refer it for further details.
IMPORTANT NOTICE:
AVS Technology, Inc. believes that the information contained in the document is accurate and reliable. However, the information is
provided “AS IS” without any kind of warranty. AVS reserves the right to change the product and the document without prior notice.
Customers are advised to obtain the latest version of the relevant information before placing order. No liability is assumed by AVS
for infringement of any patent, intellectual property, or other rights in the application that use this product and information contained
herein.
AVS Technology, Inc. assumes no liability for any kind of sequential damage due to the use of its product.
AVS Technology, Inc.
16-16
August 18, 2004
www.avstech.com
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